In-memory computing macro-cell chip-oriented test system and method

Abstract

The invention discloses an in-memory computing macro-cell chip-oriented testing system and method, and belongs to the technical field of chip testing. The test system comprises an upper computer, an FPGA (Field Programmable Gate Array), an FMC (Frequency Modulation Controller) communication adapter plate, a to-be-tested in-memory computing macro-cell chip core plate and a power supply plate, the upper computer is in connection debugging and data communication with the FPGA through the JTAG, the FPGA is in debugging connection and data communication with the computing macro-cell chip core board loaded in the memory to be tested through the FMC communication adapter board, finally, a test result is reversely transmitted back to the upper computer through the UART of the FPGA for data comparison, whether the function of the chip meets the expectation or not is judged, and if yes, the function of the chip meets the expectation. The whole system is powered by a power panel loaded with a power management circuit. Therefore, the in-memory computing macro-cell chip is tested, and the whole system has the advantages of simple structure, high automation degree, low test cost and the like, so that the test efficiency can be effectively improved, the manual test cost is reduced, and the verification test requirements of different types of in-memory computing macro-cell chips are met.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a testing system and method for an in-memory computing macro unit chip. Background Art

[0002] In the traditional von Neumann architecture, the limitation of memory performance becomes a bottleneck for further improving the overall performance of the system. This problem is called the "memory wall" problem of the von Neumann architecture. With the rapid development of artificial intelligence technology, the demand for computing power has increased dramatically. However, traditional digital computing arrays consume a lot of energy and time during data transmission, which makes it difficult to meet the demand for efficient computing in edge computing scenarios. Therefore, the application of in-memory computing macro-unit chips with high energy efficiency and area efficiency is becoming more and more widespread.

[0003] With the continuous development of in-memory computing macro-unit chip technology, how to effectively improve the testing efficiency of in-memory computing macro-unit chips has become a technical problem that needs to be solved urgently in the industry. At the same time, the high test complexity and diversity of in-memory computing macro-unit chips themselves further limit the improvement of their testing efficiency. Existing testing systems and methods usually require designers and testers to adapt different types of in-memory computing macro-unit chips one by one, resulting in more manual operations and observations during the testing process, and low test coverage and automation, which increases the complexity and time cost of the test. Therefore, there is an urgent need for a universal and automated testing system and method to meet the verification and testing needs of various types of in-memory computing macro-unit chips. Summary of the invention

[0004] The present invention provides a testing system and method for in-memory computing macro unit chips, which realizes the testing of in-memory computing macro unit chips, and the overall system has the advantages of simple structure, high degree of automation and low testing cost. Through the corresponding automated process testing method, a relatively comprehensive and efficient testing of the in-memory computing macro unit chips is achieved.

[0005] The first aspect of the present invention provides a test system for an in-memory computing macro unit chip, comprising: a host computer, a field editable gate array, an FMC communication adapter board, a core board of the in-memory computing macro unit chip to be tested, and a power supply board;

[0006] The host computer includes a software development kit and a UART serial port debugging assistant for a field editable gate array, the host computer is connected to the field editable gate array through JTAG, the programmable system of the field editable gate array is controlled and debugged through a joint test working group, and the test result of the corresponding in-memory computing macro unit chip is transmitted back to the host computer through the UART of the programmable logic circuit in the field editable gate array, so as to perform data comparison through the universal asynchronous receiver and transmitter serial port debugging assistant;

[0007] The FMC communication adapter board connects the field editable gate array and the in-memory computing macro unit chip core board to be tested, and is responsible for the transmission of data and control signals during the test process;

[0008] The in-memory computing macro unit chip core board to be tested is connected to the FMC communication adapter board and the power supply board, and the control and data signals in the test process are received or sent through the FMC communication adapter board, and the in-memory computing macro unit chip core board to be tested is powered by the power supply board;

[0009] The power board is connected to the in-memory computing macro unit chip core board to be tested, converts the mains power into direct current through an AC-DC converter, and converts the fixed voltage output by the AC-DC adapter into the required voltage of the in-memory computing macro unit chip core board to be tested through the DC-DC converter chip carried by the power board.

[0010] Optionally, in one embodiment of the present invention, the host computer is connected to a JTAG debugger and a UART serial port debugger via a USB interface, wherein the field editable gate array includes an onboard FMC adapter interface, a UART serial port debugging interface and an SD card slot, and the field editable gate array is connected to the in-memory computing macro unit chip core board to be tested via the FMC communication adapter board, and the host computer reads the test results output by the in-memory computing macro unit chip core board to be tested via UART, and the SD card slot is used to store the test data and test results.

[0011] Optionally, in one embodiment of the present invention, the programmable system of the field-editable gate array includes an ARM A53 core and multiple peripherals, and the data to be tested is encapsulated as top-level instructions of the in-memory computing macro unit to be tested by writing a C code software program; the programmable logic of the field-editable gate array includes multiple programmable configurable hardware circuits, and the programmable logic circuit is integrated into an interface handshake circuit between the programmable system and the in-memory computing macro unit chip to be tested by writing RTL code, which is used to realize communication between the FPGA and the in-memory computing macro unit chip to be tested.

[0012] Optionally, in one embodiment of the present invention, the FMC communication adapter board uses an FMC adapter interface packaged in ASP-134486-01, which is connected to the field editable gate array and the in-memory computing macro unit chip core board to be tested.

[0013] Optionally, in one embodiment of the present invention, the in-memory computing macro unit chip core board to be tested includes: an in-memory computing macro unit chip to be tested, an FMC adapter, a DC power supply adapter, and a test LED and a switch; it is connected to the field editable gate array through the FMC adapter for data communication, and data communication is performed with the in-memory computing macro unit chip to be tested through the on-board in-memory computing macro unit chip slot to be tested, and power is supplied to the in-memory computing macro unit chip to be tested through the DC power supply adapter. The test LED and the switch are used to indicate the current system test running status and control the current system test.

[0014] Optionally, in one embodiment of the present invention, the power board includes: an AC-DC power supply interface, n DC-DC conversion circuits and a DC power supply adapter; the AC-DC power supply interface provides a DC voltage converted from the mains and serves as the input of the n DC-DC conversion circuits.

[0015] A second aspect of the present invention provides a test method for an in-memory computing macro unit chip, which is used in the test system for an in-memory computing macro unit chip described in the above embodiment. The test method includes the following steps:

[0016] S100, acquiring test data and storing it in an SD card, the test data including weight data and test input data;

[0017] S101, writing a program through the host computer SDK to control the programmable system of the field editable gate array to read the weight data and input data to be tested stored in the SD card, and encapsulate them into the top-level instructions of the in-memory computing macro unit chip to be tested and store them in the memory of the programmable logic circuit of the field editable gate array;

[0018] S102, after the programmable system of the field editable gate array waits for the start test mark, the top-level instructions of the in-memory computing macro unit chip to be tested in the programmable logic circuit memory of the field editable gate array are transmitted to the core board of the in-memory computing macro unit chip to be tested through the FMC communication adapter board cycle by cycle;

[0019] S103, the in-memory computing macro unit chip to be tested receives the top-level instruction to be tested, and performs weight update, calculation and readout functions based on the top-level instruction to be tested, and finally outputs the test data result to the FMC transfer interface;

[0020] S104, the test data results are transmitted to the FIFO in the programmable logic circuit of the field editable gate array through the FMC communication adapter board for storage;

[0021] S105, the programmable system of the field editable gate array reads the output result data stored in the FIFO and compares it with the expected calculation result of the calculation macro unit chip in the memory to be tested. After traversing all the data to be tested and the results are correct, it is determined whether the chip function meets the expectations and the test ends.

[0022] The test system and method for in-memory computing macro unit chips of the embodiments of the present invention enable testers to directly modify test data according to different test requirements, and directly modify the test instruction flow through the SDK to control the in-memory computing macro unit chip to be tested. The test results will also be automatically stored in the FIFO in the FPGA programmable logic circuit, which can be conveniently provided for testers to combine and call at any time and automatically compare with the expected results. The overall system and test method have the advantages of simple process, high degree of automation and low testing cost, which can effectively improve test efficiency and reduce manual testing costs, and solve the problem that chip verification of different in-memory computing macro units requires one-by-one adaptation and complex and difficult testing.

[0023] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0025] Figure 1 A schematic diagram of the structure of a test system for an in-memory computing macro unit chip provided according to an embodiment of the present invention;

[0026] Figure 2 A structural diagram of a core board of an in-memory computing macro unit chip to be tested according to an embodiment of the present invention;

[0027] Figure 3 A structural diagram of a power board provided according to an embodiment of the present invention;

[0028] Figure 4 The present invention is a flowchart of a testing method for an in-memory computing macro unit chip provided in accordance with an embodiment of the present invention.

[0029] Figure symbol: The letter n means that there are n DC-DC conversion circuits in total, outputting n different DC voltage values. DETAILED DESCRIPTION

[0030] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0031] The present invention proposes a test system for in-memory computing macro-unit chips, wherein a host computer is connected to debug and communicate data with a field programmable gate array (FPGA) through a joint test action group (JTAG), and the FPGA is debugged and connected with a core board carrying the in-memory computing macro-unit chip to be tested through an FPGA mezzanine card (FMC), and finally the test result is transmitted back to the host computer through a universal asynchronous receiver transmitter (UART) of the FPGA for data comparison, and it is judged whether the chip function meets expectations, and the whole system is powered by a power supply board carrying a power management circuit. Thus, the present invention realizes the test of the in-memory computing macro-unit chip, and the overall system has the advantages of simple structure, high degree of automation and low testing cost, so as to effectively improve the test efficiency, reduce the cost of manual testing, and meet the verification test requirements of different types of in-memory computing macro-unit chips.

[0032] Figure 1 A schematic diagram of a test system for an in-memory computing macro unit chip provided according to an embodiment of the present invention.

[0033] like Figure 1 As shown, the test system for the in-memory computing macro unit chip includes: a host computer, a field editable gate array, an FMC communication adapter board, a core board of the in-memory computing macro unit chip to be tested, and a power supply board.

[0034] In an embodiment of the present invention, the host computer is connected to the FPGA and the overall test system.

[0035] The field-programmable gate array consists of two parts: a programmable logic processing system (Processing System) and a programmable logic circuit (Progarmmable Logic).

[0036] Specifically, the host computer programs and controls the FPGA through the Software Development Kit (SDK), connects and debugs the FPGA through JTAG, and transmits the test data results of the in-memory computing macro unit chip to be tested to the host computer through the UART serial port on the FPGA board.

[0037] In an embodiment of the present invention, the FPGA programmable system and the programmable logic circuit are connected to the host computer and the core board of the in-memory computing macro unit chip to be tested, and are used to process the top-level instruction stream of the in-memory computing macro unit chip to be tested written by the host computer and control the in-memory computing macro unit chip to be tested.

[0038] The host computer includes a software development kit for FPGA and a universal asynchronous receiver-transmitter serial port debugging assistant. The host computer and FPGA are connected through a joint test working group, and the programmable system of FPGA is controlled and debugged through JTAG. The test results of the corresponding in-memory computing macro unit chip are transmitted back to the host computer through the UART of the programmable logic circuit in the FPGA for data comparison through the UART serial port debugging assistant.

[0039] The FMC communication adapter board connects the field editable gate array and the in-memory computing macro unit chip core board to be tested, and is responsible for the transmission of data and control signals during the test process.

[0040] The in-memory computing macro unit chip core board to be tested is connected to the FMC communication adapter board and the power supply board, receives or sends control and data signals during the test through the FMC communication adapter board, and supplies power to the in-memory computing macro unit chip core board to be tested through the power supply board.

[0041] The power board is connected to the core board of the in-memory computing macro unit chip to be tested, and converts the mains power into direct current through an AC-DC converter (AC-DC converter, AC-DC), and converts the fixed voltage output by the AC-to-DC adapter into the required voltage of the in-memory computing macro unit chip core board to be tested through a DC-to-DC converter (DC-DC converter, DC-DC) chip carried by the power board.

[0042] Preferably, in one embodiment of the present invention, the host computer is connected to the JTAG debugger and the UART serial port debugger via a USB interface. The field editable gate array includes an onboard FMC adapter, a UART serial port debugging interface and an SD card slot. The field editable gate array is connected to the in-memory computing macro unit chip core board to be tested via an FMC communication adapter board. The host computer reads the test results output by the in-memory computing macro unit chip core board to be tested via UART, and the SD card slot is used to store the test data and test results.

[0043] In an embodiment of the present invention, the FPGA programmable system and the programmable logic circuit are connected to the host computer and the core board of the in-memory computing macro unit chip to be tested, and are used to process the top-level instruction stream of the in-memory computing macro unit chip to be tested written by the host computer and control the in-memory computing macro unit chip to be tested.

[0044] Preferably, in one embodiment of the present invention, the programmable system of the field editable gate array includes an ARM A53 core and multiple peripherals, and the data to be tested is encapsulated as top-level instructions of the in-memory computing macro unit to be tested by writing a C code software program; the programmable logic of the field editable gate array includes multiple programmable configurable hardware circuits, and the programmable logic circuit is integrated into an interface handshake circuit between the programmable system and the in-memory computing macro unit chip to be tested by writing RTL code, which is used to realize the communication between the FPGA and the in-memory computing macro unit chip to be tested.

[0045] Preferably, in one embodiment of the present invention, the FMC communication adapter board uses an FMC adapter interface packaged in ASP-134486-01, and is connected to a field editable gate array and an in-memory computing macro unit chip core board to be tested.

[0046] In an embodiment of the present invention, the FMC communication adapter board includes two FMC interfaces, one male and one female, with a specific model of ASP-134486-01, which are electrically connected to the FPGA and the in-memory computing macro unit chip core board to be tested.

[0047] Figure 2 The structure diagram of the core board of the in-memory computing macro unit chip to be tested according to an embodiment of the present invention is as follows: Figure 2 As shown, on the basis of the above embodiments, as a preferred embodiment, the in-memory computing macro unit chip core board to be tested includes: an in-memory computing macro unit chip to be tested, an FMC adapter, a DC power supply adapter, a test LED and a switch; the in-memory computing macro unit chip to be tested is connected to the in-memory computing macro unit chip core board to be tested through the in-memory computing macro unit chip slot to be tested; the FMC adapter is connected to the in-memory computing macro unit chip slot to be tested through PCB routing; the DC power supply adapter receives various DC voltages transmitted from the power supply board and supplies power to the in-memory computing macro unit chip to be tested through the PCB routing; the test LED and the switch are used to indicate the operating status during the test or control the test process.

[0048] Figure 3 1 is a structural diagram of a power board according to an embodiment of the present invention. Figure 3 As shown, based on the above embodiments, as a preferred embodiment, the power board includes: an AC-DC power supply interface, n DC-DC conversion circuits and a DC power supply adapter; the AC-DC power supply interface provides a DC voltage converted from the mains, and serves as the input of the n-way DC-DC conversion circuit.

[0049] Furthermore, the AC-DC power supply interface is used to receive the DC voltage provided by the AC-DC converter to power the entire system; the n DC-DC conversion circuits convert the DC voltage input by the DC power supply interface into n different DC voltages required by the computing macro unit chip in the memory to be tested and output them through the DC power supply adapter.

[0050] Specifically, this embodiment provides 11 DC voltage outputs, including three fixed voltage outputs (0.9V, 1.8V and 3.3V) and eight adjustable voltage outputs (ranging from 0.1V to 1.2V) to meet the testing requirements of different in-memory computing macro unit chips.

[0051] Figure 4 The present invention is a schematic diagram of a test flow for an in-memory computing macro unit chip provided according to an embodiment of the present invention.

[0052] like Figure 4 As shown, the test method of the test system for the in-memory computing macro unit chip includes the following steps:

[0053] S100, acquiring test data and storing it in an SD card, the test data including weight data and test input data;

[0054] S101, write a program through the host computer SDK to control the FPGA programmable system to read out the weights and input data to be tested stored in the SD card and encapsulate them into the top-level instructions of the in-memory computing macro unit chip to be tested and store them in the memory of the FPGA programmable logic circuit;

[0055] S102, after the FPGA programmable system waits for the start test mark, it transmits the top-level instructions of the in-memory computing macro unit chip to be tested in the memory of the FPGA programmable logic circuit to the core board of the in-memory computing macro unit chip to be tested through the FMC communication adapter board cycle by cycle;

[0056] S103, the in-memory computing macro unit chip to be tested receives the top-level instruction to be tested, and performs weight update, calculation and readout functions based on the top-level instruction to be tested, and finally outputs the test data result to the FMC transfer interface;

[0057] S104, the test data results are transmitted to the FIFO in the FPGA programmable logic circuit through the FMC communication adapter board for storage;

[0058] S105, the FPGA programmable system reads the output result data stored in the FIFO and compares it with the expected calculation result of the calculation macro unit chip in the memory to be tested. After traversing all the data to be tested and the results are correct, it is determined whether the chip function meets the expectations and the test ends.

[0059] The present invention provides a test system and method for in-memory computing macro-unit chips. The software program is programmed through the host computer SDK, and the test data is encapsulated into top-level instructions and stored in the memory of the FPGA programmable logic system, thereby improving the processing efficiency of the test data. By controlling the programmable logic system to read out the top-level instructions of the in-memory computing macro-unit chip to be tested in the memory cycle by cycle, the weight update / calculation / readout control is performed on the in-memory computing macro-unit chip to be tested. By comparing the output of the in-memory computing macro-unit chip to be tested automatically stored in the FIFO in the programmable logic circuit with the expected result, it is determined whether the function of the in-memory computing macro-unit chip to be tested is correct. The overall system and test method of the present invention have the advantages of simple process, high degree of automation and low test cost, thereby effectively improving the test efficiency and reducing the cost of manual testing, solving the technical problems that the chip verification of different in-memory computing macro-units needs to be adapted one by one and the test is complex and difficult, and provides an efficient and reliable solution for the test of in-memory computing macro-unit chips.

[0060] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0061] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "N" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0062] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present invention belong.

Claims

1. A test system for in-memory computing macro unit chips, characterized in that: include: Host computer, field editable gate array, FMC communication adapter board, in-memory computing macro unit chip core board to be tested, and power supply board; The host computer includes a software development kit and a UART serial port debugging assistant for a field editable gate array, the host computer is connected to the field editable gate array through JTAG, the programmable system of the field editable gate array is controlled and debugged through a joint test working group, and the test result of the corresponding in-memory computing macro unit chip is transmitted back to the host computer through the UART of the programmable logic circuit in the field editable gate array, so as to perform data comparison through the universal asynchronous receiver and transmitter serial port debugging assistant; The FMC communication adapter board connects the field editable gate array and the in-memory computing macro unit chip core board to be tested, and is responsible for the transmission of data and control signals during the test process; The in-memory computing macro unit chip core board to be tested is connected to the FMC communication adapter board and the power supply board, and the control and data signals in the test process are received or sent through the FMC communication adapter board, and the in-memory computing macro unit chip core board to be tested is powered by the power supply board; The power board is connected to the in-memory computing macro unit chip core board to be tested, converts the mains power into direct current through an AC-DC converter, and converts the fixed voltage output by the AC-DC adapter into the required voltage of the in-memory computing macro unit chip core board to be tested through the DC-DC converter chip carried by the power board.

2. The system according to claim 1, characterized in that The host computer is connected to a JTAG debugger and a UART serial port debugger via a USB interface, wherein the field editable gate array includes an onboard FMC adapter, a UART serial port debugging interface and an SD card slot, and the field editable gate array is connected to the in-memory computing macro unit chip core board to be tested via the FMC communication adapter board, and the host computer reads the test results output by the in-memory computing macro unit chip core board to be tested via UART, and the SD card slot is used to store the data to be tested and the test results.

3. The system according to claim 1, characterized in that The programmable system of the field editable gate array includes an ARM A53 core and multiple peripherals. The data to be tested is encapsulated as the top-level instructions of the in-memory computing macro unit to be tested by writing a C code software program; the programmable logic of the field editable gate array includes multiple programmable configurable hardware circuits. The programmable logic circuit is integrated into an interface handshake circuit between the programmable system and the in-memory computing macro unit chip to be tested by writing an RTL code, which is used to realize the communication between the FPGA and the in-memory computing macro unit chip to be tested.

4. The system according to claim 1, characterized in that The FMC communication adapter board adopts the FMC adapter interface packaged in ASP-134486-01, and is connected to the field editable gate array and the in-memory computing macro unit chip core board to be tested.

5. The system according to claim 1, characterized in that The in-memory computing macro unit chip core board to be tested includes: an in-memory computing macro unit chip to be tested, an FMC adapter, a DC power supply adapter, and a test LED and a switch; it is connected to the field editable gate array through the FMC adapter for data communication, and is used to communicate data with the in-memory computing macro unit chip to be tested through the on-board in-memory computing macro unit chip slot to be tested, and the in-memory computing macro unit chip to be tested is powered through the DC power supply adapter. The test LED and the switch are used to indicate the current system test running status and control the current system test.

6. The system according to claim 1, characterized in that The power board includes: an AC-DC power interface, n DC-DC conversion circuits and a DC power supply adapter; the AC-DC power interface provides a DC voltage converted from the mains and serves as an input for the n DC-DC conversion circuits.

7. A test method for an in-memory computing macro unit chip, used in a test system for an in-memory computing macro unit chip as claimed in any one of claims 1 to 6, characterized in that: The test method includes the following steps: S100, acquiring test data and storing it in an SD card, the test data including weight data and test input data; S101, writing a program through the host computer SDK to control the programmable system of the field editable gate array to read the weight data and input data to be tested stored in the SD card, and encapsulate them into the top-level instructions of the in-memory computing macro unit chip to be tested and store them in the memory of the programmable logic circuit of the field editable gate array; S102, after the programmable system of the field editable gate array waits for the start test mark, the top-level instructions of the in-memory computing macro unit chip to be tested in the programmable logic circuit memory of the field editable gate array are transmitted to the core board of the in-memory computing macro unit chip to be tested through the FMC communication adapter board cycle by cycle; S103, the in-memory computing macro unit chip to be tested receives the top-level instruction to be tested, and performs weight update, calculation and readout functions based on the top-level instruction to be tested, and finally outputs the test data result to the FMC transfer interface; S104, the test data results are transmitted to the FIFO in the programmable logic circuit of the field editable gate array through the FMC communication adapter board for storage; S105, the programmable system of the field editable gate array reads the output result data stored in the FIFO and compares it with the expected calculation result of the calculation macro unit chip in the memory to be tested. After traversing all the data to be tested and the results are correct, it is determined whether the chip function meets the expectations and the test ends.

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