Testing method of distance measuring chip and computer readable storage medium
By configuring preset histograms and comparative test histograms, the problem of insufficient testing dimensions of the existing ranging chip test methods is solved, and multi-dimensional testing and functional verification of the ranging chip are realized, improving the yield and shipment quality of the chip.
Patent Information
- Application Number
- CN202411906554.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-03-28
AI Technical Summary
The existing ranging chip testing methods have too few test dimensions, so they cannot fully test the chip functional points, resulting in higher chip usage costs.
By configuring the preset histogram to configure the test function to register, each ranging chip is activated for ranging, a test histogram is generated, and the test histogram is compared with the MCU and the preset histogram to obtain the test results.
Multi-dimensional testing of the ranging chip is realized to ensure the normal operation of the chip functional points and improve the chip yield and shipment quality.
Smart Images
Figure CN119716482A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of distance measurement technology, and in particular to a testing method for a distance measurement chip and a computer-readable storage medium. Background Art
[0002] In the field of integrated circuits, with the development of technology and processes, the density and complexity of integrated circuits are also growing exponentially. Circuits must be fully verified and tested during the design phase. Wafer manufacturing uses more microscopic printing and etching technology, and defects and process deviations are unavoidable in the process, which will cause changes in circuit parameters, affect performance, and even cause the entire system to crash.
[0003] Wafer cutting, wire bonding, plastic sealing and other processes in the packaging process cannot guarantee a 100% yield rate. This requires that the chip needs to be tested before it leaves the factory to prevent defective chips from flowing out and improve the quality of shipment. The existing method of testing the histogram of the ranging chip has the problem of too few test dimensions and cannot fully test the functional points of the chip, which will increase the cost of using the chip. Summary of the invention
[0004] In view of this, the present invention provides a testing method of a ranging chip and a computer-readable storage medium.
[0005] The present application provides a method for testing a ranging chip, the method being applied to a chip ranging system, the chip ranging system comprising a plurality of ranging chips, the ranging chip comprising a SPAD array, an MCU, a TDC module, a register and an SRAM, the method comprising: configuring a test function to the register, configuring a preset histogram to the register according to the test function; starting each ranging chip to perform ranging and generating a test histogram; according to the test function, the MCU comparing the test histogram with the preset histogram to obtain a test result of the test function.
[0006] Furthermore, configuring the test function to the register includes: configuring at least one of the following test functions to the register: TDC upper and lower limit threshold function, histogram overflow protection function, peak detection function, SPAD switch selection function, nonlinear bin function, histogram bin data judgment function, histogram ID function, and a mapping relationship between a histogram and SRAM.
[0007] In some embodiments, configuring a preset histogram to a register according to the test function includes: configuring one of the following preset histograms to a register according to the test function: a V-type histogram, an M-type histogram, a type I histogram, or an I-type histogram.
[0008] Further, configuring a preset histogram to a register according to the test function includes: when the test function is configured as a nonlinear bin function, configuring a type one histogram to the register.
[0009] Further, configuring a preset histogram to a register according to the test function includes: when the test function is configured as a histogram ID function and / or a mapping relationship between a histogram and an SRAM, configuring an I-type histogram to a register.
[0010] Further, configuring a preset histogram to a register according to the test function includes: when the test function is configured as a SPAD switch selection function and / or a histogram bin data judgment function, configuring a type I histogram or a type I histogram to the register.
[0011] Further, configuring a preset histogram to a register according to the test function includes: when the test function is configured as a TDC upper and lower threshold function, configuring a V-type histogram, an M-type histogram, or a type I histogram to a register.
[0012] Further, configuring a preset histogram to a register according to the test function includes: when the test function is configured as an overflow protection function, configuring an M-type histogram, a I-type histogram, or an I-type histogram to a register.
[0013] Furthermore, the method further comprises: searching the test histogram in the SRAM, and when the test histogram is normally output to the SRAM, a test result indicating that the storage function of the SRAM is normal is obtained.
[0014] The present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores an executable program, and when the executable program is executed by a processor, the test method as described in any one of the above items is implemented.
[0015] The testing method of the ranging chip provided in the present application tests whether different functional points of the ranging chip are working normally by configuring a preset histogram, thereby meeting the requirements of multi-dimensional testing of the ranging chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 A schematic diagram of a test method according to an embodiment of the present invention;
[0017] Figure 2 A schematic diagram of a V-shaped histogram provided in an embodiment of the present application and a comparison with a test histogram;
[0018] Figure 3 A schematic diagram of the M-type histogram provided in the embodiment of the present application and its comparison with the test histogram;
[0019] Figure 4A schematic diagram of a type of histogram provided in an embodiment of the present application and a comparison with a test histogram;
[0020] Figure 5 A schematic diagram of a type I histogram provided in an embodiment of the present application and its comparison with a test histogram. DETAILED DESCRIPTION
[0021] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.
[0022] In the ranging chip, the histogram is an important way to complete the ranging. The ranging principle of DToF (direct time of flight) is as follows: the transmitting end emits a light beam to the ranging area. The transmitted light beam reaches the target object and is reflected by the target object to form a reflected light beam. Part of the photon signal of the reflected light beam is received by the receiving end, and each single photon in the photon signal is incident on the SPAD array (avalanche photodiode) to generate an avalanche signal. Then the SAPD outputs the avalanche signal to the TDC (time-to-digital converter). The TDC then detects the time interval from the transmitting end to the avalanche. The histogram counting statistics of each photon are performed according to the time interval of each photon. The statistical histogram finally formed can determine the time corresponding to the peak value (the highest frequency of occurrence), and then determine the time T required for the light beam to be emitted by the transmitting end and received by the receiving end according to the time corresponding to the peak value. The histogram includes multiple histogram bars, each of which corresponds to the distance of a different SPAD array. The histogram ordinate Counts represents the bin depth, such as the number of detected photons, which is time information and specifically represents the number of bins.
[0023] The present application provides a method for testing a ranging chip, which is applied to a chip ranging system. The chip ranging system includes a plurality of ranging chips, and the ranging chip includes a SPAD array, an MCU (microcontroller unit), a TDC module, a register and an SRAM (static random-access memory). Figure 1 See the flow chart of the test method provided in the embodiment of the present application. Figure 1 , the method comprising:
[0024] Step S100: configuring a test function to the register, and configuring a preset histogram to the register according to the test function. In an embodiment of the present application, configuring a test function to the register includes: configuring at least one of the following test functions to the register: TDC upper and lower limit threshold function, histogram overflow protection function, peak detection function, SPAD switch gating function, nonlinear bin function, histogram bin data judgment function, histogram ID function, and a mapping relationship between a histogram and SRAM.
[0025] Here, the TDC upper and lower threshold functions are: filter out unnecessary TDC data to ensure that the histogram stores valid TDC data. The histogram overflow protection function is: prevent the value of the statistical histogram from exceeding the SRAM bit width and causing data overflow. The peak detection function is: generate a fixed peak histogram through test data to detect whether the subsequent peak algorithm is correct. The SPAD switch selection function is: multiple SPAD signals will converge together and share the same TDC channel. This function can selectively turn on different SPAD signals in the same channel. The nonlinear bin function is: the SRAM depth is fixed, so to achieve a longer ranging distance, you can count photon data at multiple different time intervals into the same TDC. The histogram bin data judgment function is: test data to test whether the data of the statistical histogram is correct. The histogram ID function is: test whether the mapping relationship between the histogram ID and the corresponding histogram is correct. The mapping relationship between the histogram and SRAM refers to the mapping relationship between TDC data and SRAM.
[0026] In an embodiment of the present application, configuring a preset histogram to a register according to the test function includes: configuring one of the following preset histograms to a register according to the test function: a V-type histogram, an M-type histogram, a type I histogram, or an I-type histogram.
[0027] Here, configuring a preset histogram to a register according to the test function includes: when the test function is configured as a nonlinear bin function, configuring a type one histogram to the register.
[0028] When the test function is configured as a histogram ID function and / or a mapping relationship between a histogram and an SRAM, a type I histogram is configured to the register.
[0029] When the test function is configured as a SPAD switch selection function and / or a histogram bin data judgment function, a type I histogram or a type I histogram is configured to the register.
[0030] When the test function is configured as the TDC upper and lower limit threshold function, a V-type histogram, an M-type histogram, or a type I histogram is configured in the register.
[0031] When the test function is configured as an overflow protection function, an M-type histogram, a I-type histogram, or an I-type histogram is configured in the register.
[0032] Step S200: start each ranging chip to perform ranging and generate a test histogram.
[0033] Step S300: According to the test function, the MCU compares the test histogram with the preset histogram to obtain a test result of the test function.
[0034] In the embodiment of the present application, the test function is tested according to the preset histogram corresponding to the test function configuration, and after the test result is output, the test function is changed and steps S100 to S300 are repeated until all required function tests are completed.
[0035] In some embodiments, the method further includes step S400: searching the test histogram in the SRAM, and when the test histogram is normally output to the SRAM, a test result indicating that the SRAM storage function is normal is obtained. Here, when testing the SRAM storage function, any preset histogram can be configured, and when the test histogram is normally output to the SRAM, it indicates that the SRAM storage function is normal.
[0036] In the embodiment of the present application, the MCU reads the test histogram, and compares the test histogram with the preset histogram, and obtains the test result of the test function according to the comparison. Figure 2 The V-shaped histogram provided in the embodiment of the present application and the comparison diagram with the test histogram are shown in FIG. Figure 2 , the upper limit values of all bins of the V-shaped histogram are connected to form a "V"-shaped pattern. By checking the beginning and end of the V-shaped histogram, it can be confirmed whether the TDC upper and lower limit threshold functions are normal. The histogram overflow protection function is tested by whether the peak value output by the V-shaped histogram exceeds the overflow upper limit. In some embodiments, the test histogram and the V-shaped histogram can also be compared to perform a peak detection function to test whether the algorithm module can detect edge peaks.
[0037] Figure 3 The M-type histogram provided in the embodiment of the present application and the comparison diagram with the test histogram are shown in FIG. Figure 3 , the upper limits of all bins of the M-type histogram are connected to form an "M"-shaped pattern. By checking the beginning and end of the pattern, you can confirm whether the TDC upper and lower threshold functions are normal. The histogram overflow protection function is tested by the peak value output by the M-type histogram. The pattern can also perform peak shape detection to test whether the algorithm module can detect multiple peaks.
[0038] Figure 4 A schematic diagram of a type of histogram provided in an embodiment of the present application and a comparison with a test histogram, see Figure 4 , the upper limits of all bins of a type one histogram are connected to form a "one" type pattern. By checking the beginning and end of the pattern, you can confirm whether the TDC upper and lower threshold functions are normal. The peak value of the pattern output is used to test whether the different SPAD switch gating functions, nonlinear bin functions, and histogram bin data in each group of pixels are normal. The pattern can also perform peak detection to test whether the algorithm module can detect no peaks.
[0039] Figure 5 The schematic diagram of the comparison between the type I histogram provided in the embodiment of the present application and the test histogram is shown in FIG. Figure 5 , the bin corresponding to the I-type histogram number forms an "I" pattern, and there is no value in other bins. The mapping relationship between the histogram and SRAM can be confirmed by checking whether the pattern can be output normally. Figure 5 The red dotted line in the middle is the peak value. The peak value of the pattern output is used to test whether the SPAD switch gating function, histogram overflow protection function and histogram bin data in each group of pixels are normal; by checking whether the pattern appears in the corresponding bin of the histogram, the histogram ID function is judged to be normal. The pattern can also be used for peak detection to test whether the algorithm module can detect a single peak.
[0040] The embodiment of the present application provides four preset histograms for testing different functional points of the histogram during the chip testing process; through register configuration, the data source of the histogram is switched to the preset histogram determined internally, and then the normal chip ranging process is performed, and then the test histogram is read through the MCU, and the test histogram is compared with the preset histogram to determine whether different functional points are normal. Specifically, the SPAD switch gating function, TDC data upper and lower limit threshold function, nonlinear bin function, SRAM storage function, histogram ID function, histogram and SRAM mapping relationship, histogram overflow protection function, and histogram bin data judgment function in each group of pixels can be tested. The peak detection of the algorithm module can also be tested, including whether it can detect multiple situations such as no peak, edge peak, single peak, and multiple peaks. The test method of the ranging chip provided in the embodiment of the present application includes a multi-dimensional test function, which can comprehensively test whether each function of the ranging chip is normal and improve the yield of the ranging chip.
[0041] An embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores an executable program, and when the executable program is executed by a processor, the following steps are implemented: configuring a test function to the register, and configuring a preset histogram to the register according to the test function; starting each ranging chip to perform ranging and generating a test histogram; according to the test function, the MCU compares the test histogram with the preset histogram to obtain a test result of the test function.
[0042] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: configuring at least one of the following test functions to the register: TDC upper and lower limit threshold function, histogram overflow protection function, peak detection function, SPAD switch gating function, nonlinear bin function, histogram bin data judgment function, histogram ID function, and a mapping relationship between a histogram and SRAM.
[0043] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: according to the test function, one of the following preset histograms is configured to the register: V-type histogram, M-type histogram, type I histogram, and type I histogram.
[0044] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: when the test function is configured as a non-linear bin function, configuring a type one histogram to the register.
[0045] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the test function is configured as a histogram ID function and / or a mapping relationship between a histogram and an SRAM, a type I histogram is configured to a register.
[0046] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the test function is configured as a SPAD switch selection function and / or a histogram bin data judgment function, a type I histogram or a type I histogram is configured to the register.
[0047] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the test function is configured as the TDC upper and lower limit threshold function, a V-type histogram, an M-type histogram, or a type I histogram is configured in the register.
[0048] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: when the test function is configured as an overflow protection function, an M-type histogram, a I-type histogram, or an I-type histogram is configured to the register.
[0049] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: searching the test histogram in the SRAM, and when the test histogram is normally output to the SRAM, a test result indicating that the SRAM storage function is normal is obtained.
[0050] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0051] The above description is only the preferred embodiment of the present invention and is not intended to limit the present invention. Any technician familiar with the profession may make various changes, modifications, substitutions and variations to these embodiments without departing from the principle and purpose of the present invention. The scope of the present invention is defined by the claims and their equivalents.
Claims
1. A method for testing a ranging chip, characterized in that: The method is applied to a chip ranging system, the chip ranging system includes a plurality of ranging chips, the ranging chip includes a SPAD array, an MCU, a TDC module, a register and an SRAM, and the method includes: configuring a test function to the register, and configuring a preset histogram to the register according to the test function; Start each ranging chip to measure the distance and generate a test histogram; According to the test function, the MCU compares the test histogram with the preset histogram to obtain the test result of the test function.
2. The method according to claim 1, characterized in that The configuring a test function to the register comprises: The register is configured with at least one of the following test functions: TDC upper and lower threshold functions, histogram overflow protection function, peak detection function, SPAD switch gating function, nonlinear bin function, histogram bin data judgment function, histogram ID function, and a mapping relationship between a histogram and SRAM.
3. The method according to claim 2, characterized in that Configuring a preset histogram to a register according to the test function includes: Configure one of the following preset histograms to the register according to the test function: V-type histogram, M-type histogram, I-type histogram, I-type histogram.
4. The method according to claim 3, characterized in that Configuring a preset histogram to a register according to the test function includes: When the test function is configured as a non-linear bin function, a type histogram is configured to the register.
5. The method according to claim 3, characterized in that: Configuring a preset histogram to a register according to the test function includes: When the test function is configured as a histogram ID function and / or a mapping relationship between a histogram and an SRAM, a type I histogram is configured to the register.
6. The method according to claim 3, characterized in that Configuring a preset histogram to a register according to the test function includes: When the test function is configured as a SPAD switch selection function and / or a histogram bin data judgment function, a type I histogram or a type I histogram is configured to the register.
7. The method according to claim 3, characterized in that Configuring a preset histogram to a register according to the test function includes: When the test function is configured as the TDC upper and lower limit threshold function, a V-type histogram, an M-type histogram, or a type I histogram is configured in the register.
8. The method according to claim 3, characterized in that Configuring a preset histogram to a register according to the test function includes: When the test function is configured as an overflow protection function, an M-type histogram, a I-type histogram, or an I-type histogram is configured in the register.
9. The method according to any one of claims 1 to 8, characterized in that: The method further comprises: searching the test histogram in the SRAM, When the test histogram is normally output to the SRAM, a test result indicating that the storage function of the SRAM is normal is obtained.
10. A computer-readable storage medium storing an executable program, characterized in that: When the executable program is executed by a processor, the method for testing the ranging chip according to any one of claims 1 to 8 is implemented.