Grinding and polishing sample of chip

Abstract

The invention discloses a grinding and polishing sample of a chip. The grinding and polishing sample comprises a to-be-ground chip; the chip to be ground comprises a front surface and a back surface which are opposite, and a side surface vertical to the front surface; a chip placement part; a to-be-ground chip is positioned in the chip placing part; an extension portion; the extension part at least covers the side edge of the chip placing part; wherein the front surface of the chip to be ground is flush with the lower edge of the extension part; the vertical distance between the side face of the chip to be ground and the side edge of the chip containing part is smaller than or equal to 0.5 mm. According to the technical scheme, the fringe effect generated in the delamination grinding and polishing process of the single chip can be relieved, and the integrity of each layer of circuit after delamination grinding and polishing of the chip is guaranteed.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor failure analysis, and in particular to a grinding and polishing sample of a chip. Background Art

[0002] The chip is composed of multiple layers of metal wires, dielectric layers and through-holes, where each layer of metal wires is isolated by dielectric layers and connected by through-holes. When the chip fails or the internal circuit structure is analyzed, the chip needs to be polished and de-layered to find the specific failure point. Therefore, the quality of polishing will directly affect whether the chip can be accurately analyzed.

[0003] When polishing and de-laminating a chip, manual polishing is the most common method for precise de-lamination of the chip. Manual polishing is usually performed on a polishing pad with an appropriate amount of polishing fluid. However, the edge effect during manual polishing is an issue that requires special attention. The edge effect refers to the problem of uneven surface roughness and thickness after polishing due to uneven force on the material at the edge of the chip and the material in the internal area of ​​the chip during the polishing process. This will seriously affect the integrity of each layer of the chip circuit during the de-lamination process, resulting in excessive wear and loss of the circuit at the edge of the chip. Summary of the invention

[0004] The present invention provides a chip polishing sample to solve the problems existing in the prior art, alleviate the edge effect generated during the de-lamination and polishing process of a single chip, and ensure the integrity of each layer of circuits after the chip is de-lamination and polished.

[0005] In a first aspect, the present invention provides a polishing sample of a chip, comprising:

[0006] The chip to be ground includes a front side and a back side opposite to each other, and a side surface perpendicular to the front side;

[0007] A chip placement portion; the chip to be ground is located in the chip placement portion;

[0008] An extension portion; the extension portion at least covers the side edge of the chip placement portion;

[0009] The front side of the chip to be ground is flush with the lower edge of the extension portion; the vertical distance D1 between the side of the chip to be ground and the side edge of the chip placement portion has a value range of: D1≤0.5mm.

[0010] Optionally, the extension portion is made of epoxy resin.

[0011] Optionally, the extension portion is cylindrical.

[0012] Optionally, the extension portion is made of metal or metal alloy.

[0013] Optionally, the chip placement portion includes a chip limiting device; the chip limiting device is located on the back side of the chip to be ground.

[0014] Optionally, the chip limiting device includes a counterweight pressing block and a counterweight limiting unit; the counterweight limiting unit is connected to the counterweight pressing block, and the counterweight limiting unit is located on a side of the counterweight pressing block away from the chip to be ground.

[0015] Optionally, the extension portion includes an upper edge opposite to the lower edge; the counterweight limiting unit includes a fixing plate and a spring;

[0016] The fixing plate is fixed to the upper edge of the extension portion; the fixing plate, the spring and the counterweight pressing block are connected in sequence.

[0017] Optionally, the extension portion includes an upper edge opposite to the lower edge; the chip placement portion passes through the extension portion;

[0018] The counterweight limiting unit includes a limiting plate; the limiting plate is located above the upper edge, and the length of the limiting plate is greater than the length of the chip placement portion.

[0019] Optionally, the chip placement portion passes through the extension portion; and at least a portion of the inner edge of the extension portion is provided with a first thread;

[0020] The counterweight limiting unit includes a limiting rod; the limiting rod includes a second thread matched with the first thread.

[0021] Optionally, a vertical distance D2 between an outer edge of the extension portion and a side surface of the chip placement portion has a value range of: D2 ≥ 2 cm.

[0022] Optionally, a value range of the height H of the extension portion is: H ≥ 2 cm.

[0023] The technical solution of the present invention is to make the extended part of the chip grinding and polishing sample at least partially cover the chip placing part, the chip to be ground is located in the chip placing part, and the front side of the chip to be ground is flush with the lower edge of the extended part, and the vertical distance between the side of the chip to be ground and the side edge of the chip placing part is less than or equal to 0.5mm, so that when the chip grinding and polishing sample is subjected to de-layering and grinding and polishing treatment, the edge of the chip to be ground is extended to the edge of the chip grinding and polishing sample, thereby transferring the edge effect of the chip to be ground to the edge of the extended part. In this way, the edge effect generated at the edge of the chip to be ground can be greatly alleviated, which is beneficial to improving the integrity of the chip circuit after the chip to be ground is subjected to de-layering and grinding and polishing treatment.

[0024] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A schematic diagram of the force of a chip de-layering and polishing process in the prior art;

[0027] Figure 2 A schematic diagram of the morphology of a chip after de-layering and polishing in the prior art;

[0028] Figure 3 A schematic structural diagram of a chip grinding and polishing sample provided by an embodiment of the present invention;

[0029] Figure 4 A schematic structural diagram of another chip grinding and polishing sample provided by an embodiment of the present invention;

[0030] Figure 5 A schematic structural diagram of a grinding and polishing sample of another chip provided by an embodiment of the present invention;

[0031] Figure 6 A schematic structural diagram of a grinding and polishing sample of another chip provided by an embodiment of the present invention;

[0032] Figure 7 A schematic structural diagram of a grinding and polishing sample of another chip provided by an embodiment of the present invention;

[0033] Figure 8 A schematic structural diagram of a grinding and polishing sample of another chip provided by an embodiment of the present invention;

[0034] Fig. 9 A schematic structural diagram of a polished sample of another chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein.

[0037] Figure 1 It is a schematic diagram of the force of a chip de-layering and polishing process in the prior art. Figure 2 This is a schematic diagram of the morphology of a chip after delamination and polishing in the prior art. Figure 1 and Figure 2 It can be seen that during the de-lamination and polishing process of chip 01, under the action of the downward pressure F, chip 01 will slightly sink into the hair 021 of the polishing pad 02. Due to the presence of grinding liquid 03 in the hair 021, in the middle part A of chip 01, only the lower surface of chip 01 (i.e., the front of chip 01) is subject to the friction of the grinding liquid 03 on the hair 021, while in the edge area B of chip 01, in addition to the lower surface of chip 01 being subject to the friction of the grinding liquid 03 on the hair 021, some areas on the side of chip 01 are also subject to the friction of the grinding liquid 03 on the hair 021, which makes the grinding rate of the edge of chip 01 higher, resulting in a serious edge effect of chip 01 after de-lamination and polishing, causing the circuit structure of the chip to be lost.

[0038] In order to solve the above technical problems, the embodiment of the present invention makes the extended part of the chip grinding and polishing sample at least partially cover the chip placing part, the chip to be ground is located in the chip placing part, and the front side of the chip to be ground is flush with the lower edge of the extension part, and the vertical distance between the side of the chip to be ground and the side edge of the chip placing part is less than or equal to 0.5mm, so that when the chip grinding and polishing sample is subjected to de-layering and polishing treatment, the edge of the chip to be ground is extended to the edge of the chip grinding and polishing sample, thereby transferring the edge effect of the chip to be ground to the edge of the extension part. In this way, the edge effect generated at the edge of the chip to be ground can be greatly alleviated, which is beneficial to improving the integrity of the chip circuit after the de-layering and polishing treatment.

[0039] The above is the core idea of ​​the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0040] Figure 3 Schematic diagram of the structure of a chip polishing sample provided by an embodiment of the present invention. It should be noted that in this embodiment, Figure 3 As shown, the direction in which the back side of the chip to be ground points to the front side is upward, and the direction in which the front side of the chip to be ground points to the back side is downward.

[0041] This embodiment provides a chip grinding and polishing sample, referring to Figure 3 As shown, the chip grinding and polishing sample includes: a chip to be ground 1, a chip placement portion 2 and an extension portion 3; the chip to be ground 1 includes a front side and a back side relative to each other, and a side surface perpendicular to the front side; the chip to be ground 1 is located in the chip placement portion 2; the extension portion 3 at least covers the side edge of the chip placement portion 2; wherein the front side of the chip to be ground 1 is flush with the lower edge of the extension portion 3; the vertical distance D1 between the side surface of the chip to be ground 1 and the side edge of the chip placement portion 2 has a value range of: D1≤0.5mm.

[0042] The chip to be ground 1 is a chip whose internal circuit needs to be analyzed. The front side of the chip to be ground 1 refers to the side surface with a metal pattern in the chip to be ground 1. The lower edge of the extension part 3 is the edge below the extension part 3.

[0043] The extension portion 3 at least covers the side edge of the chip placement portion 2, which can be understood as the extension portion 3 covering the side edge of the chip placement portion 2, or the extension portion 3 covering the side edge and the upper edge of the chip placement portion 2. The front face of the chip to be ground 1 is flush with the lower edge of the extension portion 3, which can be understood as the front face of the chip to be ground 1 and the lower edge of the extension portion 3 are located in the same plane.

[0044] The chip to be ground 1 is located in the chip placement part 2, the side edge of the chip placement part 2 is parallel to the side of the chip to be ground 1, and the vertical distance between the side of the chip to be ground 1 and the side edge of the chip placement part 2 is the gap between the side of the chip to be ground 1 and the side edge of the chip placement part 2. It can be understood that the smaller the gap between the side of the chip to be ground 1 and the side edge of the chip placement part 2, the less likely the side of the chip to be ground 1 is to be subjected to the friction of the grinding and polishing pad. When the vertical distance between the side of the chip to be ground 1 and the side edge of the chip placement part 2 is greater than 0.5 mm, the side of the chip to be ground 1 is subjected to the friction of the grinding and polishing pad because the vertical distance between the side of the chip to be ground 1 and the side edge of the chip placement part 2 is too large, thereby failing to achieve the purpose of alleviating the edge effect generated at the edge of the chip to be ground 1.

[0045] By making the front side of the chip 1 to be ground flush with the lower edge of the extension portion 3, and the vertical distance between the side of the chip 1 to be ground and the side edge of the chip placement portion 2 is less than or equal to 0.5 mm, the gap between the side of the chip 1 to be ground and the side edge of the chip placement portion 2 is small enough, so that the lower edge of the extension portion 3 becomes the extended surface of the front side of the chip to be ground 1, so that when the chip grinding and polishing sample is de-layered, the side surface of the chip to be ground will not be subject to the friction of the fluff of the grinding and polishing pad.

[0046] In the present embodiment, by making the extended portion of the chip polishing sample at least partially cover the chip placing portion, the chip to be polished is located in the chip placing portion, and the front side of the chip to be polished is flush with the lower edge of the extended portion, and the vertical distance between the side of the chip to be polished and the side edge of the chip placing portion is less than or equal to 0.5 mm, so that when the chip polishing sample is subjected to de-layering and polishing treatment, the edge of the chip to be polished is extended to the edge of the chip polishing sample, thereby transferring the edge effect of the chip to be polished to the edge of the extended portion. In this way, the edge effect generated at the edge of the chip to be polished can be greatly alleviated, which is beneficial to improving the integrity of the chip circuit after the de-layering and polishing treatment.

[0047] It should be noted that the present embodiment does not specifically limit the material of the extension portion 3. It can be achieved that when the front side of the chip 1 to be ground is flush with the lower edge of the extension portion 3, the lower edge of the extension portion 3 becomes the extension surface of the front side of the chip 1 to be ground. Thus, when the chip 1 to be ground is de-layered and polished, the purpose of alleviating the edge effect of the chip 1 to be ground can be achieved.

[0048] Optionally, the extension portion 3 is made of epoxy resin.

[0049] Epoxy resin is a thermosetting resin that can cure quickly at a certain temperature and has a low shrinkage rate. Using epoxy resin to prepare the extension portion 3 can simplify the production process and production cost of the chip grinding and polishing sample.

[0050] In this embodiment, the chip to be ground 1 is coated with epoxy resin, wherein the front surface of the chip to be ground 1 is flush with the lower edge of the epoxy resin, and a chip grinding and polishing sample is prepared. Exemplarily, the specific preparation process of the chip grinding and polishing sample is as follows: first, the chip to be ground 1 is cleaned with an organic solvent and deionized water, and then the chip to be ground 1 is inverted on a smooth carrier, such as a glass slide, a wafer or a ceramic sheet, and then an open container is surrounded around the chip to be ground 1, and finally epoxy resin is poured into the open container. After the epoxy resin solidifies, the epoxy resin is demolded from the open container to obtain a chip grinding and polishing sample.

[0051] In an optional embodiment, the extension portion 3 can also be prepared by hot melt adhesive. Hot melt adhesive is a plastic adhesive that is solid at room temperature, and when heated and melted to a certain temperature, it becomes a flowable liquid with a certain viscosity. Therefore, using hot melt adhesive to prepare the extension portion 3 can also achieve the purpose of simplifying the production process and production cost of the chip polishing sample.

[0052] Optionally, when the extension portion 3 is made of epoxy resin, the extension portion 3 may be cylindrical, that is, the open container is a circular open container, so that the epoxy resin is easy to be removed from the open container, which is beneficial to further simplify the production process of the polishing sample of the chip.

[0053] In an exemplary embodiment, when the epoxy resin is poured into the open container, a release agent may be added to make it easier to peel the epoxy resin from the open container.

[0054] Figure 4 A schematic diagram of the structure of another chip polishing sample provided by an embodiment of the present invention, referring to Figure 4 As shown, in this embodiment, the polishing sample of the chip prepared by epoxy resin is used, and the chip 1 to be polished can completely fill the chip placement portion, and the front side of the chip 1 to be polished is flush with the lower edge of the extension portion 3, so that the edge effect of the chip 1 to be polished during the de-layering and polishing process can be completely transferred to the edge of the extension portion 3, thereby further alleviating the edge effect of the chip 1 to be polished and achieving the integrity of the circuit after de-layering and polishing.

[0055] However, after the de-lamination grinding and polishing, the extension portion 3 made of epoxy resin will also be consumed as the chip 1 to be ground is ground, resulting in that the extension portion 3 of the ground and polished sample of the chip cannot be recycled.

[0056] Optionally, the extension portion 3 is made of metal or metal alloy, so that the extension portion 3 will not be consumed during the grinding of the chip 1 to be ground, and can be recycled.

[0057] In an optional embodiment, the extension portion 3 can be made of, but is not limited to, copper, aluminum alloy, stainless steel or other materials.

[0058] Optional, Figure 5 A schematic diagram of a structure of a polished sample of another chip provided in an embodiment of the present invention, referring to Figure 5 As shown, the chip placement portion 2 includes a chip limiting device 21; the chip limiting device 21 is located on the back side of the chip 1 to be ground.

[0059] The chip limiting device 21 is used to limit the position of the chip 1 to be ground, so as to ensure that the front of the chip 1 to be ground is flush with the lower edge of the extension portion 3 when the chip 1 to be ground is subjected to de-layering and polishing.

[0060] In this embodiment, the chip to be ground 1 is located in the chip placement portion 2, and the vertical distance between the side of the chip to be ground 1 and the side edge of the chip placement portion 2 is less than or equal to 0.5 mm, and the chip limiting device 21 is located on the back of the chip to be ground 1, and the extension portion 3 covers the side edge of the chip placement portion 2, so that when the chip to be ground 1 is subjected to de-layering and polishing, the front side of the chip to be ground 1 is flush with the lower edge of the extension portion 3, so that when the chip to be ground is subjected to de-layering and polishing, the edge of the chip to be ground 1 can be extended to the edge of the chip polishing sample when the chip polishing sample is subjected to de-layering and polishing, thereby transferring the edge effect of the chip to be ground 1 to the edge of the extension portion 3, so as to alleviate the edge effect generated at the edge of the chip to be ground 1, which is beneficial to improving the integrity of the chip circuit after the de-layering and polishing process.

[0061] Optional, Figure 6 A schematic diagram of a structure of a polished sample of another chip provided in an embodiment of the present invention, referring to Figure 6 As shown, the chip limiting device 21 includes a counterweight block 211 and a counterweight limiting unit 212; the counterweight limiting unit 212 is connected to the counterweight block 211, and the counterweight limiting unit 212 is located on the side of the counterweight block 211 away from the chip 1 to be ground.

[0062] The connection between the counterweight limiting unit 212 and the counterweight pressing block 211 can be understood as a detachable connection or a fixed connection between the counterweight limiting unit 212 and the counterweight pressing block 211. The counterweight pressing block 211 uses its gravity to limit the position of the chip to be ground 1, so that during the forward grinding and polishing process, the front of the chip to be ground 1 is always flush with the lower edge of the extension portion 3. The counterweight limiting unit 212 is used to limit the position of the counterweight pressing block 211 to prevent the counterweight pressing block 211 from falling out of the chip placement portion 2, thereby facilitating the storage of the chip grinding and polishing samples.

[0063] It should be noted that, in this embodiment, the counterweight limiting unit 212 can limit the position of the counterweight pressing block 211, and the structure of the counterweight limiting unit 212 can be designed according to actual needs, which is not specifically limited in this embodiment.

[0064] Optional, Figure 7 A schematic diagram of a structure of a polished sample of another chip provided in an embodiment of the present invention, referring to Figure 7 As shown, the extension portion 3 includes an upper edge opposite to the lower edge; the counterweight limiting unit 212 includes a fixing plate 2121 and a spring 2122; the fixing plate is fixed to the upper edge of the extension portion 3; the fixing plate 2121, the spring 2122 and the counterweight pressing block 211 are connected in sequence.

[0065] The upper edge of the extension portion 3 is the edge above the extension portion 3. The fixing plate 2121, the spring 2122 and the counterweight pressing block 211 are sequentially connected, which can be understood as the fixing plate 2121, the spring 2122 and the counterweight pressing block 211 are sequentially detachably connected or fixedly connected.

[0066] In this embodiment, the fixed plate 2121 is fixed to the upper edge of the extension portion 3, and the fixed plate 2121, the spring 2122 and the counterweight block 211 are connected in sequence, so that the fixed plate 2121 can limit the position of the counterweight block 211 through the spring 2122 to prevent the counterweight block 211 from falling out of the chip placement portion 2.

[0067] Optional, Figure 8 A schematic diagram of a structure of a polished sample of another chip provided in an embodiment of the present invention, referring to Figure 8 As shown, the chip placement part 2 passes through the extension part 3; the counterweight limiting unit 212 includes a limiting plate 2123, which is connected to the side of the counterweight block 211 away from the chip to be ground 1, and the limiting plate 2123 is located above the upper edge of the extension part 3, and the length of the limiting plate 2123 is greater than the length of the chip placement part 2, so that the limiting plate 2123 can limit the position of the counterweight block 211.

[0068] Optional, Fig. 9 A schematic diagram of a structure of a polished sample of another chip provided in an embodiment of the present invention, referring to Fig. 9 As shown, the chip placement portion 2 passes through the extension portion 3 , and at least part of the inner edge of the extension portion 3 is provided with a first thread 31 . The counterweight limiting unit 212 includes a limiting rod 2124 , and the limiting rod 2124 includes a second thread 2125 adapted to the first thread 31 .

[0069] Among them, the inner edge of the extension part 3 can be understood as the edge where the extension part 3 is connected to the chip placement part 2, that is, the side edge of the chip placement part 2. By making the counterweight limiting unit 212 include a limiting rod 2124, the limiting rod 2124 is connected to the counterweight pressing block 211, and the limiting rod 2124 includes a second thread 2125 adapted to the first thread 31, so that the limiting rod 2124 can limit the position of the configuration pressing block 211; at the same time, by rotating the limiting rod 2124, the counterweight pressing block 211 can be moved upward or downward, so that under the cooperation of the first thread 31 and the second thread 2125, the front of the chip 1 to be ground can be flush with the lower edge of the extension part 3, so that when the chip grinding and polishing sample is subjected to de-layering grinding and polishing, the edge effect of the chip 1 to be ground is transferred to the edge of the extension part 3, so as to alleviate the edge effect generated at the edge of the chip 1 to be ground, which is conducive to improving the integrity of the chip circuit after the de-layering grinding and polishing process.

[0070] In an optional embodiment, in conjunction with reference Figure 3-Figure 9 As shown, the vertical distance D2 between the outer edge of the extension portion 3 and the side surface of the chip placement portion 2 has a value range of: D2 ≥ 2 cm.

[0071] The outer edge of the extension portion 3 refers to an edge of the extension portion 3 which is parallel to the side surface of the chip to be ground 1 and is away from the chip to be ground 1 .

[0072] It can be understood that the lower edge of the extension portion 3 is the extension surface of the front side of the chip 1 to be ground, and the larger its width (i.e., the vertical distance between the outer edge of the extension portion 3 and the side of the chip placement portion 2), the more the edge effect of the chip 1 to be ground can be alleviated. Therefore, by making the vertical distance between the outer edge of the extension portion 3 and the side of the chip placement portion 2 greater than or equal to 2 cm, it can be ensured that the edge effect of the chip 1 to be ground is completely transferred to the edge of the extension portion 3, which is beneficial to improving the integrity of the chip circuit after de-layering and polishing. However, when the vertical distance between the outer edge of the extension portion 3 and the side of the chip placement portion 2 is too large, the volume of the chip polishing sample will be larger, and the weight of the chip polishing sample will be larger, so that the experimenter will consume more physical strength when performing de-layering and polishing on the chip polishing sample, which is not conducive to the conduct of the experiment.

[0073] In an optional embodiment, a vertical distance D2 between the outer edge of the extension portion 3 and the side surface of the chip placement portion 2 is less than 6 cm to ensure the portability of the chip polishing sample and improve the test efficiency.

[0074] In some embodiments, the vertical distance between the outer edge of the extension portion 3 and the side of the chip placement portion 2 is 3 cm. In some embodiments, the vertical distance between the outer edge of the extension portion 3 and the side of the chip placement portion 2 is 4.5 cm.

[0075] In an optional embodiment, in conjunction with reference Figure 3-Figure 9 As shown, the height H of the extension portion 3 has a value range of H≥2 cm.

[0076] The height H of the extension portion 3 refers to the height of the extension portion 3 in a direction perpendicular to the front side of the chip 1 to be ground.

[0077] It is understandable that the tester needs to hold the polished sample of the chip on the polishing pad to perform de-layering on the chip 1 to be polished. When the height of the polished sample of the chip is too small, it is not conducive to the tester to grasp the polished sample of the chip, thereby affecting the test. Therefore, the height H of the extension portion 3 is in the range of H≥2cm, which can facilitate the tester to grasp the polished sample of the chip and facilitate the test.

[0078] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip polishing sample, characterized in that: include: The chip to be ground includes a front side and a back side opposite to each other, and a side surface perpendicular to the front side; Chip placement unit; The chip to be ground is located in the chip placement portion; An extension portion; the extension portion at least covers the side edge of the chip placement portion; The front side of the chip to be ground is flush with the lower edge of the extension portion; the vertical distance D1 between the side of the chip to be ground and the side edge of the chip placement portion has a value range of: D1≤0.5mm.

2. The polished sample of the chip according to claim 1, characterized in that: The extension part is made of epoxy resin.

3. The polished sample of the chip according to claim 2, characterized in that: The extended portion is cylindrical.

4. The polished sample of the chip according to any one of claim 1, characterized in that: The extended portion is made of metal or metal alloy.

5. The polished sample of chip according to claim 1, characterized in that: The chip placement portion includes a chip limiting device; the chip limiting device is located on the back side of the chip to be ground.

6. The polished sample of the chip according to claim 5, characterized in that: The chip limiting device comprises a counterweight pressing block and a counterweight limiting unit; the counterweight limiting unit is connected to the counterweight pressing block, and the counterweight limiting unit is located on a side of the counterweight pressing block away from the chip to be ground.

7. The polished sample of the chip according to claim 6, characterized in that: The extension portion includes an upper edge opposite to the lower edge; the counterweight limiting unit includes a fixing plate and a spring; The fixing plate is fixed to the upper edge of the extension portion; the fixing plate, the spring and the counterweight pressing block are connected in sequence.

8. The polished sample of the chip according to claim 6, characterized in that: The extension portion includes an upper edge opposite to the lower edge; the chip placement portion passes through the extension portion; The counterweight limiting unit includes a limiting plate; the limiting plate is located above the upper edge, and the length of the limiting plate is greater than the length of the chip placement portion.

9. The polished sample of the chip according to claim 6, characterized in that: The chip placement portion passes through the extension portion; at least a portion of the inner edge of the extension portion is provided with a first thread; The counterweight limiting unit includes a limiting rod; the limiting rod includes a second thread matched with the first thread.

10. The polished sample of chip according to claim 1, characterized in that: The vertical distance D2 between the outer edge of the extension portion and the side surface of the chip placement portion has a value range of: D2 ≥ 2 cm.

11. The polished sample of chip according to claim 1, characterized in that: The height H of the extension portion has a value range of H≥2 cm.

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