Self-adaptive dead time test circuit and test method

Abstract

The invention relates to the technical field of integrated circuits, and provides a self-adaptive dead time test circuit and a test method, which are used for testing an HVIC (High Voltage Integrated Circuit) chip. Comprising a first power supply, a first capacitor, a second power supply, a first resistor, a first oscilloscope, a second oscilloscope, a third oscilloscope, a fourth oscilloscope, a fifth oscilloscope, a first signal generator, a second signal generator, a third signal generator and a second capacitor. A first end of the first power supply is connected with a first end of the first capacitor and is grounded, and a second end of the first power supply is connected with a second end of the first capacitor and is connected to a VCC port of the HVIC chip; the first end of the first oscilloscope is connected with the first end of the first signal generator and is connected to the HIN port of the HVIC chip, and the second end of the first oscilloscope and the second end of the first signal generator are respectively grounded. The self-adaptive dead time test circuit is good in test effect and high in product percent of pass.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an adaptive dead time test circuit and a test method. Background Art

[0002] High voltage integrated circuit, or HVIC, is an integrated circuit product that converts MCU signals into IGBT driving signals. HVIC integrates PMOS tubes, NMOS tubes, triodes, diodes, voltage regulator tubes, resistors, and capacitors to form Schmitt, low voltage level, high voltage level, pulse generation circuit, dead zone circuit, interlock circuit, delay circuit, filter circuit, overcurrent protection circuit, overheat protection circuit, undervoltage protection circuit, and enable EN circuit. On the one hand, HVIC receives the control signal of MCU to drive the subsequent IGBT or MOS to work, and on the other hand, it sends the system status detection signal back to MCU. It is a key chip inside IPM.

[0003] With the rapid development of industry, IPM intelligent power modules are widely used in various fields. As one of the key components inside IPM, the performance of driver IC (HVIC) determines the performance of IPM. Among them, the EN enable circuit is a very important circuit inside HVIC. The function of this circuit is to control the opening or closing of HVIC through the threshold of EN. In the application of IPM intelligent power module motor control, the EN enable signal is used to control the switch of the entire circuit. By controlling the enable signal, it can be determined whether the motor receives the drive signal to rotate. The enabling circuit plays an important role in ensuring equipment safety, improving functional flexibility and optimizing energy use.

[0004] Therefore, when HVIC is produced off the production line, its adaptive dead zone circuit performance indicators must be tested to see if they meet the standards. Summary of the invention

[0005] The invention provides an adaptive dead time test circuit and a test method, aiming to solve the problems of poor test effect and poor pass rate of the existing HVIC chip at different temperatures.

[0006] An embodiment of the present invention provides an adaptive dead time test circuit for testing an HVIC chip, comprising: a first power supply, a first capacitor, a second power supply, a first resistor, a first oscilloscope, a second oscilloscope, a third oscilloscope, a fourth oscilloscope, a fifth oscilloscope, a first signal generator, a second signal generator, a third signal generator and a second capacitor;

[0007] A first end of the first power supply is connected to a first end of the first capacitor and is grounded, a second end of the first power supply is connected to a second end of the first capacitor and is connected to a VCC port of the HVIC chip; a first end of the first oscilloscope is connected to a first end of the first signal generator and is connected to a HIN port of the HVIC chip, a second end of the first oscilloscope and a second end of the first signal generator are grounded respectively;

[0008] The first end of the second oscilloscope is connected to the first end of the second signal generator and connected to the LIN port of the HVIC chip, the second end of the second oscilloscope is connected to the second end of the second signal generator and grounded, and the second end of the second signal generator is also connected to the ITRIP port of the HVIC chip;

[0009] The first end of the third oscilloscope is connected to the first end of the third signal generator and connected to the EN port of the HVIC chip, and the second end of the third oscilloscope is connected to the second end of the third signal generator and grounded;

[0010] A first end of the second power supply is grounded, a second end of the second power supply is connected to a first end of the first resistor, and a second end of the first resistor is connected to a FAULT port of the HVIC chip;

[0011] The first end of the fourth oscilloscope is connected to the HO port of the HVIC chip, the second end of the fourth oscilloscope is connected to the first end of the fifth oscilloscope and is connected to the COM port of the HVIC chip, the second end of the fifth oscilloscope is connected to the LO port of the HVIC chip, the first end of the second capacitor is connected to the VB port of the HVIC chip, and the second end of the second capacitor is respectively connected to the VS port of the HVIC chip and the first end of the fifth oscilloscope.

[0012] In a second aspect, an embodiment of the present invention provides an adaptive dead time testing method, the testing method is implemented based on the above-mentioned adaptive dead time testing circuit, and the testing method comprises the following steps:

[0013] S1, start the thermostat and set the temperature to the preset temperature;

[0014] S2, start the first DC power supply and set it to 15V, and supply power to the HVIC chip;

[0015] S3, start the second DC power supply and set it to 5V, and pull up the EN port of the HVIC chip to 5V through the first resistor;

[0016] S4, starting the first signal generator, the second signal generator and the third signal generator to output pulse signals to the HIN port, the LIN port and the EN port of the HVIC chip respectively;

[0017] S5, respectively inputting and outputting signals to the HIN port, the LIN port, the EN port, the HO port, the LO port and the FAULT port through the first oscilloscope, the second oscilloscope, the third oscilloscope, the fourth oscilloscope and the fifth oscilloscope;

[0018] S6. Collect and record the signals of the HIN port, LIN port, EN port, HO port, LO port and FAULT port; record the EN voltage when the EN signal rises from 0V to 5V and HO and LO have output, recorded as VEN1; record the EN voltage when the EN signal rises from 5V to 0V and HO and LO shut down output, recorded as EN2;

[0019] S7, judge V ENH +(95%) <V EN1 <V ENH +(1+5%);

[0020] V ENH -(95%) <V EN2 <V ENH -(1+5%); whether it meets the requirements, if yes, then cycle through S1-S6; if not, then the test ends and the product fails.

[0021] Preferably, the preset temperature of S1 is 25°C.

[0022] Preferably, the preset temperature of S1 is -40°C.

[0023] Preferably, the preset temperature of S1 is 125°C.

[0024] Compared with the prior art, the beneficial effect of the present invention lies in that the first end of the first power supply is connected to the first end of the first capacitor and grounded, the second end of the first power supply is connected to the second end of the first capacitor and connected to the VCC port of the HVIC chip; the first end of the first oscilloscope is connected to the first end of the first signal generator and connected to the HIN port of the HVIC chip, the second end of the first oscilloscope and the second end of the first signal generator are grounded respectively; the first end of the second oscilloscope is connected to the first end of the second signal generator and connected to the LIN port of the HVIC chip, the second end of the second oscilloscope is connected to the second end of the second signal generator and grounded, and the second end of the second signal generator is also connected to the ITRIP port of the HVIC chip; the first end of the third ...; the second end of the second oscilloscope is connected to the second end of the second signal generator and grounded, and the second end of the second signal generator is also connected to the ITRIP port of the HVIC chip; the first end of the third oscilloscope is connected to the first end of the first signal generator and connected to the HIN port of the HVIC chip; the second end of the third oscilloscope is connected to the first end of the second signal generator and connected to the LIN port of the HVIC chip; the second end of the second oscilloscope is connected to the second end of the second signal generator and grounded, and the second end of the second signal generator is also connected to the ITRIP port of the H The first end of the third signal generator is connected and connected to the EN port of the HVIC chip, and the second end of the third oscilloscope is connected to the second end of the third signal generator and grounded; the first end of the second power supply is grounded, the second end of the second power supply is connected to the first end of the first resistor, and the second end of the first resistor is connected to the FAULT port of the HVIC chip; the first end of the fourth oscilloscope is connected to the HO port of the HVIC chip, the second end of the fourth oscilloscope is connected to the first end of the fifth oscilloscope and connected to the COM port of the HVIC chip, the second end of the fifth oscilloscope is connected to the LO port of the HVIC chip, the first end of the second capacitor is connected to the VB port of the HVIC chip, and the second end of the second capacitor is respectively connected to the VS port of the HVIC chip and the first end of the fifth oscilloscope. The test circuit and the test method of the present invention test the EN enable threshold at different temperatures, the EN input is 0-5V, the rise time is 10ms, and the fall time is 10ms. During the EN signal rise process, it is detected that the HVIC works normally and has a drive output, and the EN voltage is what; during the EN signal fall process, it is detected that the HVIC stops working and has no drive output, and the EN voltage is what; it is judged whether the EN enable threshold and the shutoff threshold are within the qualified range, so as to prevent products with unqualified EN enable thresholds from entering the market. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:

[0026] Figure 1 is a circuit diagram of an adaptive dead time test circuit provided by an embodiment of the present invention;

[0027] Figure 2 is a waveform of a fault output port / FAULT provided in an embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of PWM parameters of an EN input signal provided by an embodiment of the present invention;

[0029] Figure 4 is a test timing diagram of an adaptive dead time test circuit provided by an embodiment of the present invention;

[0030] Figure 5 is a flow chart of an adaptive dead time testing method provided by an embodiment of the present invention;

[0031] Figure 6 1 is a flow chart of different temperatures of the adaptive dead time testing method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0033] First, combined with the Figure 1-Figure 4 As shown, an embodiment of the present invention provides an adaptive dead time test circuit for testing an HVIC chip 0201, comprising: a first power supply 0202, a first capacitor C1, a second power supply 0212, a first resistor R1, a first oscilloscope 0204, a second oscilloscope 0205, a third oscilloscope 0209, a fourth oscilloscope 0210, a fifth oscilloscope 0211, a first signal generator 0206, a second signal generator 0207, a third signal generator 0208 and a second capacitor C2;

[0034] A first end of the first power supply 0202 is connected to a first end of the first capacitor C1 and is grounded, a second end of the first power supply 0202 is connected to a second end of the first capacitor C1 and is connected to a VCC port of the HVIC chip 0201; a first end of the first oscilloscope 0204 is connected to a first end of the first signal generator 0206 and is connected to a HIN port of the HVIC chip 0201, and a second end of the first oscilloscope 0204 and a second end of the first signal generator 0206 are grounded respectively;

[0035] A first end of the second oscilloscope 0205 is connected to a first end of the second signal generator 0207 and is connected to a LIN port of the HVIC chip 0201, a second end of the second oscilloscope 0205 is connected to a second end of the second signal generator 0207 and is grounded, and a second end of the second signal generator 0207 is also connected to an ITRIP port of the HVIC chip 0201;

[0036] A first end of the third oscilloscope 0209 is connected to a first end of the third signal generator 0208 and is connected to an EN port of the HVIC chip 0201, and a second end of the third oscilloscope 0209 is connected to a second end of the third signal generator 0208 and is grounded;

[0037] A first end of the second power supply 0212 is grounded, a second end of the second power supply 0212 is connected to a first end of the first resistor R1, and a second end of the first resistor R1 is connected to a FAULT port of the HVIC chip 0201;

[0038] A first end of the fourth oscilloscope 0210 is connected to the HO port of the HVIC chip 0201, a second end of the fourth oscilloscope 0210 is connected to a first end of the fifth oscilloscope 0211 and is connected to the COM port of the HVIC chip 0201, a second end of the fifth oscilloscope 0211 is connected to the LO port of the HVIC chip 0201, a first end of the second capacitor C2 is connected to the VB port of the HVIC chip 0201, and a second end of the second capacitor C2 is respectively connected to the VS port of the HVIC chip 0201 and the first end of the fifth oscilloscope 0211.

[0039] Specifically, a bridge arm has input ports HIN1, LIN1, VB1, VS1, an enable input EN port and an overcurrent protection ITRIP port, output ports HO1, LO1, a fault output port / FAULT, a power supply VCC and ground terminals GND, COM.

[0040] The first power supply 0202 is a DC power supply with a maximum output voltage ≥ 20 V and a maximum output current > 0.5 A. The first capacitor C1 is a pin capacitor of the first power supply 0202, which is generally 1 uF.

[0041] The first oscilloscope 0204, the second oscilloscope 0205, the third oscilloscope 0209, the fourth oscilloscope 0210, and the fifth oscilloscope 0211 are the voltage difference between the low-voltage side output and the low-voltage side of five common probes.

[0042] The three output ports PWM1, PWM2 and PWM3 of the first signal generator 0206, the second signal generator 0207 and the third signal generator 0208, PWM1 and PWM2 are complementary PWM signals. The fault output port / FAULT is connected to 5V through the first resistor R1 of 6.8K. The positive output terminal of the first DC power supply is connected to the VCC of the tested HVIC and one end of the first capacitor C1, and the negative output is connected to the GND of the tested HVIC and the other end of the first capacitor C1; the output terminal PWM1 of the first signal generator 0206 is connected to the HIN123 of the tested HVIC, and the output terminal PWM2 of the second signal generator 0207 is connected to the LIN123 of the tested HVIC; the output terminal PWM3 of the third signal generator 0208 is connected to the EN of the tested HVIC, which is a PWM wave with a pulse period of T, a pulse width of W, a rise time of ton, and a fall time toff of 0 to 5V. VB123 of the tested HVIC chip 0201 is connected to one end of the bootstrap capacitor C1, and VS123, the other end of the second capacitor C2, and VS123 are connected to COM.

[0043] In a specific implementation, a first end of a first power supply 0202 is connected to a first end of a first capacitor C1 and is grounded, a second end of the first power supply 0202 is connected to a second end of the first capacitor C1 and is connected to a VCC port of an HVIC chip 0201; a first end of a first oscilloscope 0204 is connected to a first end of a first signal generator 0206 and is connected to a HIN port of an HVIC chip 0201, a second end of the first oscilloscope 0204 and a second end of the first signal generator 0206 are grounded respectively; a first end of a second oscilloscope 0205 is connected to a first end of a second signal generator 0207 and is connected to a LIN port of an HVIC chip 0201, a second end of the second oscilloscope 0205 is connected to a second end of the second signal generator 0207 and is grounded, and a second end of the second signal generator 0207 is also connected to an ITRIP port of an HVIC chip 0201; a first end of a third oscilloscope 0209 is connected to a third signal generator 0208 The first end of the third oscilloscope 0209 is connected to the EN port of the HVIC chip 0201, the second end of the third oscilloscope 0209 is connected to the second end of the third signal generator 0208 and grounded; the first end of the second power supply 0212 is grounded, the second end of the second power supply 0212 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the FAULT port of the HVIC chip 0201; the first end of the fourth oscilloscope 0210 is connected to the HO port of the HVIC chip 0201, the second end of the fourth oscilloscope 0210 is connected to the first end of the fifth oscilloscope 0211 and connected to the COM port of the HVIC chip 0201, the second end of the fifth oscilloscope 0211 is connected to the LO port of the HVIC chip 0201, the first end of the second capacitor C2 is connected to the VB port of the HVIC chip 0201, and the second end of the second capacitor C2 is respectively connected to the VS port of the HVIC chip 0201 and the first end of the fifth oscilloscope 0211. The test circuit and the test method of the present invention test the EN enable threshold at different temperatures, the EN input is 0-5V, the rise time is 10ms, and the fall time is 10ms. During the EN signal rise process, it is detected that the HVIC works normally and has a drive output, and the EN voltage is what; during the EN signal fall process, it is detected that the HVIC stops working and has no drive output, and the EN voltage is what; it is judged whether the EN enable threshold and the shutoff threshold are within the qualified range, so as to prevent products with unqualified EN enable thresholds from entering the market.

[0044] Second, combined with the Figure 1-Figure 6 As shown, an embodiment of the present invention provides an adaptive dead time testing method, the testing method is implemented based on the above-mentioned adaptive dead time testing circuit, and the testing method includes the following steps:

[0045] S1, start the thermostat and set the temperature to the preset temperature;

[0046] S2, start the first DC power supply and set it to 15V, and supply power to the HVIC chip 0201;

[0047] S3, start the second DC power supply and set it to 5V, and pull up the EN port of the HVIC chip 0201 to 5V through the first resistor R1;

[0048] S4, starting the first signal generator 0206, the second signal generator 0207 and the third signal generator 0208 to output pulse signals to the HIN port, the LIN port and the EN port of the HVIC chip 0201 respectively;

[0049] S5, respectively inputting and outputting signals to the HIN port, the LIN port, the EN port, the HO port, the LO port and the FAULT port through the first oscilloscope 0204, the second oscilloscope 0205, the third oscilloscope 0209, the fourth oscilloscope 0210 and the fifth oscilloscope 0211;

[0050] S6. Collect and record the signals of the HIN port, LIN port, EN port, HO port, LO port and FAULT port; record the EN voltage when the EN signal rises from 0V to 5V and HO and LO have output, recorded as VEN1; record the EN voltage when the EN signal rises from 5V to 0V and HO and LO shut down output, recorded as EN2;

[0051] S7, judge V ENH +(95%) <V EN1 <V ENH +(1+5%);

[0052] V ENH -(95%) <V EN2 <V ENH -(1+5%); whether it meets the requirements, if yes, then cycle through S1-S6; if not, then the test ends and the product fails.

[0053] In this embodiment, the preset temperature of S1 is 25°C.

[0054] In this embodiment, the preset temperature of S1 is -40°C.

[0055] In this embodiment, the preset temperature of S1 is 125°C.

[0056] Specifically, this test method tests the EN enable threshold at different temperatures, with an EN input of 0-5V, a rise time of 10ms, and a fall time of 10ms. During the EN signal rise process, the voltage of EN is detected when the HVIC is working normally and has a drive output; during the EN signal fall process, the voltage of EN is detected when the HVIC stops working and has no drive output; and it is determined whether the EN enable turn-on threshold and turn-off threshold are within the qualified range to prevent products with unqualified EN enable thresholds from entering the market.

[0057] The six-channel HVIC has three bridge arms. The upper and lower bridges of each bridge arm drive HIN and LIN signals, and the output terminals HO and LO each control the conduction of an IGBT. The upper and lower bridge drive signal output is granted to the HVIC enable EN. When the enable EN signal input is higher than the turn-on threshold, the upper and lower bridge drive signals will be output; when the enable EN signal input is lower than the turn-on threshold, the upper and lower bridge drive signals will shut down the output, and the fault signal / FAULT will be pulled low.

[0058] The working power supply of the six-channel HVIC is 12V-20V, the commonly used working power supply is generally 15V, and the working temperature is -40℃-125℃. The working characteristics of HVIC will change to a certain extent at different temperatures. Therefore, to determine whether the performance of an HVIC meets the standard, it is necessary to test the parameters of each functional circuit at different temperatures to see whether they meet the standard.

[0059] This test method: Under 15V power supply, select three temperatures for testing: the highest temperature 125℃, the normal temperature 25℃, and the lowest temperature -40℃.

[0060] This method is mainly used to test the EN threshold voltage parameters. Shorter connections should be used as much as possible to reduce the impact of external connection parasitic capacitance on the results.

[0061] The test equipment is as follows:

[0062] 1. Temperature control box: temperature control range: -45℃~145℃; control accuracy: 1℃.

[0063] 2.Signal generator: three-channel output; >20V Vp-p; >0.5A current output capability; >500MHz bandwidth.

[0064] 3. Oscilloscope: multiple inputs; >500MHz bandwidth.

[0065] 4. Power supply: multi-channel output DC power supply, maximum output voltage>20V; maximum output current>0.5A.

[0066] Test standard: Connect 15V power supply to VCC of HVIC, pull up the fault output port to 5V through resistor R, connect overcurrent protection input port to ground, connect bootstrap circuit port VB123 and VS123 to bootstrap capacitor, connect output port 0206PWM1 of signal generator to HIN123 of HVIC under test, connect output port 0208PWM2 of signal generator to LIN123 of HVIC under test; EN input pulse cycle is T, pulse width is W, rise time is ton, fall time toff is 0 to 5V PWM wave, during EN signal rise, detect HVIC normal operation, when there is drive output, EN voltage is within the range of plus or minus 5% of HVIC enable EN turn-on threshold; during EN signal fall, detect HVIC stop working, when there is no drive output, EN voltage is within the range of plus or minus 5% of HVIC enable EN turn-off threshold. The tested HVIC is qualified.

[0067] Figure 4 It is the EN input signal PWM parameter description: T is the pulse period, W is the pulse width, ton is the pulse rise time from 0 to 5V, and toff is the pulse fall time from 5V to 0.

[0068] Figure 5 The test timing diagram is as follows: HIN is the input PWM signal of the upper bridge driver of the HVIC under test, LIN is the input PWM signal of the lower bridge driver of the HVIC under test, EN is the EN enable input PWM signal of the HVIC under test, V ENH+ EN enable turn-on threshold, V ENH- EN is the enable shutdown threshold, HO is the upper bridge driver output signal of the HVIC under test, LO is the lower bridge driver output signal of the HVIC under test, and / FAULT is the fault signal output signal of the HVIC under test.

[0069] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.

[0070] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. An adaptive dead time test circuit for testing HVIC chips, characterized in that: include: A first power supply, a first capacitor, a second power supply, a first resistor, a first oscilloscope, a second oscilloscope, a third oscilloscope, a fourth oscilloscope, a fifth oscilloscope, a first signal generator, a second signal generator, a third signal generator, and a second capacitor; A first end of the first power supply is connected to a first end of the first capacitor and is grounded, a second end of the first power supply is connected to a second end of the first capacitor and is connected to a VCC port of the HVIC chip; a first end of the first oscilloscope is connected to a first end of the first signal generator and is connected to a HIN port of the HVIC chip, a second end of the first oscilloscope and a second end of the first signal generator are grounded respectively; The first end of the second oscilloscope is connected to the first end of the second signal generator and connected to the LIN port of the HVIC chip, the second end of the second oscilloscope is connected to the second end of the second signal generator and grounded, and the second end of the second signal generator is also connected to the ITRIP port of the HVIC chip; The first end of the third oscilloscope is connected to the first end of the third signal generator and connected to the EN port of the HVIC chip, and the second end of the third oscilloscope is connected to the second end of the third signal generator and grounded; A first end of the second power supply is grounded, a second end of the second power supply is connected to a first end of the first resistor, and a second end of the first resistor is connected to a FAULT port of the HVIC chip; The first end of the fourth oscilloscope is connected to the HO port of the HVIC chip, the second end of the fourth oscilloscope is connected to the first end of the fifth oscilloscope and is connected to the COM port of the HVIC chip, the second end of the fifth oscilloscope is connected to the LO port of the HVIC chip, the first end of the second capacitor is connected to the VB port of the HVIC chip, and the second end of the second capacitor is respectively connected to the VS port of the HVIC chip and the first end of the fifth oscilloscope.

2. An adaptive dead time testing method, characterized in that: The test method is implemented based on the adaptive dead time test circuit according to claim 1, and the test method comprises the following steps: S1, start the thermostat and set the temperature to the preset temperature; S2, start the first DC power supply and set it to 15V, and supply power to the HVIC chip; S3, start the second DC power supply and set it to 5V, and pull up the EN port of the HVIC chip to 5V through the first resistor; S4, starting the first signal generator, the second signal generator and the third signal generator to output pulse signals to the HIN port, the LIN port and the EN port of the HVIC chip respectively; S5, respectively inputting and outputting signals to the HIN port, the LIN port, the EN port, the HO port, the LO port and the FAULT port through the first oscilloscope, the second oscilloscope, the third oscilloscope, the fourth oscilloscope and the fifth oscilloscope; S6. Collect and record the signals of the HIN port, LIN port, EN port, HO port, LO port and FAULT port; record the EN voltage when the EN signal rises from 0V to 5V and HO and LO have output, recorded as VEN1; record the EN voltage when the EN signal rises from 5V to 0V and HO and LO shut down output, recorded as EN2; S7, judge V ENH +(95%) <V EN1 <V ENH +(1+5%); V ENH -(95%) <V EN2 <V ENH -(1+5%); whether it meets the requirements, if yes, then cycle through S1-S6; if not, then the test ends and the product fails.

3. The adaptive dead time testing method according to claim 2, characterized in that: The preset temperature of S1 is 25°C.

4. The adaptive dead time testing method according to claim 3, characterized in that: The preset temperature of S1 is -40°C.

5. The adaptive dead time testing method according to claim 4, characterized in that: The preset temperature of S1 is 125°C.

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