HVIC adaptive dead time test circuit and method

Abstract

The invention provides an HVIC self-adaptive dead time test circuit and an HVIC self-adaptive dead time test method. According to the method, each group of upper and lower bridge input complementary driving signals without dead time are tested at different temperatures, whether the upper and lower bridge driving signals can output different dead time according to different loads and the upper and lower bridge driving signals or not is tested, and due to different loads and different falling time of a to-be-tested circuit VS, the dead time of the to-be-tested circuit VS is determined by matching the relationship between different loads and dead time. According to the test method, whether the corresponding dead time is qualified or not is determined according to the self-adaptive dead time of the HVIC, the effect of testing the HVIC self-adaptive dead time circuit function is achieved, the circuit test efficiency can be improved through the test method, and products with unqualified self-adaptive dead time functions are prevented from flowing into the market.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a HVIC adaptive dead time test circuit and method. Background Art

[0002] With the rapid development of industry, IPM intelligent power modules are widely used in various fields. As one of the key components inside IPM, the performance of driver IC (HVIC) determines the performance of IPM. The adaptive dead zone circuit is a very important circuit inside HVIC. The function of this circuit is: when LIN and HIN are complementary signals without dead time, the adaptive dead zone circuit will set a suitable dead time according to the change of the application system load to prevent the upper and lower bridges from passing through and causing damage to the IGBT. Therefore, when HVIC is produced off the line, it is necessary to test whether the performance indicators of its adaptive dead zone circuit meet the standards.

[0003] However, the existing HVIC adaptive dead time circuit test process is not unified, the detection process does not have a relatively complete standard, and the test results are relatively incomplete. Summary of the invention

[0004] The invention provides an HVIC adaptive dead time test circuit and method, aiming to solve the problems that the dead time test process of the existing HVIC circuit is not standard and the test result is not comprehensive.

[0005] In order to solve the above technical problems, in a first aspect, the present invention provides an HVIC adaptive dead time test circuit, which is used to test the dead time of the HVIC circuit to be tested. The HVIC adaptive dead time test circuit includes a DC power supply, a filter capacitor, a signal generator interface and an oscilloscope port, wherein:

[0006] A first end of the DC power supply is connected to a power supply end of the HCIV circuit to be tested, and a second end of the DC power supply is connected to a ground end of the HCIV circuit to be tested;

[0007] The first end of the filter capacitor is connected to the first end of the DC power supply, and the second end of the filter capacitor is connected to the second end of the DC power supply;

[0008] The signal generator interface includes a first interface and a second interface, wherein a first end of the first interface is connected to a high level input end of the HCIV circuit to be tested, and a second end of the first interface is connected to a ground end of the HCIV circuit to be tested; a first end of the second interface is connected to a low level input end of the HCIV circuit to be tested, and a second end of the second interface is connected to a ground end of the HCIV circuit to be tested;

[0009] The oscilloscope port includes a first port and a second port, wherein the first end of the first port is connected to the high level output end of the HCIV circuit to be tested, and the second end of the first port is connected to the ground end of the HCIV circuit to be tested; the first end of the second port is connected to the low level output end of the HCIV circuit to be tested, and the second end of the second port is connected to the ground end of the HCIV circuit to be tested;

[0010] The HVIC adaptive dead time test circuit further includes a first capacitor, a second capacitor, a third capacitor, a first transistor, a second transistor, a first inductor, a first resistor, a second resistor, a third resistor, a first switch and a second switch, wherein:

[0011] The first end of the first capacitor is connected to the VB end of the HCIV circuit to be tested, and the second end of the first capacitor is connected to the VS end of the HCIV circuit to be tested;

[0012] The first end of the first inductor is connected to the second end of the first capacitor, and the second end of the first inductor is connected to the first end of the second capacitor; the second end of the second capacitor is connected to the ground end of the HCIV circuit to be tested;

[0013] A first end of the third capacitor is connected to a high voltage DC power supply, and a second end of the third capacitor is connected to a ground terminal of the HCIV circuit to be tested;

[0014] The gate of the first transistor is connected to the high level output terminal of the HCIV circuit to be tested, the drain of the first transistor is connected to the high voltage DC power supply, and the gate of the first transistor is connected to the first end of the first inductor;

[0015] The gate of the second transistor is connected to the low level output terminal of the HCIV circuit to be tested, the drain of the second transistor is connected to the ground terminal of the HCIV circuit to be tested, and the gate of the second transistor is connected to the first end of the first inductor;

[0016] The first resistor, the second resistor, and the third resistor are connected in series in sequence, a first end of the first resistor is connected to a second end of the first inductor, and a second end of the third resistor is connected to a ground terminal of the HCIV circuit to be tested;

[0017] The first end of the first switch is connected to the first end of the second resistor, and the second end of the first switch is connected to the second end of the second resistor; the first end of the second switch is connected to the first end of the third resistor, and the second end of the second switch is connected to the second end of the third resistor.

[0018] Furthermore, the maximum output voltage of the DC power supply is greater than 20V, and the maximum output current is greater than 0.5A.

[0019] Furthermore, the output voltage range of the signal generator interface is 0 - 15V.

[0020] Furthermore, both the first transistor and the second transistor are gallium nitride field effect transistors.

[0021] In a second aspect, the present invention also provides an HVIC adaptive dead-time testing method implemented based on the above-mentioned HVIC adaptive dead-time testing circuit, including the following steps:

[0022] S101. Determine the dead time T1 when the preset load first resistor in the HVIC circuit to be tested, the dead time T2 when the load is the first resistor and the second resistor, and the dead time T3 when the load is the first resistor, the second resistor, and the third resistor;

[0023] S102. Set the test temperature of the HVIC circuit to be tested;

[0024] S103. Close the first switch and the second switch, and turn on the DC power supply and the high-voltage DC power supply;

[0025] S104. Start the signal generator to output a signal, and record, through an oscilloscope, the time when the output voltage value at the high-level output terminal of the HVIC circuit to be tested drops from the highest value to 50% of the output range as the first test time a1, or record, through the oscilloscope, the time when the output voltage value at the low-level output terminal of the HVIC circuit to be tested rises from the lowest value to 50% of the output range as the second test time a2;

[0026] S105. Determine whether T1(95%) < a1 < T1(1 + 5%) or T1(95%) < a2 < T1(1 + 5%) holds. If not, exit the test;

[0027] S106. Turn off the DC power supply and the high-voltage DC power supply;

[0028] S107. Open the first switch, close the second switch, and turn on the DC power supply and the high-voltage DC power supply;

[0029] S108. Start the signal generator to output a signal, and record, through the oscilloscope, the time when the output voltage value at the high-level output terminal of the HVIC circuit to be tested drops from the highest value to 50% of the output range as the third test time a3, or record, through the oscilloscope, the time when the output voltage value at the low-level output terminal of the HVIC circuit to be tested rises from the lowest value to 50% of the output range as the fourth test time a4;

[0030] S109. Determine whether T2(95%) < a3 < T2(1 + 5%) or T2(95%) < a4 < T2(1 + 5%) holds. If not, exit the test.

[0031] S1010. Turn off the DC power supply and the high - voltage DC power supply.

[0032] S1011. Turn on the first switch and the second switch, and turn on the DC power supply and the high - voltage DC power supply.

[0033] S1012. Start the signal generator to output a signal, and record, using the oscilloscope, the time it takes for the output voltage value at the high - level output terminal of the HVIC circuit under test to reach 50% of the output range from the highest value as the fifth test time a5, or record, using the oscilloscope, the time it takes for the output voltage value at the low - level output terminal of the HVIC circuit under test to reach 50% of the output range from the lowest value as the sixth test time a6.

[0034] S1013. Determine whether T3(95%) < a5 < T3(1 + 5%) or T3(95%) < a6 < T3(1 + 5%) holds. If not, exit the test; if so, output the dead - time test result of the HVIC circuit under test.

[0035] Furthermore, the HVIC adaptive dead - time test method further includes the step of:

[0036] S1014. Determine the operating temperature of the HVIC circuit under test. After changing the current test temperature through the temperature - control box, return to step S103.

[0037] Furthermore, in steps S103, S107, and S1011, set the output of the DC power supply to 15V and the output of the high - voltage DC power supply to 300V.

[0038] The beneficial effects achieved by the present invention are as follows: A HVIC adaptive dead - time test circuit and method implemented using different loads are proposed. This method tests, at different temperatures, the driving signals of the upper and lower bridges that are complementary inputs and have no dead time in each group, and checks whether the driving signals of the upper and lower bridges output different dead times according to different loads. Since, for different loads, the fall time of VS of the circuit under test is different, by matching the relationship between different loads and dead times, it is determined whether the corresponding dead times are qualified, so as to achieve the effect of testing the function of the HVIC adaptive dead - time circuit. Through the test method of the present invention, the efficiency of circuit testing can be improved, and products with unqualified adaptive dead - time functions can be prevented from entering the market. Description of the Drawings

[0039] Figure 1is a structural schematic diagram of an HVIC adaptive dead time test circuit provided by an embodiment of the present invention;

[0040] Figure 2 Schematic diagram of complementary PWM waves of the HVIC circuit to be tested provided by an embodiment of the present invention;

[0041] Figure 3 It is a schematic diagram of the test dead time provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0043] Please refer to Figure 1 , Figure 1 1 is a schematic diagram of the structure of an HVIC adaptive dead time test circuit 200 provided in an embodiment of the present invention. The HVIC adaptive dead time test circuit 200 is used to test the dead time of an HVIC circuit 201 to be tested. The HVIC adaptive dead time test circuit 200 includes a DC power supply 202, a filter capacitor 203, a signal generator interface and an oscilloscope port, wherein:

[0044] A first end of the DC power supply 202 is connected to a power supply terminal VCC of the HCIV circuit to be tested, and a second end of the DC power supply 202 is connected to a ground terminal GND of the HCIV circuit to be tested;

[0045] The first end of the filter capacitor 203 is connected to the first end of the DC power supply 202, and the second end of the filter capacitor 203 is connected to the second end of the DC power supply 202;

[0046] The signal generator interface includes a first interface 204 and a second interface 205, wherein a first end of the first interface 204 is connected to a high level input terminal HIN of the HCIV circuit to be tested, and a second end of the first interface 204 is connected to a ground terminal GND of the HCIV circuit to be tested; a first end of the second interface 205 is connected to a low level input terminal LIN of the HCIV circuit to be tested, and a second end of the second interface 205 is connected to a ground terminal GND of the HCIV circuit to be tested;

[0047] The oscilloscope port includes a first port 206 and a second port 207, wherein a first end of the first port 206 is connected to a high level output end HO of the HCIV circuit to be tested, and a second end of the first port 206 is connected to a ground end GND of the HCIV circuit to be tested; a first end of the second port 207 is connected to a low level output end LO of the HCIV circuit to be tested, and a second end of the second port 207 is connected to a ground end GND of the HCIV circuit to be tested;

[0048] The HVIC adaptive dead time test circuit 200 further includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a first transistor GaN FET1, a second transistor GaN FET2, a first inductor L1, a first resistor R1, a second resistor R2, a third resistor R3, a first switch K1 and a second switch K2, wherein:

[0049] A first end of the first capacitor C1 is connected to the VB end of the HCIV circuit to be tested, and a second end of the first capacitor C1 is connected to the VS end of the HCIV circuit to be tested;

[0050] The first end of the first inductor L1 is connected to the second end of the first capacitor C1, and the second end of the first inductor L1 is connected to the first end of the second capacitor C2; the second end of the second capacitor C2 is connected to the ground terminal GND of the HCIV circuit to be tested;

[0051] A first end of the third capacitor C3 is connected to a high voltage direct current power supply DC, and a second end of the third capacitor C3 is connected to a ground terminal GND of the HCIV circuit to be tested;

[0052] The gate of the first transistor GaN FET1 is connected to the high level output terminal HO of the HCIV circuit to be tested, the drain of the first transistor GaN FET1 is connected to the high voltage DC power supply DC, and the gate of the first transistor GaN FET1 is connected to the first end of the first inductor L1;

[0053] The gate of the second transistor GaN FET2 is connected to the low level output terminal LO of the HCIV circuit to be tested, the drain of the second transistor GaN FET2 is connected to the ground terminal GND of the HCIV circuit to be tested, and the gate of the second transistor GaN FET2 is connected to the first end of the first inductor L1;

[0054] The first resistor R1, the second resistor R2, and the third resistor R3 are connected in series in sequence, a first end of the first resistor R1 is connected to a second end of the first inductor L1, and a second end of the third resistor R3 is connected to a ground terminal GND of the HCIV circuit to be tested;

[0055] The first end of the first switch K1 is connected to the first end of the second resistor R2, and the second end of the first switch K1 is connected to the second end of the second resistor R2; the first end of the second switch K2 is connected to the first end of the third resistor R3, and the second end of the second switch K2 is connected to the second end of the third resistor R3.

[0056] Furthermore, the maximum output voltage of the DC power supply 202 is greater than 20V, and the maximum output current is greater than 0.5A.

[0057] Furthermore, the output voltage range of the signal generator interface is 0-15V.

[0058] Furthermore, both the first transistor GaN FET1 and the second transistor GaN FET2 are gallium nitride field effect transistors.

[0059] The complementary PWM wave of the HVIC circuit 201 to be tested is as follows: Figure 2 As shown, the adaptive dead zone circuit sets the corresponding dead zone time according to the load conditions to prevent the upper bridge power device and the lower bridge power device from being damaged by direct conduction. The embodiment of the present invention tests the dead zone time of this function by the following method.

[0060] The embodiment of the present invention further provides an HVIC adaptive dead time test method implemented based on the HVIC adaptive dead time test circuit 200 as described above, comprising the following steps:

[0061] S101, determining a dead time T1 when a preset first resistor R1 is loaded in the HVIC circuit 201 to be tested, a dead time T2 when the first resistor R1 and the second resistor R2 are loaded, and a dead time T3 when the first resistor R1, the second resistor R2 and the third resistor R3 are loaded;

[0062] S102, setting the test temperature of the HVIC circuit 201 to be tested;

[0063] S103, close the first switch K1 and the second switch K2, and turn on the DC power supply 202 and the high-voltage DC power supply DC;

[0064] S104, start the signal generator to output a signal, and record the time from the highest value to 50% of the output interval of the output voltage value of the high level output terminal HO of the HVIC circuit 201 to be tested by an oscilloscope as the first test time a1, or record the time from the lowest value to 50% of the output interval of the output voltage value of the low level output terminal LO of the HVIC circuit 201 to be tested by an oscilloscope as the second test time a2; the schematic diagram of the test dead time is as shown in Figure 3 As shown;

[0065] S105. Determine whether T1(95%) < a1 < T1(1 + 5%) or T1(95%) < a2 < T1(1 + 5%) holds. If not, exit the test;

[0066] S106. Turn off the DC power supply 202 and the high-voltage DC power supply DC;

[0067] S107. Turn on the first switch K1, close the second switch K2, and turn on the DC power supply 202 and the high-voltage DC power supply DC;

[0068] S108. Start the signal generator to output a signal, and record, using the oscilloscope, the time it takes for the output voltage value of the high-level output terminal HO of the HVIC circuit under test 201 to reach 50% of the output range from the highest value as the third test time a3, or record, using the oscilloscope, the time it takes for the output voltage value of the low-level output terminal LO of the HVIC circuit under test 201 to reach 50% of the output range from the lowest value as the fourth test time a4;

[0069] S109. Determine whether T2(95%) < a3 < T2(1 + 5%) or T2(95%) < a4 < T2(1 + 5%) holds. If not, exit the test;

[0070] S1010. Turn off the DC power supply 202 and the high-voltage DC power supply DC;

[0071] S1011. Turn on the first switch K1 and the second switch K2, and turn on the DC power supply 202 and the high-voltage DC power supply DC;

[0072] S1012. Start the signal generator to output a signal, and record, using the oscilloscope, the time it takes for the output voltage value of the high-level output terminal HO of the HVIC circuit under test 201 to reach 50% of the output range from the highest value as the fifth test time a5, or record, using the oscilloscope, the time it takes for the output voltage value of the low-level output terminal LO of the HVIC circuit under test 201 to reach 50% of the output range from the lowest value as the sixth test time a6;

[0073] S1013. Determine whether T3(95%) < a5 < T3(1 + 5%) or T3(95%) < a6 < T3(1 + 5%) holds. If not, exit the test; if so, output the dead-time test result of the HVIC circuit under test 201.

[0074] Furthermore, the HVIC adaptive dead-time test method further includes the steps of:

[0075] S1014, determining the operating temperature of the HVIC circuit 201 to be tested, and changing the current test temperature through the temperature control box, and then returning to step S103. Generally speaking, the operating temperature of the HVIC circuit 201 to be tested is -40°C to 125°C. During the implementation process, a test cycle can be defined to complete the test process for a specific temperature in the working range, for example, a test of -40°C, 25°C, and 125°C is performed in a cycle.

[0076] Furthermore, in steps S103, S107, and S1011, the output of the DC power supply 202 is set to 15V, and the output of the high-voltage DC power supply DC is set to 300V.

[0077] In the above process, if the HVIC circuit 201 to be tested can completely execute the process of the HVIC adaptive dead time test method provided by the embodiment of the present invention, it can be considered that the adaptive dead time circuit function of the circuit is normal; if the test is exited at any step in the process, the functional test fails.

[0078] The beneficial effect achieved by the present invention is that a HVIC adaptive dead time test circuit and method using different loads are proposed. The method tests each group of upper and lower bridge inputs complementary and dead time-free drive signals at different temperatures, and tests whether the upper and lower bridge drive signals output different dead times according to different loads. Due to different loads, the fall time of the circuit to be tested VS is different. By matching the relationship between different loads and the dead time, it is determined whether the corresponding dead time is qualified, so as to achieve the effect of testing the function of the HVIC adaptive dead time circuit. The test method of the present invention can improve the efficiency of circuit testing and prevent products with unqualified adaptive dead time functions from entering the market.

[0079] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM).

[0080] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0081] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0082] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A HVIC adaptive dead time test circuit, used to test the dead time of an HVIC circuit to be tested, characterized in that: The HVIC adaptive dead time test circuit includes a DC power supply, a filter capacitor, a signal generator interface and an oscilloscope port, wherein: A first end of the DC power supply is connected to a power supply end of the HCIV circuit to be tested, and a second end of the DC power supply is connected to a ground end of the HCIV circuit to be tested; The first end of the filter capacitor is connected to the first end of the DC power supply, and the second end of the filter capacitor is connected to the second end of the DC power supply; The signal generator interface includes a first interface and a second interface, wherein a first end of the first interface is connected to a high level input end of the HCIV circuit to be tested, and a second end of the first interface is connected to a ground end of the HCIV circuit to be tested; a first end of the second interface is connected to a low level input end of the HCIV circuit to be tested, and a second end of the second interface is connected to a ground end of the HCIV circuit to be tested; The oscilloscope port includes a first port and a second port, wherein the first end of the first port is connected to the high level output end of the HCIV circuit to be tested, and the second end of the first port is connected to the ground end of the HCIV circuit to be tested; the first end of the second port is connected to the low level output end of the HCIV circuit to be tested, and the second end of the second port is connected to the ground end of the HCIV circuit to be tested; The HVIC adaptive dead time test circuit further includes a first capacitor, a second capacitor, a third capacitor, a first transistor, a second transistor, a first inductor, a first resistor, a second resistor, a third resistor, a first switch and a second switch, wherein: The first end of the first capacitor is connected to the VB end of the HCIV circuit to be tested, and the second end of the first capacitor is connected to the VS end of the HCIV circuit to be tested; The first end of the first inductor is connected to the second end of the first capacitor, and the second end of the first inductor is connected to the first end of the second capacitor; the second end of the second capacitor is connected to the ground end of the HCIV circuit to be tested; A first end of the third capacitor is connected to a high voltage DC power supply, and a second end of the third capacitor is connected to a ground terminal of the HCIV circuit to be tested; The gate of the first transistor is connected to the high level output terminal of the HCIV circuit to be tested, the drain of the first transistor is connected to the high voltage DC power supply, and the gate of the first transistor is connected to the first end of the first inductor; The gate of the second transistor is connected to the low level output terminal of the HCIV circuit to be tested, the drain of the second transistor is connected to the ground terminal of the HCIV circuit to be tested, and the gate of the second transistor is connected to the first end of the first inductor; The first resistor, the second resistor, and the third resistor are connected in series in sequence, a first end of the first resistor is connected to a second end of the first inductor, and a second end of the third resistor is connected to a ground terminal of the HCIV circuit to be tested; The first end of the first switch is connected to the first end of the second resistor, and the second end of the first switch is connected to the second end of the second resistor; the first end of the second switch is connected to the first end of the third resistor, and the second end of the second switch is connected to the second end of the third resistor.

2. The HVIC adaptive dead time test circuit according to claim 1, characterized in that: The maximum output voltage of the DC power supply is greater than 20V, and the maximum output current is greater than 0.5A.

3. The HVIC adaptive dead time test circuit according to claim 1, characterized in that: The output voltage range of the signal generator interface is 0 - 15V.

4. The HVIC adaptive dead time test circuit according to claim 1, characterized in that: Both the first transistor and the second transistor are gallium nitride field effect transistors.

5. A method for testing HVIC adaptive dead time implemented by the HVIC adaptive dead time testing circuit according to any one of claims 1 to 4, characterized in that: It includes the following steps: S101. Determine the dead time T1 when the preset load first resistor in the HVIC circuit under test, the dead time T2 when the load is the first resistor and the second resistor, and the dead time T3 when the load is the first resistor, the second resistor, and the third resistor; S102. Set the test temperature of the HVIC circuit under test; S103. Close the first switch and the second switch, and turn on the DC power supply and the high - voltage DC power supply; S104. Start the signal generator to output a signal, and record, through the oscilloscope, the time when the output voltage value of the high - level output terminal of the HVIC circuit under test drops from the highest value to 50% of the output range as the first test time a1, or record, through the oscilloscope, the time when the output voltage value of the low - level output terminal of the HVIC circuit under test rises from the lowest value to 50% of the output range as the second test time a2; S105. Judge whether T1(95%) < a1 < T1(1 + 5%) or T1(95%) < a2 < T1(1 + 5%) holds. If not, exit the test; S106. Turn off the DC power supply and the high - voltage DC power supply; S107. Open the first switch, close the second switch, and turn on the DC power supply and the high - voltage DC power supply; S108. Start the signal generator to output a signal, and record, through the oscilloscope, the time when the output voltage value of the high - level output terminal of the HVIC circuit under test drops from the highest value to 50% of the output range as the third test time a3, or record, through the oscilloscope, the time when the output voltage value of the low - level output terminal of the HVIC circuit under test rises from the lowest value to 50% of the output range as the fourth test time a4; S109. Judge whether T2(95%) < a3 < T2(1 + 5%) or T2(95%) < a4 < T2(1 + 5%) holds. If not, exit the test; S1010. Turn off the DC power supply and the high - voltage DC power supply; S1011. Open the first switch and the second switch, and turn on the DC power supply and the high - voltage DC power supply; S1012. Start the signal generator to output a signal, and record, through the oscilloscope, the time when the output voltage value of the high - level output terminal of the HVIC circuit under test drops from the highest value to 50% of the output range as the fifth test time a5, or record, through the oscilloscope, the time when the output voltage value of the low - level output terminal of the HVIC circuit under test rises from the lowest value to 50% of the output range as the sixth test time a6; S1013. Judge whether T3(95%) < a5 < T3(1 + 5%) or T3(95%) < a6 < T3(1 + 5%) holds. If not, exit the test; if so, output the dead - time test result of the HVIC circuit under test.

6. The HVIC adaptive dead time testing method according to claim 5, characterized in that: The HVIC adaptive dead - time test method further includes the steps: S1014, determining the operating temperature of the HVIC circuit to be tested, changing the current test temperature through the temperature control box, and then returning to step S103.

7. The HVIC adaptive dead time testing method according to claim 5, characterized in that: In steps S103, S107, and S1011, the output of the DC power supply is set to 15V, and the output of the high-voltage DC power supply is set to 300V.

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