SoC PHY ATE serial and parallel hybrid scalable multi-level connection test architecture

Abstract

The present invention discloses a SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture, which relates to the field of system-level chip testing, and implements the access of the PHY to be tested based on a preset access logic, wherein the preset access logic specifically includes: connecting the test interfaces of multiple PHYs of the same type in parallel through a JTAG_HUB module, and accessing the JTAG Chain via the JTAG_HUB module; based on the type of PHY, if the number of the current type of PHY is only one, directly accessing the JTAG Chain when it is a JTAG test interface, and accessing the JTAG Chain via a TAP_FSM module when it is a TDR test interface; inserting a JTAG_PIPE module based on the distance between access nodes in the JTAG Chain. The present application can effectively solve the problem of PHY test duration.

Description

Technical Field

[0001] The present application relates to the field of system-on-chip testing, and in particular to a SoC PHY ATE serial-parallel hybrid scalable multi-level connection testing architecture. Background Art

[0002] Currently, the testing of various types of PHY (Physical Layer) generally adopts JTAG Chain serial structure or single-point star structure. Figure 1 The JTAG Chain serial structure is a chain structure formed by connecting multiple devices in series through the JTAG (Joint Test Action Group, an international standard test protocol) interface. It is mainly used for chip internal testing and debugging. Figure 2 As shown, it is a single-point star structure.

[0003] However, for the existing test structure, the efficiency of the simple JTAG Chain serial structure is difficult to meet the ATE (Automatic Test Equipment) test requirements of SoC (System on Chip) containing multiple and multiple PHYs, and the single-point star structure is difficult to increase the frequency of JATG testing, which is severely restricted by the limitation of physical location. It can be seen that the above two test structures are difficult to solve the problem of test time caused by the number of cycles of a given pattern (test vector). Summary of the invention

[0004] The present application provides a SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture, which can effectively solve the problem of PHY test duration.

[0005] In a first aspect, an embodiment of the present application provides a SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture, which is implemented based on a JTAG Chain serial structure. In the SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture, a PHY access to be tested is implemented based on a preset access logic, and the preset access logic specifically includes:

[0006] Connect multiple PHY test interfaces of the same type in parallel through the JTAG_HUB module, and access the JTAG Chain through the JTAG_HUB module;

[0007] Based on the type of PHY, if there is only one PHY of the current type, it is directly connected to the JTAG Chain when it is a JTAG test interface, and is connected to the JTAG Chain via the TAP_FSM module when it is a TDR test interface;

[0008] Based on the distance between access nodes in the JTAG Chain, insert the JTAG_PIPE module when the distance between two adjacent access nodes is greater than the preset distance;

[0009] The JTAG_HUB module is used to implement the parallel test control of the same type of PHY, the TAP_FSM module is used to parse the JTAG test interface input signal and extract the JTAG instruction, and the JTAG_PIPE module is used to optimize the timing.

[0010] In combination with the first aspect, in one implementation, the TAP_FSM module is further used to extract a JTAG DR control signal, return a TDO signal according to a serial input, and generate a reset signal according to a TAP state.

[0011] In combination with the first aspect, in one implementation,

[0012] The JTAG_HUB module is connected to the JTAG Chain through the TAP_FSM module, the same type of PHY participating in the parallel test is specified through the TDR module, and the TDO signal fitting algorithm is specified through the TDR module;

[0013] The TDR module implements the access of TAP DR through shift register, and each PHY connected to the JTAG_HUB module is correspondingly connected to a TDR module for controlling or collecting the test interface signal of the PHY.

[0014] In combination with the first aspect, in one implementation,

[0015] The TDR module includes two directions: RX and TX;

[0016] The TX is used to control the PHY test;

[0017] The RX is used to collect the output data of the PHY and return it in a serial manner.

[0018] In combination with the first aspect, in one implementation,

[0019] When the distance between the TDR modules corresponding to each PHY connected to the TAP_FSM module and the JTAG_HUB module is greater than the set distance, insert the DR_PIPE module between the TAP_FSM module and the TDR module;

[0020] The DR_PIPE module is used to optimize timing.

[0021] In combination with the first aspect, in one implementation,

[0022] The TAP_FSM module is also provided with a TDO_MUX module, and the TDR modules corresponding to each PHY connected to the JTAG_HUB module are all connected to the TDO_MUX module;

[0023] The TDO_MUX module is used to fit multiple groups of TDO signals into one TDO signal, so as to achieve TDO signal output fitting of parallel testing PHY.

[0024] In combination with the first aspect, in one implementation,

[0025] The TDO_MUX module implements the fitting of the TDO signal based on the TDO signal fitting algorithm;

[0026] The TDO signal fitting algorithm includes performing AND logic calculation on multiple groups of TDO signals, performing OR logic calculation on multiple groups of TDO signals, outputting AND logic first and then outputting OR logic, and executing Debug mode;

[0027] The Debug mode is to output multiple groups of TDO signal values ​​one by one.

[0028] In combination with the first aspect, in one implementation,

[0029] A TDO_SEL module is provided between the TAP_FSM module and the TDO_MUX module, and between the TDO_MUX module and the TDR modules corresponding to each PHY connected to the JTAG_HUB module;

[0030] The TDO_SEL module is used to select the TDO signal output within the same PHY, and select a group of TDO signals from multiple groups of TDO signals for output.

[0031] In combination with the first aspect, in one implementation, the JTAG_HUB module supports the PHY of the JTAG test interface or the TDR test interface.

[0032] In combination with the first aspect, in one implementation, the JTAG_HUB module is further used to implement a bypass function through a TDR module, and supports JTAG bypass instructions and undefined instructions.

[0033] The beneficial effects brought by the technical solution provided in the embodiments of the present application include:

[0034] It supports multi-level connection SoC PHY test architecture for parallel testing and can be expanded according to actual needs. It can solve the problem of parallel testing of PHYs with the same type of JTAG / TDR interface, and can increase the SoC JTAG ChainTCK frequency by inserting multi-level PIPE. It can realize concise and standardized custom JTAG instructions for parallel requirements. It adopts building block module design to flexibly realize the internal physical position, timing and connection requirements of SoC, and adapts to SoC PHY test requirements through standardized interface module splicing, which can effectively solve the problem of PHY test duration. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic diagram of the JTAG Chain serial structure;

[0036] Figure 2 It is a schematic diagram of a single-point star structure;

[0037] Figure 3 This is a schematic diagram of the structure of the SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture of this application;

[0038] Figure 4 This is a schematic diagram of the structure of the JTAG_PIPE module;

[0039] Figure 5 It is a schematic diagram of the structure of the TAP_FSM module;

[0040] Figure 6 This is a schematic diagram of the structure of the JTAG_HUB module;

[0041] Figure 7 It is a schematic diagram of the structure of the TDR module;

[0042] Figure 8 It is the structural diagram of DR_PIPE module;

[0043] Fig. 9 This is a structural diagram of the TDO_MUX module. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0045] In the description of the present application, it should be noted that the terms "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. Unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0046] It should be noted that, in this application, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0047] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0048] First of all, it should be noted that Figure 1In the figure, JTAG PORT indicates JTAG port; ‌TCK‌ indicates test clock input, which is used to drive the operation of TAP (Test Access Port) controller; TRST‌_N indicates test reset, which is an input pin and is valid at low level; TMS‌ indicates test mode selection, which is used to control the conversion of TAP state machine and determine the working mode of JTAG interface; TDI‌ indicates test data input, and data is input into JTAG port through this pin; TDO‌ indicates test data output, and data is output from JTAG port through this pin; PHY_A, PHY_B, PHY_C, and PHY_D refer to different types of PHY, and PHY_A_0 ~ PHY_A_M represent multiple instantiations of the same PHY_A type, PHY_B_0 ~ PHY_B_N represent multiple instantiations of the same PHY_B type, PHY_C_0 ~ PHY_C_X represent multiple instantiations of the same PHY_C type, and PHY_D type has only one instantiation. Different types of PHY refer to PHYs with different functions, such as USB (Universal Serial Bus, Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, fast peripheral interconnect standard), DDR (Double Data Rate Synchronous Dynamic Random Access Memory), etc. Figure 2 In the JTAG debugging process, JTAG MUX refers to the multiplexer that switches different devices.

[0049] ‌On the first aspect, the embodiment of the present application provides a SoC PHY ATE serial-parallel hybrid scalable multi-level connection test architecture, which is implemented based on the JTAG Chain serial structure. The SoC PHY ATE serial-parallel hybrid scalable multi-level connection test architecture of the present application can improve the parallelism of PHY ATE tests, increase the JTAG Chain TCK frequency, simplify the JTAG custom instruction type, and realize a friendly small modular design.

[0050] In one embodiment, referring to Figure 3 , Figure 3 This is a schematic diagram of the structure of the SoC PHY ATE serial-parallel hybrid scalable multi-level connection test architecture of this application. Figure 3 As shown, in the SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture of the present application, the PHY access to be tested is implemented based on the preset access logic, and the preset access logic specifically includes:

[0051] Connect multiple PHY test interfaces of the same type in parallel through the JTAG_HUB module and connect them to the JTAG Chain via the JTAG_HUB.

[0052] Based on the type of PHY, if there is only one PHY of the current type, it is directly connected to the JTAG Chain when it is a JTAG test interface, and is connected to the JTAG Chain via the TAP_FSM module when it is a TDR test interface;

[0053] Based on the distance between access nodes in the JTAG Chain, insert the JTAG_PIPE module when the distance between two adjacent access nodes is greater than the preset distance;

[0054] The JTAG_HUB module is used to implement the parallel test control of the same type of PHY, the TAP_FSM module is used to parse the JTAG test interface input signal and extract the JTAG instruction, and the JTAG_PIPE module is used to optimize the timing.

[0055] Specifically, since the IP under test (i.e., PHY IP) may be distributed in various locations of the SoC, from a global perspective, the connection method of the JTAGChain is helpful for back-end implementation. The IP under test can be connected to the global JTAG Chain in different ways depending on whether it is of the same type.

[0056] For the same type or the same PHY, the test interfaces of the PHY are connected in parallel through the JTAG_HUB module, and then connected to the JTAG Chain via the JTAG_HUB module, for example Figure 3 PHY_A_0 ~ PHY_A_M, and PHY_B_0 ~ PHY_B_N in the JTAG test interface. If there is only one PHY of a certain type and it is a JTAG test interface, it can be directly connected to the JTAG Chain, for example Figure 3 If there is only one PHY of a certain type and it is a TDR (Test Data Register) test interface, it is connected to the JTAG Chain via the TAP_FSM module, for example Figure 3 If the distance between two access nodes on the JTAG Chain is far, you can insert the JTAG_PIPE module to increase the JTAG Chain TCK frequency. TCK and TRST_N are global signals and need to be routed to all JTAG Chain access nodes, while local modules can use the TCK gated clock depending on whether it is the object under test.

[0057] Furthermore, for the JTAG_PIPE module, its purpose is to optimize the timing. When the distance between two adjacent access nodes of the JTAG Chain is too long and the Timing is not satisfied, this module can be inserted. The insertion level needs to be set according to the Timing requirements, which is a hardware parameter. Figure 4 As shown in the figure, it is a schematic diagram of the structure of the JTAG_PIPE module. Figure 4 In the figure, the I after TDO represents input, O represents output, the I after TDI represents input, O represents output, and the I after TMS represents input, O represents output.

[0058] Furthermore, the TAP_FSM module is a standard module used to extract JTAG instructions (JTAG instructions include standard instructions and user-defined instructions) by parsing the input signal of the JTAG test interface, and also used to extract the JTAG DR (data register) control signal, and also used to return the TDO signal according to the serial input, and also used to generate a reset signal according to the TAP state. Figure 5 As shown in the figure, it is a schematic diagram of the structure of the TAP_FSM module. Figure 5 In the figure, Instruction indicates a standard or user-defined JTAG instruction, tap_reset indicates the reset signal of the TAP state machine, dr_update is a high-level pulse signal, indicating that the current state is the update state of DR, dr_shift is a high-level pulse signal, indicating that the current state is the shift state of DR, dr_capture is a high-level pulse signal, indicating that the current state is the capture state of DR, and ser_out indicates that one or more DR serial output signals are input to the TAP_FSM module after passing through the MUX (multiplexer).

[0059] See also Figure 6 As shown in the figure, it is a schematic diagram of the structure of the JTAG_HUB module. The JTAG_HUB module is connected to the JTAG Chain through the TAP_FSM module, the same type of PHY participating in the parallel test is specified through the TDR module, and the TDO signal fitting algorithm is specified through the TDR module.

[0060] For the TDR module, the TDR module uses a shift register to access the TAP DR, and each PHY connected to the JTAG_HUB module is connected to a corresponding TDR module to control or collect the test interface signals of the PHY. The TDR module includes two directions: RX (receive) and TX (transmit); TX is used to control the PHY test; RX is used to collect the output data of the PHY and return it in serial form. The DR register width is specified by a parameter, which is a hardware parameter. See Figure 7 As shown in the figure, it is a schematic diagram of the structure of the TDR module. Figure 7In the register, Select is a level signal, which indicates that the current DR is selected when it is high; Capture is a high-level pulse signal, indicating that the current state is the capture state of DR; Shift is a high-level pulse signal, indicating that the current state is the shift state of DR; Update is a high-level pulse signal, indicating that the current state is the update state of DR; TDRCLK indicates TCK or the gated clock of TCK; WRST_N indicates the synchronous reset signal of TRST_N or TRST_N under TDRCLK; WSI indicates the delay signal of TDI or TDI under TCK; TDO indicates the shift output signal of the current DR register; Capture_val indicates the capture value of the current DR, which is entered into the shift register in the capture state and sent to the upstream through TDO in the shift state; Update_val indicates the update value of the current DR, which shifts the value of WSI to the shift register in the shift state and records the value of the shift register in the update state.

[0061] Furthermore, for the JTAG_HUB module, when the distance between the TAP_FSM module and the TDR modules corresponding to each PHY connected to the JTAG_HUB module is greater than the set distance, a DR_PIPE module is inserted between the TAP_FSM module and the TDR module. The DR_PIPE module is used to optimize the timing. That is, when the distance between the TAP_FSM module and the TDR module is too large, a DR_PIPE module can be inserted to optimize the timing. See Figure 8 As shown in the figure, it is a schematic diagram of the structure of the DR_PIPE module. Figure 8 In the figure, TDRCLK represents TCK or the gated clock of TCK; WRST_N represents TRST_N or the synchronous reset signal of TRST_N under TDRCLK; WSI_I represents PIPE input, which is the delay signal of TDI or TDI under TCK; CAPTURE_I represents PIPE input, which is a high-level pulse signal, indicating that the current state is the capture state of DR; SHIFT_I represents PIPE input, which is a high-level pulse signal, indicating that the current state is the shift state of DR; UPDATE_I represents PIPE input, which is a high-level pulse signal, indicating that the current state is the update state of DR; WSI_O represents the PIPE output of WSI_I; CAPTURE_O represents the PIPE output of CAPTURE_I; SHIFT_O represents the PIPE output of SHIFT_I; UPDATE_O represents the PIPE output of UPDATE_I.

[0062] Furthermore, for the JTAG_HUB module, a TDO_MUX module is also provided on the TAP_FSM module, and the TDR modules corresponding to each PHY connected to the JTAG_HUB module are all connected to the TDO_MUX module; a TDR module is also connected to the TDO_MUX module for specifying a TDO signal fitting algorithm.

[0063] The TDO_MUX module is used to fit multiple groups of TDO signals into one TDO signal to implement TDO signal output fitting of parallel testing PHY. Specifically, the TDO_MUX module implements TDO signal fitting based on the TDO signal fitting algorithm; the TDO signal fitting algorithm includes performing AND (and operation) logic calculation on multiple groups of TDO signals, performing OR (or operation) logic calculation on multiple groups of TDO signals, outputting AND logic first and then outputting OR logic, and executing Debug mode; Debug mode is to output the values ​​of multiple groups of TDO signals one by one.

[0064] See also Fig. 9 As shown in the figure, it is a schematic diagram of the structure of the TDO_MUX module. Fig. 9 In the example, RST_N is TRST_N or the synchronous reset signal of TRST_N under CLK / TCK, and CLK is TCK or the gated clock of TCK.

[0065] Furthermore, for the JTAG_HUB module, a TDO_SEL module is provided between the TAP_FSM module and the TDO_MUX module, and between the TDO_MUX module and the TDR modules corresponding to each PHY connected to the JTAG_HUB module. A TDR module is also provided on the TDR module between the TAP_FSM module and the TDO_MUX module to specify the same type of PHYs participating in the parallel test.

[0066] The TDO_SEL module is used to select the TDO signal output within the same PHY, and to select a group of TDO signals from multiple groups of TDO signals for output.

[0067] The JTAG_HUB module is used to implement parallel test control of the same type or the same PHY. The following describes the specific functions that the JTAG_HUB module can implement:

[0068] (1) Access the JTAG Chain through the TAP_FSM module;

[0069] (2) The bypass function is realized through the TDR module, supporting JTAG bypass instructions and undefined instructions. Undefined instructions are bypassed by default;

[0070] (3) Customize the PHY_SEL command to specify the same type / same PHY to be tested in parallel through the TDR module;

[0071] (4) Customize the MUX_CAL instruction and specify the TDO signal fitting algorithm through the TDR module;

[0072] (5) Customize the SIG_SET instruction to set the signal of each PHY test interface through the TDR module, support the requirements of PHY Test for the test interface status, the test interface setting of each PHY needs to be controlled independently, and each PHY needs to have a corresponding TDR module;

[0073] (6) Other custom instructions, controlling or collecting the test interface signals of the PHY under test through the TDR module;

[0074] (7) PHY that supports JTAG test interface or TDR test interface;

[0075] (8) Implement TDO signal output fitting of parallel test PHY through TDO_MUX module;

[0076] (9) TDO_SEL is used to select the TDO signal output within the same PHY, which is selected by the current IR stage or DR stage and the current IR (instruction register) and DR contents.

[0077] It should be noted that the JTAG_HUB module is built up of basic modules. Most of the basic module interfaces are static signals. The timing problem of non-static signals can be solved by adding DR_PIPE. Therefore, the JTAG_HUB module can be split according to actual needs without causing timing problems. Figure 6 In the SIG_SET, the current TDR module implements the PHY test interface signal setting, MUX_CAL indicates that the current TDR module implements the TDO signal fitting algorithm selection for fitting multiple groups of TDO signals into one TDO signal, PHY_SEL indicates that the current TDR module implements the selection of the PHY to be tested, and PHY_APP indicates that the current TDR module implements the application requirements unique to the current PHY, which may be multiple TDR modules, depending on the application.

[0078] The SoC PHY ATE serial-parallel hybrid scalable multi-level connection test architecture of the embodiment of the present application supports a multi-level connection SoC PHY test architecture for parallel testing, and can be expanded according to actual needs. It can solve the problem of parallel testing of the same type of JTAG / TDR interface PHY, and can increase the SoC JTAG Chain TCK frequency by inserting multi-level PIPE, and can realize concise standardized custom JTAG instructions for parallel requirements. It adopts a building block module design to flexibly realize the internal physical position, timing and connection requirements of the SoC, and adapts to the SoC PHY test requirements through standardized interface module splicing, which can effectively solve the problem of PHY test duration.

[0079] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit "first", "second" and "third" to different types.

[0080] In the description of the embodiments of the present application, "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a specific way.

[0081] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; the “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0082] In some processes described in the embodiments of the present application, multiple operations or steps that appear in a specific order are included, but it should be understood that these operations or steps may not be executed in the order in which they appear in the embodiments of the present application or in parallel, and the sequence number of the operation is only used to distinguish the different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed in sequence or in parallel, and these operations or steps may be combined.

[0083] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD) as described above, and includes a number of instructions for a terminal device to execute the methods described in each embodiment of the present application.

[0084] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A SoC PHY ATE serial-parallel hybrid scalable multi-level connection test architecture based on the JTAG Chain serial structure, characterized in that: The SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture implements the PHY access to be tested based on the preset access logic, and the preset access logic specifically includes: Connect multiple PHY test interfaces of the same type in parallel through the JTAG_HUB module, and connect them to the JTAG Chain via the JTAG_HUB module; Based on the type of PHY, if there is only one PHY of the current type, it is directly connected to the JTAG Chain when it is a JTAG test interface, and is connected to the JTAG Chain via the TAP_FSM module when it is a TDR test interface; Based on the distance between access nodes in the JTAG Chain, insert the JTAG_PIPE module when the distance between two adjacent access nodes is greater than the preset distance; The JTAG_HUB module is used to implement parallel test control of the same type of PHYs, the TAP_FSM module is used to parse the JTAG test interface input signal and extract the JTAG instructions, and the JTAG_PIPE module is used to optimize the timing.

2. A SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture as claimed in claim 1, characterized in that: The TAP_FSM module is also used to extract the JTAG DR control signal, return the TDO signal according to the serial input, and generate a reset signal according to the TAP state.

3. A SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture as claimed in claim 2, characterized in that: The JTAG_HUB module is connected to the JTAG Chain through the TAP_FSM module, the same type of PHY participating in the parallel test is specified through the TDR module, and the TDO signal fitting algorithm is specified through the TDR module; The TDR module implements the access of TAP DR through shift register, and each PHY connected to the JTAG_HUB module is correspondingly connected to a TDR module for controlling or collecting the test interface signal of the PHY.

4. A SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture as claimed in claim 3, characterized in that: The TDR module includes two directions: RX and TX; The TX is used to control the PHY test; The RX is used to collect the output data of the PHY and return it in a serial manner.

5. The SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture as claimed in claim 3, characterized in that: When the distance between the TDR modules corresponding to each PHY connected to the TAP_FSM module and the JTAG_HUB module is greater than the set distance, insert the DR_PIPE module between the TAP_FSM module and the TDR module; The DR_PIPE module is used to optimize timing.

6. A SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture as claimed in claim 3, characterized in that: The TAP_FSM module is also provided with a TDO_MUX module, and the TDR modules corresponding to each PHY connected to the JTAG_HUB module are all connected to the TDO_MUX module; The TDO_MUX module is used to fit multiple groups of TDO signals into one TDO signal, so as to achieve TDO signal output fitting of parallel testing PHY.

7. A SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture as claimed in claim 6, characterized in that: The TDO_MUX module implements the fitting of the TDO signal based on the TDO signal fitting algorithm; The TDO signal fitting algorithm includes performing AND logic calculation on multiple groups of TDO signals, performing OR logic calculation on multiple groups of TDO signals, outputting AND logic first and then outputting OR logic, and executing Debug mode; The Debug mode is to output multiple groups of TDO signal values ​​one by one.

8. The SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture as claimed in claim 6, characterized in that: A TDO_SEL module is provided between the TAP_FSM module and the TDO_MUX module, and between the TDO_MUX module and the TDR modules corresponding to each PHY connected to the JTAG_HUB module; The TDO_SEL module is used to select the TDO signal output within the same PHY, and select a group of TDO signals from multiple groups of TDO signals for output.

9. The SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture as claimed in claim 3, characterized in that: The JTAG_HUB module supports the PHY of the JTAG test interface or the TDR test interface.

10. The SoC PHY ATE serial-parallel hybrid scalable multi-stage connection test architecture as claimed in claim 3, characterized in that: The JTAG_HUB module is also used to implement the bypass function through the TDR module, and supports JTAG bypass instructions and undefined instructions.

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