Circuit breaker opening and closing speed detection method based on DSP-FPGA

Abstract

The invention provides a DSP-FPGA-based circuit breaker opening and closing speed detection method and system, a storage medium and electronic equipment, and relates to the field of circuit breaker opening and closing speed detection. On the premise that the internal structure of a circuit breaker operating mechanism does not need to be changed, a non-contact rapid detection method is designed to accurately calculate the speed curve of opening and closing of the circuit breaker by adopting a machine vision technology. Moreover, the efficient calculation capability of the DSP and the flexible data transmission capability of the FPGA are fully utilized, and efficient data processing and transmission are realized. In addition, the system is deployed on an embedded platform, is convenient for field application, and is less affected by environmental conditions where the equipment is located.

Description

Technical Field

[0001] The present invention relates to the field of circuit breaker opening and closing speed detection, and in particular to a circuit breaker opening and closing speed detection method, system, storage medium and electronic equipment based on DSP-FPGA. Background Art

[0002] High-voltage circuit breakers play an important role in control and protection in power systems, and are also the switch devices that can cope with the most types of tasks and needs in power systems. If the opening and closing speed is too high, it will cause increased bounce. If the bounce is too large, the repeated collision between the moving and static contacts may cause arcing and aggravate the wear of the contacts, causing mechanical failure of the high-voltage circuit breaker. If the opening and closing speed is too low, the fault current cannot be cut off, which may cause accidents such as over-tripping or explosion, and even cause system protection failure. Therefore, the opening and closing speed characteristics of high-voltage circuit breakers are necessary factors for analyzing their breaking current performance and safety status.

[0003] In related technologies, some studies have proposed using a high-speed camera to capture video of the movement of the connecting rod when the circuit breaker is opened and closed, and using a template matching method to track the connecting rod to obtain the motion trajectory, and finally calculating the opening and closing speed of the circuit breaker. Compared with traditional measurement methods, there is no need to change the internal structure of the circuit breaker operating mechanism, and non-contact measurement can be achieved.

[0004] However, although the above solution achieves tracking, the use of high-speed cameras to collect videos is costly and complicated to operate. In addition, the matching template used is not much different from the background color, matching is difficult, the error is high, and it cannot adapt to miniaturized and low-power application scenarios. Summary of the invention

[0005] 1. Technical issues to be resolved

[0006] In view of the shortcomings of the prior art, the present invention provides a DSP-FPGA-based circuit breaker opening and closing speed detection method, system, storage medium and electronic device, which solve the technical problems of high cost and complex operation of using high-speed cameras to collect videos, and the matching template and background color are not very different, matching is difficult, the error is high, and it cannot adapt to miniaturized and low-power application scenarios.

[0007] (II) Technical solution

[0008] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0009] A circuit breaker opening and closing speed detection method based on DSP-FPGA, deployed on an embedded platform, includes:

[0010] After receiving the shooting instruction, the FPGA controls the camera module to collect the color video sequence of the circuit breaker when it is about to open and close, and transmits it to the DSP;

[0011] Based on the video sequence, the operating mechanism is tracked by DSP using a filtering algorithm combined with a background differentiation model, and a travel curve of the operating mechanism is obtained and analyzed to obtain a speed curve of the circuit breaker opening and closing;

[0012] The method of tracking the operating mechanism by using a filtering algorithm combined with a background discrimination model includes:

[0013] Selecting a target area of ​​the operating mechanism on the first video frame, recording an initial target position of the target area, and constructing an initial filter model; wherein the filter model includes correlation filters based on HOG features and CN features respectively;

[0014] Based on the target position of the previous video frame, multiple rectangular windows are set as search areas on the current video frame, HOG features and CN features are extracted in the search area, and background distinguishing features are extracted in the search area using the background distinguishing model;

[0015] Based on the HOG features, CN features and background distinguishing features of the current video frame, combined with the previous filter model, update the target position on the current video frame;

[0016] Cutting off the current video frame, based on the target position on each video frame, the current filter model is optimized for tracking the target position of the next video frame.

[0017] Preferably, the circuit breaker opening and closing speed detection method further includes:

[0018] The speed curve is returned to the FPGA through the DSP, the corresponding data is stored and the display is controlled through the FPGA, and the data is uploaded to the host computer.

[0019] Preferably, the background differentiation model is based on a Bayesian filter.

[0020] Preferably, the HOG feature, CN feature and background distinguishing feature based on the current video frame are combined with the previous filter model to update the target position on the current video frame; it is expressed as:

[0021]

[0022] Where, the subscript t represents the index of the video frame; t represents the tth video frame; p t Indicates I t The target area where the target position is located; S t Indicates I t The set of all possible rectangular windows; T(I t ,p) indicates that in It The extracted HOG features, CN features and background distinguishing features; θ t-1 Represents the parameters of the t-1th filter model;

[0023] f(T(I t ,p);θ t-1 ) represents the calculation of the score for any rectangular window p, and the calculation process is expressed as:

[0024] f(I t )=c tmpl f tmpl (I t )+c hist f hist (I t )+(1-c tmpl -c hist )f qf (I t ) (2)

[0025] Among them, f tmpl (I t ), f hist (I t ), f qf (I t ) respectively represent and I t The corresponding HOG feature response score, CN feature response score, and background distinguishing feature histogram score; c tmpl 、c hist The feature coefficients representing the response scores of the HOG feature and the CN feature, respectively.

[0026] Preferably, the loss function of the filter model is:

[0027]

[0028] Where θ represents the parameters of the filter model; T is the total number of video frames; w t is the weighting coefficient; l(I t ,p t ,θ) represents the t The loss function includes:

[0029]

[0030] Wherein, the subscripts tmpl and hist represent the correlation filters based on HOG features and CN features respectively; tmpl (I t ,p t ,h),l hist (I t ,p t,h) represent the loss function of the correlation filter; h, β represent the parameters of the correlation filter; q tmpl ,q hist are the parameter dimension indices in the correlation filter, and the total dimension is Q. Represent the corresponding multi-channel feature maps The qth dimension parameter of tmpl ,y hist They represent the expected output of the correlation filter using Gaussian distribution; tmpl , hist They represent the regularization coefficients of the correlation filter respectively.

[0031] Preferably, the parameters of the current filter model are optimized by minimizing the loss function; expressed as:

[0032] θ t =argmin θ∈Ω {L(θ;I t )+λR(θ)} (5)

[0033] Among them, θ t The parameters of the t-th filter model; Ω is the parameter model space; λ represents the regularization coefficient, and R(θ) is the regularization term.

[0034] A circuit breaker opening and closing speed detection system based on DSP-FPGA, deployed on an embedded platform, includes:

[0035] The acquisition module is used to control the camera module to acquire the color video sequence of the circuit breaker when it is about to open and close after the FPGA receives the shooting instruction, and transmit it to the DSP;

[0036] A tracking module is used to track the operating mechanism based on the video sequence by using a filtering algorithm combined with a background differentiation model through DSP, and obtain and analyze the travel curve of the operating mechanism to obtain the speed curve of the circuit breaker opening and closing;

[0037] The method of tracking the operating mechanism by using a filtering algorithm combined with a background discrimination model includes:

[0038] Selecting a target area of ​​the operating mechanism on the first video frame, recording an initial target position of the target area, and constructing an initial filter model; wherein the filter model includes correlation filters based on HOG features and CN features respectively;

[0039] Based on the target position of the previous video frame, multiple rectangular windows are set as search areas on the current video frame, HOG features and CN features are extracted in the search area, and background distinguishing features are extracted in the search area using the background distinguishing model;

[0040] Based on the HOG features, CN features and background distinguishing features of the current video frame, combined with the previous filter model, update the target position on the current video frame;

[0041] Cutting off the current video frame, based on the target position on each video frame, the current filter model is optimized for tracking the target position of the next video frame.

[0042] Preferably, the circuit breaker opening and closing speed detection system further includes:

[0043] The display module is used to return the speed curve to the FPGA through the DSP, store the corresponding data through the FPGA and control the display, and upload the data to the host computer.

[0044] A storage medium stores a computer program for detecting the opening and closing speed of a circuit breaker based on DSP-FPGA, wherein the computer program enables a computer to execute the circuit breaker opening and closing speed detection method as described above.

[0045] An electronic device, comprising:

[0046] One or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the programs include a method for executing the circuit breaker opening and closing speed detection method as described above.

[0047] (III) Beneficial effects

[0048] The present invention provides a circuit breaker opening and closing speed detection method, system, storage medium and electronic device based on DSP-FPGA. Compared with the prior art, it has the following beneficial effects:

[0049] The present invention adopts machine vision technology and designs a non-contact rapid detection method to accurately calculate the speed curve of the circuit breaker opening and closing without changing the internal structure of the circuit breaker operating mechanism. In addition, the efficient computing power of DSP and the flexible data transmission capacity of FPGA are fully utilized to achieve efficient data processing and transmission. In addition, the present invention is deployed on an embedded platform, which is convenient for field application and is less affected by the environmental conditions of the equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 A schematic diagram of a circuit breaker opening and closing speed detection scenario provided in an embodiment of the present invention.

[0052] Figure 2 A flow chart of a circuit breaker opening and closing speed detection method based on DSP-FPGA is provided in an embodiment of the present invention.

[0053] Figure 3 A schematic diagram of a DSP-FPGA embedded architecture provided in an embodiment of the present invention.

[0054] Figure 4 A block diagram of a circuit breaker opening and closing speed detection method provided by an embodiment of the present invention.

[0055] Figure 5 A block diagram of another circuit breaker opening and closing speed detection method provided by an embodiment of the present invention.

[0056] Figure numerals: circuit breaker SF6 gas chamber 1, grounding switch 2, grounding switch control box 3, circuit breaker operating mechanism observation window 4, circuit breaker opening and closing control box 5, camera module 6, FPGA+DSP processing system 7, host computer 8. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are clearly and completely described. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] The embodiments of the present application provide a DSP-FPGA-based circuit breaker opening and closing speed detection method, system, storage medium and electronic device to solve the technical problems of high cost and complex operation of using high-speed cameras to collect videos, and the matching templates used have little difference from the background color, making matching difficult, with high errors, and being unable to adapt to miniaturized and low-power application scenarios.

[0059] The technical solution in the embodiment of the present application is to solve the above technical problems, and the overall idea is as follows:

[0060] The embodiment of the present invention is used for detecting the opening and closing speed of a circuit breaker. Figure 1 As shown, Figure 1 A schematic diagram of a circuit breaker opening and closing speed detection scenario is given, and the provided method is deployed on an embedded platform, involving software and hardware parts. Among them:

[0061] For the software part, one of the key points is how to track the circuit breaker actuator in the video frame. Figure 2 As shown, an improved correlation filtering algorithm (i.e., a filtering algorithm combined with a background discrimination model) is used to track the circuit breaker operating mechanism area. The process of this method is divided into four key stages: initialization, target detection and response map generation, target position update, and model update.

[0062] In the initial stage, the algorithm first selects the initial position of the target. Based on the target information, the algorithm constructs and trains the initial filter model, which will be continuously updated in the subsequent tracking process to match the changes of the target. After entering the tracking process, the algorithm sets the search area based on the target position predicted by the previous video frame and extracts image features in this area. By performing operations with the trained correlation filter model, the estimated position of the target in the current frame is indicated, and the position information of the target is updated accordingly. According to the target state (including position and size, etc.) of the current video frame, the algorithm further adjusts and optimizes the correlation filter model so that it can adapt to changes in the appearance and size of the target.

[0063] As for the hardware part, the embodiment of the present invention introduces a DSP-FPGA embedded system, which fully utilizes the efficient computing capability of DSP and the flexible data transmission capability of FPGA. Figure 3 As shown in the figure, data instruction parsing and target tracking algorithm calculation functions are implemented in DSP, and DSP also returns instruction execution results to FPGA. FPGA mainly plays the role of data transmission, including image frames, data instructions, models and instruction execution results. DSP and FPGA communicate through SRIO, and the communication between the host computer and FPGA uses RS232 serial port. FPGA displays the instruction execution results and images on the display, and the host computer sends execution data instructions and receives results.

[0064] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0065] Embodiment 1:

[0066] like Figure 4 As shown, a circuit breaker opening and closing speed detection method based on DSP-FPGA is deployed on an embedded platform, including:

[0067] S1. After receiving the shooting instruction, the FPGA controls the camera module to collect the color video sequence of the circuit breaker when it is about to open and close, and transmits it to the DSP;

[0068] S2. Based on the video sequence, the operating mechanism is tracked by DSP using a filtering algorithm combined with a background differentiation model, and a travel curve of the operating mechanism is acquired and analyzed to obtain a speed curve of the circuit breaker opening and closing;

[0069] The method of tracking the operating mechanism by using a filtering algorithm combined with a background discrimination model includes:

[0070] S10, selecting a target area of ​​the operating mechanism on the first video frame, recording an initial target position of the target area, and constructing an initial filter model; wherein the filter model includes correlation filters based on HOG features and CN features respectively;

[0071] S20, based on the target position of the previous video frame, multiple rectangular windows are set as search areas on the current video frame, HOG features and CN features are extracted in the search area, and background distinguishing features are extracted in the search area using the background distinguishing model;

[0072] S30, based on the HOG feature, CN feature and background distinguishing feature of the current video frame, combined with the previous filter model, updating the target position on the current video frame;

[0073] S40, ending the current video frame and optimizing the current filter model based on the target position on each video frame to track the target position of the next video frame.

[0074] In an optional embodiment, if Figure 5 As shown, the circuit breaker opening and closing speed detection method provided by the embodiment of the present invention also includes:

[0075] S3, returning the speed curve to FPGA through DSP, storing corresponding data through FPGA and controlling the display, and uploading the data to the host computer.

[0076] The embodiment of the present invention adopts machine vision technology to design a non-contact rapid detection method to accurately calculate the speed curve of the circuit breaker opening and closing without changing the internal structure of the circuit breaker operating mechanism. In addition, the efficient computing power of DSP and the flexible data transmission capacity of FPGA are fully utilized to achieve efficient data processing and transmission. In addition, the present invention is deployed on an embedded platform, which is convenient for field application and is less affected by the environmental conditions of the equipment.

[0077] Next, we will introduce the steps of the above scheme:

[0078] In step S1, after receiving the shooting instruction, the FPGA controls the camera module to collect a color video sequence when the circuit breaker is about to open or close, and transmits it to the DSP.

[0079] In this step, if Figure 3 As shown, the camera module collects video frames and transmits them to the FPGA. The FPGA receives data instructions sent by the host computer, packages the received video frames and data instructions, and sends them to the DSP through the SRIO interface.

[0080] In step S2, based on the video sequence, the operating mechanism is tracked by DSP using a filtering algorithm combined with a background differentiation model, and the travel curve of the operating mechanism is acquired and analyzed to obtain the speed curve of the circuit breaker opening and closing.

[0081] In this step, if Figure 3 As shown, after receiving the image frame and data instruction sent by FPGA, DSP parses the data instruction and executes the instruction.

[0082] In actual tracking scenarios, due to the fast opening and closing actions of circuit breakers, short opening and closing times, and the complex and changeable substation environment, manual marking of tracking frames during on-site operations will cause marking errors, thereby affecting the normal tracking of the algorithm. In order to reduce the marking errors caused by manual marking of tracking frames, an embodiment of the present invention provides a model training matching function.

[0083] Accordingly, in this step, a filtering algorithm combined with a background discrimination model is used to track the operating mechanism, including the following sub-steps:

[0084] S10, selecting a target area of ​​the operating mechanism on the first video frame, recording an initial target position of the target area, and constructing an initial filter model; wherein the filter model includes correlation filters based on HOG features and CN features respectively;

[0085] S20, based on the target position of the previous video frame, multiple rectangular windows are set as search areas on the current video frame, HOG features and CN features are extracted in the search area, and background distinguishing features are extracted in the search area using the background distinguishing model;

[0086] S30, based on the HOG feature, CN feature and background distinguishing feature of the current video frame, combined with the previous filter model, updating the target position on the current video frame;

[0087] S40, ending the current video frame and optimizing the current filter model based on the target position on each video frame to track the target position of the next video frame.

[0088] Specifically, in sub-step S10, a target area of ​​the operating mechanism is selected on the first video frame, an initial target position of the target area is recorded, and an initial filter model is constructed; wherein the filter model includes correlation filters based on HOG features and CN features, respectively.

[0089] The correlation filter tracking algorithm requires the target coordinate information to be known in the first video frame for subsequent tracking. Therefore, this substep constructs a training set by densely collecting positive samples (the target itself) and negative samples (background or other non-target areas) around the target. These samples are used to train the classifier to distinguish between the target and the background. And construct the following loss function:

[0090]

[0091] Where θ represents the parameters of the filter model; T is the total number of video frames; w t is the weighting coefficient; p t Indicates I t The target area where the target location is located

[0092] l(I t ,p t ,θ) represents the t The loss function includes:

[0093]

[0094] The parameter solutions are obtained through two independent ridge regression problems to improve the speed and timeliness of the correlation filter. The subscripts tmpl and hist represent the correlation filter based on HOG features and CN features respectively; l tmpl (I t ,p t ,h),l hist (I t ,p t ,h) represent the loss function of the correlation filter; h, β represent the parameters of the correlation filter; q tmpl ,q hist are the parameter dimension indices in the correlation filter, and the total dimension is Q. Represent the corresponding multi-channel feature maps The qth dimension parameter of tmpl ,y hist They represent the expected output of the correlation filter using Gaussian distribution; tmpl , hist They represent the regularization coefficients of the correlation filter respectively.

[0095] It can be understood that the model can be subsequently updated by minimizing the above loss function, which measures the difference between the predicted output and the true label.

[0096] In sub-step S20, based on the target position of the previous video frame, multiple rectangular windows are set as search areas on the current video frame, HOG features and CN features are extracted within the search area, and the background differentiation model is used to extract background differentiation features within the search area.

[0097] It should be noted that the image features designed in the embodiment of the present invention include HOG features, CN features and background distinguishing features.

[0098] Regarding the HOG (Histogram of Oriented Gradient) feature, it constructs the feature by calculating and counting the gradient direction histogram of the local area of ​​the image. The extraction method is:

[0099] First, the color video frames are converted into grayscale images to simplify subsequent processing, and then the grayscale images are normalized by applying gamma correction to reduce the influence of illumination changes and noise.

[0100] Next, the magnitude and direction of the gradient of each pixel are calculated, and these gradients are obtained by convolution with a simple difference operator.

[0101] Then, the grayscale image is divided into small square cells. In these cells, a histogram is constructed by weighting the gradient direction of the pixel points. In order to improve the robustness of the feature, several adjacent cells are combined into a block. The number of cells in each block is a free parameter, and the gradient strength is normalized within the block.

[0102] Finally, the gradient histogram information collected in all normalized blocks is combined to form the HOG feature descriptor representing the original image, which can be used for object recognition tasks.

[0103] The response function of the HOG feature is:

[0104]

[0105] Among them, Δ is the size of the sample grid, the solution is the position coordinate of a pixel in the image, h is the model parameter, φ x is the image gradient feature.

[0106] Regarding the CN (Color Names) feature, it is a feature description method based on human perception of color. CN is a very practical image feature extraction method, which can not only effectively characterize the image content, but also has strong distinguishing ability.

[0107] The response function of the CN feature is:

[0108]

[0109] Where H is a finite grid, β is a model parameter, and ψ x is the image color feature.

[0110] Regarding the background distinguishing features, it is additionally noted that the background area and the target area are similar in the video frame tracking the circuit breaker operating mechanism (or circuit breaker manipulator).

[0111] In order to distinguish target pixels from background pixels, an embodiment of the present invention proposes a background distinction model. The model is based on a Bayesian filter. The image is first converted into a grayscale histogram, and then a structure model is constructed for the grayscale information of the target in the histogram. The simplified formula for the probability that the pixel x belongs to the target is:

[0112]

[0113] Among them, B is the background pixel area, A is the target pixel area, l x is the pixel brightness value.

[0114] Search for pixel x in the area and calculate its probability P of belonging to the target object. t (x), and calculate the integral graph under the current probability, and the histogram score is:

[0115]

[0116] In sub-step S30, based on the HOG features, CN features and background distinguishing features of the current video frame, combined with the previous filter model, the target position on the current video frame is updated; it is expressed as:

[0117]

[0118] Where, the subscript t represents the index of the video frame; t represents the tth video frame; p t I t The target area where the target position is located; S t I t The set of all possible rectangular windows; T(I t ,p) indicates that in I t The extracted HOG features, CN features and background distinguishing features; θ t-1 Represents the parameters of the t-1th filter model;

[0119] f(T(I t ,p);θ t-1 ) indicates that the score is calculated for any rectangular window p. The larger the score, the more similar it is to the target. The calculation process is expressed as:

[0120] f(I t )=ctmpl f tmpl (I t )+c hist f hist (I t )+(1-c tmpl -c hist )f qf (I t ) (8)

[0121] Among them, f tmpl (I t ), f hist (I t ), f qf (I t ) respectively represent and I t The corresponding HOG feature response score, CN feature response score, and background distinguishing feature histogram score; c tmpl 、c hist The feature coefficients representing the response scores of the HOG feature and the CN feature, respectively.

[0122] In particular, when the shape of the tracked target changes significantly, such as changes in the size of the tracked target, in-plane rotation, and out-of-plane rotation, the robustness of the CN feature is better than that of the HOG feature; when the target shape does not change much, the robustness of the HOG feature to illumination changes and rapid motion is better than that of the CN feature. The target tracked by the embodiment of the present invention is a high-voltage circuit breaker robot arm. When the robot arm moves in opening and closing, the degree of shape change is small. However, since the substation site is mostly outdoors and maintenance is mostly carried out during the day, there is sunlight and reflection from the high-voltage circuit breaker casing, and the brightness changes significantly during movement. Taking the above issues into consideration, when selecting the feature coefficient, the corresponding weight of the HOG feature should be higher than the CN feature response. Therefore, the HOG feature coefficient c can be used as an example. tmpl is 0.45, and the characteristic coefficient c of CN hist Set to 0.25.

[0123] In sub-step S40, the current video frame is terminated, and based on the target position on each video frame, the current filter model is optimized to track the target position of the next video frame; it is expressed as:

[0124] θ t =argmin θ∈Ω {L(θ;I t )+λR(θ)} (9)

[0125] Among them, θ t The parameters of the t-th filter model; Ω is the parameter model space; λ represents the regularization coefficient, and R(θ) is the regularization term.

[0126] In step S3, the speed curve is returned to the FPGA through the DSP, the corresponding data is stored and the display is controlled through the FPGA, and the data is uploaded to the host computer.

[0127] In this step, if Figure 3 As shown, DSP returns the result after executing the instruction, FPGA receives the result, displays it on the monitor, and uploads it to the host computer.

[0128] So far, the embodiment of the present invention has completed the entire process of the circuit breaker opening and closing speed detection method based on DSP-FPGA.

[0129] Embodiment 2:

[0130] The embodiment of the present invention provides a circuit breaker opening and closing speed detection system based on DSP-FPGA, which is deployed on an embedded platform and includes:

[0131] The acquisition module is used to control the camera module to acquire the color video sequence of the circuit breaker when it is about to open and close after the FPGA receives the shooting instruction, and transmit it to the DSP;

[0132] A tracking module is used to track the operating mechanism based on the video sequence by using a filtering algorithm combined with a background differentiation model through DSP, and obtain and analyze the travel curve of the operating mechanism to obtain the speed curve of the circuit breaker opening and closing;

[0133] The method of tracking the operating mechanism by using a filtering algorithm combined with a background discrimination model includes:

[0134] Selecting a target area of ​​the operating mechanism on the first video frame, recording an initial target position of the target area, and constructing an initial filter model; wherein the filter model includes correlation filters based on HOG features and CN features respectively;

[0135] Based on the target position of the previous video frame, multiple rectangular windows are set as search areas on the current video frame, HOG features and CN features are extracted in the search area, and background distinguishing features are extracted in the search area using the background distinguishing model;

[0136] Based on the HOG features, CN features and background distinguishing features of the current video frame, combined with the previous filter model, update the target position on the current video frame;

[0137] Cutting off the current video frame, based on the target position on each video frame, the current filter model is optimized for tracking the target position of the next video frame.

[0138] In an optional implementation manner, the circuit breaker opening and closing speed detection system provided by the embodiment of the present invention further includes:

[0139] The display module is used to return the speed curve to the FPGA through the DSP, store the corresponding data through the FPGA and control the display, and upload the data to the host computer.

[0140] Embodiment 3:

[0141] An embodiment of the present invention provides a storage medium storing a computer program for detecting the opening and closing speed of a circuit breaker based on DSP-FPGA, wherein the computer program enables a computer to execute the circuit breaker opening and closing speed detection method as described in Example 1.

[0142] Embodiment 4:

[0143] An embodiment of the present invention provides an electronic device, including:

[0144] One or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the programs include a method for executing the circuit breaker opening and closing speed detection method as described in Example 1.

[0145] It can be understood that the circuit breaker opening and closing speed detection system, storage medium and electronic device based on DSP-FPGA provided in the embodiment of the present invention correspond to the circuit breaker opening and closing speed detection method based on DSP-FPGA provided in the embodiment of the present invention. The explanation, examples and beneficial effects of the relevant contents can refer to the corresponding parts in the circuit breaker opening and closing speed detection method, which will not be repeated here.

[0146] In summary, compared with the prior art, the present invention has the following beneficial effects:

[0147] The embodiment of the present invention adopts machine vision technology to design a non-contact rapid detection method to accurately calculate the speed curve of the circuit breaker opening and closing without changing the internal structure of the circuit breaker operating mechanism. In addition, the efficient computing power of DSP and the flexible data transmission capacity of FPGA are fully utilized to achieve efficient data processing and transmission. In addition, the present invention is deployed on an embedded platform, which is convenient for field application and is less affected by the environmental conditions of the equipment.

[0148] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0149] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A circuit breaker opening and closing speed detection method based on DSP-FPGA, characterized in that: Deployed on embedded platforms, including: After receiving the shooting instruction, the FPGA controls the camera module to collect the color video sequence of the circuit breaker when it is about to open and close, and transmits it to the DSP; Based on the video sequence, the operating mechanism is tracked by DSP using a filtering algorithm combined with a background differentiation model, and a travel curve of the operating mechanism is obtained and analyzed to obtain a speed curve of the circuit breaker opening and closing; The method of tracking the operating mechanism by using a filtering algorithm combined with a background discrimination model includes: Selecting a target area of ​​the operating mechanism on the first video frame, recording an initial target position of the target area, and constructing an initial filter model; wherein the filter model includes correlation filters based on HOG features and CN features respectively; Based on the target position of the previous video frame, multiple rectangular windows are set as search areas on the current video frame, HOG features and CN features are extracted in the search area, and background distinguishing features are extracted in the search area using the background distinguishing model; Based on the HOG features, CN features and background distinguishing features of the current video frame, combined with the previous filter model, update the target position on the current video frame; Cutting off the current video frame, based on the target position on each video frame, the current filter model is optimized for tracking the target position of the next video frame.

2. The circuit breaker opening and closing speed detection method according to claim 1, characterized in that: Also includes: The speed curve is returned to the FPGA through the DSP, the corresponding data is stored and the display is controlled through the FPGA, and the data is uploaded to the host computer.

3. The circuit breaker opening and closing speed detection method according to claim 1 or 2, characterized in that: The background differentiation model is based on a Bayesian filter.

4. The circuit breaker opening and closing speed detection method according to claim 1, characterized in that: The HOG feature, CN feature and background distinguishing feature of the current video frame are combined with the previous filter model to update the target position on the current video frame; it is expressed as: Where, the subscript t represents the index of the video frame; t represents the tth video frame; p t Indicates I t The target area where the target position is located; S t Indicates I t The set of all possible rectangular windows; T(I t ,p) indicates that in I t The extracted HOG features, CN features and background distinguishing features; θ t-1 Represents the parameters of the t-1th filter model; f(T(I t ,p);θ t-1 ) represents the calculation of the score for any rectangular window p, and the calculation process is expressed as: f(I t )=c tmpl f tmpl (I t )+c hist f hist (I t )+(1-c tmpl -c hist )f qf (I t ) (2) Among them, f tmpl (I t ), f hist (I t ), f qf (I t ) respectively represent and I t The corresponding HOG feature response score, CN feature response score, and background distinguishing feature histogram score; c tmpl 、c hist The feature coefficients representing the response scores of the HOG feature and the CN feature, respectively.

5. The circuit breaker opening and closing speed detection method according to claim 4, characterized in that: The loss function of the filter model is: Where θ represents the parameters of the filter model; T is the total number of video frames; w t is the weighting coefficient; l(I t ,p t ,θ) represents the t The loss function includes: Wherein, the subscripts tmpl and hist represent the correlation filters based on HOG features and CN features respectively; tmpl (I t ,p t ,h),l hist (I t ,p t ,h) represent the loss function of the correlation filter; h, β represent the parameters of the correlation filter; q tmpl ,q hist are the parameter dimension indices in the correlation filter, and the total dimension is Q. Represent the corresponding multi-channel feature maps The qth dimension parameter of tmpl ,y hist They represent the expected output of the correlation filter using Gaussian distribution; tmpl , hist They represent the regularization coefficients of the correlation filter respectively.

6. The circuit breaker opening and closing speed detection method according to claim 5, characterized in that: By minimizing the loss function, the parameters of the current filter model are optimized; expressed as: i t =argmin θ∈Ω {L(θ;I t )+λR(θ)} (5) Among them, θ t The parameters of the t-th filter model; Ω is the parameter model space; λ represents the regularization coefficient, and R(θ) is the regularization term.

7. A circuit breaker opening and closing speed detection system based on DSP-FPGA, characterized in that: Deployed on embedded platforms, including: The acquisition module is used to control the camera module to acquire the color video sequence of the circuit breaker when it is about to open and close after the FPGA receives the shooting instruction, and transmit it to the DSP; A tracking module is used to track the operating mechanism based on the video sequence by using a filtering algorithm combined with a background differentiation model through DSP, and obtain and analyze the travel curve of the operating mechanism to obtain the speed curve of the circuit breaker opening and closing; The method of tracking the operating mechanism by using a filtering algorithm combined with a background discrimination model includes: Selecting a target area of ​​the operating mechanism on the first video frame, recording an initial target position of the target area, and constructing an initial filter model; wherein the filter model includes correlation filters based on HOG features and CN features respectively; Based on the target position of the previous video frame, multiple rectangular windows are set as search areas on the current video frame, HOG features and CN features are extracted in the search area, and background distinguishing features are extracted in the search area using the background distinguishing model; Based on the HOG features, CN features and background distinguishing features of the current video frame, combined with the previous filter model, update the target position on the current video frame; Cutting off the current video frame, based on the target position on each video frame, the current filter model is optimized for tracking the target position of the next video frame.

8. The circuit breaker opening and closing speed detection system according to claim 7, characterized in that: Also includes: The display module is used to return the speed curve to the FPGA through the DSP, store the corresponding data through the FPGA and control the display, and upload the data to the host computer.

9. A storage medium, characterized in that: The computer program for detecting the opening and closing speed of a circuit breaker based on DSP-FPGA is stored therein, wherein the computer program enables the computer to execute the circuit breaker opening and closing speed detection method according to any one of claims 1 to 6.

10. An electronic device, characterized in that: include: one or more processors; Memory; and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the programs include programs for executing the circuit breaker opening and closing speed detection method according to any one of claims 1 to 6.

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