Low-dropout linear voltage regulator with current limit protection, chip and electronic device

Abstract

The application discloses a low-dropout linear voltage regulator with current limiting protection, a chip and electronic equipment. The low-dropout linear voltage regulator comprises an LDO main loop unit, a voltage buffer unit and a current limiting protection unit; the LDO main loop unit comprises a first error amplifier, a power tube, a first resistor and a second resistor. When the LDO output current exceeds the threshold current, the current limiting protection unit starts the current limiting protection function, controls the gain of the voltage buffer unit to reduce to zero, and then disconnects the LDO main loop control, so that the LDO output current is stably controlled at the threshold current by the current limiting loop; while the LDO current limiting protection is realized, the competition problem of the two loop controls is effectively avoided, and the circuit is thus free from the oscillation phenomenon.

Description

TECHNICAL FIELD

[0001] The present application relates to a low dropout regulator with current limit protection, and also relates to an integrated circuit chip comprising the low dropout regulator and a corresponding electronic device, and belongs to the technical field of integrated circuits. BACKGROUND

[0002] Low dropout regulator (LDO) is a kind of voltage regulator with excellent performance such as micro power consumption, low noise and high power supply rejection ratio, which is widely used in various integrated circuits and electronic devices. The power supply reliability of LDO circuit is a very important performance index. In practical application, the output driving capability of LDO is usually limited. When the load current exceeds the set range, a large amount of heat loss will be generated in the power tube, which will cause the temperature of LDO to rise, resulting in the phenomenon of reduced service life or even burning of LDO. The good setting of current limit protection function in LDO circuit can greatly improve the power supply reliability of LDO.

[0003] In the prior art, a typical LDO current limit protection circuit is shown in Figure 1 . Among them, the PMOS tube PM2 copies the output current of the power tube PM1 through the current mirror structure, and the mirror current is converted into voltage V3 through the resistance R3 and compared with the reference voltage V_ocp representing the current threshold. When the voltage V3 is greater than the reference voltage V_ocp, the comparator CMP1 reverses, controls the PMOS tube PM3 to open, clamps the gate voltage of the power tube PM1 to the power supply voltage VDD to close the power tube PM1, or reaches the steady-state clamping output current to the current threshold, so as to realize the overcurrent protection. The problem of the above technical scheme is that when the output current reaches the current threshold, the current limit loop starts to work to control the gate voltage of the power tube PM1. If the PMOS tube PM3 works in the switching state, the circuit will constantly oscillate in the state of "PM1 overcurrent->close PM1->PM1 no overcurrent->open PM1->PM1 overcurrent". If the PMOS tube PM3 works in the saturation region, the output of the comparator CMP1 will no longer be a logic level but a stable voltage. Through the loop, the output current of the power tube PM1 is stabilized at the current threshold, and the input voltage V3 and the reference voltage V_ocp of the comparator CMP1 are equal. In this state, the current limit loop will conflict with the error amplifier EA1 of the LDO main loop, causing the circuit to oscillate.

[0004] In addition, in Chinese Invention Patent No. ZL 202310627415.0, a current limiting protection circuit for a low dropout linear regulator and a linear regulator are disclosed. The current limiting protection circuit includes a current sampling unit, a voltage comparison unit, and a current limiting loop control unit. The current limiting loop control unit is used to turn on or turn off the current limiting according to the output of the voltage comparison unit. When the current limiting is turned on, the sampling current of the current sampling unit is fed back to the gate of the power tube to limit the current flowing through the power tube. SUMMARY

[0005] The primary technical problem to be solved by the present application is to provide a low dropout linear regulator with current limiting protection.

[0006] Another technical problem to be solved by the present application is to provide an integrated circuit chip comprising the low dropout linear regulator.

[0007] Still another technical problem to be solved by the present application is to provide an electronic device comprising the low dropout linear regulator.

[0008] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0009] According to a first aspect of an embodiment of the present application, a low dropout linear regulator with current limiting protection is provided, comprising an LDO main path unit, a voltage buffer unit, and a current limiting protection unit. The LDO main path unit comprises a first error amplifier, a power tube, a first resistor, and a second resistor. Wherein,

[0010] The negative input end of the first error amplifier is connected with the reference voltage end, and the output end is connected with the input end of the voltage buffer unit. The output end of the voltage buffer unit is connected with the gate end of the power tube and the input end and the output end of the current limiting protection unit. The source end of the power tube is connected with the power supply voltage end, and the drain end is connected with the first resistor and the LDO output end. The other end of the first resistor is connected with the second resistor on one hand, and connected with the positive input end of the first error amplifier on the other hand. The other end of the second resistor is connected with the ground potential end.

[0011] The LDO main path unit is used to generate an output voltage according to the input reference voltage and provide it to the load circuit.

[0012] The voltage buffer unit is used to buffer the output voltage of the first error amplifier and provide it to the power tube.

[0013] The current limiting protection unit is used to turn on or turn off the current limiting protection function according to the comparison result of the LDO output current and the threshold current.

[0014] When the LDO output current exceeds the threshold current, the current limiting protection unit opens the current limiting protection function, controls the gain of the voltage buffer unit to reduce to zero and then disconnects the LDO main loop control, and controls the LDO output current to be stable at the threshold current by the current limiting loop, thereby realizing LDO current limiting protection.

[0015] Preferably, the voltage buffer unit comprises a first PMOS tube, a second PMOS tube and a first NMOS tube; wherein the first PMOS tube, the second PMOS tube and the first NMOS tube constitute a source follower amplifier with a gain of 1.

[0016] The source-drain current value of the first NMOS tube is greater than the source-drain current value of the first PMOS tube.

[0017] Preferably, in the voltage buffer unit, the gate end of the second PMOS tube is connected to the output end of the first error amplifier as an input end, the source end of the second PMOS tube is connected to the drain end of the first PMOS tube, the gate end of the power tube and the input end and the output end of the current limiting protection unit as an output end; the source end of the first PMOS tube is connected to a power voltage end, and the gate end of the first PMOS tube is connected to a first bias voltage end; the drain end of the second PMOS tube is connected to the drain end of the first NMOS tube NM1, and the source end of the first NMOS tube NM1 is connected to a ground potential end; the gate end of the first NMOS tube NM1 is connected to a second bias voltage end.

[0018] Preferably, the current limiting protection unit comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, and a second NMOS tube and a third NMOS tube; wherein,

[0019] The third PMOS tube and the power tube constitute a current mirror structure with a proportion of M:1, which is used for detecting the size of the LDO output current; wherein M is a positive integer;

[0020] The second NMOS tube and the third NMOS tube constitute a current mirror structure, which is used for copying the mirror output current to the threshold current branch for comparison;

[0021] The fourth PMOS tube is the threshold current branch;

[0022] The fifth PMOS tube and the sixth PMOS tube constitute a current mirror structure with a proportion of 1:K, which is used for mirroring the difference between the mirror output current and the threshold current to the output end of the current limiting protection unit, so as to control the opening or closing state of the current limiting protection function; wherein K is a positive integer.

[0023] Wherein preferably, in the current limiting protection unit, the gate end of the third PMOS tube is connected with the gate end of the power tube and the output end of the voltage buffer unit as an input end, the source end of the third PMOS tube is connected with a power voltage end, and the drain end of the third PMOS tube is connected with the drain end of the second NMOS tube; the drain end and the gate end of the second NMOS tube are short-circuited and connected with the gate end of the third NMOS tube, and the source ends of the second NMOS tube and the third NMOS tube are connected with a ground potential end; the drain end of the third NMOS tube is connected with the drain ends of the fourth PMOS tube and the fifth PMOS tube, the drain end of the fifth PMOS tube is short-circuited with the gate end and connected with the gate end of the sixth PMOS tube; the source ends of the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are connected with the power voltage end; the gate end of the fourth PMOS tube is connected with a first bias voltage end; and the drain end of the sixth PMOS tube is connected with the gate end of the power tube and the output end of the voltage buffer unit as an output end.

[0024] Wherein preferably, in the normal load working condition, the first PMOS tube and the second PMOS tube in the voltage buffer unit work in a saturation region, and the first NMOS tube works in a linear region; when the load gradually increases to an overload, the current limiting protection function is started, the second PMOS tube in the voltage buffer unit gradually changes from working in the saturation region to working in the linear region, so that the gain of the voltage buffer unit gradually decreases from 1 to 0, thereby disconnecting the control of the LDO main loop.

[0025] Wherein preferably, the first PMOS tube in the voltage buffer unit is replaced by a native NMOS tube to realize accurate following of the input and output voltages.

[0026] Wherein preferably, the current limiting protection unit further comprises a second error amplifier for accurately mirroring the LDO output current; wherein,

[0027] The negative input end of the second error amplifier is connected with an LDO output end, the positive input end is connected with the drain ends of the third PMOS tube and the second NMOS tube, and the output end is connected with the gate ends of the second NMOS tube and the third NMOS tube.

[0028] According to a second aspect of the embodiment of the present application, an integrated circuit chip is provided, and the integrated circuit chip comprises the low dropout linear voltage regulator with current limiting protection.

[0029] According to a third aspect of the embodiment of the present application, an electronic device is provided, and the electronic device comprises the low dropout linear voltage regulator with current limiting protection.

[0030] Compared with the prior art, the low-dropout linear voltage regulator with current limiting protection provided by the application has the beneficial effects that the technical scheme is adopted that the current exceeding the threshold of the LDO output current is amplified and used as a control signal to control the working state of the voltage buffer unit, in the overcurrent state, the negative feedback control of the main loop is changed to the current limiting control of the output current by the current limiting loop, the competition problem of the two control loops is effectively avoided while the LDO current limiting protection function is realized, and the circuit will not have the oscillation phenomenon. Therefore, the low-dropout linear voltage regulator with current limiting protection provided by the application has the beneficial effects that the structure design is ingenious and reasonable, the power supply reliability is high, and the current limiting effect is excellent. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 A typical LDO current limiting protection circuit schematic diagram in the prior art;

[0032] Figure 2 A structure block diagram of the low-dropout linear voltage regulator with current limiting protection provided by the embodiment of the application;

[0033] Figure 3 A circuit schematic diagram of the low-dropout linear voltage regulator with current limiting protection in the embodiment of the application;

[0034] Figure 4 A circuit schematic diagram of the voltage buffer unit in the second scheme in the embodiment of the application;

[0035] Figure 5 A circuit schematic diagram of the current limiting protection unit in the second scheme in the embodiment of the application;

[0036] Figure 6 A simulation test result diagram of the LDO current limiting protection in the embodiment of the application;

[0037] Figure 7 A schematic diagram of an electronic device adopting the low-dropout linear voltage regulator provided by the embodiment of the application. DETAILED DESCRIPTION

[0038] The technical content of the application will be described in detail below in combination with the drawings and specific embodiments.

[0039] As Figure 2As shown in the figure, the low-dropout linear regulator with current limit protection provided by the embodiment of the present application comprises an LDO main loop unit, a voltage buffer unit and a current limit protection unit; the LDO main loop unit comprises a first error amplifier EA1, a power transistor PM1, a first resistor R1 and a second resistor R2; wherein the negative input terminal of the first error amplifier EA1 is connected with a reference voltage (VREF) terminal, and the output terminal is connected with the input terminal of the voltage buffer unit; the output terminal of the voltage buffer unit is connected with the gate terminal of the power transistor PM1 and the input terminal and the output terminal of the current limit protection unit; the source terminal of the power transistor PM1 is connected with a power supply voltage (VDD) terminal, and the drain terminal is connected with the first resistor R1 and an LDO output terminal (VOUT); the other terminal of the first resistor R1 is connected with the second resistor R2 on one hand and connected with the positive input terminal of the first error amplifier EA1 on the other hand; the other terminal of the second resistor R2 is connected with a ground terminal.

[0040] The LDO main loop unit is used to generate an output voltage VOUT according to an input reference voltage VREF and provide the output voltage VOUT to a load circuit. The voltage buffer unit is used to buffer the output voltage of the first error amplifier EA1 and provide the output voltage to the power transistor PM1. The current limit protection unit is used to start or stop the current limit protection function according to the comparison result of the LDO output current and the threshold current.

[0041] When the LDO output current exceeds the threshold current, the current limit protection unit starts the current limit protection function, controls the gain of the voltage buffer unit to reduce to zero, and then disconnects the LDO main loop control, so that the LDO output current is stably controlled at the threshold current by the current limit loop, and the LDO current limit protection is realized.

[0042] In an embodiment of the present application, as Figure 3 As shown in the figure, the low-dropout linear regulator with current limit protection provided by the embodiment of the present application comprises an LDO main loop unit, a voltage buffer unit and a current limit protection unit; the LDO main loop unit comprises a first error amplifier EA1, a power transistor PM1, a first resistor R1 and a second resistor R2; wherein the circuit structure and working principle of the voltage buffer unit and the current limit protection unit are as follows.

[0043] The voltage buffer unit comprises a first PMOS tube PM4, a second PMOS tube PM5 and a first NMOS tube NM1; wherein the gate end of the second PMOS tube PM5 is connected with the output end of the first error amplifier EA1 as an input end, the source end of the second PMOS tube PM5 is connected with the drain end of the first PMOS tube PM4, the gate end of the power tube PM1 and the input end and the output end of the current-limiting protection unit as an output end; the source end of the first PMOS tube PM4 is connected with the power voltage (VDD) end, the gate end of the first PMOS tube PM4 is connected with the first bias voltage (VBP) end; the drain end of the second PMOS tube PM5 is connected with the drain end of the first NMOS tube NM1, the source end of the first NMOS tube NM1 is connected with the ground potential end; the gate end of the first NMOS tube NM1 is connected with the second bias voltage (VBN) end.

[0044] In the voltage buffer unit, the first PMOS tube PM4, the second PMOS tube PM5 and the first NMOS tube NM1 constitute a source follower amplifier structure (referred to as a source follower), the output end voltage of which changes with the change of the input end voltage, the gain of the structure amplifier is approximately 1, and the original function of the LDO main loop is not affected under normal load working conditions. At the same time, in theory, the source-drain current of the first NMOS tube NM1 is equal to the drain-source current of the first PMOS tube PM4, considering the actual process deviation of the MOS tube and the consistency of mass production, in the embodiment, for the convenience of circuit and layout design, the source-drain current (2*I0) of the first NMOS tube NM1 is 2 times of the source-drain current (I0) of the first PMOS tube PM4, so as to ensure that the drain end voltage V2 of the first NMOS tube NM1 is low under normal load working conditions, and the loop does not affect the working condition. In other embodiments, the source-drain current of the first NMOS tube NM1 is greater than the drain-source current of the first PMOS tube PM4.

[0045] The current-limiting protection unit comprises a third PMOS tube PM2, a fourth PMOS tube PM6, a fifth PMOS tube PM7, a sixth PMOS tube PM8, a second NMOS tube NM2 and a third NMOS tube NM3. The gate end of the third PMOS tube PM2 is connected with the gate end of the power tube PM1 and the output end of the voltage buffer unit as an input end, the source end of the third PMOS tube PM2 is connected with a power voltage (VDD) end, and the drain end of the third PMOS tube PM2 is connected with the drain end of the second NMOS tube NM2. The drain end and the gate end of the second NMOS tube NM2 are short-circuited and connected with the gate end of the third NMOS tube NM3, and the source ends of the second NMOS tube NM2 and the third NMOS tube NM3 are connected with a ground potential end. The drain end of the third NMOS tube NM3 is connected with the drain ends of the fourth PMOS tube PM6 and the fifth PMOS tube PM7, the drain end of the fifth PMOS tube PM7 is short-circuited with the gate end and connected with the gate end of the sixth PMOS tube PM8. The source ends of the fourth PMOS tube PM6, the fifth PMOS tube PM7 and the sixth PMOS tube PM8 are connected with the power voltage (VDD) end. The gate end of the fourth PMOS tube PM6 is connected with a first bias voltage (VBP) end, and the drain end of the sixth PMOS tube PM8 is connected with the gate end of the power tube PM1 and the output end of the voltage buffer unit as an output end.

[0046] In the current-limiting protection unit, the third PMOS tube PM2 and the power tube PM1 of the LDO main unit constitute a current mirror structure with a ratio of M:1 (M is a positive integer) for detecting the size of the LDO output current. Assuming that M=1000, the relationship between the mirror output current Isense and the LDO output current Iout is: Isense=Iout / 1000. The second NMOS tube NM2 and the third NMOS tube NM3 constitute a current mirror structure with a ratio of 1:1 for copying the mirror output current Isense to the threshold current branch for comparison. The fourth PMOS tube PM6 is a threshold current branch, and the threshold of the LDO output current can be set by controlling the fourth PMOS tube PM6 through the first bias voltage VBP. According to the ratio M:1, the threshold current Iocp of the threshold current branch is 1 / M of the actual current threshold. When M=1000, the threshold current Iocp=Iocp_a / 1000, and Iocp_a represents the threshold of the LDO output current. The fifth PMOS tube PM7 and the sixth PMOS tube PM8 constitute a current mirror structure with a ratio of 1:K (K is a positive integer) for mirroring the overcurrent Idelta formed by the difference between the mirror output current Isense and the threshold current Iocp to the output end of the current-limiting protection unit. The current is K*Idelta, which is used to control the opening or closing state of the current-limiting protection function.

[0047] In the low dropout linear regulator with current limit protection provided by the embodiment of the present application, the LDO main loop unit and the voltage buffer unit constitute an LDO main loop, which is used to perform negative feedback control on the output of the LDO under normal load working conditions; the current limit protection unit, the voltage buffer unit and the power transistor PM1 in the LDO main loop unit constitute a current limit loop, which is used to perform current limit control on the output of the LDO when overcurrent occurs under super load; the specific working principles are described in detail as follows.

[0048] Under normal load working conditions, the LDO output current Iout is less than the set threshold current Iocp_a, the mirror output current Isense is less than the threshold current Iocp in the current limit protection unit, and the overcurrent Idelta formed by the difference between the mirror output current Isense and the threshold current Iocp is approximately 0, so the sixth PMOS transistor PM8 is in the off state, i.e., the current limit function is in the off state. At this time, the first PMOS transistor PM4 and the second PMOS transistor PM5 in the voltage buffer unit work in the saturation region, and the current of the first NMOS transistor NM1 is 2*I0. Since the current provided by the first PMOS transistor PM4 is 1*I0, the drain voltage V2 of the first NMOS transistor NM1 will be low and close to 0 volts, so the first NMOS transistor NM1 works in the linear region. The output voltage V1 of the first error amplifier EA1 is input to the gate end of the second PMOS transistor PM5, and then a driving voltage Vdrv is generated at the output end, i.e., the source end of the second PMOS transistor PM5, and Vdrv≈V1+Vth; wherein Vth is the conduction threshold voltage of the second PMOS transistor PM5. The driving voltage Vdrv drives the power transistor PM1 to generate a stable output voltage VOUT at the output end of the LDO, which is provided to the load circuit. At the same time, the voltage dividing network composed of the first resistor R1 and the second resistor R2 in the LDO main loop unit feeds back the generated feedback voltage Vfb to the positive input end of the first error amplifier EA1; in the LDO main loop, when the output voltage VOUT rises, the feedback voltage Vfb rises, so that the feedback voltage Vfb is greater than the reference voltage VREF at the negative input end, the output voltage V1 of the first error amplifier EA1 rises, and the driving voltage Vdrv output by the voltage buffer unit rises, which drives the power transistor PM1 to make the output voltage VOUT of the LDO decrease, forming negative feedback control of the LDO main loop. When the stable state is reached, VOUT=G1*(Vfb-VREF), wherein G1 is the open-loop gain of the first error amplifier EA1.

[0049] When the load gradually increases to the overload, the LDO output current Iout is greater than the set threshold current Iocp_a, in the current limiting protection unit, the mirror output current Isense is greater than the threshold current Iocp, the difference between the mirror output current Isense and the threshold current Iocp forms the overcurrent Idelta which starts to increase, the sixth PMOS PM8 becomes the conducting state, that is, the current limiting function becomes the open state. The output current Ipm8 of the sixth PMOS PM8 (that is, equal to K*Idelta) starts to gradually increase from 0, when Ipm8<I0, the sum of the current I0 of the first PMOS PM4 in the voltage buffer unit and Ipm8 is less than 2*I0, so the first NMOS NM1 still works in the linear region, the drain voltage V2 of the first NMOS NM1 is kept in the state close to 0, the second PMOS PM5 works in the saturation region, and the voltage buffer unit works normally. When the output current Ipm8 of the sixth PMOS PM8 is greater than I0, the drain voltage V2 of the first NMOS NM1 gradually rises, because the driving voltage Vdrv at the output end of the voltage buffer unit, that is, the source end of the second PMOS PM5 is V2+Vds, wherein Vds is the source-drain voltage of the second PMOS PM5, therefore, the driving voltage Vdrv gradually rises with the voltage V2, so that the second PMOS PM5 works in the linear region, the source follower voltage following function fails, and the first error amplifier EA1 loses the control of the driving voltage Vdrv. At this time, the influence of the drain voltage V2 of the first NMOS NM1 on the driving voltage Vdrv becomes dominant, that is, the current limiting loop composed of the current limiting protection unit starts to control the change of the driving voltage Vdrv. In the overcurrent state, the driving voltage Vdrv gradually rises with the voltage V2, and this driving voltage Vdrv drives the power tube PM1, so that the LDO output current Iout decreases, and finally reaches a stable state, so that the output current Iout is stabilized near the threshold current Iocp_a. At the same time, in the overcurrent state, the increase of the driving voltage Vdrv makes the output voltage VOUT of the LDO decrease, and the output voltage V1 of the first error amplifier EA1 of the LDO main loop decreases in order to make VOUT rise, because it cannot control the source follower, it will continuously pull down the output voltage V1 until it is close to 0V, so that the second PMOS PM5 enters the linear region more quickly.

[0050] As can be seen from the above description, the fifth PMOS PM7 and the sixth PMOS PM8 constitute a current mirror pair in the current limiting protection unit, amplify the current Idelta exceeding the threshold value part of the LDO output current by K times, and take (K*Idelta) as a control signal to control the working state of the voltage buffer unit, i.e., the source follower. In the overcurrent state, the output current K*Idelta of the current limiting protection unit gradually increases, so that the working state of the second PMOS PM5 gradually enters the linear region from the saturation region, the gain of the voltage buffer unit, i.e., the source follower, gradually decreases from 1 to 0, and the LDO main loop control is gradually disconnected due to the decrease of the gain of the source follower. When the gain of the source follower decreases to 0, the current limiting loop dominated by the current limiting protection unit completely controls the driving voltage Vdrv and the output current Iout, so that the output current Iout is stabilized near the threshold current Iocp_a, and the current limiting protection function of the LDO is realized. When the LDO recovers from overload to normal load, the current limiting protection function is turned off, and the LDO main loop again dominates the negative feedback control of the LDO output, so there is no competition problem between the two control loops, and the circuit will not oscillate.

[0051] As can be seen, by adjusting the proportional coefficient K of the current mirror composed of the fifth PMOS PM7 and the sixth PMOS PM8 in the current limiting protection unit, the size of the output current K*Idelta of the current limiting protection unit can be changed, so that the stability of the system regulation is optimized. In addition, by adjusting the values of the proportional coefficients K and M, the threshold value of the LDO output current can be adjusted and set.

[0052] It should be noted that the circuit structure of the current limiting protection unit and the voltage buffer unit in the embodiments of the present application is not limited, and the circuit structure capable of realizing the functions of the units can be used in other embodiments. For example, in another embodiment of the present application, the circuit structure of the voltage buffer unit is as shown in Figure 4 The difference between the above embodiment and the present embodiment is that the core amplifier of the voltage buffer unit in the above embodiment is the second PMOS PM5, and in the present embodiment, a native NMOS is used instead, i.e., the fourth NMOS NM5. The native NMOS has the characteristic of near-zero threshold voltage, so that the driving voltage Vdrv generated at the source end, i.e., the output end, of the fourth NMOS NM5 satisfies Vdrv≈V1+Vth≈V1; wherein V1 is the gate voltage of the fourth NMOS NM5, Vth is the threshold voltage of the fourth NMOS NM5, and Vth≈0; therefore, the source follower constituted by the voltage buffer unit in the present embodiment can realize more accurate input-output voltage following function.

[0053] For another example, in another embodiment of the present application, the circuit structure of the current limiting protection unit is as shown in Figure 5 The difference from the above embodiment is that, in addition to the current mirror structure, the current limiting protection unit further comprises a second error amplifier EA2 for accurately mirroring the LDO output current. The negative input terminal of the second error amplifier EA2 is connected with the LDO output terminal, the positive input terminal is connected with the drain terminals of the third PMOS PM2 and the second NMOS NM2, and the output terminal is connected with the gate terminals of the second NMOS NM2 and the third NMOS NM3. The source-drain voltage Vds of the third PMOS PM2 in the current limiting protection unit is completely equal to that of the power transistor PM1, and the drain voltage Vsense of the third PMOS PM2 is completely equal to the drain voltage VOUT of the power transistor PM1 through the adjustment of the second error amplifier EA2, so that the mirror output current Isense is more accurate, and the precision of the current limiting protection is improved.

[0054] In order to verify the current limiting protection effect of the low-dropout linear regulator provided by the embodiment of the present application, the inventor has carried out simulation test of the current limiting protection of the technical scheme, the threshold current of the low-dropout linear regulator is set to 150mA, and the test result is as shown in Figure 6 From the simulation test result, in the process of increasing the load current iload from low to 600mA, when the load current exceeds 150mA, the LDO output current I is limited to about 160mA, and the current limiting protection effect is very significant.

[0055] Based on the low-dropout linear regulator with current limiting protection described above, the embodiment of the present application further provides an integrated circuit chip, which comprises the low-dropout linear regulator with current limiting protection described above, and is used as an important component of a power module in an integrated circuit system to provide reliable power supply voltage for the system. The specific structure of the low-dropout linear regulator with current limiting protection in the integrated circuit chip will not be described here.

[0056] The low-dropout linear regulator provided by the embodiment of the present application can also be used in electronic equipment as an important component of a power component. As shown in Figure 7As shown, the electronic device at least includes a processor, a memory and a power supply component, and can further include a communication component, a sensor component, a multimedia component and an input / output interface according to actual needs. Among them, the memory, the communication component, the sensor component, the power supply component, the multimedia component and the input / output interface are connected with the processor. The memory can be a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc. The processor can be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable logic gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. Other communication components, sensor components, multimedia components, etc. can be realized by using general components, which will not be specifically described here.

[0057] In summary, compared with the prior art, the low-dropout linear voltage regulator with current limiting protection provided by the present application has the beneficial effects of ingenious and reasonable structure design, high power supply reliability and excellent current limiting effect, etc.

[0058] It should be noted that the above multiple embodiments are only illustrative. The technical solutions of each embodiment can be combined, and all are within the protection scope of the present application.

[0059] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0060] The low-dropout linear voltage regulator with current limiting protection, chip and electronic device provided by the present application are described in detail above. Any obvious modification made by a person skilled in the art without departing from the essential content of the present application will constitute an infringement of the patent right of the present application and will bear the corresponding legal responsibility.

Claims

1. A low-dropout linear regulator with current limit protection, characterized by The low dropout regulator comprises an LDO main loop unit, a voltage buffer unit and a current limiting protection unit. The LDO main loop unit comprises a first error amplifier, a power tube, a first resistor and a second resistor. The negative input terminal of the first error amplifier is connected with a reference voltage terminal, and the output terminal is connected with the input terminal of the voltage buffer unit. The output terminal of the voltage buffer unit is connected with the gate terminal of the power tube and the input terminal and the output terminal of the current limiting protection unit. The source terminal of the power tube is connected with a power voltage terminal, and the drain terminal is connected with the first resistor and an LDO output terminal. The other terminal of the first resistor is connected with the second resistor on one side and connected with the positive input terminal of the first error amplifier on the other side. The other terminal of the second resistor is connected with a ground terminal. The LDO main loop unit is used for generating an output voltage according to an input reference voltage and providing the output voltage to a load circuit. The voltage buffer unit is used for buffering the output voltage of the first error amplifier and providing the output voltage to the power tube. The current limiting protection unit is used for starting or stopping the current limiting protection function according to the comparison result of the LDO output current and a threshold current. When the LDO output current exceeds the threshold current, the current limiting protection unit starts the current limiting protection function, mirrors the overcurrent formed by the difference between the threshold current and the mirror output current to the output terminal of the current limiting protection unit as the output current of the current limiting protection unit, and uses the output current of the current limiting protection unit to gradually change the working state of the second PMOS tube in the voltage buffer unit from the saturation region to the linear region, so that the gain of the voltage buffer unit gradually decreases from 1 to 0, thereby disconnecting the control of the LDO main loop and stabilizing the LDO output current at the threshold current by the current limiting loop composed of the current limiting protection unit, and realizing the LDO current limiting protection.

2. The low dropout regulator with current limiting protection according to claim 1, wherein: The voltage buffer unit comprises a first PMOS tube, a second PMOS tube and a first NMOS tube. The source-drain current value of the first NMOS tube is greater than the source-drain current value of the first PMOS tube.

3. The low dropout regulator with current limiting protection according to claim 2, wherein: In the voltage buffer unit, the gate terminal of the second PMOS tube is connected with the output terminal of the first error amplifier as the input terminal, the source terminal of the second PMOS tube is connected with the drain terminal of the first PMOS tube, the gate terminal of the power tube and the input terminal and the output terminal of the current limiting protection unit as the output terminal. The source terminal of the first PMOS tube is connected with a power voltage terminal, and the gate terminal of the first PMOS tube is connected with a first bias voltage terminal. The drain terminal of the second PMOS tube is connected with the drain terminal of the first NMOS tube NM1, the source terminal of the first NMOS tube NM1 is connected with a ground terminal, and the gate terminal of the first NMOS tube NM1 is connected with a second bias voltage terminal.

4. The low dropout linear regulator with current limit protection of claim 1, wherein: the current limit protection unit comprises a third PMOS, a fourth PMOS, a fifth PMOS, a sixth PMOS, a second NMOS and a third NMOS; wherein, the third PMOS and the power transistor form a first current mirror structure with a ratio of M: 1, for detecting the LDO output current; wherein, M is a positive integer; the second NMOS and the third NMOS form a second current mirror structure, for copying the mirror output current to the threshold current branch for comparison; the fourth PMOS is the threshold current branch; the fifth PMOS and the sixth PMOS form a third current mirror structure with a ratio of 1: K, for mirroring the overcurrent formed by the difference between the mirror output current and the threshold current to the output end of the current limit protection unit, to control the opening or closing state of the current limit protection function; wherein, K is a positive integer.

5. The low dropout linear regulator with current limit protection of claim 4, wherein: in the current limit protection unit, the gate end of the third PMOS is connected to the gate end of the power transistor and the output end of the voltage buffer unit as an input end, the source end of the third PMOS is connected to the power supply voltage end, and the drain end of the third PMOS is connected to the drain end of the second NMOS; the drain end and the gate end of the second NMOS are shorted and connected to the gate end of the third NMOS, and the source ends of the second NMOS and the third NMOS are connected to the ground potential end; the drain end of the third NMOS is connected to the drain ends of the fourth PMOS and the fifth PMOS, the drain end and the gate end of the fifth PMOS are shorted and connected to the gate end of the sixth PMOS; the source ends of the fourth PMOS, the fifth PMOS and the sixth PMOS are connected to the power supply voltage end; the gate end of the fourth PMOS is connected to the first bias voltage end; and the drain end of the sixth PMOS is connected to the gate end of the power transistor and the output end of the voltage buffer unit as an output end.

6. The low dropout linear regulator with current limit protection of claim 2, wherein: under normal load working conditions, the first PMOS and the second PMOS in the voltage buffer unit work in the saturation region, and the first NMOS works in the linear region.

7. The low dropout linear regulator with current limit protection of claim 2, wherein: the first PMOS in the voltage buffer unit is replaced by a native NMOS to achieve accurate following of the input and output voltages.

8. The low dropout linear regulator with current limit protection of claim 4, wherein: the current limit protection unit further comprises a second error amplifier for accurately mirroring the LDO output current; wherein, ​ ​ ​ ​ ​ ​ ​ ​ ​ The negative input end of the second error amplifier is connected with the LDO output end, the positive input end is connected with the drain end of the third PMOS tube and the second NMOS tube, and the output end is connected with the gate end of the second NMOS tube and the third NMOS tube.

9. An integrated circuit chip, characterized by The low dropout linear regulator with current limit protection of any one of claims 1-8.

10. An electronic device, characterized in that... The low dropout linear regulator with current limit protection of any one of claims 1-8.

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