Method for processing NVMe write command and control component

Abstract

The invention provides a method for processing an NVMe write command and a control component, and the method comprises the steps: responding to the NVMe write command sent by a host, and processing a DMA command corresponding to the NVMe write command; under the condition that all DMA commands corresponding to the NVMe write command are processed, a first message and a second message are generated, and the first message and the second message both indicate that the NVMe write command is processed; and sequentially sending the first message to a storage command processing unit and sending the second message to the host. The first message is sent to the storage command processing unit firstly, and then the second message is sent to the host, so that the storage command processing unit has received the first message before the host receives the second message, and when the storage command corresponding to the subsequent NVMe read command is received, the storage command corresponding to the NVMe read command is sent to the host. The storage command processing unit has processed a storage command corresponding to the NVMe write command based on the first message.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a method and control component for processing NVMe write commands. Background Art

[0002] Figure 1A The block diagram of the storage device is shown. The storage device 102 is coupled to the host to provide storage capacity for the host. The host and the storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and the storage device 102 through a variety of storage protocols such as SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fiber Channel, wireless communication network, etc. The host can be an information processing device that can communicate with the storage device in the above manner, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data of the DRAM 110. The DRAM can store the data of the FTL (Flash Translation Layer) table and / or cached IO commands.

[0006] The control component 104 includes a flash memory interface controller (or medium interface controller, flash memory channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that complies with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

[0007] In the storage device 102, the FTL table is used to maintain the mapping information from the logical address to the physical address. The logical address constitutes the storage space of the storage device perceived by the upper-layer software such as the operating system. The physical address is the address of the physical storage unit used to access the storage device. In the related art, the address mapping can also be implemented using the intermediate address form. For example, the logical address is mapped to the intermediate address, and then the intermediate address is further mapped to the physical address. The FTL table is an important metadata in the storage device. Usually, the data items of the FTL table record the address mapping relationship in the storage device in units of a specified size of storage units (such as 512 bytes, 2KB, 4KB, etc.).

[0008] The logical address space is the storage address space provided by the storage device to the host. The host uses the elements (logical addresses) in the logical address space to access the storage device. For the logical address space, the storage device manages the mapping between the logical address and the physical address through the FTL table. The host sends a read / write command that satisfies the NVMe protocol (hereinafter referred to as NVMe command) to the storage device. The NVMe command indicates the logical address (Logical Block Address, LBA) to be accessed. The storage device converts the LBA into a physical address (PPA) based on the FTL table managed in the control component 104, and then the control component accesses the NVM chip according to the physical address.

[0009] Figure 1B A detailed block diagram showing the control components of a storage device.

[0010] The host accesses the storage device with read / write commands that follow the NVMe protocol. The control component generates one or more media interface commands based on the NVMe command from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, erase commands) that follow the interface protocol of the NVM chip based on the media interface command. The control component also tracks that all media interface commands generated from an NVMe command have been executed and indicates the processing result of the NVMe command to the host.

[0011] See also Figure 1B The control components include, for example, a host interface, a host command processing unit, a storage command processing unit, a medium interface controller, and a storage medium management unit. The host interface obtains the NVMe command provided by the host, and generates a storage command to provide to the storage command processing unit. Storage commands, for example, access storage space of the same size, such as 4KB. The data unit corresponding to the data accessed by a storage command recorded in the NVM chip is called a data frame. A physical page records one or more data frames. For example, if the size of the physical page is 17664 bytes and the size of the data frame is 4KB, then one physical page can store 4 data frames.

[0012] The storage medium management unit maintains the conversion of the logical address to the physical address for each storage command. For example, the storage medium management unit includes an FTL table. For a read command, the storage medium management unit outputs the physical address corresponding to the logical address accessed by the storage command. For a write command, the storage medium management unit allocates an available physical address and records the mapping relationship between the logical address accessed and the allocated physical address.

[0013] The storage command processing unit operates the media interface controller to issue a storage media access command to the NVM chip according to the physical address provided by the storage media management unit. For the purpose of clarity, the command sent by the host to the storage device is called an NVMe command, the command sent by the host command processing unit to the storage command processing unit is called a storage command, the command sent by the storage command processing unit to the media interface controller is called a media interface command, and the command sent by the media interface controller to the NVM chip is called a storage media access command. The storage media access command follows the interface protocol of the NVM chip.

[0014] Figure 2 The structure of the host command processing unit is shown.

[0015] See also Figure 2 , the control component includes a write initiation circuit, a (Direct Memory Access) DMA transmission circuit and a read initiation circuit. The write initiation circuit is used to accelerate the processing of NVMe write commands, and the write initiation circuit and the DMA transmission circuit cooperate with each other to realize the process of moving data from the host to the storage device cache (buffer). The read initiation circuit is used to process NVMe read commands, and the read initiation circuit and the DMA transmission circuit cooperate with each other to realize the process of moving data from the storage device cache (buffer) to the host. The working principles of the write initiation circuit are described in Chinese Patent 202110746142.2 and the read initiation circuit are described in Chinese Patent 202110746144.1, and their contents are incorporated here.

[0016] The process of writing initiator circuit to process NVMe write command is shown in Figure 2 As shown:

[0017] Step 1( Figure 2 (Indicated by the figure mark (1)), the write initiation circuit receives the PRP / SGL index corresponding to the NVMe write command issued by the host.

[0018] The host command processing unit also includes a PRP (Physical Region Page) / SGL (Scatter / Gather List) unit and a cache unit ( Figure 2 (not shown), the PRP / SGL unit is coupled to the cache unit to write the initiation circuit. In response to the received NVMe write command, the PRP / SGL unit obtains the SGL / PRP corresponding to the NVMe write command, stores the SGL / PRP in the cache unit, and the cache unit is coupled to the write initiation circuit to provide the PRP / SGL index to the write initiation circuit.

[0019] PRP and SGL are two ways to describe the data to be transmitted between the host and the storage device. In the PRP method, a number of linked PRP entries are used, each of which includes a 64-bit memory physical address, which is used to describe a physical page (Page) of the host memory. SGL is a linked list, consisting of one or more SGL segments, each of which consists of one or more SGL descriptors; each SGL descriptor describes the address and length of the data cache of the host memory, that is, each SGL descriptor corresponds to a host memory address space; each SGL descriptor has, for example, a fixed size (for example, 16 bytes).

[0020] The PRP / SGL index has various forms. For example, the PRP / SGL index carries the host memory address indicated in the PRP / SGL entry, or the PRP / SGL index carries a pointer to a cache unit, in which the PRP / SGL entry is stored. The PRP / SGL entry is obtained from the cache unit through the PRP / SGL index to obtain the host memory address. Optionally, the PRP / SGL index corresponds to the PRP / SGL entry one by one. Obtaining the PRP / SGL entry and the PRP / SGL index from the NVMe write command belongs to the prior art and will not be described here.

[0021] Step 2A: The write initiation circuit generates a DMA command according to the PRP / SGL index corresponding to the NVMe write command and sends it to the DMA transmission circuit.

[0022] Step 2B: The DMA transmission circuit moves data from the host to the storage device buffer according to the DMA command.

[0023] The write initiation circuit obtains the SGL / PRP from the cache unit, generates one or more DMA commands according to the SGL / PRP, and provides the generated DMA commands to the DMA transmission circuit.

[0024] The DMA command indicates the mapping relationship between the host memory address space and the storage device cache address space (e.g., DRAM address), and is used to control the DMA transfer circuit to perform data transfer. The host memory address indicated by the DMA command is determined based on the address space indicated by the SGL or PRP, and the storage device cache address is allocated by the storage device. Each DMA command is used to perform a data movement operation between the host and the storage device.

[0025] Step 3: After completing the DMA command, the DMA transmission circuit returns a DMA completion message to the write initiation circuit.

[0026] The DMA transmission circuit responds to the received DMA command, moves data between the host memory and the storage device cache according to the DMA command, and after the data movement is completed, provides a message indicating that the DMA command processing is completed to the write initiation circuit.

[0027] Step 4A: After the write initiation circuit recognizes that all DMA commands corresponding to the NVMe write command have been processed, an NVMe write command processing completion message is returned to the host.

[0028] Step 4B: After the write initiation circuit recognizes that the DMA command has been processed, it sends a storage command corresponding to the NVMe write command to the storage command processing unit, and the storage command carries the DMA completion message corresponding to the DMA completion message.<LBA,Buffer_Index> , wherein Buffer_Index represents a storage device cache index, for example, the storage device cache index is an address where the data moved by executing the DMA command is stored in the storage device cache.

[0029] In response to receiving the storage command, the storage command processing unit allocates a physical address PPA to the LBA indicated by the storage command, and generates a media interface command according to the allocated physical address. The media interface controller (such as Figure 1B As shown in the figure, the medium interface command is processed to generate a storage medium access command, and the data corresponding to Buffer_Index (storage device cache index) is moved from the storage device cache to the NVM chip according to the storage medium access command.

[0030] Step 4B is executed multiple times during the processing of an NVMe write command, for example, step 4B is executed once after each DMA command is processed. Step 4A is executed only once during the processing of an NVMe write command, for example, it is executed once after all DMA commands corresponding to the NVMe write command are processed.

[0031] See also Figure 3 As shown, the coupling of the write initiation circuit with the DMA transmission circuit, the host interface and the storage command processing unit is shown, wherein the write initiation circuit includes an acquisition circuit, a DMA command generation circuit, a storage command generation circuit and a completion message generation circuit, and the acquisition circuit provides the acquired information (such as PRP entries) to the DMA command generation circuit, and the DMA command generation circuit is used to generate DMA commands and provide the DMA commands to the DMA transmission circuit coupled thereto. The storage command generation circuit is coupled to the DMA transmission circuit, and after receiving the DMA command processing completion message sent by the DMA transmission circuit, it generates a storage command and provides the storage command to the storage command processing unit. When all DMA commands corresponding to the NVMe write command are processed, the completion message generation circuit generates an NVMe write command processing completion message.

[0032] The process of the read initiator circuit processing NVMe read commands is shown in Figure 2 As shown:

[0033] Step 5 Figure 2 (Indicated by the reference numeral (5) in the figure), the read initiation circuit receives the NVMe read command issued by the host.

[0034] Step 6. The read initiation circuit generates one or more storage commands according to the NVMe read command, and sends the storage command corresponding to the NVMe read command to the storage command processing unit.

[0035] The storage command processing unit queries the FTL table according to the LBA indicated by the storage command to determine the physical address PPA in the corresponding NVM chip, reads the data according to the physical address and caches it in the storage device cache, and the data to be read in response to the storage command is stored in the storage device cache. The storage command processing unit generates a storage command processing completion message and feeds it back to the read initiation circuit. The read initiation circuit generates a DMA command according to the received storage command processing completion message, and sends the DMA command to the DMA transmission circuit. The DMA transmission circuit moves data from the storage device buffer to the host according to the DMA command. Summary of the invention

[0036] The host can send multiple NVMe commands to the storage device at the same time. Whether the storage device returns a completion message of the NVMe command to the host does not affect the host's issuance of the NVMe command, but it affects the expected result of the NVMe command issued by the host. For example, after receiving the completion message of the NVMe write command to access LBAn, the host issues a read command to access LBA n, and the host expects the read data to be the data written by the previous NVMe write command. If the host issues a read command to access LBA n, but has not received a completion message for the NVMe write command to access LBA n, then even if the NVMe write command has been sent to the storage device before the NVMe read command, the data read by the host may still not be the data written by the NVMe write command.

[0037] When the host receives the NVMe write command processing completion message, the host believes that the NVMe write command has been processed, and the data indicated by the NVMe write command can be correctly read by sending an NVMe read command. However, for the storage device, its processing of the NVMe write command is not completed. The control component processes the NVMe write command, including two stages of data movement: from the host to the storage device cache and from the storage device cache to the NVM chip. When all the data indicated by the NVMe write command are stored in the NVM chip, the NVMe write command is considered to be processed. After all the DMA commands corresponding to the NVMe write command are processed, the control component feedbacks the NVMe write command processing completion message to the host. For the storage device, the completion of all DMA commands corresponding to the NVMe write command only means that the data indicated by the NVMe write command is moved from the host to the storage device cache. It is also necessary to generate a storage command and send it to the storage command processing unit to move the data in the storage device cache to the NVM chip.

[0038] In some scenarios, the host first sends an NVMe write command to the storage device. After all DMA commands corresponding to the NVMe write command are processed, the storage device sends an NVMe write command processing completion message to the host. After receiving the NVMe write command processing completion message, the host sends an NVMe read command to the storage device, and the NVMe write command and NVMe read command access the same LBA, for example, LBA = 100. See also Figure 2 Since the read initiation circuit and the write initiation circuit are two independent circuits that work in parallel with each other, there is no fixed order between the operations indicated by step (4B) and the operations indicated by step (6). If for some reason, the message path of step (4B) is blocked, although the read command accessing LBA=100 is issued by the host after the write command accessing LBA=100, the processing indicated by step (6) in the processing of the read command accessing LBA=100 may occur before the processing indicated by step (4B) in the processing of the write command accessing LBA=100. This causes the storage command processing unit to query the physical address according to LBA=100 by accessing the FTL table when processing step (6). At this time, the processing corresponding to the write command accessing LBA=100 indicated by step (4B) has not yet occurred, so the physical address or cache index of the data written by the write command is not recorded in the FTL table, which results in that the data will not be obtained by the read command accessing LBA=100, so that the host cannot read the data written by the write command accessing LBA=100 through the read command. Furthermore, if data has not been written to LBA=100 in the logical address space before the write command accessing LBA=100, an error of reading blank data will be triggered when processing the read command accessing LBA=100.

[0039] This application hopes to provide a solution to solve the above technical problems.

[0040] In a first aspect, an embodiment of the present application provides a command processing method, which is applied to a control component, and the method includes:

[0041] In response to an NVMe write command sent by the host, processing a DMA command corresponding to the NVMe write command;

[0042] When all DMA commands corresponding to the NVMe write command are processed, a first message and a second message are generated, both of which indicate that the NVMe write command processing is completed;

[0043] The first message is sent to the storage command processing unit and the second message is sent to the host in sequence.

[0044] Optionally, after generating the first message and the second message, the method further includes:

[0045] Allocate a physical address for the LBA indicated by the storage command corresponding to the NVMe write command, store the data corresponding to the LBA indicated by the storage command into the NVM chip according to the physical address, and update the FTL table according to the physical address; or

[0046] The FTL table is updated based on the storage device cache index indicated by the storage command corresponding to the NVMe write command.

[0047] Optionally, the method further comprises:

[0048] In response to the NVMe read command sent by the host, query the FTL table according to the LBA indicated by the NVMe read command to obtain address information, where the address information is a physical address or a storage device cache index;

[0049] Data is read from the NVM chip according to the physical address or data is read from the storage device cache according to the storage device cache index.

[0050] Optionally, the method further comprises:

[0051] When sending the first message to the storage command processing unit, obtaining the working status of the storage command processing unit;

[0052] When the storage command processing unit is in a busy state, temporarily suspending sending the second message to the host;

[0053] When the storage command processing unit is not in a busy state, after sending the first message to the storage command processing unit, the second message is sent to the host.

[0054] Optionally, obtaining the working state of the storage command processing unit includes:

[0055] Detecting the state of the message queue of the last storage command for transmitting the NVMe write command;

[0056] If the message queue is in a full state, determining that the storage command processing unit is in a busy state;

[0057] When the message queue is in a non-full state, determining that the storage command processing unit is in a non-busy state.

[0058] Optionally, the method further includes:

[0059] Updating the write cache table according to the <LBA, storage device cache index> indicated by the storage command corresponding to the NVMe write command;

[0060] Updating the FTL table according to the write cache table.

[0061] Optionally, updating the write cache table according to the <LBA, storage device cache index> indicated by the storage command corresponding to the NVMe write command includes:

[0062] After receiving a storage command corresponding to the NVMe write command, updating the write cache table according to the <LBA, storage device cache index> indicated by the storage command; or

[0063] When all DMA commands corresponding to the NVMe write command are processed, updating the write cache table according to the <LBA, storage device cache index> indicated by each storage command corresponding to the NVMe write command.

[0064] Optionally, the method further includes:

[0065] In response to a storage command corresponding to the NVMe read command sent by the host, detecting whether there is a first storage device cache index of the LBA indicated by the storage command corresponding to the NVMe read command in the write cache table;

[0066] If the first storage device cache index exists, reading data from the storage device cache according to the first storage device cache index and feeding it back to the host;

[0067] If the first storage device cache index does not exist, querying the FTL table according to the LBA indicated by the storage command corresponding to the NVMe read command to determine the corresponding address information, and reading data based on the address information and feeding it back to the host, where the address information is a physical address or a storage device cache index.

[0068] Optionally, the method further comprises:

[0069] Add a set of LBA values ​​indicated by the storage command corresponding to the NVMe write command to the LBA filter;

[0070] The LBA filter is used to identify whether the LBA value to be detected exists in the LBA filter.

[0071] Optionally, the method further comprises:

[0072] In response to a storage command corresponding to the NVMe read command sent by the host, detecting whether a first LBA indicated by the storage command corresponding to the NVMe read command exists in the LBA filter;

[0073] If the first LBA indicated by the storage command corresponding to the NVMe read command exists in the LBA filter, suspend processing of the storage command;

[0074] If the first LBA indicated by the storage command corresponding to the NVMe read command does not exist in the LBA filter, the FTL table is queried according to the first LBA to determine the address information of the FTL table entry corresponding to the first LBA, and data is read based on the address information and fed back to the host, where the address information is a physical address or a storage device cache index.

[0075] Optionally, the method further comprises:

[0076] Taking out the LBA value in the LBA filter, updating the FTL table according to the taken out LBA value, and clearing the taken out LBA value from the LBA filter;

[0077] Acquire the first storage command whose processing is suspended, and detect whether the first LBA indicated by the first storage command is in the LBA filter;

[0078] If the first LBA is in the LBA filter, continue to suspend processing of the first storage command;

[0079] If the first LBA is not in the LBA filter, determine the address information of the FTL table entry corresponding to the first LBA, read data based on the address information and feed it back to the host.

[0080] Optionally, the method further comprises:

[0081] After receiving a storage command corresponding to the NVMe write command, the FTL table entry corresponding to the LBA indicated by the storage command is locked to prevent processing of the storage command accessing the LBA.

[0082] Optionally, the method further comprises:

[0083] In response to a storage command corresponding to the NVMe read command sent by the host, query the FTL table according to the LBA indicated by the storage command corresponding to the NVMe read command, and determine the corresponding first FTL table entry;

[0084] If the first FTL table entry corresponding to the LBA indicated by the storage command corresponding to the NVMe read command is locked, suspend processing of the storage command;

[0085] If the first FTL table entry corresponding to the LBA indicated by the storage command corresponding to the NVMe read command is not locked, data is read according to the address information of the first FTL table entry and fed back to the host.

[0086] In a second aspect, an embodiment of the present application provides a control component, including: a write initiation circuit, a DMA transmission circuit, and a storage command processing unit;

[0087] The write initiation circuit and the DMA transmission circuit cooperate to process the NVMe write command corresponding to the DMA command;

[0088] When all DMA commands corresponding to the NVMe write command are processed, the write initiation circuit generates a first message and a second message, both of which indicate that the NVMe write command processing is completed;

[0089] The write initiation circuit sends the first message to the storage command processing unit and the second message to the host in sequence.

[0090] Optionally, after generating the first message and the second message;

[0091] The storage command processing unit allocates a physical address to the LBA indicated by the storage command corresponding to the NVMe write command, stores the data corresponding to the LBA indicated by the storage command into the NVM chip according to the physical address, and updates the FTL table according to the physical address; or

[0092] The storage command processing unit updates the FTL table based on the storage device cache index indicated by the storage command corresponding to the NVMe write command.

[0093] Optionally, the storage command processing unit queries the FTL table to obtain address information according to the LBA indicated by the storage command corresponding to the NVMe read command sent by the host, in response to the storage command corresponding to the NVMe read command, where the address information is a physical address or a storage device cache index;

[0094] Read data from the NVM chip according to the physical address or read data from the storage device cache according to the storage device cache index.

[0095] Optionally, when the write initiation circuit sends the first message to the storage command processing unit, it obtains the working state of the storage command processing unit;

[0096] When the storage command processing unit is in a busy state, suspend sending the second message to the host;

[0097] When the storage command processing unit is not in a busy state, after sending the first message to the storage command processing unit, send the second message to the host.

[0098] Optionally, the write initiation circuit is further configured to:

[0099] Detect the status of the message queue of the last storage command for transmitting the NVMe write command;

[0100] If the message queue is in a full state, determine that the storage command processing unit is in a busy state;

[0101] When the message queue is in a non-full state, determine that the storage command processing unit is not in a busy state.

[0102] Optionally, the storage command processing unit is configured to:

[0103] Update the write cache table according to the <LBA, storage device cache index> indicated by the storage command corresponding to the NVMe write command;

[0104] Update the FTL table according to the write cache table.

[0105] Optionally, the storage command processing unit is further configured to:

[0106] After receiving a storage command corresponding to the NVMe write command, update the write cache table according to the <LBA, storage device cache index> indicated by the storage command; or

[0107] When all DMA commands corresponding to the NVMe write command are processed, update the write cache table according to the <LBA, storage device cache index> indicated by each storage command corresponding to the NVMe write command.

[0108] Optionally, the storage command processing unit is further configured to:

[0109] In response to a storage command corresponding to the NVMe read command sent by the host, detecting whether there is a first storage device cache index of the LBA indicated by the storage command corresponding to the NVMe read command in the write cache table;

[0110] If the first storage device cache index exists, reading data from the storage device cache according to the first storage device cache index and feeding it back to the host;

[0111] If the first storage device cache index does not exist, the corresponding address information is determined by querying the FTL table according to the LBA indicated by the storage command corresponding to the NVMe read command, and data is read based on the address information and fed back to the host, where the address information is a physical address or a storage device cache index.

[0112] Optionally, the storage command processing unit is further used for:

[0113] Add a set of LBA values ​​indicated by the storage command corresponding to the NVMe write command to the LBA filter;

[0114] The LBA filter is used to identify whether the LBA value to be detected exists in the LBA filter.

[0115] Optionally, the storage command processing unit is further used for:

[0116] In response to a storage command corresponding to the NVMe read command sent by the host, detecting whether a first LBA indicated by the storage command corresponding to the NVMe read command exists in the LBA filter;

[0117] If the first LBA indicated by the storage command corresponding to the NVMe read command exists in the LBA filter, suspend processing of the storage command;

[0118] If the first LBA indicated by the storage command corresponding to the NVMe read command does not exist in the LBA filter, the FTL table is queried according to the first LBA to determine the address information of the FTL table entry corresponding to the first LBA, and data is read based on the address information and fed back to the host, where the address information is a physical address or a storage device cache index.

[0119] Optionally, the storage command processing unit is further used for:

[0120] Taking out the LBA value in the LBA filter, updating the FTL table according to the taken out LBA value, and clearing the taken out LBA value from the LBA filter;

[0121] Acquire the first storage command whose processing is suspended, and detect whether the first LBA indicated by the first storage command is in the LBA filter;

[0122] If the first LBA is in the LBA filter, continue to suspend processing of the first storage command;

[0123] If the first LBA is not in the LBA filter, determine the address information of the FTL table entry corresponding to the first LBA, read data based on the address information and feed it back to the host.

[0124] Optionally, the storage command processing unit is further used for:

[0125] After receiving a storage command corresponding to the NVMe write command, the FTL table entry corresponding to the LBA indicated by the storage command is locked to prevent processing of the storage command accessing the LBA.

[0126] Optionally, the storage command processing unit is further used for:

[0127] In response to a storage command corresponding to the NVMe read command sent by the host, query the FTL table according to the LBA indicated by the storage command corresponding to the NVMe read command, and determine the corresponding first FTL table entry;

[0128] If the first FTL table entry corresponding to the LBA indicated by the storage command corresponding to the NVMe read command is locked, suspend processing of the storage command;

[0129] If the first FTL table entry corresponding to the LBA indicated by the storage command corresponding to the NVMe read command is not locked, data is read according to the address information of the first FTL table entry and fed back to the host.

[0130] According to an embodiment of the present application, when all DMA command processing corresponding to the NVMe write command is completed, a first message and a second message indicating that the NVMe write command processing is completed are generated, and the first message is sent to the storage command processing unit and the second message is sent to the host in sequence. By sending the first message first and then the second message, the storage command processing unit has received the first message before the host receives the second message, and then when the storage command corresponding to the subsequent NVMe read command is received, the storage command processing unit has processed the storage command corresponding to the NVMe write command based on the first message. BRIEF DESCRIPTION OF THE DRAWINGS

[0131] Figure 1A A block diagram representing a storage device;

[0132] Figure 1B A detailed block diagram showing the control components of a storage device;

[0133] Figure 2 A flowchart showing an implementation of a control component processing an NVMe command in the prior art;

[0134] Figure 3 A schematic diagram showing the coupling of a write initiation circuit with a DMA transfer circuit, a host interface, and a storage command processing unit;

[0135] Figure 4 A flowchart showing an implementation of a control component processing an NVMe command provided in an embodiment of the present application;

[0136] Figure 5 A schematic diagram showing the corresponding DMA commands for processing different stages provided by an embodiment of the present application;

[0137] Figure 6 A schematic diagram showing the interaction between a storage command processing unit and a storage command generating circuit based on a message queue provided in an embodiment of the present application;

[0138] Figure 7 A schematic diagram showing a storage device cache index for caching LBAs through a write cache table provided in an embodiment of the present application;

[0139] Figure 8 A schematic diagram showing that a storage command processing unit provided in an embodiment of the present application writes the contents of a write cache table into an FTL table;

[0140] Fig. 9 A schematic diagram showing writing LBA in an LBA filter provided by an embodiment of the present application;

[0141] Fig.10 A schematic diagram showing locking and releasing of FTL table entries provided in an embodiment of the present application. DETAILED DESCRIPTION

[0142] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0143] Embodiment 1

[0144] In the embodiment of the present application, the write initiation circuit in the control component first sends the NVMe write command processing completion message to the storage command processing unit and then to the host during the NVMe write command processing process, so that when the NVMe read command sent by the host after receiving the NVMe write command processing completion message is processed by the control component, the storage command processing unit has received all the storage commands corresponding to the NVMe write command before receiving the storage command corresponding to the NVMe read command. Therefore, when the storage command processing unit receives the storage command corresponding to the NVMe read command, it can know the correct storage location of the data corresponding to the logical address indicated by the storage command corresponding to the NVMe read command in the storage device cache or NVM chip.

[0145] The following is a detailed description of the process of the control component processing the NVMe write command in the embodiment of the present application. The process can be found in Figure 4 .

[0146] Step 1. The PRP acquisition circuit included in the write initiation circuit receives the PRP / SGL index corresponding to the NVMe write command.

[0147] Step 2: The PRP acquisition circuit acquires the PRP entry from the cache unit according to the PRP index and sends the PRP entry to the DMA command generation circuit.

[0148] Step 3: The DMA command generation circuit generates a DMA command according to the PRP and sends the DMA command to the DMA transmission circuit.

[0149] Step 4: The DMA transmission circuit moves the data indicated by the DMA command from the host to the storage device cache (such as DRAM) according to the DMA command, and after the DMA command processing is completed, the DMA transmission circuit sends a DMA command processing completion message to the storage command generation circuit.

[0150] Step 5A: The storage command generation circuit generates a storage command based on the DMA command processing completion message and provides it to the storage command processing unit. The generated storage command indicates to move the data in the storage device cache to the NVM chip. The storage command carries the DMA command processing completion message corresponding to the storage command processing completion message.<LBA,Buffer_Index> , LBA indicates a logical address, and the storage device cache index (Buffer_Index) indicates the location of data in the storage device cache.

[0151] Step 5B, when all DMA commands corresponding to the NVMe write command are processed, the completion message generation circuit generates an NVMe write command processing completion message, and sends the NVMe write command processing completion message to the storage command processing unit.

[0152] Step 5C, the completion message generation circuit sends the NVMe write command processing completion message to the host interface, and sends it to the host through the host interface.

[0153] As an example, in the process of processing NVMe write commands, step 5B and step 5C are only executed once. After the DMA transfers corresponding to the NVMe write commands are completed (the last DMA command corresponding to the NVMe write command is processed), step 5B is executed before step 5C. Step 5A can be executed multiple times, for example, once each DMA command is processed. For example, after the write initiation circuit receives the DMA command processing completion message through step 4, if the DMA command corresponding to the DMA command processing completion message is not the last DAM command corresponding to the NVMe write command, the write initiation circuit immediately executes step 5A. For another example, if the DMA command corresponding to the DMA command processing completion message received in step 4 is the last DAM command corresponding to the NVMe write command, the write initiation circuit first executes step 5A, and then executes steps 5B and 5C in sequence.

[0154] In the above implementation scheme, during the processing of the NVMe write command, after receiving the processing completion message of the last DMA command of the multiple DMA commands corresponding to the NVMe write command, the write initiation circuit first sends the NVMe write command processing completion message to the storage command processing unit, and then sends the NVMe write command processing completion message to the host, so that the storage command processing unit has received the NVMe write command processing completion message before the host receives the NVMe write command processing completion message, and then the storage command processing unit has processed the NVMe write command processing completion message when receiving the storage command corresponding to the subsequent NVMe read command. Optionally, the NVMe write command processing completion messages sent to the storage command processing unit and the host may have different forms, but both indicate that the NVMe write command processing is completed. For example, the NVMe write command processing completion message sent to the host has a format that complies with the requirements of the NVMe protocol, while the NVMe write command processing completion message sent to the storage command processing unit has a custom format and can be shorter.

[0155] As an example, the storage command processing unit processes the NVMe write command processing completion message, including the storage command processing unit assigning a physical address to the logical address indicated by the received storage command, and updating the FTL table with the assigned physical address; storing the data corresponding to the LBA indicated by the storage command on the NVM chip according to the assigned physical address; or updating the FTL table with the storage device cache index Buffer_Index indicated by the storage command, so that when the storage command processing unit receives the storage command corresponding to the NVMe read command, it knows the location where the data indicated by the NVMe write command is stored (storage device cache or NVM chip).

[0156] Embodiment 2

[0157] In the previous embodiment, the completion message generation circuit sends the NVMe write command processing completion message to the storage command processing unit first and then to the host, hoping that before the host receives the NVMe write command processing completion message, the storage command processing unit has updated the FTL table corresponding to the LBA accessed by the NVMe write command according to the NVMe write command processing completion message, so that when the storage command processing unit receives the NVMe read command issued by the host, it can obtain the correct result from the FTL table.

[0158] However, in some cases, for example, the storage command processing unit is overloaded, resulting in its inability to receive the NVMe write command processing completion message sent by the completion message generation circuit in a timely manner, so that when the storage command processing unit processes the storage command from the NVMe read command, the FTL table has not been fully updated. To solve such problems, according to another embodiment of the present application, when the write initiation circuit sends the NVMe write command processing completion message to the storage command processing unit, it first obtains the working status of the storage command processing unit, for example, the working status includes busy and idle; according to the working status of the storage command processing unit, it determines how to send the NVMe write command processing completion message to the storage command processing unit and the host.

[0159] For example, when the completion message generation circuit in the write initiation circuit sends the NVMe write command processing completion message to the storage command processing unit, the write initiation circuit also obtains the working status of the storage command processing unit and determines whether the storage command processing unit is busy according to the working status. If the storage command processing unit is busy, the sending of the NVMe write command processing completion message to the host is postponed (such as suspending execution). Figure 4 When it is determined that the storage command processing unit is not busy (idle), the completion message generation circuit executes the following steps: Figure 4In step 5C, an NVMe write command processing completion message is sent to the host, so that the storage command processing unit can process the NVMe write command processing completion message when receiving the storage command corresponding to the NVMe read command.

[0160] For the storage command processing unit, it does not have the function of indicating its own busy status. According to the embodiment of the present application, the message transmission process between the storage command generation circuit and the storage command processing unit is used to identify whether the storage command processing unit is busy. By temporarily suspending the sending of the NVMe write command processing completion message to the storage command processing unit when the storage command processing unit is in a busy state, the occurrence of the aforementioned technical problems caused by the storage command processing unit not having time to process the NVMe write command completion message is avoided. In an embodiment of the present application, whether to delay sending the NVMe write command processing completion message to the storage command processing unit and the host is determined based on the transmission of the last storage command between the storage command generation circuit and the storage command processing unit.

[0161] See also Figure 5 As shown, the storage command generation circuit can determine whether the current DMA command is the last DMA command based on the received DAM command processing completion message (for example, the storage command generation circuit knows the total number of DMA commands corresponding to the NVMe write command, and then can determine whether the current DMA command is the last DMA command). If so, the storage command generation circuit generates the last storage command and sends it to the storage command processing unit.

[0162] The storage command processing unit exchanges information with the write initiation circuit in the form of a message queue. The storage command processing unit includes two receiving ports, each receiving port corresponds to a message queue, one message queue is used to receive the storage command sent by the storage command generation circuit, and the other message queue is used to receive the NVMe write command processing completion message generated by the completion message generation circuit. The message queue has the function of indicating whether it is Full or Not Full.

[0163] Figure 6 A schematic diagram showing an embodiment of the present application sending a storage command to a storage command processing unit is shown. Figure 6As shown, when the storage command generation circuit generates the last storage command corresponding to the NVMe write command, the complete storage command is divided into multiple sub-data, such as sub-data 1, sub-data 2, sub-data 3, and sub-data 4. The storage command generation circuit first tentatively adds the smallest part of the storage command (such as sub-data 1) to the message queue 1, and then observes whether the message queue 1 is Full; if the message queue 1 is in the Full state, it means that there are a lot of contents in the message queue 1, so it is inferred that the storage command processing unit is now in a busy state. If the NVMe write command processing completion message is sent to the storage command processing unit at this time, the storage command processing unit is likely to be unable to process it in time, and cause subsequent read command errors. At this time, the storage command generation circuit needs to suspend sending the last storage command, and the subsequent NVMe write command processing completion message is not sent. If the message queue 1 is in the Not Full state, it means that there are not many contents in the message queue 1, so it is inferred that the storage command processing unit is not in a busy state, then the storage command generation circuit can add other sub-data to the message queue 1 to continue to add the last storage command to the message queue 1, and the completion message generation circuit continues to send the NVMe write command processing completion message.

[0164] Embodiment 3

[0165] As an optional embodiment, the storage command processing unit maintains a write cache table, the write cache table includes multiple entries, each entry is used to cache a storage device cache index corresponding to an LBA. Figure 7 As shown, after the storage command processing unit receives the storage command corresponding to the NVMe write command sent by the write initiation circuit (as shown in Figure 7 The process (5A) shown in FIG. 5A) is as follows:<LBA,Buffer_Index> To update the write cache table ( Figure 7 The process shown (5A) receives<LBA,Buffer_Index> Update to write cache table), and the FTL table can be updated according to the write cache table. Among them, the write cache table is very small and is contained inside the control component. The time to update the write cache table is very short and can be ignored, so the update of the write cache table can take effect immediately; while the FTL table is very large and outside the control component. It takes a long time (such as 50us) to update the FTL table. During the time from the start of updating the FTL table to the time it takes effect, storage commands corresponding to NVMe read commands may be received. When processing these storage commands, accessing the FTL table may obtain the results before the update, resulting in data acquisition errors. Therefore, the storage device cache index is recorded in the write cache table.

[0166] The storage command processing unit will continue to update the FTL table according to the write cache table.<LBA,Buffer_Index> It will not always be stored in the write cache table, but the storage command processing unit cannot know in advance whether the LBA indicated by the storage command corresponding to the NVMe read command is in the write cache table. Therefore, in this embodiment, the storage command processing unit must query the write cache table after receiving the storage command corresponding to the NVMe read command.

[0167] As an example, after receiving the storage command corresponding to the NVMe read command (generated by the read initiation circuit), the storage command processing unit first queries the write cache table to determine whether there is a storage device cache index of the LBA indicated by the storage command corresponding to the NVMe read command in the write cache table. If the storage device cache index of the LBA indicated by the storage command corresponding to the NVMe read command exists in the write cache table, it can be determined that the data to be read by the NVMe read command is stored in the storage device cache at this time. In response to the data to be read by the storage command corresponding to the NVMe read command being stored in the storage device cache, the storage command processing unit generates a storage command processing completion message (carrying the storage device cache index) and feeds it back to the read initiation circuit. The read initiation circuit generates a DMA command (carrying the storage device cache index) based on the received storage command processing completion message, and sends the DMA command to the DMA transmission circuit, and the DMA transmission circuit moves data from the storage device cache to the host according to the DMA command carrying the storage device cache index.

[0168] If the storage device cache index of the LBA indicated by the storage command corresponding to the NVMe read command does not exist in the write cache table, the storage command processing unit can query the FTL table to obtain the address information corresponding to the LBA based on the LBA indicated by the storage command corresponding to the NVMe read command, and read the data based on the address information. The address information can be PPA or storage device cache index. If the address information is PPA, data can be read from the NVM chip based on PPA; if the address information is a storage device cache index, data can be read from the storage device cache based on the storage device cache index.

[0169] As an example, after the FTL table is updated based on the write cache table, the NVMe write command corresponding<LBA,Buffer_Index> As another example, when the data represented by the storage command corresponding to the NVMe write command is moved from the storage device cache to the NVM chip, the PPA corresponding to the LBA is recorded in the FTL table, and the data corresponding to the storage command stored in the write cache table is deleted.<LBA,Buffer_Index> .

[0170] As another example, if there is a storage device cache index of the LBA indicated by the storage command corresponding to the NVMe read command in the write cache table, at this time, the data to be read by the NVMe read command is stored in the storage device cache, and the storage of the data to be read by the NVMe read command in the storage device cache is caused by processing the NVMe write command. After the read initiation circuit moves the data from the storage device cache to the host through the DMA transmission circuit, the storage device cache space occupied by the data to be accessed by the storage command corresponding to the NVMe read command in the storage device cache is not released.

[0171] If the data in the storage device cache to be moved to the host according to the NVMe read command is read from the NVM chip by processing the storage command corresponding to the NVMe read command, the read initiation circuit releases the storage device cache space occupied by the data to be accessed by the storage command corresponding to the NVMe read command in the storage device cache after moving the data from the storage device cache to the host through the DMA transmission circuit.

[0172] As an example, the storage command processing unit determines the FTL table entry corresponding to the LBA in the FTL table according to the LBA recorded in each entry in the write cache table, records the Buffer_Index (storage device cache index) corresponding to the LBA into the corresponding FTL table entry, and uses the Buffer_Index to replace the PPA information originally recorded in the FTL table entry.<LBA,Buffer_Index> After the information is updated to the FTL table, the data stored in the write cache table can be released.<LBA,Buffer_Index> storage space. Figure 8 As shown, it is a schematic diagram of updating the content in the write cache table to the FTL table. Figure 8 The entries in the FTL table are represented by "entry<Buffer_Index> This form of expression does not represent the information stored in the actual FTL table entries. For example, entry 0 in the FTL table<Buffer_Index0> Indicates that the address information stored in the entry with index 0 in the FTL table is the cache index Buffer_Index0 of the storage device cache; entry 1 in the FTL table<Buffer_Index1> It indicates that the address information stored in the entry with index 1 in the FTL table is the cache index Buffer_Index1 of the storage device cache.

[0173] As another example, the storage command processing unit does not update the write cache table after receiving a DMA command processing completion message, but only updates the write cache table according to the instructions of each storage command after receiving the NVMe write command processing completion message.<LBA,Buffer_Index> For example, before the storage command processing unit receives the NVMe write command processing completion message, the storage command corresponding to the NVMe read command is received. Since the write cache table is updated only after the NVMe write command processing completion message is received, at this time, the write cache table does not store the LBA corresponding to the storage command corresponding to the NVMe read command.<LBA,Buffer_Index> , the storage command processing unit cannot query the LBA indicated by the storage command corresponding to the NVMe read command from the write cache table, the storage command processing unit will query the FTL table, and determine the PPA (NVM chip physical address) corresponding to the LBA indicated by the storage command corresponding to the NVMe read command according to the FTL table.

[0174] For example, the logical addresses indicated by the NVMe write command include LBA a, LBA a+1, and LBA a+2. At time t1, the write initiation circuit moves the data corresponding to LBA a to the Buffer (storage device cache) according to DMA command 1, and sends the storage command corresponding to DAM command 1 to the storage command processing unit; at time t2 (a time after t1), the write initiation circuit moves the data corresponding to LBA a+1 to the Buffer according to DAM command 2, and sends the storage command corresponding to DAM command 2 to the storage command processing unit; at time t3 (a time after t2), if the storage command processing unit receives the storage command corresponding to the NVMe read command, the storage command indicates LBA a. After the storage command processing unit receives the NVMe write command processing completion message, it processes the data according to the instructions of each storage command.<LBA,Buffer_Index> To update the write cache table, at this time (time t3), the DAM command 3 corresponding to LBAa+2 has not been processed yet, and the storage command processing unit has not yet<LBA a,Buffer_Index a> Update to the write cache table. Although there is new data corresponding to LBA a in the Buffer, since the write cache table does not record the relationship between LBA a and the storage device cache index, the storage command processing unit will query the PPA corresponding to LBA a from the FTL table, and then read the data to be read by the storage command corresponding to the NVMe read command from the PPA obtained from the query of the FTL table.

[0175] At time t4 (after time t3), the write initiation circuit moves the data of LBA a+2 to the buffer according to DAM command 3, generates an NVMe write command processing completion message, and sends it to the storage command processing unit. The storage command processing unit responds to the received NVMe write command processing completion message and records it in the write cache table.<LBA a,Buffer_Index a> ,<LBAa+1,Buffer_Index a+1> ,<LBA a+2,Buffer_Index a+2> ; At time t5 (after time t4), if the storage command processing unit receives a storage command corresponding to the NVMe read command, the storage command indicates LBA a; at this time, since there is LBA a in the write cache table, the storage command processing unit can obtain the Buffer_Index corresponding to LBA a from the write cache table to process the storage command corresponding to the NVMe read command.

[0176] Embodiment 4

[0177] Fig. 9 The NVMe write command processing process of another embodiment of the present application is shown.

[0178] See also Fig. 9 As shown, the storage command processing unit includes an LBA filter, which can be used to record LBAs. The LBA filter will prevent the storage command processing unit from processing the storage command corresponding to the LBA recorded by the LBA filter. After receiving the NVMe write command processing completion message sent by the write initiation circuit through process (5B), the storage command processing unit updates a group of LBAs indicated by the NVMe write command to the LBA filter. At this time, the LBA filter records a group of LBAs indicated by the NVMe write command (such as LBA0 to LBAN); for each LBA in the LBA filter, the storage command corresponding to the NVMe read command accessing it will be blocked.

[0179] As an example, if the storage command processing unit receives a storage command corresponding to the NVMe read command through process (7), the LBA filter is queried to detect whether the LBA indicated by the storage command corresponding to the NVMe read command exists in the LBA filter. As an example, if the storage command corresponding to the NVMe read command indicates LBA0, the LBA filter will indicate that LBA0 exists in the LBA filter, and the processing of the storage command corresponding to LBA0 will be suspended at this time.

[0180] After the LBA value is retrieved from the LBA filter, the data corresponding to the retrieved LBA value is stored (such as stored in the NVM chip), the corresponding address information is updated to the entry of the FTL table, and the retrieved LBA value is cleared from the LBA filter. For the storage command corresponding to the suspended LBA0, it is detected whether the LBA0 corresponding to the storage command is still in the LBA filter. If LBA0 is still in the LBA filter, the storage command is continued to be suspended; if LBA0 is not in the LBA filter, the data is read based on the physical address of the NVM chip corresponding to LBA0 recorded in the entry of the FTL table.

[0181] If the LBA indicated by the storage command corresponding to the NVMe read command does not exist in the LBA filter, the FTL table is queried according to the LBA indicated by the storage command corresponding to the NVMe read command to determine the address information of the data storage corresponding to the LBA, and the data is read based on the address information. The address information can be a PPA or a storage device cache index.

[0182] Embodiment 5

[0183] As an optional embodiment, after receiving a storage command corresponding to an NVMe write command, the storage command processing unit may also lock the FTL table entry corresponding to the LBA indicated by the storage command based on the LBA corresponding to the storage command, and by locking the FTL table entry, prevent the processing of the storage command corresponding to the FTL table entry in the locked state (the storage command corresponding to the NVMe read command).

[0184] As an example, the write initiation circuit generates a storage command based on a DMA command processing completion message corresponding to the received NVMe write command and provides it to the storage command processing unit. In response to receiving a storage command, the storage command processing unit locks the FTL table entry corresponding to the LBA indicated by the storage command to indicate that the FTL table entry corresponding to the LBA indicated by the storage command is in an unreadable state. As another example, when an entry in the FTL table is locked, although the entry is in an unreadable state, data can be written to the entry; for example, when entry 1 in the FTL table is locked, the storage device cache index corresponding to the LBA can be recorded in entry 1.

[0185] As an example, when the storage command processing unit receives the NVMe write command processing completion message and determines that the locked table entry in the FTL table has completed the update, it releases the lock of the FTL table entry.

[0186] The storage command processing unit responds to receiving a storage command corresponding to the NVMe read command (such as Fig.10In the process (7) shown in the figure, the FTL table is queried. If the FTL table entry corresponding to the LBA indicated by the storage command corresponding to the NVMe read command is locked, the processing of the storage command corresponding to the LBA is suspended, and the storage command is processed again after being unlocked.

[0187] The following is an example of how to lock and release an FTL table entry. The write initiation circuit generates a storage command based on a DMA command processing completion message corresponding to the received NVMe write command and provides it to the storage command processing unit. For example, the storage command indicates<LBA0,Buffer_Index0> See also Fig.10 As shown, LBA0 corresponds to entry 0 in the FTL table. In response to the received storage command, the storage command processing unit locks entry 0 in the FTL table. For example, in the FTL table, an identifier 1 is set for a specified field in entry 0, and identifier 1 indicates that entry 0 is in an unreadable state; and entry 0 is updated with Buffer_Index0.

[0188] When the storage command processing unit receives the NVMe write command processing completion message, it detects whether the entry of LBA0 corresponding to the NVMe write command in the FTL table has been updated. If the entry in the FTL table has been updated (such as recording PPA0 corresponding to LBA0 in the entry), it releases the lock of the FTL table entry and deletes the flag 1 set in the specified field in entry 0.

[0189] The embodiment of the present application provides a control component, including: a write initiation circuit, a DMA transmission circuit and a storage command processing unit;

[0190] The write initiation circuit and the DMA transmission circuit cooperate to process the DMA command corresponding to the NVMe write command; when all DMA commands corresponding to the NVMe write command are processed, the write initiation circuit generates a first message and a second message, and both the first message and the second message indicate that the NVMe write command processing is completed; the write initiation circuit sends the first message to the storage command processing unit and the second message to the host in sequence.

[0191] Among them, the write initiation circuit and the storage command processing unit are also used to execute other implementation schemes of the above-mentioned command processing method, which will not be elaborated one by one here.

[0192] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application. Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A command processing method, characterized in that: Applied to a control component, the method includes: In response to an NVMe write command sent by a host, processing the DMA command corresponding to the NVMe write command; When all DMA commands corresponding to the NVMe write command are processed, generating a first message and a second message, both the first message and the second message indicating that the NVMe write command is processed; Sequentially sending the first message to a storage command processing unit and sending the second message to the host.

2. The method according to claim 1, characterized in that It further includes: When sending the first message to the storage command processing unit, obtaining the working state of the storage command processing unit; When the storage command processing unit is in a busy state, delaying sending the second message to the host; When the storage command processing unit is not in a busy state, after sending the first message to the storage command processing unit, sending the second message to the host.

3. The method according to claim 1 or 2, characterized in that: It further includes: Updating a write cache table according to <LBA, storage device cache index> indicated by a storage command corresponding to the NVMe write command; Updating an FTL table according to the write cache table.

4. The method according to claim 3, characterized in that The method further includes: In response to a storage command corresponding to an NVMe read command sent by the host, detecting whether there is a first storage device cache index of the LBA indicated by the storage command corresponding to the NVMe read command in the write cache table; If the first storage device cache index exists, reading data from the storage device cache according to the first storage device cache index and feeding it back to the host; If the first storage device cache index does not exist, querying the FTL table according to the LBA indicated by the storage command corresponding to the NVMe read command to determine the corresponding address information, and reading data based on the address information and feeding it back to the host, where the address information is a physical address or a storage device cache index.

5. The method according to any one of claims 1 to 4, characterized in that: It further includes: Adding a set of LBA values indicated by a storage command corresponding to the NVMe write command to an LBA filter; Wherein, the LBA filter is used to identify whether a to-be-detected LBA value exists in the LBA filter.

6. The method according to claim 5, characterized in that The method further includes: In response to a storage command corresponding to an NVMe read command sent by the host, detecting whether there is a first LBA indicated by the storage command corresponding to the NVMe read command in the LBA filter; If the first LBA indicated by the storage command corresponding to the NVMe read command exists in the LBA filter, suspending processing of the storage command; If the first LBA indicated by the storage command corresponding to the NVMe read command does not exist in the LBA filter, querying the FTL table according to the first LBA to determine the address information of the FTL table entry corresponding to the first LBA, and reading data based on the address information and feeding it back to the host, where the address information is a physical address or a storage device cache index.

7. The method according to claim 6, characterized in that It further includes: Taking out the LBA values in the LBA filter, updating the FTL table according to the taken-out LBA values, and clearing the taken-out LBA values from the LBA filter; Acquire the first storage command whose processing is suspended, and detect whether the first LBA indicated by the first storage command is in the LBA filter; If the first LBA is in the LBA filter, continue to suspend processing of the first storage command; If the first LBA is not in the LBA filter, determine the address information of the FTL table entry corresponding to the first LBA, read data based on the address information and feed it back to the host.

8. The method according to any one of claims 1 to 7, characterized in that: Also includes: After receiving a storage command corresponding to the NVMe write command, the FTL table entry corresponding to the LBA indicated by the storage command is locked to prevent processing of the storage command accessing the LBA.

9. The method according to claim 8, characterized in that The method further comprises: In response to a storage command corresponding to the NVMe read command sent by the host, query the FTL table according to the LBA indicated by the storage command corresponding to the NVMe read command, and determine the corresponding first FTL table entry; If the first FTL table entry corresponding to the LBA indicated by the storage command corresponding to the NVMe read command is locked, suspend processing of the storage command; If the first FTL table entry corresponding to the LBA indicated by the storage command corresponding to the NVMe read command is not locked, data is read according to the address information of the first FTL table entry and fed back to the host.

10. A control component, characterized in that: include: Write initiation circuit, DMA transmission circuit and storage command processing unit; The write initiation circuit and the DMA transmission circuit cooperate to process the NVMe write command corresponding to the DMA command; When all DMA commands corresponding to the NVMe write command are processed, the write initiation circuit generates a first message and a second message, both of which indicate that the NVMe write command processing is completed; The write initiation circuit sends the first message to the storage command processing unit and the second message to the host in sequence.

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