Data processing method and device and data processing chip

Abstract

The invention discloses a data processing method and device and a data processing chip, and the method comprises the steps: obtaining a first target data set; each piece of first target data in the first target data set is all valid data in each first data object corresponding to a target data processing channel; on the basis of a balanced distribution strategy, first target data in the first target data set are distributed among the available hardware processing channels in a balanced mode; and performing data processing on the distributed first target data and a second data object corresponding to the distributed first target data in a second data object set indicated by the target data processing channel on each available hardware processing channel.

Description

Technical Field

[0001] The present application belongs to the field of artificial intelligence technology, and in particular, relates to a data processing method, device and data processing chip. Background Art

[0002] Neural Networks (NN) are complex network systems formed by a large number of simple processing units (called neurons) that are widely interconnected. At present, in data processing based on neural network models, there are a series of problems such as low computing performance / low efficiency, high resource demand and low resource utilization. How to solve at least some of these problems has become a technical difficulty in this field. Summary of the invention

[0003] To this end, this application discloses the following technical solutions:

[0004] A data processing method, comprising:

[0005] Acquire a first target data set; each first target data in the first target data set is all valid data in each first data object corresponding to the target data processing channel;

[0006] Based on a balanced allocation strategy, each first target data in the first target data set is evenly allocated among each available hardware processing channel;

[0007] Data processing is performed on each available hardware processing channel on the allocated first target data and the second data object corresponding to the allocated first target data in the second data object set indicated by the target data processing channel.

[0008] Optionally, the process of determining the first target data set includes:

[0009] Acquire a binary sequence of each first data object corresponding to the target data processing channel;

[0010] Extracting valid bit data in the binary sequence of each first data object; the valid data in the first data object is the valid bit data in the binary sequence of the first data object;

[0011] Aggregation processing is performed on valid bit data in the binary sequence of each first data object to obtain the first target data set.

[0012] Optionally, each first target data corresponds to corresponding location information, and the location information includes first location information used to indicate the location of the second data object corresponding to the first data object to which the first target data belongs, and second location information used to indicate the location of the first target data in the first data object to which it belongs.

[0013] Optionally, the first location information of each first target data includes an object identifier of a first data object to which the first target data belongs and a channel identifier of a target data processing channel corresponding to the first data object;

[0014] The second data object corresponding to the first target data in the second data object set indicated by the target data processing channel is: the second data object at the target position in the second data object set corresponding to the corresponding target data processing channel;

[0015] Among them, the corresponding target data processing channel is the data processing channel indicated by the channel identifier in the first position information of the first target data, and the target position is the position indicated by the object identifier in the first position information of the first target data in the indicated data processing channel.

[0016] Optionally, the first target data set is: a valid data sequence formed by all valid data in each of the first data objects; each valid data of the same first data object in the valid data sequence is arranged adjacently in sequence;

[0017] All valid data of the same first data object share the same first position information.

[0018] Optionally, the evenly distributing each first target data in the first target data set among each available hardware processing channel based on the evenly distributed strategy includes:

[0019] The first target data are distributed to the available hardware processing channels according to the number of the first target data and the number of the available hardware processing channels, so that the numbers of the first target data respectively obtained by different available hardware processing channels meet the proximity condition.

[0020] Optionally, performing data processing on each available hardware processing channel on the allocated first target data and a second data object corresponding to the allocated first target data in a second data object set indicated by the target data processing channel includes:

[0021] Based on the parallel processing mode of inter-channel parallelism, multiplication and accumulation operations are performed on the allocated first target data and the corresponding second data objects on each available hardware processing channel.

[0022] Optionally, the valid data in the first data object is valid bit data in a binary sequence of the first data object;

[0023] The parallel processing method based on inter-channel parallelism performs multiplication and accumulation operations on the allocated first target data and the corresponding second data object on each available hardware processing channel, including:

[0024] Acquire the first target data to be processed currently and the second data object corresponding to the first target data to be processed currently in each available hardware processing channel as a data pair to be processed;

[0025] Based on the parallel processing mode of inter-channel parallelism, the data pairs to be processed obtained by each available hardware processing channel are subjected to shift-based multiplication processing according to the second position information of the first target data in the data pairs to be processed, so as to obtain the multiplication result corresponding to each available hardware processing channel;

[0026] Accumulate the multiplication operation results corresponding to each available hardware processing channel to obtain a first addition operation result;

[0027] Adding the first addition result to the current historical accumulation result to obtain a second addition result, and updating the historical accumulation result with the second addition result;

[0028] The next first target data of the first target data currently being processed and the second data object corresponding to the next first target data are respectively obtained in each available hardware processing channel, the data pair to be processed is updated based on the next first target data and the corresponding second data object, and the parallel processing method based on inter-channel parallelism is looped to perform the shift-based multiplication operation processing step on the data pair to be processed obtained in each available hardware processing channel according to the second position information of the first target data in the data pair to be processed until the processing of all the first target data is completed, and the latest historical cumulative operation result is used as the operation result of all the first target data.

[0029] A data processing device, comprising:

[0030] A data acquisition module is used to acquire a first target data set; each first target data in the first target data set is all valid data in each first data object corresponding to the target data processing channel;

[0031] A data distribution module, configured to distribute each first target data in the first target data set evenly among each available hardware processing channel based on a balanced distribution strategy;

[0032] The data processing module is used to perform data processing on each available hardware processing channel on the allocated first target data and the second data object corresponding to the allocated first target data in the second data object set indicated by the target data processing channel.

[0033] A data processing chip, comprising:

[0034] A data acquisition component, used for acquiring first target data to be processed currently by each available hardware processing channel provided by the first computing component, and a second data object corresponding to the first target data to be processed currently, as a pair of data to be processed for each available hardware processing channel;

[0035] A first computing component is used to provide a plurality of available hardware processing channels, and based on a parallel processing mode of parallelism between channels, perform a shift-based multiplication operation on the data pairs to be processed obtained by each available hardware processing channel according to the second position information of the first target data in the data pairs to be processed, so as to obtain a multiplication operation result corresponding to each available hardware processing channel;

[0036] a second operation component, configured to accumulate the multiplication operation results corresponding to the available hardware processing channels to obtain a first addition operation result; and to add the first addition operation result to a current historical accumulation operation result to obtain a second addition operation result, so as to update the historical accumulation operation result with the second addition operation result;

[0037] Storage component, used to store historical accumulation operation results;

[0038] The data acquisition component is also used to respectively acquire the next first target data of the first target data currently being processed and the second data object corresponding to the next first target data in each available hardware processing channel, update the data pair to be processed based on the next first target data and the corresponding second data object, and loop to the processing of the first operation component until the various components based on the data processing chip complete the processing of all the first target data, and use the latest historical cumulative operation result as the operation result of all the first target data.

[0039] Optionally, the first operation component includes a plurality of shift units for shifting to obtain corresponding multiplication operation results, each shift unit serving as an available hardware processing channel;

[0040] The second operation component includes a first adding operation unit for accumulating the multiplication operation results corresponding to each available hardware processing channel to obtain the first addition operation result, and a second adding operation unit for adding the first addition operation result to a current historical accumulation operation result to obtain the second addition operation result;

[0041] The storage component includes a register unit for storing historical accumulation operation results;

[0042] The number of the first adding unit, the number of the second adding unit and the number of the registering unit are each one.

[0043] It can be seen from the above scheme that the present application discloses a data processing method, a device and a data processing chip, wherein the data processing method includes: obtaining a first target data set; each first target data in the first target data set is all valid data in each first data object corresponding to a target data processing channel; based on a balanced allocation strategy, each first target data in the first target data set is evenly allocated among each available hardware processing channel; and data processing is performed on each available hardware processing channel on the allocated first target data and the second data object corresponding to the allocated first target data in the second data object set indicated by the target data processing channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0045] Figure 1 It is a schematic diagram of the architecture of a four-way hardware module parallel system provided by this application;

[0046] Figure 2 This is a schematic diagram of different effective bit numbers in weights allocated to various hardware modules in a parallel system due to weight sparsification provided by the present application;

[0047] Figure 3 It is a schematic diagram of the binary sequence corresponding to each weight in the 3*3 weight matrix provided in this application and the valid bits contained therein;

[0048] Figure 4 It is a schematic diagram of the architecture of a two-way hardware module parallel system provided by this application;

[0049] Figure 5 This application provides a two-way hardware module parallel system Figure 3 A schematic diagram of the process of processing each weight shown;

[0050] Figure 6 It is a flow chart of the data processing method provided by this application;

[0051] Figure 7(a)-Figure 7(b) It is a schematic diagram of balancing the effective bit data among various available hardware processing channels provided by the present application;

[0052] Figure 8 This is an example of recording corresponding position information for each first target data provided by the present application;

[0053] Fig. 9 is another example of recording corresponding position information for each first target data provided by the present application;

[0054] Fig.10 is a schematic diagram of an exemplary composition architecture of a parallel system provided by the present application;

[0055] Fig.11 It is a structural diagram of the data processing device provided by the present application;

[0056] Fig.12 It is a composition structure diagram of the data processing chip provided by this application. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0058] In data processing based on neural network models, known technologies have problems such as low computing performance / low efficiency, high resource requirements and low resource utilization.

[0059] In order to solve at least some of the technical problems in the known technologies, the embodiments of the present application disclose a data processing method, a device and a data processing chip. The disclosed data processing method can be applied to, but not limited to, electronic devices such as personal computers or servers. And the disclosed data processing method can be applied to, but not limited to, natural language processing, image processing, video processing, speech recognition, industrial detection (such as equipment defect detection) and other fields.

[0060] In the neural network model, the network channels of the model network layer include input channels and output channels. One output channel corresponds to multiple input channels, and each input channel corresponds to a corresponding convolution kernel (Kemel) weight matrix, referred to as the "weight matrix". Accumulating the calculation results of the weight matrices on each input channel corresponding to the same output channel and the corresponding eigenvalues ​​in the corresponding input feature map will generate an output eigenvalue of the output channel, and each output eigenvalue forms the output feature map of the output channel.

[0061] In neural network models such as deep neural networks, due to pruning and quantization operations, some bits in the weights of the model network layer Kernel will be 0, or even the entire weight will be 0 (specifically, some bits in the binary sequence of the weights will be 0, or even all bits in the entire binary sequence will be 0). According to statistics, the proportion of 0-valued bits in weights in mainstream networks can reach more than 70%. However, the applicant found that the main operations in the neural network model are multiplication and addition operations, and the value of 0 does not contribute to either multiplication or addition operations. Therefore, the 0-valued bit of the weight is an invalid bit that does not contribute to the operation. Based on this, the embodiment of the present application improves the resource utilization and computing efficiency of the system by converting the weights into a binary sequence and discarding at least some of the 0-valued bits, i.e., invalid bits, in the binary sequence of the weights.

[0062] The network layer of the neural network model needs to perform multiplication and accumulation operations on the weights in the weight matrix on each input channel corresponding to the output channel and the corresponding eigenvalues ​​in the corresponding input feature map to generate the output eigenvalue of the output channel, and then form the corresponding output feature map based on the generated output eigenvalues.

[0063] In practical applications, the multiplication operation between the weight and the eigenvalue can be converted into a bit-by-bit multiplication operation between the weight binary sequence and the eigenvalue, and the multiplication operation between the bit and the eigenvalue can be converted into a shift operation to shift the eigenvalue based on the bit value in the weight binary sequence. Figure 1 In the multi-way hardware module parallel system shown, the mainstream hardware architecture usually has two or more shift modules (hardware modules) to process multiple weights in parallel. Correspondingly, a multi-way parallel architecture formed by multiple shift modules can be used to perform shift-based multiplication operations on different weights and corresponding eigenvalues ​​in parallel, and accumulate the results of each operation. The applicant has found that when the 0-valued bits, i.e., invalid bits, in the binary sequence of weights are discarded and each weight is processed in parallel based on a parallel system, the number of valid bits of different weights is often different, resulting in different amounts of data processed by each parallel shift module. The weight with the most valid bits will become the critical path of the system, becoming a system bottleneck and restricting system performance. Figure 2 In the example, four binary sequences are provided, which are binary sequences corresponding to four weights. Sparsification causes the effective bits of each weight to be different, ranging from 1 to 5. When the four weights are respectively assigned to the four-way shift module for parallel processing, the binary sequence corresponding to the first weight has 5 effective bits, which is greater than the number of effective bits in other binary sequences, thus becoming the critical path of the system. Only after all 5 bits of the first weight are processed can the system switch to the next set of data for processing.

[0064] In practical applications, the critical path length is often much larger than other path lengths. Due to the limitations of the parallel capabilities of parallel systems, multiple rounds of allocation and processing of each weight are often required, resulting in low system resource utilization and low processing efficiency.

[0065] See also Figure 3 The example specifically provides a schematic diagram of the binary sequence corresponding to each weight in the 3*3 weight matrix and the valid bits it contains. In this example, the weight matrix contains 9 weights, each weight has 8 bits of data, and the data bits are random and sparse. The specific situation of the valid bits and invalid bits in the binary sequence of each weight is as follows Figure 3 As shown in , in a convolutional neural network, the multiplication results of the 9 weights and the corresponding eigenvalues ​​need to be accumulated to obtain a final output result (output eigenvalue). Assume that there are two hardware modules in a multi-channel hardware module parallel system that process the shift multiplication operations of each weight in parallel (shift-based multiplication operations), as shown in Figure 4 As shown, the system processing is completed only when both hardware modules are processed.

[0066] In adopting Figure 4 When the two-way hardware module parallel system processes it, the 9 weights in the 3*3 weight matrix are distributed to the two hardware modules for processing in multiple rounds in a fixed order. Two weights are processed in each round, and the 9 weights are processed in five rounds in total. Finally, the processing results corresponding to each weight in multiple rounds are accumulated into one output data through the accumulator (adder tree). The processing flow is as follows Figure 5 As shown in the figure, because each hardware module processes a fixed weight in each round, the next round of processing can only be started when both hardware modules are processed. The module with the largest amount of data in the two modules becomes the critical path of the system, so the total processing time of the system is the sum of the processing time of the five rounds of critical paths: 3+3+6+4+5=21. Among them, in some rounds of processing, the length of the critical path is much longer than the length of other paths, resulting in low resource utilization of the two hardware modules and a large number of execution rounds, which further affects the processing efficiency.

[0067] In order to address the problem of low hardware resource utilization and low computing efficiency caused by the different numbers of effective bits between bit-sparse network weights, the embodiment of the present application proposes a technical idea of ​​aggregating the effective bits of different weights in the input channel weight matrix and evenly distributing them to various hardware modules for parallel processing, so as to reduce the difference between the critical path length and the non-critical path length, and reduce the number of allocation rounds, thereby achieving the technical effects of reducing storage and transmission bandwidth requirements, reducing resource requirements, and improving system resource utilization and computing efficiency.

[0068] See also Figure 6, is a flow chart of a data processing method provided in an embodiment of the present application, and the data processing method includes the following processing steps:

[0069] Step 601, obtaining a first target data set; each first target data in the first target data set is all valid data in each first data object corresponding to a target data processing channel.

[0070] The embodiments of the present application mainly take the data processing of a neural network model (such as a deep neural network model) as an example to illustrate the solution.

[0071] The target data processing channel may include but is not limited to one or more input channels of the network layer of the neural network model. For example, for image processing based on the neural network model, the target data processing channel may specifically include any one or more input channels of the R, G, and B primary color input channels of the model convolution layer and the texture input channel and semantic input channel.

[0072] When the target data processing channel includes multiple input channels, the multiple input channels included are specifically multiple input channels corresponding to the same output channel in the model network layer.

[0073] The valid data in the first data object refers to the data contained in the first data object that has contribution value to the data processing of the first data object, and specifically can be the valid bit data in the binary sequence of the first data object; and the data contained in the first data object that does not have contribution value to the data processing can be regarded as the non-valid data or invalid data of the first data object, and specifically can be the invalid bit data in the binary sequence of the first data object.

[0074] For the data processing scenario of the neural network model, the first data object can specifically be the weight in the convolution kernel weight matrix corresponding to the corresponding input channel of the network layer of the neural network model. The valid data in the first data object can be the valid bit data in the binary sequence of the weight, that is, the valid bit data "1" (referred to as valid bit), and the invalid bit data "0" (referred to as invalid bit) in the binary sequence of the weight can be regarded as invalid data in the first data object.

[0075] The first target data set is specifically a data set formed by aggregating all valid data in each first data object corresponding to the target data processing channel. Each first target data in the first target data set is corresponding to all valid data in each first data object corresponding to the target data processing channel.

[0076] Specifically, the binary sequence of each first data object corresponding to the target data processing channel can be obtained, the valid bit data in the binary sequence of each first data object can be extracted, and the valid bit data in the binary sequence of each first data object can be aggregated to obtain the first target data set.

[0077] For the data processing scenario of the neural network model, the first target data set can be formed by converting each weight in the convolution kernel weight matrix corresponding to the target data processing channel (one or more input channels) into a binary sequence, extracting and aggregating the valid bit data "1" in the binary sequence of each weight. Each valid bit data "1" can be regarded as a first target data in the first target data set.

[0078] Step 602: Based on a balanced allocation strategy, each first target data in the first target data set is evenly allocated among each available hardware processing channel.

[0079] Available hardware processing channels are currently unoccupied hardware computing channels that can be scheduled to perform required operations on data, such as computing channels based on operators and registers. Each channel can include the required number of operators and / or registers, and can also include other required hardware.

[0080] For data processing of the neural network model, the available hardware processing channel can be a hardware module in the above-mentioned multi-channel hardware module parallel system, that is, each unoccupied hardware module in the parallel system can be regarded as an available hardware processing channel. For example, when all hardware modules in the parallel system are unoccupied, Figure 1 A parallel system with four available hardware processing channels for Figure 4 A parallel system comprising two available hardware processing channels.

[0081] After obtaining the first target data set, this step evenly distributes each first target data in the first target data set among each available hardware processing channel based on a balanced allocation strategy, which can be further implemented as follows: each first target data in the first target data set is allocated to each available hardware processing channel according to the number of first target data and the number of available hardware processing channels, so that the number of first target data obtained by different available hardware processing channels respectively meets the proximity condition.

[0082] In practical applications, based on the idea of ​​equal distribution, the first target data can be evenly distributed to the available hardware processing channels according to the number of first target data and the number of available hardware processing channels, so that the number of first target data obtained by different available hardware processing channels meets the proximity condition.

[0083] The number of first target data obtained by each available hardware processing channel satisfies the proximity condition, which may be, but is not limited to, any of the following:

[0084] a) the number of first target data obtained by each available hardware processing channel is the same;

[0085] b) The numbers of first target data obtained by at least some of the available hardware processing channels are different, but the absolute value of the difference between the numbers of first target data obtained by at least some of the available hardware processing channels is less than a set threshold.

[0086] c) After completing data allocation, the critical path length corresponding to each available hardware processing channel is reduced compared to the sum of the critical path lengths corresponding to multiple rounds of allocation of each available hardware processing channel under the conventional allocation method (i.e., allocating each weight in the weight matrix corresponding to the target data processing channel to each available hardware processing channel in multiple rounds with weight as the minimum allocation unit).

[0087] exist Figure 5 In the conventional allocation method corresponding to the example, allocation is performed with weight as the minimum allocation unit, and each valid bit contained in each weight is allocated to the same available hardware processing channel. Different from the conventional allocation method, the embodiment of the present application no longer allocates with weight as the minimum allocation unit, and the allocation granularity is refined to the first target data, and specifically based on the number of first target data in the first target data set and the number of available hardware processing channels, a round of balanced allocation is performed between the available hardware processing channels, that is, all the first target data are evenly allocated to each available hardware processing channel through one round of allocation, so as to achieve the effect of reducing the total processing time of the parallel system for all valid data in each first data object corresponding to the target data processing channel.

[0088] For example, for Figure 3 The corresponding 9 weights can be based on the method of the present application, and each valid bit in the binary sequence of the 9 weights can be aggregated together to form a first target data set. The total number of valid bits in the binary sequence of the 9 weights, that is, the number of first target data in the first target data set, is obtained by accumulating the number of valid bits contained in the binary sequence of each weight. Then, the number of valid bits that should be allocated to each available hardware processing channel (hardware module) in the parallel system is calculated in an average distribution manner: the number of valid bits allocated to a single available hardware processing channel = the total number of valid bits / the number of available hardware processing channels.

[0089] for Figure 3 For example, the total number of valid bits in the binary sequence of 9 weights is 26. Figure 4For a parallel system, the number of valid bits allocated to each of the two available hardware processing channels is 26 / 2 = 13. For specific allocation, see Figure 7(a)-Figure 7(b) As shown, compared with the conventional allocation method mentioned above, the total system processing time can be reduced from 21 to 13, which can correspondingly reduce the storage and transmission bandwidth requirements, reduce resource requirements, improve system resource utilization, and improve computing efficiency.

[0090] In practical applications, when calculating the number of valid bits allocated to a single available hardware processing channel according to the above formula, there may be a situation where the average operation result is not an integer. In this case, the average operation result can be rounded (rounded up or rounded down) to ensure that the number of valid bits allocated to a single available hardware processing channel is an integer. It is easy to understand that when the average operation result is not an integer and is rounded, the number of valid bits obtained by at least some of the available hardware processing channels is different. For example, assuming that the total number of valid bits is 27, the number of valid bits processed by the two available hardware processing channels can be 13 and 14, or 14 and 13, respectively, as long as the allocation result satisfies any of the above proximity conditions a)-c).

[0091] Step 603: Perform data processing on each available hardware processing channel on the allocated first target data and the second data object corresponding to the allocated first target data in the second data object set indicated by the target data processing channel.

[0092] Still taking the data processing scenario of the neural network model as an example, the second data object set indicated by the target data processing channel is specifically the feature map corresponding to the input channel, and the second data object is the feature value in the feature map corresponding to the input channel.

[0093] The second data object corresponding to the first target data in the second data object set indicated by the target data processing channel is the second data object corresponding to the first data object to which the first target data belongs in the second data object set indicated by the corresponding target data processing channel. Taking the first target data as the valid bit data (valid bit) in the weight as an example, the corresponding second data object is specifically the feature value corresponding to the weight to which the valid bit data belongs in the feature map of the corresponding input channel.

[0094] Among them, the feature map can be but not limited to various types of data such as images and voices. The neural network model can specifically perform one-dimensional convolution, two-dimensional convolution or three-dimensional convolution on the feature map, without limitation, depending on actual needs. For example, for a one-dimensional convolution kernel of size 1*3, a one-dimensional convolution can be performed on a 1*3 feature map based on a 1*3 weight matrix, and for a two-dimensional convolution kernel of size 3*3, a two-dimensional convolution can be performed on a 3*3 feature map based on a 3*3 weight matrix.

[0095] After the first target data in the first target data set is evenly distributed among the available hardware processing channels, the allocated first target data and the corresponding second data object can be obtained on each available hardware processing channel (such as obtaining the allocated valid bits and the corresponding eigenvalues), and based on the parallel processing method of parallelism between channels, the required data processing is performed on the allocated first target data and the corresponding second data object on each available hardware processing channel.

[0096] Among them, the first target data at corresponding positions on different available hardware processing channels are processed in parallel. For example, for two available hardware processing channels, the first valid bit data corresponding thereto are processed in parallel on the two available hardware processing channels. Similarly, the second (or third...nth) valid bit data corresponding thereto are processed in parallel on the two available hardware processing channels.

[0097] Optionally, the data processing performed may include multiplication and accumulation processing, that is, first performing a shift-based multiplication operation on the current first target data to be processed and its corresponding second data object on each available hardware processing channel, and then accumulating the multiplication results on each channel, but not limited to this. When applying this application, the data processing performed may depend on the actual application requirements.

[0098] To sum up, the data processing method disclosed in the embodiment of the present application, by aggregating all valid data in each first data object corresponding to the target data processing channel to form a first target data set, and based on a balanced allocation strategy, evenly distributes each first target data in the first target data set among each available hardware processing channel, can effectively reduce the difference between the critical path length and the non-critical path length in a multi-channel hardware module parallel system, and reduce the number of allocation rounds of all valid data in each first data object corresponding to the target data processing channel in the parallel system, which can accordingly achieve technical effects such as reducing storage and transmission bandwidth requirements, reducing resource requirements, and improving system resource utilization and computing efficiency.

[0099] In an optional embodiment, each first target data in the first target data set corresponds to corresponding position information. When the first target data set is obtained by aggregating valid bit data in the binary sequence of each first data object corresponding to the target data processing channel, the corresponding position information is also recorded and stored for each first target data in the first target data set.

[0100] The position information corresponding to the first target data includes first position information for indicating the position of the second data object corresponding to the first data object to which the first target data belongs, and second position information for indicating the position of the first target data in the first data object to which it belongs.

[0101] The second data object corresponding to the first target data in the second data object set indicated by the target data processing channel is: the second data object at the target position in the second data object set corresponding to the corresponding target data processing channel. The corresponding target data processing channel and the target position are respectively the data processing channel indicated by the first position information in the position information corresponding to the first target data and the indicated position in the indicated data processing channel.

[0102] The first position information corresponding to each first target data may further include the object identifier of the first data object to which the first target data belongs and the channel identifier of the target data processing channel corresponding to the first data object. Optionally, if the target data processing channel participating in the aggregation of valid bit data includes only one input channel, that is, the aggregation of valid bit data is performed only between the weights contained in the weight matrix corresponding to the one input channel, the channel identifier in the first position information corresponding to the first target data may be empty, or the information item of the channel identifier may not be set in the first position information, and the target data processing channel corresponding to the first data object to which the first target data belongs is assumed to be the one input channel participating in the aggregation of valid bit data (valid bit).

[0103] Therefore, the corresponding target data processing channel mentioned above is specifically the data processing channel indicated by the channel identifier in the first position information of the first target data, or is the default corresponding data processing channel that participates in the aggregation of valid bit data; the target position is specifically the position indicated by the object identifier in the first position information corresponding to the first target data in the corresponding target data processing channel.

[0104] In addition to the first position information, the present application also records the second position information of the first target data in its first data object, for example, recording the bit position information corresponding to each valid bit in the first target data set in the binary sequence of its weight, so that when a subsequent shift-based multiplication operation is performed on the valid bit and the corresponding eigenvalue, correct shift operations can be performed based on the recorded bit position information.

[0105] Still taking the data processing scenario of the neural network model as an example, the second data object set corresponding to the target data processing channel is specifically the feature map corresponding to the input channel, and the second data object is the feature value in the input feature map. After the valid bits of the weights in the weight matrix corresponding to one / multiple input channels are aggregated to obtain a first target data set containing each valid bit, optionally, the present application simultaneously records the corresponding position information for each valid bit (first target data) in the obtained first target data set, and the position information corresponding to the valid bit includes the first position information and the second position information. The first position information further includes a weight ID (Weight ID) and a channel ID (which may be empty or this information item is not set), which are respectively used to indicate the position of the weight to which the valid bit belongs in the weight matrix (such as the position in the 3*3 weight matrix), and the input channel corresponding to the weight to which it belongs, and the second position information is used to indicate the bit position corresponding to the valid bit in the binary sequence of the weight to which it belongs.

[0106] For example, for Figure 3 For example, after aggregating the valid bits in the 9 binary sequences corresponding to the 9 weights, see Figure 8 , respectively, record the corresponding weight ID and valid bit position for each valid bit, to indicate the position of the weight to which the valid bit belongs in the 3*3 weight matrix, and the bit position of the valid bit in the binary sequence of the weight to which it belongs. In this example, since only one input channel (i.e. Figure 3 The valid bits in the binary sequence of each weight corresponding to the 3*3 weight matrix corresponding to the 9 weight binary sequences in the input channel are aggregated, so the record of the channel identifier is omitted.

[0107] Thus, for each valid bit in the first target data set, the feature value of the weight ID in the first position information corresponding to the valid bit in the feature map of the input channel indicated by the channel ID in the first position information or the default input channel can be obtained as the second data object corresponding to the valid bit. And subsequently, when performing a shift-based multiplication operation on the valid bit and the corresponding feature value in the corresponding available hardware processing channel, the number of shifts for the corresponding feature value can be determined based on the second position information of the valid bit to ensure correct shift processing.

[0108] In an optional embodiment, the first target data set is: a valid data sequence formed by all valid data in each first data object corresponding to the target data processing channel; each valid data of the same first data object in the valid data sequence is arranged adjacently in sequence.

[0109] All valid data of the same first data object share the same first position information.

[0110] As described above, the valid data in the first data object is specifically valid bit data in the binary sequence of the first data object, such as valid bit "1".

[0111] In this embodiment, when the valid bit data (valid bit) in the binary sequence of each first data object corresponding to the target data processing channel is aggregated to obtain the first target data set, preferably, the valid bit data of the same first data object are arranged adjacent to each other in sequence, so that the obtained first target data set is a valid bit data sequence formed by all the valid bit data in the first data objects, and the valid bit data of the same first data object are aggregated together in the valid bit data sequence.

[0112] For this implementation, when recording and storing the corresponding first position information for each valid bit data (first target data) in the valid bit data sequence (first target data set), for each valid bit data of the same first data object, preferably, only one (one copy) of the first position information is recorded and stored therefor, and each valid bit data of the same first data object shares the same first position information.

[0113] In practical applications, optionally, the number of valid bit data corresponding to each (each copy) of the recorded first position information in the valid bit data sequence can be recorded to indicate how many valid bit data share the first position information.

[0114] against Figure 3 The binary sequences of the 9 weights in the example are aggregated according to the method of this embodiment. Fig. 9, provides a schematic diagram of the relevant position information recorded and stored for the aggregated valid bit data sequence, including the weight ID (Weight ID) and the valid bit position, which are used to indicate the position of the weight to which the corresponding valid bit belongs in the 3*3 weight matrix, and the bit position of the corresponding valid bit in the binary sequence of the weight to which it belongs. At the same time, the number of valid bits corresponding to each weight ID is also recorded ( Fig. 9 In the figure, it is represented as "Weight valid bit number"), so that each valid bit data in the valid bit data sequence can be mapped to a unique weight ID in combination with the valid bit number corresponding to the weight ID, thereby facilitating the determination of the eigenvalue corresponding to each valid bit data.

[0115] In the neural network model, the weight information corresponding to the input channel of each network layer is known after the network training is completed. In practical applications, software can be used to perform the effective bit aggregation processing proposed in the embodiment of the present application on the weights of the input channels of each network layer of the model, as well as the recording and storage processing of the corresponding position information.

[0116] In this embodiment, when the valid bit data (valid bit) in the binary sequence of each first data object corresponding to the target data processing channel is aggregated to obtain the first target data set, by arranging the valid bit data of the same first data object adjacent to each other in sequence, and by making the valid bit data of the same first data object share the same first position information, it is possible to further compress the first position information corresponding to the valid bit data (first target data) in the first target data set, thereby further saving the occupancy of storage space and saving bandwidth requirements.

[0117] In an optional embodiment, based on the parallel processing mode of inter-channel parallelism, the allocated first target data and the corresponding second data object are processed by multiplication and accumulation operations on each available hardware processing channel, which can be further implemented as the following processing process:

[0118] 11) Acquire the first target data to be processed currently and the second data object corresponding to the first target data to be processed currently in each available hardware processing channel as a data pair to be processed.

[0119] Each available hardware processing channel in a parallel system is respectively allocated a certain number of first target data, such as a certain number of valid bits. In practical applications, optionally, each first target data allocated to each available hardware processing channel can be organized in a sequence or queue manner, and can start from a preset starting position (such as the head or tail of the sequence), read the first target data in the corresponding sequence / queue in sequence, and use the read data as the first target data to be processed currently.

[0120] At the same time, a second data object corresponding to the first target data to be processed is obtained to form a data pair to be processed with the first target data to be processed.

[0121] Among them, the second data object corresponding to the first target data to be processed can be read according to the first position information corresponding to the first target data to be processed. For example, for the valid bit to be processed, according to its corresponding Weight ID, the feature value corresponding to the Weight ID is read from the feature map corresponding to the corresponding input channel as the second data object corresponding to the valid bit.

[0122] In practical applications, the parallel system can specifically determine the second data object corresponding to the first target data to be processed based on the first position information corresponding to the first target data to be processed, so as to read it; or it can also be based on software, using software to determine the second data objects corresponding to each first target data in the first target data set in advance based on the first position information corresponding to each first target data, and store them in a specified location, and at the same time establish a mapping relationship between the second data object and the first target data at the specified location, and the available hardware processing channels in the subsequent parallel system can directly read the required second data object from the specified location based on the established mapping relationship.

[0123] 12) Based on the parallel processing method of inter-channel parallelism, for the data pairs to be processed obtained by each available hardware processing channel pair, a shift-based multiplication operation is performed according to the second position information of the first target data in the data pairs to be processed, so as to obtain the multiplication operation result corresponding to each available hardware processing channel.

[0124] After each available hardware processing channel obtains the current data pair to be processed through step 11), the second data object in the data pair to be processed can be further shifted according to the second position information of the first target data in the current data pair to be processed, so as to realize the multiplication operation of the first target data and the corresponding second data object in the data pair to be processed.

[0125] For example, assuming that the convolution kernel weight corresponds to an 8-bit binary sequence, and the positions of each bit in the 8-bit binary sequence are 8, 7, 6, ..., 1 from high to low, if the second position information of the valid bit in the current data pair to be processed indicates that the bit position of the valid bit in the corresponding weight is i, i is an integer, and 1≤i≤8, then the eigenvalue corresponding to the valid bit can be moved to a higher position by (i-1) bits in the available hardware processing channel.

[0126] Each available hardware processing channel processes the obtained data to be processed in parallel.

[0127] From the perspective of hardware implementation, each available hardware processing channel can use a shifter to implement the shift processing required in this step. For an 8-bit weighted binary sequence, the shifter used can be a 7-bit shifter.

[0128] For an n-way parallel system, n shifters are required accordingly, and each shifter can be regarded as an available hardware processing channel of the parallel system. Taking a two-way parallel system as an example, an exemplary composition architecture of the parallel system is as follows: Fig.10 As shown, it includes two shifters (Shifter), two adders (Adder) for addition processing and a register (Flop) for data storage. The connection relationship of each component in the system can be found in Fig.10 .

[0129] 13) Accumulate the multiplication results corresponding to each available hardware processing channel to obtain a first addition result.

[0130] Specifically, the first adder of the two adders in the parallel system may be used to accumulate the multiplication results corresponding to each available hardware processing channel, thereby obtaining the first addition result.

[0131] For a weighted binary sequence of 8 bits in length, the first adder used may be a 16-bit adder, such as Fig.10 The 16bit Adder in .

[0132] 14) Adding the first addition result to the current historical accumulation result to obtain a second addition result, and using the second addition result to update the historical accumulation result.

[0133] The historical accumulation operation result is the multiplication and accumulation operation result of all processed data so far obtained in the process of performing multiple rounds of iterative processing on the data in the first target data set based on the parallel mode between channels by using the parallel system. It is easy to understand that when the first target data set is initially processed, the historical accumulation operation result is zero or empty.

[0134] In this step, the second adder of the two adders in the parallel system can be used to accumulate the first addition result and the current historical accumulation result to obtain the second addition result, thereby completing the processing of each current pair of data to be processed.

[0135] For a weighted binary sequence of 8 bits in length, the second adder used may be a 17-bit adder, such as Fig.10 17bit Adder in.

[0136] 15) Obtain the next first target data of the first target data currently being processed and the second data object corresponding to the next first target data in each available hardware processing channel, update the data pair to be processed based on the next first target data and the corresponding second data object, and loop to step 12) until the processing of all the first target data is completed, and use the latest historical cumulative calculation result as the calculation result of all the first target data.

[0137] After completing the processing of each current pair of data to be processed, based on the idea of ​​iteration, the next first target data of the currently processed first target data can be obtained in each available hardware processing channel, and used as the new first target data to be processed, triggering a new round of processing of the first target data to be processed and the corresponding second data object, until the parallel system completes the data processing of the first target data set, and the latest historical cumulative operation result is used as the operation result of the first target data set to obtain the corresponding output characteristic value.

[0138] The network layer of the neural network model needs to perform multiplication and accumulation operations on the weights in the weight matrix on each input channel corresponding to the output channel and the corresponding eigenvalues ​​in the corresponding input feature map to generate the output eigenvalues ​​of the output channel. The present application forms a first target data set by aggregating all valid data in each first data object corresponding to the target data processing channel, and evenly distributes the first target data in the first target data set to each available hardware processing channel for parallel multiplication and accumulation operations. It will not change the calculation results of all valid data in each first data object corresponding to the target data processing channel, and can still ensure the correctness of the calculation results.

[0139] The hardware architecture of the parallel system adopted in the embodiment of the present application is basically the same as the hardware architecture under the conventional allocation method, without adding additional hardware resources, but the system performance is significantly improved compared to the data computing performance under the conventional allocation method.

[0140] Corresponding to the above-mentioned data processing method, the embodiment of the present application also provides a data processing device, whose composition structure is as follows: Fig.11 As shown, including:

[0141] The data acquisition module 1101 is used to acquire a first target data set; each first target data in the first target data set is all valid data in each first data object corresponding to the target data processing channel;

[0142] A data allocation module 1102 is used to evenly allocate each first target data in the first target data set among each available hardware processing channel based on a balanced allocation strategy;

[0143] The data processing module 1103 is used to perform data processing on each available hardware processing channel on the allocated first target data and the second data object corresponding to the allocated first target data in the second data object set indicated by the target data processing channel.

[0144] In an optional implementation manner, the apparatus further includes a construction module for constructing the first target data set, and when constructing the first target data set, the construction module is specifically used to:

[0145] Acquire a binary sequence of each first data object corresponding to the target data processing channel;

[0146] Extracting valid bit data in the binary sequence of each first data object; the valid data in the first data object is the valid bit data in the binary sequence of the first data object;

[0147] Aggregation processing is performed on valid bit data in the binary sequence of each first data object to obtain the first target data set.

[0148] In an optional implementation, each first target data corresponds to corresponding location information, and the location information includes first location information used to indicate the location of a second data object corresponding to the first data object to which the first target data belongs, and second location information used to indicate the location of the first target data in the first data object to which it belongs.

[0149] In an optional implementation manner, the first location information of each first target data includes an object identifier of a first data object to which the first target data belongs and a channel identifier of a target data processing channel corresponding to the first data object;

[0150] The second data object corresponding to the first target data in the second data object set indicated by the target data processing channel is: the second data object at the target position in the second data object set corresponding to the corresponding target data processing channel;

[0151] Among them, the corresponding target data processing channel is the data processing channel indicated by the channel identifier in the first position information of the first target data, and the target position is the position indicated by the object identifier in the first position information of the first target data in the indicated data processing channel.

[0152] In an optional implementation manner, the first target data set is: a valid data sequence formed by all valid data in the first data objects; each valid data of the same first data object in the valid data sequence is arranged adjacently in sequence;

[0153] All valid data of the same first data object share the same first position information.

[0154] In an optional implementation, the data allocation module 1102 is specifically used to allocate each first target data to each available hardware processing channel according to the number of first target data and the number of available hardware processing channels, so that the number of first target data obtained by different available hardware processing channels respectively meets the proximity condition.

[0155] In an optional implementation, the data processing module 1103 is specifically used to perform multiplication and accumulation operations on the allocated first target data and the corresponding second data object on each available hardware processing channel based on a parallel processing method of inter-channel parallelism.

[0156] In an optional implementation, the data processing module 1103, when performing multiplication and accumulation operations on the allocated first target data and the corresponding second data object on each available hardware processing channel in a parallel processing manner based on inter-channel parallelism, is specifically configured to:

[0157] Acquire the first target data to be processed currently and the second data object corresponding to the first target data to be processed currently in each available hardware processing channel as a data pair to be processed;

[0158] Based on the parallel processing mode of inter-channel parallelism, the data pairs to be processed obtained by each available hardware processing channel are subjected to shift-based multiplication processing according to the second position information of the first target data in the data pairs to be processed, so as to obtain the multiplication result corresponding to each available hardware processing channel;

[0159] Accumulate the multiplication operation results corresponding to each available hardware processing channel to obtain a first addition operation result;

[0160] Adding the first addition result to the current historical accumulation result to obtain a second addition result, and using the second addition result to update the historical accumulation result;

[0161] The next first target data of the first target data currently being processed and the second data object corresponding to the next first target data are respectively obtained in each available hardware processing channel, the data pair to be processed is updated based on the next first target data and the corresponding second data object, and the parallel processing method based on inter-channel parallelism is looped to perform the shift-based multiplication operation processing step on the data pair to be processed obtained in each available hardware processing channel according to the second position information of the first target data in the data pair to be processed until the processing of all the first target data is completed, and the latest historical cumulative operation result is used as the operation result of all the first target data.

[0162] As for the data processing device provided in the embodiment of the present application, since it corresponds to the data processing method provided in the above method embodiment, the description is relatively simple. For the relevant similarities, please refer to the description of the above method embodiment, which will not be described in detail here.

[0163] In addition, the present application also provides a data processing chip, the composition structure of which is as follows: Fig.12 As shown, including:

[0164] The data acquisition component 1201 is used to acquire the first target data to be processed currently by each available hardware processing channel provided by the first computing component, and the second data object corresponding to the first target data to be processed currently, as a pair of data to be processed for each available hardware processing channel;

[0165] The first computing component 1202 is used to provide a plurality of available hardware processing channels, and based on a parallel processing mode of parallelism between channels, perform a shift-based multiplication operation on the data pairs to be processed obtained by each available hardware processing channel according to the second position information of the first target data in the data pairs to be processed, so as to obtain a multiplication operation result corresponding to each available hardware processing channel;

[0166] The second operation component 1203 is used to accumulate the multiplication operation results corresponding to each available hardware processing channel to obtain a first addition operation result; and to add the first addition operation result to the current historical accumulation operation result to obtain a second addition operation result, so as to update the historical accumulation operation result with the second addition operation result;

[0167] Storage component 1204, used to store historical accumulation operation results;

[0168] The data acquisition component 1201 is also used to respectively acquire the next first target data of the first target data currently being processed and the second data object corresponding to the next first target data in each available hardware processing channel, update the data pair to be processed based on the next first target data and the corresponding second data object, and loop to the processing of the first operation component until the various components based on the data processing chip complete the processing of all the first target data, and use the latest historical cumulative operation result as the operation result of all the first target data.

[0169] Optionally, the first operation component 1202 includes a plurality of shift units for shifting to obtain corresponding multiplication operation results, each shift unit serving as an available hardware processing channel;

[0170] The second operation component 1203 includes a first adding operation unit for accumulating the multiplication operation results corresponding to each available hardware processing channel to obtain the first addition operation result, and a second adding operation unit for adding the first addition operation result to the current historical accumulation operation result to obtain the second addition operation result;

[0171] Storage component 1204, including a register unit for storing historical accumulation operation results;

[0172] The number of the first adding unit, the number of the second adding unit and the number of the registering unit are each one.

[0173] The first addition unit and the second addition unit may be adders respectively, the shift unit may be a shifter, and the register unit may be a register.

[0174] The cooperation relationship between the components in the data processing chip and the corresponding more detailed processing flow can be combined with the above-mentioned Fig.10 The relevant description of the embodiment of implementing data processing by the parallel system shown is not repeated here.

[0175] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0176] For the convenience of description, the above system or device is described by dividing it into various modules or units according to its functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0177] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly contributed to the prior art in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.

[0178] Finally, it should be noted that, in this article, relational terms such as first, second, third and fourth are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0179] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A data processing method, comprising: Acquire a first target data set; Each first target data in the first target data set is all valid data in each first data object corresponding to the target data processing channel; Based on a balanced allocation strategy, each first target data in the first target data set is evenly allocated among each available hardware processing channel; Data processing is performed on each available hardware processing channel on the allocated first target data and the second data object corresponding to the allocated first target data in the second data object set indicated by the target data processing channel.

2. The method according to claim 1, wherein the process of determining the first target data set comprises: Acquire a binary sequence of each first data object corresponding to the target data processing channel; extracting valid bit data from the binary sequence of each first data object; The valid data in the first data object is valid bit data in the binary sequence of the first data object; Aggregation processing is performed on valid bit data in the binary sequence of each first data object to obtain the first target data set.

3. According to the method according to claim 1, each first target data corresponds to corresponding location information, and the location information includes first location information used to indicate the location of the second data object corresponding to the first data object to which the first target data belongs, and second location information used to indicate the location of the first target data in the first data object to which it belongs.

4. The method according to claim 3, wherein the first location information of each first target data comprises an object identifier of a first data object to which the first target data belongs and a channel identifier of a target data processing channel corresponding to the first data object; The second data object corresponding to the first target data in the second data object set indicated by the target data processing channel is: the second data object at the target position in the second data object set corresponding to the corresponding target data processing channel; in, The corresponding target data processing channel is the data processing channel indicated by the channel identifier in the first position information of the first target data, and the target position is the position indicated by the object identifier in the first position information of the first target data in the indicated data processing channel.

5. The method according to claim 3, wherein the first target data set is: a valid data sequence formed by all valid data in the first data objects; the valid data of the same first data object in the valid data sequence are arranged adjacently in sequence; All valid data of the same first data object share the same first position information.

6. The method according to claim 1, wherein the step of evenly allocating each first target data in the first target data set among each available hardware processing channel based on a balanced allocation strategy comprises: The first target data are distributed to the available hardware processing channels according to the number of the first target data and the number of the available hardware processing channels, so that the numbers of the first target data respectively obtained by different available hardware processing channels meet the proximity condition.

7. The method according to claim 3, wherein the step of performing data processing on the allocated first target data and the second data object corresponding to the allocated first target data in the second data object set indicated by the target data processing channel on each available hardware processing channel comprises: Based on the parallel processing mode of inter-channel parallelism, multiplication and accumulation operations are performed on the allocated first target data and the corresponding second data objects on each available hardware processing channel.

8. The method according to claim 7, wherein the valid data in the first data object is valid bit data in a binary sequence of the first data object; The parallel processing method based on inter-channel parallelism performs multiplication and accumulation operations on the allocated first target data and the corresponding second data object on each available hardware processing channel, including: Acquire the first target data to be processed currently and the second data object corresponding to the first target data to be processed currently in each available hardware processing channel as a data pair to be processed; Based on the parallel processing mode of inter-channel parallelism, the data pairs to be processed obtained by each available hardware processing channel are subjected to shift-based multiplication processing according to the second position information of the first target data in the data pairs to be processed, so as to obtain the multiplication result corresponding to each available hardware processing channel; Accumulate the multiplication operation results corresponding to each available hardware processing channel to obtain a first addition operation result; Adding the first addition result to the current historical accumulation result to obtain a second addition result, and updating the historical accumulation result with the second addition result; The next first target data of the first target data currently being processed and the second data object corresponding to the next first target data are respectively obtained in each available hardware processing channel, the data pair to be processed is updated based on the next first target data and the corresponding second data object, and the parallel processing method based on inter-channel parallelism is looped to perform the shift-based multiplication operation processing step on the data pair to be processed obtained in each available hardware processing channel according to the second position information of the first target data in the data pair to be processed until the processing of all the first target data is completed, and the latest historical cumulative operation result is used as the operation result of all the first target data.

9. A data processing device, comprising: A data acquisition module, used to acquire a first target data set; Each first target data in the first target data set is all valid data in each first data object corresponding to the target data processing channel; A data distribution module, configured to distribute each first target data in the first target data set evenly among each available hardware processing channel based on a balanced distribution strategy; The data processing module is used to perform data processing on each available hardware processing channel on the allocated first target data and the second data object corresponding to the allocated first target data in the second data object set indicated by the target data processing channel.

10. A data processing chip, comprising: A data acquisition component, used for acquiring first target data to be processed currently by each available hardware processing channel provided by the first computing component, and a second data object corresponding to the first target data to be processed currently, as a pair of data to be processed for each available hardware processing channel; A first computing component is used to provide a plurality of available hardware processing channels, and based on a parallel processing mode of parallelism between channels, perform a shift-based multiplication operation on the data pairs to be processed obtained by each available hardware processing channel according to the second position information of the first target data in the data pairs to be processed, so as to obtain a multiplication operation result corresponding to each available hardware processing channel; A second operation component is used to accumulate the multiplication operation results corresponding to each available hardware processing channel to obtain a first addition operation result; and for adding the first addition operation result to the current historical accumulation operation result to obtain a second addition operation result, so as to update the historical accumulation operation result with the second addition operation result; Storage component, used to store historical accumulation operation results; The data acquisition component is also used to respectively acquire the next first target data of the first target data currently being processed and the second data object corresponding to the next first target data in each available hardware processing channel, update the data pair to be processed based on the next first target data and the corresponding second data object, and loop to the processing of the first operation component until the various components based on the data processing chip complete the processing of all the first target data, and use the latest historical cumulative operation result as the operation result of all the first target data.

11. The data processing chip according to claim 10, wherein: The first operation component includes a plurality of shift units for shifting to obtain corresponding multiplication operation results, each shift unit serving as an available hardware processing channel; The second operation component includes a first adding operation unit for accumulating the multiplication operation results corresponding to each available hardware processing channel to obtain the first addition operation result, and a second adding operation unit for adding the first addition operation result to a current historical accumulation operation result to obtain the second addition operation result; The storage component includes a register unit for storing historical accumulation operation results; The number of the first adding unit, the number of the second adding unit and the number of the registering unit are each one.

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