Low-power-consumption single-emission out-of-order execution RISC-V processor and instruction processing method

Abstract

The invention discloses a low-power-consumption single-emission out-of-order execution RISC-V processor, which comprises seven stages of pipeline architecture, namely an instruction fetch unit, an instruction buffer unit, a decoding unit, an emission unit for single instruction emission, a physical register file, an execution unit for parallel out-of-order calculation and a retirement unit in sequence, and the instruction fetch unit is used as the front end of the RISC-V processor; a five-level pipeline architecture formed by the decoding unit, the transmitting unit, the physical register file, the execution unit and the retirement unit is used as the rear end of the RISC-V processor; through the technical scheme, the invention provides a micro-architecture which is more balanced in performance and power consumption, so that the applicability of a processor core in a scene with high computing requirements and sensitive power consumption is improved.

Description

Technical Field

[0001] The present invention belongs to the field of computer architecture and integrated circuit technology, and in particular to a low-power single-issue out-of-order execution RISC-V processor and an instruction processing method. Background Art

[0002] RISC-V is the abbreviation of the fifth-generation reduced instruction set (RISC), and its main features are simplicity, open source, modularity and scalability. The RISC-V instruction set includes multiple types of instruction architectures, among which the basic instruction set includes the 32-bit integer instruction set RV32I and the 64-bit integer instruction set RV64I; the extended instruction set includes 32-bit multiplication and division RV32M, 32-bit single-precision floating-point operation RV32F, 64-bit multiplication and division RV64M, etc. The names that include both the basic instruction set and the extended instruction set can be combined. For example, RV32IM indicates that the current instruction set includes the 32-bit integer instruction set and the multiplication and division instruction set.

[0003] At present, the design of processor cores based on the RISC-V instruction set architecture is mainly focused on two major directions: one is low-power design for embedded scenarios such as mobile devices and edge computing; the other is high-performance design for servers, artificial intelligence, etc. that require a lot of computing resources. In terms of low-power implementation, processors usually use fewer pipeline stages and an overall architecture of sequential execution to reduce hardware resource consumption, thereby meeting low-power requirements. However, due to the overly simple structure of the processor, this design is relatively inferior in execution efficiency, and the clock cycles of pipeline pauses caused by data conflicts will also be more, wasting more computing time. This type of design may not meet real-time requirements due to low processing efficiency. For some scenarios that require both timeliness and computing power, such as unmanned driving and edge computing, insufficient processor computing performance may cause failures. In terms of high-performance implementation, some existing processors use superscalar technology and use complex micro-architectures with multiple issuances and out-of-order execution to improve instruction parallelism, thereby enhancing the processing efficiency of the processor. However, the existing design significantly increases hardware resource consumption and energy consumption, resulting in large core resource consumption and power consumption. In power- and cost-sensitive application scenarios such as edge computing, how to improve the computing efficiency of the processor by utilizing fewer hardware resources and consuming lower power has become a difficult problem that needs to be solved urgently. Summary of the invention

[0004] In order to solve the above technical problems, the present invention proposes a low-power single-issue out-of-order execution RISC-V processor microarchitecture, which fully considers the low-power design of the microarchitecture while improving the processor instruction parallelism and processing efficiency. By developing a microarchitecture that is more balanced in performance and power consumption, the applicability of the processor core in high computing demand and power consumption sensitive scenarios is improved, so as to solve the problems existing in the above-mentioned prior art.

[0005] To achieve the above object, the present invention provides a low-power single-issue out-of-order execution RISC-V processor, including a seven-stage pipeline architecture, which are respectively: an instruction fetch unit, an instruction buffer unit, a decoding unit, an issue unit for single instruction issue, a physical register stack, an execution unit for parallel out-of-order calculation, and a retirement unit;

[0006] In addition, the present invention also provides an instruction processing method for the RISC-V instruction set, including processing input RISC-V instructions based on the seven-stage pipeline architecture of the above-mentioned RISC-V processor.

[0007] Compared with the prior art, the present invention has the following advantages and technical effects:

[0008] The present invention successfully reduces the power consumption of the entire core while maintaining efficient execution of the processor through various technical means such as clock gating, input gating, and glitch optimization, so that the performance and energy efficiency of the processor can be better balanced. These optimization measures play an important role in the energy consumption management of the core, so that the processor can maintain the characteristics of low power consumption while running efficiently. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0010] Figure 1 This is a diagram of the overall micro-architecture of the RISC-V processor core according to an embodiment of the present invention;

[0011] Figure 2 An internal structure diagram of an instruction fetch unit according to an embodiment of the present invention;

[0012] Figure 3 A flow chart of a method for executing branch prediction of an instruction fetch unit according to an embodiment of the present invention;

[0013] Figure 4 An internal structure diagram of a register renaming unit according to an embodiment of the present invention;

[0014] Figure 5 A logic operation structure diagram of a priority arbitration tree according to an embodiment of the present invention;

[0015] Figure 6 A flow chart of a method and steps of a register renaming process according to an embodiment of the present invention;

[0016] Figure 7 An internal structure diagram of a transmitting unit according to an embodiment of the present invention;

[0017] Figure 8 An internal structure diagram of a memory access path accessing a peripheral device to perform data loading and storage according to an embodiment of the present invention;

[0018] Fig. 9 A schematic diagram showing a comparison of Coremark scores between the kernel of an embodiment of the present invention and the existing kernel;

[0019] The reference numerals are as follows: 10, instruction fetch unit; 11, dynamic branch predictor; 12, program counter; 13, first-level tightly coupled instruction cache unit; 20, instruction buffer unit; 30, decoding unit; 31, decoding logic circuit; 32, register renaming unit; 321, physical register free list; 322, prediction renaming mapping table; 323, physical register ready list; 324, register allocation logic circuit; 325, first priority arbitration tree; 326, physical register free list Checkpoint; 327, architecture rename map; 40, launch unit; 41, distribution logic; 411, launch ready logic; 412, allocation logic; 413, age arbitration tree; 50, physical register stack; 60, execution unit; 61, arithmetic logic unit ALU; 62, multiplication and division calculation unit MDU; 63, memory access unit LSU; 64, first-level tightly coupled data cache unit; 70, retirement unit; 71, reorder cache; 80, cache bus; 90, AXI interface. DETAILED DESCRIPTION

[0020] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0021] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0022] In view of the application scenarios of embedded, mobile, edge devices, etc. in the prior art, where hardware resources and energy are limited but the computing performance requirements are high, the present invention aims to design a low-power, single-issue, dynamically scheduled, out-of-order execution processor based on the RISC-V instruction set that is more balanced between performance and power consumption and has higher execution efficiency. The present invention mainly focuses on two key issues in processor design: one is how to improve the performance and processing efficiency of the processor and enhance the parallelism of instructions to adapt to the increasing computing demand; the other is how to reduce the power consumption of the processor so that it can run efficiently in a mobile embedded environment with limited hardware resources and power consumption. In view of the above-mentioned related problems that need to be solved, the purpose of the present invention is to fully consider the low-power design of the micro-architecture while improving the parallelism and processing efficiency of the processor instructions, and to improve the applicability of the processor core in high computing demand and power consumption sensitive scenarios by developing a micro-architecture that is more balanced in performance and power consumption.

[0023] The present invention proposes a pipeline micro-architecture solution for a processor that is more balanced in terms of performance and power consumption, which improves the parallelism of processor instructions while also taking into account the low power consumption of the micro-architecture.

[0024] like Figure 1 As shown, the low-power single-issue out-of-order execution RISC-V processor provided by the present invention includes a seven-stage pipeline architecture, which are respectively: an instruction fetch unit 10, an instruction buffer unit 20, a decoding unit 30, a single instruction issuance unit 40, a physical register stack 50, an execution unit 60 for parallel out-of-order calculation, and a retirement unit 70.

[0025] The instruction fetch unit 10 serves as the front end of the RISC-V processor; the five-stage pipeline architecture composed of the decoding unit 30, the emission unit 40, the physical register stack 50, the execution unit 60 and the retirement unit 70 serves as the back end of the RISC-V processor.

[0026] The instruction fetch unit 10 is used to read the corresponding RISC-V instruction in the off-chip memory according to the PC value of the current cycle and transmit it to the instruction buffer unit 20; it is also used to predict the PC value of the next cycle through the dynamic branch predictor 11. Specifically, the PC value refers to the output value of the program counter 12 (Program Counter, PC for short) in the processor. The PC value points to the storage address of the instruction to be executed in the current cycle in the off-chip memory, so the PC value is also the read address of the off-chip memory storing the instruction to be executed, so as to fetch the RISC-V instruction to be executed in the current cycle. In this embodiment, the RISC-V instructions to be processed are stored off-chip (i.e., outside the processor), which helps to reduce the hardware resource consumption and chip area of ​​the RISC-V processor itself; but there is usually a certain reading clock consumption as a cost. Therefore, in order to reduce clock delay and realize efficient instruction reading of off-chip storage, the embodiment of the present invention further sets a first-level tightly coupled instruction cache unit 13 in the instruction fetch unit 10.

[0027] The first-level tightly coupled instruction cache unit 13 is used to access the RISC-V instructions in the off-chip memory through the cache bus 80 and the AXI interface 90 according to the PC value of the current cycle, and read out and cache multiple RISC-V instructions corresponding to the PC value of the current cycle and the PC value of the adjacent cycle.

[0028] The first-level tightly coupled instruction cache unit 13 is also used to retrieve whether it has cached corresponding RISC-V instructions according to the PC value of the current cycle; if so, the RISC-V instructions corresponding to the PC value of the current cycle in the cache are transmitted to the instruction buffer unit 20; otherwise, the off-chip memory is accessed through the cache bus 80 and the AXI interface 90, the RISC-V instructions corresponding to the PC value of the current cycle are transmitted to the instruction buffer unit 20, and multiple RISC-V instructions corresponding to the PC values ​​of adjacent cycles are read out and cached therein.

[0029] The instruction buffer unit 20 is used to sequentially receive RISC-V instructions from the instruction fetch unit 10 to form an instruction buffer queue, and isolate the front-end calculation and back-end calculation of the RISC-V processor;

[0030] The five-stage pipeline architecture of the RISC-V processor backend is used to sequentially decode RISC-V instructions, issue single instructions, read and write physical register stack 50, execute out of order, and retire, to implement register data path and memory access path. The register data path and memory access path have the same path in the three-stage pipeline of instruction fetch, instruction buffer, and decoding, but are different in the path of the four-stage pipeline of issue, read and write physical register stack 50, execute, and retire, as shown in the following figure. Figure 1The core difference between the memory access path and the register data path is that the memory access path is used to execute load instructions and store instructions, and reads and writes the physical register file 50 through an independent memory access issue queue, and reads and writes off-chip data through an independent execution unit 60, namely, the memory access unit LSU63.

[0031] In most cases, the value of PC will automatically increase as the instruction is executed, thereby ensuring that the program is executed in order. However, the RISC-V instruction set contains unconditional jump instructions JAL (jump link) and J (direct jump) instructions, as well as conditional jump instructions such as beq (jump if equal), bne (jump if unequal), and blt (jump if less than). Therefore, the RISC-V processor designed in this embodiment needs to be able to adapt to the execution of such branch instructions (also known as jump instructions or branch jump instructions). When the RISC-V processor provided in the embodiment of the present invention encounters a branch instruction (including conditional jump and unconditional jump), the designed dynamic branch predictor 11 will predict and modify the final PC value according to the jump address (jump target PC) in the instruction, thereby changing the execution flow of the program. In specific implementation, since it is impossible to know whether the instruction is a jump instruction before executing the instruction of the current cycle, it is necessary to perform branch prediction on the PC value corresponding to each instruction to be executed in the instruction fetching stage, and it can be known whether the PC value is predicted successfully in the decoding stage or the execution stage; if successful, the execution of the instruction of the next cycle can be quickly entered, if unsuccessful, it is necessary to restore the pipelines of the processor at all levels. The RISC-V processor provided by the embodiment of the present invention has the above functions of fast branch prediction and branch prediction failure recovery.

[0032] In a preferred embodiment, a circuit implementation architecture of the dynamic branch predictor 11 in the instruction fetch unit 10 is as follows: Figure 2 Specifically, the dynamic branch predictor 11 includes: a prediction global history register (P-GHR), a query circuit ( Figure 2 not shown), Pattern History Table (PHT), Saturation Counter (SC), Branch Target Buffer (BTB), Return Address Stack (RAS) and Jump Arbiter (JA).

[0033] Each address space of the pattern history table (PHT) stores a saturated count value indicating whether to jump; the branch target buffer (BTB) records the PC value and jump address of the branch instruction in which the jump occurred; the return address stack (RAS) stores the function call target address corresponding to the function return instruction.

[0034] The query circuit is used to perform a logical operation on the PC value of the current cycle and the global jump history prediction value output by the predicted global history register (P-GHR) to obtain an index address, and query the pattern history table (PHT) according to the index address to determine whether the PC value of the current cycle jumps.

[0035] The saturated counter (SC) is used to update the corresponding saturated count value in the pattern history table (PHT) according to the jump state of the PC value of the current cycle. In this embodiment, a 2-bit saturated counter is preferably used to predict and represent the jump state ("jump" or "no jump") of the instruction, that is, the saturated count value generated by it is a 2-bit binary value 00-11. When the saturated count value is 00, it indicates that the current instruction is predicted to be a strong no jump (SNT), indicating that the historical execution results show that the instruction almost does not jump; 01 is a weak no jump (WNT), indicating that the historical execution results show that the instruction sometimes jumps and sometimes does not jump; similarly, 10 is a weak jump (WT) and 11 is a strong jump (ST). Although the saturated counter is a 2-bit counter and the output value has four states, the present invention predicts the instruction of the current cycle as no jump when the saturated count value is 00 and 01; when the saturated count value is 10 and 11, the instruction of the current cycle is predicted to jump. This has the advantage of improving the accuracy of branch prediction. When the saturation counter is working, if the current instruction is predicted to jump, the saturation count value is "+1", and the current saturation count value moves one step in the ST direction (00→01→10→11), and stays at 11 if it jumps all the time; if the current instruction is predicted not to jump, the saturation count value is "-1", and moves one step in the SNT direction (11→10→01→00), and stays at 00 if it does not jump all the time. The advantages of using this 2-bit saturation counter to predict the PC value are simple implementation and low hardware overhead, which can effectively improve the efficiency of the instruction pipeline and reduce pipeline pauses caused by branch prediction errors; and it is more adaptable and accurate than a 1-bit saturation counter, and can adaptively adjust the prediction results according to the execution status of the program. The saturation counter (SC) maintains a count value for each branch instruction separately, which is stored in the pattern history table (PHT). Therefore, by querying the value of the storage space of the PHT pointed to by the corresponding address, the prediction result of whether the current instruction will jump can be obtained.

[0036] The query address of PHT can be realized by the PC value output by the program counter. However, since the length of the PC value of each instruction is relatively long, for example, the PC value length of the RV32I instruction set is 32 bits, but the off-chip memory storing the instruction is usually stored byte by byte (8 bits), and each instruction needs to occupy k=4 bytes. Therefore, when querying PHT to obtain the jump prediction result of the corresponding instruction, only the bit values ​​of the 2nd bit (the 0th and 1st bits are meaningless) and above are needed as the query address. In this embodiment, since the hardware resources of the processor are limited, the storage space of PHT cannot be increased infinitely. Therefore, only a certain storage space of PHT is used to reuse the prediction result of the PC value, and the partial bit values ​​of the PC value are used as the corresponding query address. For example, when the storage depth of PHT is 1024, only the 10-bit PC[11:2] value needs to be intercepted as the query address of PHT. As long as the PC values ​​of the [2nd]th bit to the [11th]th bit are the same, the saturated count value of the corresponding position is queried to predict the jump state of the current instruction. However, the instruction jump prediction result obtained by such query may have a low accuracy rate. Therefore, the embodiment of the present invention further combines the global jump history predicted by the predicted global history register (P-GHR) to improve the accuracy of branch prediction.

[0037] The Prediction Global History Register (P-GHR) is different from the Pattern History Table (PHT) which uses a saturation counter (SC) to maintain a separate count value for each branch instruction. The P-GHR is used to predict the jump behavior of all branch instructions, and only needs to maintain a globally shared historical jump record. However, in actual design, since the hardware resources of the processor are limited, the length of the P-GHR must be a finite value, and it is impossible to use registers one by one to save all jump prediction results. Therefore, this embodiment uses a shift register to implement the P-GHR, which only records the predicted jump results of multiple branch instructions that have been executed recently to form a bit vector. For example, a 6-bit shift register is used to record the jump direction of the last 6 instructions ("jump" or "no jump", which can be represented by 0 or 1 accordingly). Preferably, if Figure 2 As shown, in order to improve the prediction accuracy of branch instructions, the predicted global jump history information is combined in this embodiment to search for the prediction result. In specific implementation, the P-GHR is XORed with a partial PC value of the current branch instruction (for example, a local 6-bit PC value: PC[12:7]) to obtain an index value, and then the prediction result of whether to jump is searched from the PHT according to the index value.

[0038] Preferably, the instruction fetch unit 10 further includes: an architecture global history register (A-GHR). The architecture global history register (A-GHR) records the accurate value of the global jump history after the instruction is executed, and is used to use the accurate value of the global jump history to overwrite the predicted value of the global jump history in the predicted global history register in the next cycle when the branch prediction fails. The global branch history table includes the architecture global history register (A-GHR) and the predicted global history register (P-GHR). The A-GHR is updated in the retirement stage by the retirement unit 70, and the P-GHR is updated by the instruction fetch unit 10 for instruction pre-decoding in the instruction fetch stage. When the branch prediction fails, the A-GHR is used to overwrite and restore the information of the predicted global branch history table in the P-GHR, and then the global jump history in the P-GHR (also called the global branch history table) is XORed with the partial value of the PC, and combined with other partial values ​​of the PC, a jump information index is provided to the mode history table PHT, and the mode history table PHT is addressed according to the jump information index to obtain the jump direction of whether the current PC jumps. Since the instruction jump results stored in the P-GHR are also predicted results, there may be prediction errors or prediction failures, but it is necessary to know whether the prediction is successful when the current instruction reaches the execution stage. Therefore, when obtaining all instruction information after the current instruction is executed, it is necessary to promptly update and record the information predicted by the previous multi-stage pipeline to ensure that the execution of each instruction (including the instruction jump direction) is correct. Specifically, for the global jump history prediction, after the instruction is executed and retired, the correct jump result needs to be returned to the A-GHR and branch target buffer (BTB) in the instruction fetch stage. The A-GHR records the correct jump results ("jump" or "no jump") of multiple branch instructions that have been executed recently; the BTB records the PC values ​​and corresponding jump addresses corresponding to all branch instructions executed to the current moment. Therefore, when the branch prediction is successful, it is only necessary to promptly record the corresponding jump information of the branch instruction after retirement in A-GHR (at this time, the contents of A-GHR and P-GHR are the same) and BTB; when the branch prediction fails, A-GHR can be used to quickly overwrite P-GHR within one cycle, so that the instructions executed in the previous cycle can be re-predicted.

[0039] The jump arbiter (JA) is used to predict the PC value of the next cycle according to the jump state of the PC value of the current cycle, including:

[0040] If a jump occurs, it is determined whether the PC value of the current cycle hits any branch instruction in the branch target buffer (BTB); if it hits, it is further determined whether the hit branch instruction is a function return instruction; if it is a function return instruction, the corresponding function call target address in the return address stack (RAS) is predicted as the jump address of the PC value of the next cycle; if it is not a function return instruction, the jump address corresponding to the hit branch instruction is predicted as the jump address of the PC value of the next cycle;

[0041] If no jump occurs, or if a jump occurs but no branch instruction in the branch target buffer (BTB) is hit, the jump address of the PC value of the next cycle is predicted to be PC+k; PC is the PC value of the current cycle, and k is a user-defined constant. Generally, for the RV32I instruction set, since the instruction width is 32 bits, when each byte in the off-chip memory is 8 bits, the constant k is set to 4; similarly, for the RV64I instruction set, the instruction width is 64 bits, so the constant k is set to 8.

[0042] BTB and RAS correspond to the jump address or function return address of the predicted branch instruction. In this embodiment, when the branch instruction is executed and a jump occurs, a new jump address will be obtained. At this time, the PC and jump address of the jump will be updated synchronously to the BTB. Therefore, the PC of the branch instruction that has jumped and its corresponding jump address are recorded in the BTB. However, there is a special case among the jump branch instructions. When the instruction that jumps is a function call (return) instruction, the information whether the current PC is a function return will also be updated synchronously to the BTB. Therefore, the PC judged as a jump in the current cycle is used to find the PC value of all items in the BTB. If the PC of any item in the BTB is equal to the PC of the current cycle, it is judged as a PC hit (Hit), and then it is further judged whether the PC is recorded as a function return in the BTB. If so, the corresponding address in the pop-up return address stack RAS is used as the branch prediction result, that is, the predicted function return address; if not, the target address hit in the BTB is taken out as the branch jump address of the current PC. If there is no item in the BTB whose PC is equal to the PC of the current cycle, sequential instruction fetch is still performed, that is, the predicted result of PC is PC+k.

[0043] Therefore, the dynamic branch predictor provided by the embodiment of the present invention is a two-level adaptive branch predictor. The global history register of the present invention is used to record this global branch jump information, as the first-level branch history of the branch predictor of this design; the second level uses PHT, BTB and RAS to predict the branch jump direction and jump address. In a program, the jump direction of a branch instruction may be related to the previous branch jump result, so it is necessary to use GHR (including A-GHR and P-GHR) to record the jump information of the previous and next branch instructions as the basis for branch prediction; and the saturation counter in PHT can further predict the possibility of whether the instruction pointed to by the current PC will jump in this cycle. The two-level adaptive branch predictor provided by this embodiment can make predictions quickly within one cycle, preventing the processor front-end pipeline from being too long while also ensuring the accuracy of branch prediction.

[0044] In one implementable method, PHT is a 2-bit saturated counter table with a depth of 1024 entries. The query address of PHT is the PC value of the 6-bit middle bit and the 6-bit P-GHR output value, and then the concatenation value with the lower 4 bits PC[5:2], that is: {{PC[11:6](XOR)P-GHR[5:0]},PC[5:2]}; BTB is composed of a 32-entry fully associative cache, which can make predictions quickly within one cycle, preventing the processor front-end pipeline from being too long while also ensuring the accuracy of branch prediction.

[0045] like Figure 3 The flowchart is a flowchart of an implementation of the branch prediction method provided by an embodiment of the present invention. Specifically, the specific steps of branch prediction in the instruction fetch stage are as follows:

[0046] Step S301: read the program counter 12 of the PC value to be predicted, obtain the output PC value, and only take part of the bit width value (6th to 11th bits PC[11:6]);

[0047] Step S302: Read the global jump history prediction value of the prediction global history register (P-GHR);

[0048] Step S303: Utilize the partial bit width value of the PC and the global jump history prediction value mentioned above to generate a read address for searching PHT, that is, perform an XOR operation on PC[11:6] and the 6-bit P-GHR output value and then concatenate it with the lower 4 bits of PC[5:2] to generate a 10-bit query address or index that incorporates the branch history jump information: Addr_read = {{PC[11:6](XOR)P-GHR[5:0]}, PC[5:2]}. Directly using PC or P-GHR to generate an index may cause conflicts, especially when different branch instructions share the same PC low bits or have the same history pattern. By performing an XOR operation on the partial bit width of the middle bits of the PC (such as bits 6 to 11) with the P-GHR, the generated index can effectively combine the information of the two and reduce such conflicts. The PC corresponding to the branch instruction is often relatively fixed in the low bits. For example, the alignment requirement of the 32-bit PC is 4 bytes at a time, so that the lowest two bits do not change. Directly using the high bits may not fully reflect the historical information. Therefore, this embodiment selects the middle bits such as 6 to 11 bits to XOR with the P-GHR to ensure a more uniform index distribution and reduce the prediction table conflicts caused by address similarity.

[0049] Step S304: Use the 10-bit query address Addr_read to read the mode history table (PHT) with a depth of 1024. According to the query result of the PHT, determine whether the PC value corresponding to the instruction to be executed in the next cycle jumps. If it jumps, execute step S305; if not, execute step S306;

[0050] Step S305: Search the BTB to check whether there is record information of the PC value currently predicted as a jump; if there is no hit, execute step S306; if the PC value of any item in the BTB is equal to the PC of the current cycle, it means that the PC value hits the BTB item, but because the BTB also records the call record of the return function, its priority is higher. Therefore, if the current PC hits the BTB item, it is necessary to execute step S307 to determine whether it is a return instruction. Specifically, the BTB includes 32 items of information, each of which stores the PC of the branch instruction that has jumped in the past, the jump address corresponding to the PC, and whether it is a function return. The PC value of the current cycle is compared with the PC of each item in the BTB. If there is an item whose PC value is equal to the PC value of the current cycle, it is determined that the PC value of the current cycle hits the content of the BTB.

[0051] Step S306: predict the prediction result of PC as PC+4. It can be seen that if one of the PHT and BTB misses, both are predicted as no jump, and the instructions are directly fetched sequentially, that is, PC is incremented by k=4 each time.

[0052] Step S307: determine whether the instruction of the BTB hit by the current PC is a return instruction; if not, execute step S308; if yes, execute step S309;

[0053] Step S308: Use the target address recorded by the hit item in the BTB as the jump address (prediction result) of the current PC;

[0054] Step S309: Pop the pop target address of the return address stack RAS, that is, the function return address, as the prediction result.

[0055] RAS is a hardware structure specifically used to predict function calls and returns, designed to accelerate branch prediction, especially the prediction of function calls and returns. Its structural design is closely related to the "call" and "return" instructions of function calls. When the processor encounters a function call instruction (such as call), the instruction will push the return address (that is, the address of the next instruction of the called function) into RAS. This address indicates where the program should return to after the function is executed. At the same time, the processor jumps according to the target address of the function call and executes the called function. When the processor encounters a function return instruction (such as return), it checks whether there is an available return address in RAS. If so, RAS pops the address at the top of the stack as the predicted address of the return instruction. This return address is used as the predicted address of the next instruction to be executed (that is, the program execution returns to the call point). The main purpose of RAS is to improve the prediction accuracy of function calls and returns. The structural design of RAS ensures that whenever a function returns, the processor can quickly and accurately obtain the return address to avoid performance loss caused by function return prediction errors.

[0056] In summary, according to the prediction result of the dynamic branch predictor 11, the processor will select the instruction address to be fetched in the next cycle. If the current PC is predicted to jump, the target jump address recorded in the associated BTB or the return address of the RAS is searched as the target address, and the instruction fetch address of the next cycle is this target address; if the PC is predicted not to jump, the instruction fetch address is the next sequential address of the current PC (PC+k). Through this mechanism, the processor can start fetching instructions in advance without fully determining whether the branch jump occurs, so as to reduce the pause in the instruction execution pipeline. If the prediction is wrong, the processor will discard the instructions on the wrong path and restart from the correct address. This optimization can greatly improve the efficiency of the pipeline of the present invention and improve the overall performance.

[0057] In this embodiment, the second-stage pipeline architecture is an instruction buffer stage, which is mainly provided with an instruction buffer unit 20. Preferably, the instruction buffer unit 20 adopts a sequential non-compressed first-in-first-out architecture for buffering the RISC-V instructions sent from the front end of the RISC-V processor to adapt to the difference in computing speed between the front end and the back end.

[0058] Specifically, Figure 1 As shown, the present invention adopts a sequential first-in-first-out (FIFO) buffer with a depth of d (preferably d=8 or d=16) in the instruction buffer unit 20. The processor is divided into a processor front end and a processor back end through the first-in-first-out queue. The processor front end is responsible for generating program calculations and fetching instructions, while the processor back end is responsible for processing the fetched instructions, executing instructions and completing the submission of results (writing back and retiring). The FIFO setting with a depth of 8 or 16 is a compromise solution. It can provide sufficient instruction capacity to cope with the difference in front-end and back-end rates and the needs of out-of-order execution, while avoiding excessive increase in hardware resources and complexity. On the one hand, the use of instruction buffering can decouple the front and back ends of the processor. Since there are many states of the front and back ends, using a control logic to control the front and back ends will cause the control logic to be huge and become the key path of the kernel. After the front-end and back-end are decoupled, the control logic of the front-end and back-end can be implemented separately, thereby simplifying the control modules of the front-end and back-end and achieving a faster frequency. On the other hand, due to the inconsistent processing capacity and processing rate of the front-end and back-end, the back-end may be blocked due to various factors (such as the clock cycle required to access the off-chip memory when the front-end fetches instructions is too long, and the execution of multi-cycle instructions causes the back-end transmission queue to fill up, etc.). The problem of inconsistent rates between the front-end and back-end can be matched through the instruction buffer. When the back-end is blocked, if the instruction buffer is not full, the instruction fetching front-end can still fetch instructions normally. The decoupling of the front-end and back-end simplifies the design of the control module and improves the pipeline throughput.

[0059] In addition, unlike the existing FIFO structure, the present embodiment adopts a non-compressed first-in-first-out architecture for the instruction buffer unit 20. Each time an instruction is input, it is not necessary to move all bytes of data in the instruction buffer unit 20. Instead, a free space in the instruction buffer unit 20 is searched first, and then the newly entered instruction is written into the free space. When the instruction is pushed out of the queue, the oldest instruction in the queue is pushed out to the next level of the pipeline according to the age of the instruction, thereby realizing a first-in-first-out mechanism. The advantage of using a non-compressed architecture for the instruction buffer unit 20 is that it can quickly access data, ensure timely access to instructions, avoid delays caused by decompression, and has higher data integrity, and is less likely to be damaged or lost.

[0060] As some embodiments, in the third-stage pipeline architecture, which is a decoding and register renaming stage, a decoding unit 30 is mainly provided. The decoding unit 30 includes a decoding logic circuit 31, which is used to parse the RISC-V instruction obtained from the instruction buffer unit 20, obtain the control information required for instruction execution, and jointly encode the control information using a one-hot code and a binary code.

[0061] In order to simplify the instruction information parsed and translated by the decoding logic circuit 31, so as to facilitate the fast operation of the subsequent pipeline architectures, the embodiment of the present invention re-encodes the information obtained by decoding, and mainly uses a combination of partial unique hot codes and partial binary codes to encode instructions. Since the calculations involved in the RISC-V instruction set are mainly single-cycle arithmetic and logical operations (the instruction architecture is mainly RV32I), multi-cycle multiplication and division (the instruction architecture is RV32M), and memory access instructions (mainly load instructions and store instructions, when accessing off-chip devices, it usually takes multiple cycles to complete the execution of instructions), the sixth-level pipeline execution unit 60 is also provided with three parallel and independently executed functional units, namely, the arithmetic logic operation unit ALU61 (the branch instruction unit BRU is also implemented by ALU), the multiplication and division calculation unit MDU62 and the memory access unit LSU63.

[0062] Specifically, the decoding stage uses a coding method combining part of the unique hot code with part of the binary code to generate the control information of the subsequent pipeline. Specifically, the present embodiment preferably uses a 17-bit information encoding for the control information of the subsequent pipeline, wherein the operation type classification of the three instructions is binary-encoded using a two-bit bit width, specifically, the arithmetic logic operation using the arithmetic logic unit ALU61 is encoded as 00, the instruction operation using the multiplication and division calculation unit MDU62 is encoded as 01, and the instruction code requiring the memory access unit LSU63 to access the memory is 10; and then a 15-bit bit width is used for different instruction operations (various instruction operations under each instruction operation type, for example, addition, subtraction, and, or, XOR, etc. under the RV32I instruction set; multiplication and division under the RV32M instruction set; load or store) for unique hot code encoding, and each bit of different instruction operation types has different control information, therefore, all instruction operations of the RV32IM instruction set can realize the encoding expression of the decoding information through the overall encoding of 17 bits shared by the multiplexer. The number of instructions in other standard instruction sets may be different, so it is necessary to adapt the length of the joint code. The main reason for using joint coding is that although the one-hot code can increase the frequency of subsequent decoding, if a longer one-hot code is used, the demand for the next-stage register will increase, resulting in an increase in power consumption and area. By reusing the combined architecture of the one-hot code and the binary code, the register demand of the next-stage pipeline is reduced. If the one-hot code is used alone without the multiplexing architecture, more than 40 bits of information are required for the control of the next-stage pipeline for the standard RV32I instruction set. Although the binary code only requires a bit width of about 10 bits for encoding, the next stage still requires a decoder of about 10 bits to decode the information when the control information is obtained, increasing the critical path length of the next-stage pipeline. The joint coding architecture of the one-hot code and the binary code provided by the embodiment of the present invention is superior to the full one-hot code in terms of area and power consumption, and the performance is higher than that of the full binary code, which better balances the frequency, area and power consumption of the overall decoding circuit.

[0063] The decoding unit 30 also includes a register renaming unit 32, which is used to dynamically map the logical registers involved in the RISC-V instruction set to physical registers, and generate access control information for the physical register stack 50 to avoid read and write conflicts in the register data path. Among them, the logical register refers to the general logical register of the RISC-V instruction set, which is the register directly used in the instruction; the physical register is the hardware register actually existing inside the processor. For the RV32IM instruction set, it has 32 logical registers x0~x31. When multiple RISC-V instructions of the processor enter the pipeline, data conflicts will occur, among which the WAR (WriteAfter Read) conflict is: when the pre-order instruction needs to read a certain register, the post-order instruction needs to write the same register, and the post-order instruction must wait until the pre-order instruction is finished before writing, otherwise the pre-order instruction will read the wrong data. The WAW (Write After Write) conflict is: the pre-order instruction and the post-order instruction need to write the same register, and the post-order instruction must wait until the pre-order instruction is finished before writing, otherwise the pre-order instruction will overwrite the value written by the post-order instruction, causing calculation errors. Since the number of logical registers in the RV32IM instruction set is limited, frequent WAW and WAR conflicts are likely to occur. The two data conflicts of WAW and WAR are caused by the use of the same register. In order to solve this problem, the number of registers of the processor must be increased and different register names must be used. This solution is also called register renaming. Therefore, this embodiment introduces register renaming technology. When renaming registers, it is only necessary to change the register name and map the logical register number to a different physical register number. However, the renamed physical registers actually exist in the physical register stack 50 of the processor. Specifically, register renaming allows the number of physical registers to exceed the number of logical registers defined by the instruction set. Through hardware dynamic management, the logical registers of each operation are mapped to the actual physical registers to ensure that no competition conditions occur during the execution process. In this embodiment, 64 physical registers are preferably set in the physical register stack 50 to support pipeline operations and register renaming, and after the same instruction is executed twice in succession, the physical registers occupied by the first execution (the previous destination physical registers) are released after the second execution of the instruction is completed and retired, so that the storage space in the physical register stack 50 can be reused cyclically. This method not only improves the parallelism of instructions, but also effectively reduces the performance loss caused by data dependence with lower hardware resource consumption.

[0064] like Figure 4As shown, it is a schematic diagram of an implementation structure of a register renaming unit provided in an embodiment of the present invention. The register renaming adopted in the embodiment of the present invention is explicit renaming, that is, a unified register renaming method. Preferably, the register renaming unit 32 is provided with: a physical register free list 321, a predictive renaming mapping table 322, a physical register ready list 323 and a register allocation logic circuit 324. The input information of the register renaming unit 32 includes branch information, a source logical register rs1 to be renamed, a source logical register rs2 to be renamed, and a destination logical register rd to be renamed. Different instructions may contain different numbers of source logical registers and destination logical registers. The output information of the register renaming unit 32 includes the corresponding renamed physical register 1 and its ready state, physical register 2 and its ready state, the destination physical register, and the former destination physical register.

[0065] The physical register idle list 321 is used to mark the idle state of each physical register. When a physical register is idle, its corresponding idle state is set to "1", and when it is not idle, it is set to "0".

[0066] The predicted rename mapping table 322 is used to record the dynamic mapping relationship between logical registers and physical registers. The 32 logical registers of the instruction are dynamically mapped to the 64 physical registers of the physical register stack 50. Whenever the instruction enters the renaming stage of the pipeline, the register allocation logic circuit 324 will allocate an idle physical register to the destination logical register of the instruction; and the source logical register only needs to query the predicted rename mapping table 322 to obtain the corresponding physical register.

[0067] Specifically, the register allocation logic circuit 324 is used to detect whether the physical register free list 321 is available when an instruction is executed to write the destination logical register; if not, wait for the physical register to be released after the subsequent pipeline operation is completed; if so, arbitrate an idle physical register in the physical register free list 321 through the first priority arbitration tree 325, allocate it as the destination physical register to the destination logical register to be written, and update the corresponding mapping relationship between the logical register and the physical register in the predicted renaming mapping table 322.

[0068] The register allocation logic circuit 324 is also used to find the corresponding source physical register number in the prediction rename mapping table 322 when the instruction executes to read the source logical register, and find the ready state of the corresponding source physical register in the physical register ready list 323 according to the source physical register number. When the instruction reads the data of the physical register, the ready state of the physical register must be known in conjunction with the data dependency detection mechanism to ensure that no data dependency problem occurs when the instruction reads the physical register. The physical register ready list 323 proposed in the present invention records the ready state of all physical registers: when the register is in the ready state, the corresponding bit is set to 1; when it is not ready, it is 0. Therefore, the physical register ready list 323 is actually a 64-bit binary sequence, and the data ready state of the physical register is managed by updating the physical register ready list 323. When a physical register is in the ready state, it means that no instruction needs to write the result back to the register, so its data can be read by subsequent instructions and no data conflict will occur; if the physical register is in the unready state, a data conflict will occur when reading its value, and it is necessary to wait for the previous instruction to be executed and the result to be written back to the register to obtain the correct value.

[0069] The register allocation logic circuit 324 is also used to integrate the destination physical register number, source physical register number, and ready state of the source physical register corresponding to the current instruction into the access control information for output. The unready physical register state will be passed from the renaming stage to the emission stage. If the physical register required by the instruction is not ready, the instruction cannot be emitted and executed until the relevant register is written back and becomes ready again. The update of the physical register ready list 323 occurs in the renaming stage and the instruction execution stage. After the instruction is renamed, the corresponding physical register is occupied, but because it has not been executed yet, the result has not been written back. At this time, the register state is unready. Therefore, it is necessary to update its ready state to 0 to reflect its unready state. After the instruction is executed and written back, the occupied physical register will be released, the result in the physical register has been updated, and no data conflict will occur when the subsequent instruction reads the physical register. Therefore, the state of the corresponding item in the physical register ready list 323 is updated to 1 and becomes ready.

[0070] Preferably, the unified register renaming technical solution adopted by the present invention expands the 32 logical registers x0-x31 defined by the RV32IM instruction set into 64 physical registers to form a unified physical register stack 50 for renaming, and the physical address indexes of the renamed source logical registers and the destination logical registers correspond one-to-one to the specific physical register numbers in the physical register stack 50, and the operation results obtained by the later pipeline are uniformly written back to the unique physical register stack 50. Compared with renaming using a reorder buffer (RoB) and renaming by expanding the logical registers, this renaming method changes the mapping relationship between the logical registers and the physical registers by changing the predicted renaming mapping table 322, and the data only needs to be written back to the physical register stack 50 once, which can greatly reduce data movement and reduce the power consumption of the core.

[0071] Preferably, the arbitration of the physical register free list 321 is implemented by using a priority arbitration tree architecture with a fixed priority, that is, the first priority arbitration tree 325 is a comparison multiplexing merging arbiter with a fixed low-order priority. A specific structure of the priority arbitration tree provided in an embodiment of the present invention is as follows: Figure 5 As shown. Since the physical register stack 50 contains 64 physical registers, the physical register free list 321 only needs to use a 64-bit binary number to mark the free state of the corresponding physical register. For example, when it is free, it is marked as "R = 1", and when it is not free, it is marked as "R = 0". Then a design such as Figure 5 The arbitration tree with low-order first order is shown in the 64-bit tag information R0 to R1 in the physical register free list 321. n-1 (n=64) find the free physical register that is first "1" from the lowest bit to the highest bit. Therefore, the 64-bit tag information can be used as the selection signal R0~R n-1 (n=64), physical register numbers I0~I n-1 As Figure 5 The input signal of the priority arbitration tree is arbitrated, and the first R from the low to high bits can be found from the 64-bit tag information. x =1 corresponds to the physical register I x . Figure 5 The core design principle of the priority arbitration tree provided is: the maximum value comparator MAX is in the tag information R of two physical registers 左 and R 右 Compare them to find the largest R value. Since the R value can only be between 0 and 1, just find the R value of "1". If the input mark information on both sides is 1, the logic of MAX is low-order first, that is, always take the R on the right. 右If both are 0, it means that the physical registers represented by the two input mark signals are not idle. At this time, it is preferred to use the higher number for output, that is, take the R on the left. 左 Therefore, when the R value and the paired physical register number I are input into the priority arbitration tree in pairs, the R value obtained by the current comparison can be used as the selection signal of the "two-choice" selector MUX, and the corresponding first idle physical register number or index I from right to left is output. x The priority arbitration tree puts the arbitration data path (input physical register number data I0~I n-1 ) and control path (selection signal R0~R n-1 ) is coupled to a balanced tree, generates an arbitration selection signal while performing multiple selection on each item (physical register number) in the physical register free list 321, and can quickly arbitrate the free items in the physical register free list 321.

[0072] Specifically, the bit width of the physical register free list 321 is 64 bits, and each bit corresponds to the free state of a physical register. For example, the 0th bit of the physical register free list 321 corresponds to the free state of the physical register No. 0, the 1st bit corresponds to the free state of the physical register No. 1, and so on. When the physical register is free, the state of the corresponding bit is 1; when it is not free, it is 0. Therefore, it can be quickly utilized Figure 5 The priority arbitration tree shown selects the first value of 1 from the low to high bits in the physical register free list 321, thereby selecting the physical register with the corresponding number as the free physical register, and assigning it to the destination physical register required for the current instruction to perform the write operation. The update of the physical register free list 321 occurs when the instruction enters the renaming stage and the instruction is submitted for retirement. After the instruction allocates the free physical register in the renaming stage, the items in the free list 321 that are in the free state will be reduced. When the instruction retires and the subsequent instruction no longer uses the physical register, the free state of the physical register will be restored, thereby increasing the items in the free list that are in the free state. The mechanism of this embodiment for judging whether a physical register can be vacated is: save the previous destination physical register. When an instruction and a subsequent instruction are written to the same destination logical register, and the subsequent instruction is submitted for retirement, the physical register corresponding to the destination logical register of the preceding instruction will no longer be used. Therefore, it is necessary to record the previous destination physical register of each instruction so that the corresponding item in the physical register free list 321 can be released when retiring.

[0073] Furthermore, the register renaming unit 32 is also provided with: a physical register free list checkpoint 326, and an architecture renaming mapping table 327. In addition to using the physical register free list 321 to allocate free physical registers, the renaming logic of this embodiment also tracks the mapping relationship between each logical register and the physical register through the renaming mapping table (including the architecture renaming mapping table 327 and the predicted renaming mapping table 322). After the instruction enters the renaming stage, the physical register numbers corresponding to all the logical registers of the instruction after renaming can be obtained by querying the predicted renaming mapping table 322. The physical registers obtained by looking up the two source logical registers of the instruction will be used in the subsequent physical register stack reading stage, and the physical registers obtained by looking up the destination logical register will be used as the former destination physical register.

[0074] The physical register free list checkpoint 326 is used to mark the current RISC-V instruction as a branch instruction, generate a branch number and back up the physical register free list 321. In the embodiment of the present invention, only the physical register free list 321 corresponding to the branch instruction needs to be backed up. Other non-branch instructions do not have the problem of branch prediction errors and are sequentially fetched, so there is no need to back up the physical register free list 321.

[0075] The register renaming unit 32 is also used to restore the content of the physical register free list 321 using the physical register free list checkpoint 326 corresponding to the branch number in the next cycle when the branch prediction fails, and to restore the content of the predicted rename mapping table 322 using the architecture rename mapping table 327. In this embodiment, the physical register free list checkpoint 326 and the architecture rename mapping table 327 are used to perform fast branch prediction recovery in the register renaming stage. Among them, the rename mapping table includes the predicted rename mapping table 322 and the architecture rename mapping table 327, and the predicted rename mapping relationship is recorded by the predicted rename mapping table 322, and the correct architecture rename mapping relationship is recorded by the architecture rename mapping table 327. When a branch prediction fails, the architecture rename mapping table 327 overwrites the rename mapping relationship of the predicted rename mapping table 322 according to the correct rename mapping relationship in one cycle. When a branch prediction fails, the backup information of the physical register free list with the corresponding number in the physical register free list checkpoint 326 is used to overwrite the content of the physical register free list 321 in one cycle.

[0076] Furthermore, the register allocation logic circuit 324 also includes a register wake-up logic. The register wake-up logic is used to detect whether there is an early wake-up signal returned from the emission unit 40 when the source physical register to be read by the current instruction is not ready; if yes, compare the register number carried in the early wake-up signal with the source physical register number to be read by the current instruction, and if they are the same, update the source physical register to be read by the current instruction to the ready state; if they are not the same or there is no early wake-up signal, detect whether the write address of the physical register stack 50 by the execution unit 60 is consistent with the source physical register number to be read by the current instruction; if they are consistent, update the source physical register to be read by the current instruction to the ready state; if they are inconsistent, wait for the source physical register to be executed.

[0077] The physical register stack 50 is used to perform a write operation on an idle destination physical register or a read operation on a ready source physical register according to the access control information.

[0078] As some embodiments, for branch instructions, the branch instruction flag position is marked as 1 through the physical register free list checkpoint 326, and the branch instruction number is generated and provided to the physical register free list 321 and the physical register free list is backed up. If it is not a branch instruction, the input instruction is directly provided to the physical register free list 321, and the physical register free list 321 selects the register according to the input instruction or branch instruction number through the first priority arbitration tree 325 to generate the destination physical register number; and for the renaming of the source register, the source logical register obtains the source register renaming mapping number by searching the predicted renaming mapping table 322, and further determines whether the two source physical registers are ready by searching the physical register ready list 323. If they are ready, all the control information obtained by decoding and the information of the renamed source physical register and destination physical register are retained in the ready register and transmitted to the next level pipeline emission unit 40; if it is not ready, but the physical register stack address written back in the execution stage of the current cycle happens to be consistent with the physical index of the two renamed source registers, the corresponding unready physical register is awakened.

[0079] Figure 6 The following describes a specific implementation method of register renaming. The core process steps mainly include:

[0080] 1) Check whether the physical register free list 321 and the physical register free list checkpoint 326 are available. If they are full, wait for the next stage pipeline to release resources.

[0081] 2) Instruction decoding, determine whether the instruction is a branch instruction. If it is a branch instruction, mark the current instruction as a branch, set the branch instruction flag to 1, and use the physical register free list checkpoint 326 to generate a branch number and back up the physical register free list 321 for rapid recovery from subsequent branch prediction failures.

[0082] 3) The physical register free list 321 generates the destination physical register number; for the source register, the source logical register obtains the renaming mapping number as the physical address index of the renamed source physical register through the address prediction renaming mapping table 322, and then searches the physical register ready list 323 to obtain whether one or two source physical registers (the number of source registers depends on the current instruction content) of the current instruction are ready. If the address to be written back to the physical register stack 50 by the execution unit 60 in the current cycle happens to be consistent with the physical index of the two renamed source physical registers, the corresponding ready source physical register is awakened. In addition, if the physical register number returned by the emission unit 40 for early awakening is the same as the source physical register number to be read, the corresponding physical register can also be awakened.

[0083] 4) Integrate all the control information obtained by decoding, the renamed source physical register, and the destination physical register information generated above into an output signal and send it to the next stage of the pipeline.

[0084] In addition, for the recovery of branch prediction failure, the present invention designs a circuit architecture for fast branch prediction recovery. In a dynamically scheduled processor, when branch prediction fails, due to the out-of-order execution of instructions, instructions younger than the jump instructions that failed the branch prediction may have already affected the state of the processor. At this time, it is necessary to restore the processor state to the position where the branch instruction prediction error occurred. The various components of the register renaming stage, such as the predicted renaming mapping table 322 that records the renaming mapping relationship of the processor, and the physical register free list 321 that records the free registers, are important components that need to be restored after the branch prediction fails. If the recovery fails, the processor will run incorrectly. On the other hand, the recovery time of the renaming stage after the branch prediction fails also affects the performance of the processor. If the recovery cycle is large, it will cause subsequent instructions to be blocked, and more bubbles will be inserted into the pipeline, affecting the throughput of the pipeline. Therefore, fast branch prediction recovery has a significant improvement in processor performance.

[0085] like Figure 4As shown, the branch prediction failure recovery circuit architecture adopted by the present invention is configured with two renaming mapping tables. The predicted renaming mapping table 322 is used to record the speculated renaming mapping relationship and is in a speculative state; the architecture renaming mapping table 327 is used to record the accurate architecture renaming mapping relationship and is in a determined state. It is updated after the instruction is executed and submitted for retirement. When the branch prediction fails, the present invention quickly recovers by overwriting the speculated predicted renaming mapping table 322 with the accurate architecture renaming mapping table 327. During the recovery, the registers in the architecture renaming mapping table 327 are used as the input of the registers in the predicted renaming table, and the register numbers correspond one to one. During the recovery, only one clock cycle is needed to restore the erroneous predicted renaming mapping table 322 to the accurate mapping table, and the mapping relationship of the renaming mapping table is quickly restored. The physical register free list 321 used to allocate the renaming number is designed for backup, such as Figure 4 As shown in the physical register free list checkpoint 326 in the embodiment, the number of backup circuits of the physical register free list checkpoint 326 set by the present invention is 4. When the branch instruction enters the renaming stage in the pipeline, Figure 4 One of the four backup circuits of the checkpoint in the kernel will perform a quick backup to record the idle list status before the current branch instruction. When a branch prediction failure occurs, the backup idle list is used for overwriting. The recovery cost of the branch prediction failure is only one cycle, and there is no need to perform multiple data reads and writes to restore the kernel status. The recovery of the renaming mapping table and the idle list only takes one clock cycle, achieving the effect of quickly restoring the processor status, improving the performance of the kernel while also reducing power consumption.

[0086] Furthermore, in the transmission phase, transmission is performed through different transmission queue architectures. Specifically, Figure 1 and Figure 7 As shown, the launch unit 40 includes three independent parallel launch queues: a logic operation launch queue, a multiplication and division launch queue, and a memory access launch queue; each launch queue is a non-compressed and non-data capture queue. Instructions in each queue will be launched to the arithmetic logic unit ALU61, the multiplication and division calculation unit MDU62, and the memory access unit LSU63 in the execution unit 60 for calculation and processing respectively.

[0087] The transmitting unit 40 further includes a distribution logic 41, which includes a transmit ready logic 411, an allocation logic 412, and an age arbitration tree 413. In specific implementation, a set of distribution logic 41 can be independently set for the three transmit queues, with independent transmit ready logic 411, allocation logic 412, and age arbitration tree 413; or a set of distribution logic 41 can be shared. Figure 7The illustrated implementation scheme provides a set of distribution logic 41 for each queue, and utilizes independent transmit ready logic 411, allocation logic 412 and age arbitration tree 413 to perform arbitration distribution on each queue.

[0088] The emission-ready logic 411 is used to determine whether the current RISC-V instruction obtained from the decoding unit 30 is ready to be emitted. When all source physical registers involved in the current RISC-V instruction are awakened, the current RISC-V instruction is determined to be ready to be emitted, and the ready-to-emit RISC-V instruction is distributed to one of the emission queues according to its instruction type. If the current instruction is an arithmetic logic operation instruction and a branch jump instruction, it is sent to the logic operation emission queue; if it is a multiplication, division, remainder, etc. instruction in the RV32M or RV64M instruction architecture, it is sent to the multiplication and division emission queue; if it is a memory access instruction such as load or store, it is sent to the memory access emission queue.

[0089] The allocation logic 412 searches for an idle item in the corresponding transmit queue through the second priority arbitration tree and writes the ready-to-transmit instruction into the idle item. Figure 5 The same implementation scheme as the first priority arbitration tree shown in FIG. 1 is used, but its architecture should adjust the number of comparison levels in the priority arbitration tree accordingly according to the different bit widths n of the input signals.

[0090] The age arbitration tree 413 is used to sort the instructions in each transmit queue by age, and arbitrate the oldest instructions in each of the three transmit queues for parallel transmission.

[0091] In particular, the transmit ready logic 411 of the logical operation transmit queue in this embodiment is also provided with an early wake-up logic, which is used to release the source physical register involved in the instruction after an instruction is transmitted, return the source physical register number associated with the instruction, and compare it with the source physical register involved in the instruction of the next cycle. When the returned source physical register is the same as the source physical register involved in the instruction of the next cycle, the source physical register corresponding to the instruction of the next cycle can be awakened in advance; if the instruction of the next cycle includes two source physical registers, they need to be awakened one by one, and the transmit ready signal is issued only when all the physical registers involved in the instruction of the next cycle are awakened. The specific implementation circuit structure can be adopted Figure 7Circuit implementation scheme in the upper left corner. It should be noted that the present embodiment takes into account the following features: only the instructions in the arithmetic logic operation emission queue can be executed in the arithmetic logic operation unit ALU61 within one clock cycle, and the multiplication and division calculation unit MDU62 and the memory access unit LSU63 require multiple cycles to execute instructions. Therefore, the present invention can send an early wake-up signal after the instructions in the arithmetic logic operation emission queue are emitted, and the source physical registers involved in the instructions of the next cycle are woken up in advance; otherwise, the source physical registers can only wait until the execution of the current cycle instructions is completed and the register information (i.e. Figure 7 The physical registers are then compared with the source physical registers of the instructions of the next cycle (tag1 and tag2 in the upper left corner) to decide whether to wake up the physical registers. Since the latter needs to wait for multiple clock cycles, the execution efficiency of the processor will be low. It should be noted that the number of source logical registers and destination logical registers in the basic RISC-V instructions has been standardized by the RISC-V instruction set. Therefore, the number of source physical registers and destination physical registers involved in different RISC-V instructions may be different.

[0092] In the specific implementation, during the launch phase, such as Figure 7 As shown, the emission queue of the embodiment of the present invention is different from the existing single, compressed and data-type emission queue. This embodiment designs a distributed, non-compressed, non-data-captured emission queue architecture. Specifically, the distributed emission queue divides the traditional single emission queue into three queues according to the characteristics of the instruction type: a logical operation emission queue, a multiplication and division emission queue, and a memory access emission queue. This distributed design effectively avoids the complex design of multiple read and write ports in the traditional long emission queue, significantly improves power consumption performance, and can distinguish the emission logic of single-cycle instructions and multi-cycle instructions, and supports early wake-up of the source physical register of the next cycle instruction.

[0093] Furthermore, each of the emission queues in this embodiment is designed as a non-compressed emission architecture, which reduces unnecessary data changes in the queue, and each piece of data is only read and written once when entering and exiting the queue. The working mode of the traditional compression queue is similar to that of the standard FIFO. Whenever the instruction in the queue is emitted, all the subsequent instructions entering the queue need to move forward to form a "newest-oldest" order, that is, in each emission, multiple instruction items in the queue will perform data read and write operations. In contrast, when the instruction of the current cycle of the non-compressed emission queue leaves, the position of other instructions will not change, and the un-emitted instructions will remain in their original position; when the instruction of the next cycle enters the queue, it will find the free position in the queue through the priority arbitration tree for writing. Therefore, the emission queue selection circuit of the non-compressed queue can also shorten the timing path of the arbitration logic by selecting data while arbitrating. It should be noted that, unlike the sequential first-in-first-out instruction queue of the instruction buffer unit 20, the three emission queues are all disordered first-in-first-out queues to ensure that the instructions in the emission queue can be executed in disorder according to their ready state and the required execution cycle, thereby improving the execution efficiency of the instructions.

[0094] Furthermore, each transmit queue in this embodiment is designed as a non-data capture queue architecture. The non-data capture queue architecture does not need to record the internal storage data of the required physical registers, but only needs to record the corresponding physical register numbers or tags. Since the temporarily stored data is usually large in bit width, and the register tag bit width is very small, the data bit width for data calculation in the transmit pipeline stage and subsequent pipeline stages is also reduced, thereby reducing the storage space requirements of the processor, reducing area and power consumption. Figure 7 As shown, the present invention adopts an "oldest first" transmission arbitration allocation mechanism, and finds the oldest instruction in the transmission ready list through the age arbitration tree 413 for transmission, giving priority to solving subsequent data correlation problems. In the wake-up design of the transmission queue, when the logic operation transmission queue is selected by the transmission arbitration, the physical registers of the items in the related queue will be awakened and activated; while for the multiplication and division transmission queue and the memory access transmission queue, they do not support early wake-up. By simplifying the wake-up circuit architecture, the fan-out of the wake-up logic is low, so that the circuit architecture of the overall transmission unit 40 can achieve higher frequency and lower power consumption.

[0095] As some embodiments, the execution unit 60 is used to use an input gating circuit to receive decoding information of one or more RISC-V instructions emitted by the emission unit 40, dispatch it to corresponding functional units for calculation, and submit the calculation results to the register data path or the memory access path.

[0096] like Figure 1As shown, the functional unit includes an independent arithmetic logic unit ALU61, a multiplication and division calculation unit MDU62 and a memory access unit LSU63; the arithmetic logic unit ALU61 is used to process single-cycle arithmetic operation instructions and branch jump instruction calculations; the multiplication and division calculation unit MDU62 is used to process M-type extended instruction set instruction calculations; the memory access unit LSU63 is used to process load instructions and store instructions. It should be noted that since both logic operations and branch jump operations only involve simple arithmetic logic operations, the function of the branch jump unit BRU required for branch jumps can also be directly implemented in the arithmetic logic unit ALU61.

[0097] During specific implementation, the execution unit 60 adopts an input-gated circuit architecture, which can achieve data isolation when the input signal is not enabled and fix the operand to zero. In addition, although the present invention adopts a low-power dynamic scheduling scheme, the power consumption of the entire kernel is still relatively high. In order to further optimize the power consumption of the kernel, the present invention adopts a variety of low-power design methods of register transfer level (RTL) to optimize the power consumption of the kernel in an all-round way. Specifically, the entire kernel of the RISC-V processor adopts gated clock technology, and at the same time, optimizes the power consumption of each stage of the pipeline, including the use of input gating design for functional units in the execution stage. The flip frequency of the clock signal in the chip is very high, which is the main reason for most dynamic power consumption. By using gated clock technology, the present invention enables the register clock of each stage to be turned on only when enabled, which greatly reduces the power consumption of registers at each stage of the pipeline. This design is particularly significant in the overall power consumption optimization of the kernel, greatly reducing unnecessary power consumption waste.

[0098] In particular, for the execution phase, the present invention adopts an input gating design for the functional units in the execution unit 60 (such as the arithmetic logic unit ALU61 and the multiplication and division calculation unit MDU62). When the input operand is in the disabled state, it is fixed to a constant value, thereby isolating the operand and reducing the number of subsequent flips of related combinational logic gate circuits. This significantly reduces the power consumption in the execution phase and further improves the energy efficiency of the processor.

[0099] Furthermore, the present invention also optimizes the problem of unnecessary flipping caused by glitches in the combinational logic. Glitches are short-term unstable states caused by delay differences in the combinational logic circuit. Such unnecessary signal flipping will cause additional power consumption. To this end, the present invention performs a balanced design on the cascade circuit in the overall architecture. By improving the multi-stage cascaded two-choice selector into a tree structure, not only the critical path of the combinational logic is shortened, but also the glitch problem caused by delay is effectively avoided, thereby preventing further increase in power consumption.

[0100] In addition, the execution unit 60 also reuses a large number of circuits with the same functions to reduce the area of ​​the logic circuit. For example, the addition and subtraction operations are reused in the same adder, and the comparison and XOR operations are reused in the same XOR circuit. Through different configurations, one logic circuit can realize multiple logic functions, thereby eliminating the need to set up independent circuits for different logic functions and saving resource consumption.

[0101] Furthermore, if Figure 8 As shown, the memory access path includes a non-compressed load queue and a first-in-first-out storage queue; the storage instruction is used to write data to an external device through the memory access path; and the load instruction is used to read data from an external device to the physical register stack through the memory access path.

[0102] The memory access unit LSU63 is used to sequentially execute the storage instructions (store instructions) in the storage queue, and to execute the load instructions (load instructions) in the load queue whose age is greater than the to-be-retired storage instructions out of order.

[0103] Preferably, the memory access path further includes a first-level tightly coupled data cache unit 64. The first-level tightly coupled data cache unit 64 is used to cache data required to be read in by a load instruction in a load queue or data required to be written out by a store instruction in a store queue.

[0104] In an embodiment of the present invention, the memory access path adopts a partially out-of-order memory access circuit design, that is, the storage queue performs storage access strictly in order, and when the retirement enable signal of the retirement unit 70 is received, the instructions in the storage queue are retired in a first-in-first-out order; and because the load instruction reads data from the peripheral device and does not affect the peripheral device data, multiple load instructions can be executed out of order and in parallel, so the load queue adopts out-of-order memory access. Specifically, for the load instruction between two store instructions, one or more load instructions are allowed to perform memory access operations out of order. The specific implementation method is to broadcast the age of the oldest store instruction to be retired in the storage queue to the load queue. When the age in the load queue item is greater than the age broadcast from the storage queue, it indicates that the data to be written to the peripheral device does not conflict with the load instruction with an older age, and the item in the load queue can be loaded for memory access. The present invention manages all memory access instructions through load and store queues, and all memory access operations for external communication will not be stalled due to whether the data cache hits or not, but continue to be written into the load and store queues waiting for subsequent resource release, forming a non-blocking, partially disordered memory access mechanism. This memory access design based on load and store queues has significant advantages. First, it can achieve higher instruction parallelism with a smaller area overhead, thereby significantly improving the overall performance of the kernel; second, the non-blocking design avoids the memory access bottleneck caused by insufficient cache hit rate, ensures the smooth execution of the instruction stream, and further enhances the performance of the processor. In addition, since a first-level tightly coupled data cache unit 64 is provided, multiple adjacent data can be read from the peripheral to the first-level tightly coupled data cache unit 64 at one time each time the peripheral data is written or read, or multiple adjacent data to be written to the peripheral can be stored in the first-level tightly coupled data cache unit 64. When executing a store or load instruction to write or read a peripheral, the first level tightly coupled data cache unit 64 is searched to see if there is any hit data. If so, the load instruction can quickly write the data back to the physical register stack 50 and the reorder cache 71; the store instruction can continuously and directly write the data in the cache to the peripheral.

[0105] As some embodiments, the retirement unit 70 is provided with a first-in-first-out reordering cache 71, a branch prediction failure recovery logic, and an interrupt exception detection logic. In the retirement stage, branch prediction failure recovery and interrupt exception detection functions are provided. In the retirement stage, a circular first-in-first-out (FIFO) queue is provided, and branch prediction failure and interrupt exception detection are performed at the read FIFO address.

[0106] The retirement unit 70 is used to retire the instructions entering the reorder cache 71 in order, and return the accurate value of the global jump history of the retired instruction to the instruction fetch unit 10, and return the physical register number and register mapping relationship released by the retired instruction to the decoding unit 30. Specifically, the accurate value of the global jump history is returned to the architecture global history register (A-GHR) in the instruction fetch unit 10, the corresponding instruction jump information and its corresponding jump address are returned to the BTB for recording; the physical register number and register mapping relationship are returned to the architecture renaming mapping table 327 of the decoding unit 30.

[0107] The retirement unit 70 is also used to perform branch prediction failure detection and interrupt exception detection at the dequeue pointer of the reorder cache 71 using the branch prediction failure recovery logic and interrupt exception detection logic, and flush the pipeline architecture of each level of the RISC-V processor when a branch prediction failure or interrupt exception occurs, and use the accurate value of the global jump history and the correct register mapping relationship to perform calculation recovery on the RISC-V processor.

[0108] Specifically, the reorder cache 71 in the retirement stage uses a circular queue and a first-in-first-out (FIFO) design. In addition, a design is adopted to perform branch prediction failure recovery and interrupt exception recovery at the retirement point. This recovery mechanism can, on the one hand, uniformly restore the processor state at retirement, and only needs to detect branch prediction failure and interrupt exception at the dequeue pointer, i.e., the FIFO read address, without the need for additional logic for exception detection, simplifying the recovery logic and reducing the power consumption of the circuit. On the other hand, since a recovery circuit for fast kernel recovery is configured for backup in the previous stage, such as the register renaming stage, the cost of recovery is only one cycle. This simple detection mechanism and fast recovery circuit combination simplifies the logic design of branch prediction failure recovery and reduces the power consumption of the overall kernel architecture.

[0109] In summary, in order to achieve a better balance between processor performance and power consumption, the present invention optimizes the processor core as a whole by optimizing the settings of the core architecture pipeline and adopting different configuration strategies in each pipeline stage. The design of each pipeline stage not only focuses on performance improvement, but also pays attention to the realization of low power consumption. Balanced design is adopted in many technical points, which simplifies the logic while ensuring the function and reduces the data changes in the data path, so that the overall processor achieves a more ideal balance between performance and power consumption.

[0110] The entire processor core micro-architecture adopts dynamic scheduling technology to realize out-of-order execution of instructions, and fully considers the design requirements of low power consumption. Compared with the traditional sequential pipeline, dynamic scheduling adds a large number of circuits to handle data conflict problems in the processor pipeline, prevent pipeline stagnation and bubble insertion caused by data conflicts, thereby ensuring the improvement of instruction parallelism. However, although dynamic scheduling can improve core performance, the additional circuits introduced by it will increase chip area and power consumption. Therefore, in dynamic scheduling, the selection of renaming scheme, emission scheme and branch prediction recovery scheme has a significant impact on the overall performance, power consumption and area of ​​the core micro-architecture. Therefore, after sufficient weighing, the present invention selects an implementation scheme with more balanced performance and power consumption, and optimizes some circuits, especially in terms of power consumption.

[0111] The optimized configuration adopted by the present invention, such as unified register renaming, non-compression, non-data capture, distributed emission queue, unified branch prediction and interrupt exception recovery mechanism at the retirement point, simplifies the implementation of dynamic scheduling, not only ensures the out-of-order execution of instructions, but also significantly reduces the frequent data flipping required for dynamic scheduling in the pipeline, and greatly reduces the power consumption of the processor core.

[0112] In general, the present invention successfully reduces the power consumption of the entire core while maintaining efficient execution of the processor through various technical means such as clock gating, input gating, and glitch optimization, so that the performance and energy efficiency of the processor can be better balanced. These optimization measures play an important role in the energy consumption management of the core, so that the processor can maintain the characteristics of low power consumption while running efficiently.

[0113] Based on the same inventive concept of the above embodiments, this embodiment further provides an embodiment of an instruction processing method based on the RISC-V instruction set, and based on the seven-stage pipeline architecture of the RISC-V processor described in any one of the above items, the input RISC-V instruction is processed, including:

[0114] Combination Figure 1 As shown, specifically, a low-power single-issue out-of-order execution RISC-V processor indicated in this embodiment includes a seven-stage pipeline architecture, which are respectively: an instruction fetch unit 10, an instruction buffer unit 20, a decoding unit 30, a single instruction issuance unit 40, a physical register stack 50, an execution unit 60 for parallel out-of-order calculation, and a retirement unit 70.

[0115] Based on the seven-stage pipeline architecture of the above-mentioned processor and based on the same logical concept, an instruction processing method for the RISC-V instruction set provided in an embodiment of the present invention processes the input RISC-V instruction based on the seven-stage pipeline architecture of the RISC-V processor described in any one of the above items to implement it. It should be noted that the specific structure involved in the seven-stage pipeline architecture of the RISC-V processor in this embodiment and the specific instruction processing method for the input RISC-V instruction have been described and demonstrated in the embodiment corresponding to the RISC-V processor. Those skilled in the art can implement the instruction processing method for the RISC-V instruction set according to the structure and instruction processing method of the above-mentioned seven-stage pipeline architecture, which will not be repeated here.

[0116] Beneficial effects that can be achieved by the present invention: The present invention proposes a low-power embedded processor core micro-architecture based on dynamic scheduling, which can support out-of-order execution of instructions and exhibit strong instruction parallelism. By adopting low-power dynamic scheduling design and a series of register transfer-level low-power technologies, the low-power characteristics of the core micro-architecture are ensured, and a good balance between processor performance and power consumption is achieved.

[0117] The present invention takes the RV32IM instruction architecture as an example, and its core micro-architecture completes prototype verification on FPGA, and evaluates the frequency, power consumption and area of ​​the chip based on the 40nm (nanometer) process.

[0118] On the FPGA platform of the ZYNQ-7020 core board, the FPGA chip model is XC7Z020CLG400-2, and the maximum operating frequency of the processor core is 95MHz. At this frequency, Fig. 9 As shown, the processor achieved a score of 3.6Coremark / MHz through the Coremark benchmark, which is better than most sequentially executed processor cores.

[0119] Under the 40nm CMOS integrated circuit process, after comprehensive optimization, the maximum operating frequency of the processor core reaches 588MHz, the dynamic power consumption is only 14.36μW / MHz, and the area is 0.063mm 2 . Detailed experimental results are shown in Table 1. Compared with most sequential execution processor cores under the same process, the present invention has significant advantages in frequency and power consumption, although due to the use of dynamic scheduling design, the logic circuit is increased, making the area slightly larger than the sequential execution core. The experimental results show that the low-power embedded processor core microarchitecture designed by the present invention performs well in performance and power consumption, and is particularly suitable for application scenarios with high computing requirements and power consumption sensitivity.

[0120] Table 1

[0121]

[0122] Specifically, the data in the first column of Table 1 are the ASIC implementation results of the core micro-architecture of the present invention under the 40nm process. The ASIC implemented by the present invention under the 40nm process has significant performance advantages, and its maximum operating frequency can reach 588.23MHz. At this frequency, the chip area is 0.063mm 2 , dynamic power consumption is only 14.36μW / MHz. In addition, the benchmark CoreMark running score reached 3.6CoreMark / MHz, showing excellent computing efficiency. Fig. 9 The performance of the processor core microarchitecture of the present invention and other embedded processors in the benchmark test CoreMark was compared. The results show that the benchmark score of the present invention is significantly better than that of most embedded processors, which proves the superior performance of the processor provided by the present invention on the embedded platform and can meet the computing power requirements of the platform.

[0123] Table 1 also shows a comprehensive comparison of the present invention with several existing processors in terms of performance, frequency, area and power consumption at the 40nm process node. It can be seen that the highest frequency of the present invention exceeds that of other processor cores, thanks to its optimized critical path design. Due to the use of the technology of dynamically scheduling out-of-order execution instructions, the core of the present invention requires more logic circuits to complete complex control functions, resulting in an area slightly larger than some sequential execution processors. However, through the combination of a low-power out-of-order scheduling scheme and a series of optimized designs, even when running at a maximum frequency close to 600MHz, the dynamic power consumption of the core remains at 14.36μW / MHz, which is better than most sequential processor cores.

[0124] The experimental results further prove that the processor core of the present invention has significant advantages in frequency and power consumption, which is due to the low-power dynamic scheduling scheme, optimized circuit configuration, and a series of low-power design methods for micro-architecture. The processor core of the present invention has the characteristics of high frequency, high performance and low power consumption, and performs particularly well in application scenarios that are sensitive to power consumption and have high requirements for processor performance.

[0125] In general, the present invention is based on the RISC-V instruction set and adopts a low-power embedded processor core microarchitecture with dynamic scheduling technology, which achieves a good balance between performance and power consumption, and is particularly suitable for scenarios with high requirements on both power consumption and performance.

[0126] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A low-power single-issue out-of-order execution RISC-V processor, characterized in that: It includes a seven-stage pipeline architecture, which are: instruction fetch unit, instruction buffer unit, decoding unit, single instruction issuance unit, physical register stack, parallel out-of-order computing execution unit, and retirement unit. The instruction fetch unit serves as the front end of the RISC-V processor; the five-stage pipeline architecture composed of the decoding unit, the emission unit, the physical register file, the execution unit and the retirement unit serves as the back end of the RISC-V processor; The instruction fetch unit is used to read the corresponding RISC-V instruction in the off-chip memory according to the PC value of the current cycle and transmit the corresponding RISC-V instruction to the instruction buffer unit; the instruction fetch unit is also used to predict the PC value of the next cycle through a dynamic branch predictor; The instruction buffer unit is used to sequentially receive RISC-V instructions from the instruction fetch unit to form an instruction buffer queue, and isolate the front-end calculation and back-end calculation of the RISC-V processor; The five-stage pipeline architecture of the RISC-V processor backend is used to sequentially decode RISC-V instructions, issue single instructions, read and write physical register stacks, perform out-of-order execution, and perform retirement operations to implement register data paths and memory access paths.

2. The low-power single-issue out-of-order execution RISC-V processor according to claim 1, characterized in that: The dynamic branch predictor in the instruction fetch unit includes: a prediction global history register, a query circuit, a mode history table, a saturation counter, a branch target buffer, a return address stack and a jump arbiter; Each address space in the pattern history table stores a saturation count value indicating whether to jump; the branch target buffer records the PC value and jump address of the branch instruction that has jumped; the return address stack stores the function call target address corresponding to the function return instruction; The query circuit is used to perform a logic operation on the PC value of the current cycle and the global jump history prediction value output by the prediction global history register to obtain an index address, and query the mode history table according to the index address to determine whether the PC value of the current cycle jumps; The saturation counter is used to update the corresponding saturation count value in the mode history table according to the jump state of the PC value of the current cycle; The jump arbiter is used to predict the PC value of the next cycle according to the jump state of the PC value of the current cycle, including: If a jump occurs, it is determined whether the PC value of the current cycle hits any branch instruction in the branch target buffer; if it hits, it is further determined whether the hit branch instruction is a function return instruction; if it is a function return instruction, the corresponding function call target address in the return address stack is predicted as the jump address of the PC value of the next cycle; if it is not a function return instruction, the jump address corresponding to the hit branch instruction is predicted as the jump address of the PC value of the next cycle; If no jump occurs, or if a jump occurs but the PC value of the current cycle does not hit any branch instruction in the branch target cache, the jump address of the PC value of the next cycle is predicted to be PC+k; k is a user-defined constant.

3. The low-power single-issue out-of-order execution RISC-V processor according to claim 1, characterized in that: The instruction fetch unit also includes: an architecture global history register; The architecture global history register records the accurate global jump history value after the instruction is executed, and is used to overwrite the predicted global jump history value in the predicted global history register with the accurate global jump history value in the next cycle when branch prediction fails.

4. The low-power single-issue out-of-order execution RISC-V processor according to claim 1, characterized in that: The instruction fetch unit further comprises: a first-level tightly coupled instruction cache unit; The first-level tightly coupled instruction cache unit is used to access the RISC-V instructions in the off-chip memory through the cache bus and the AXI interface according to the PC value of the current cycle, and read out and cache several RISC-V instructions corresponding to the PC value of the current cycle and the PC value of the adjacent cycle; The first-level tightly coupled instruction cache unit is also used to retrieve whether it has cached corresponding RISC-V instructions according to the PC value of the current cycle; if so, the RISC-V instructions corresponding to the PC value of the current cycle inside it are transmitted to the instruction buffer unit; otherwise, the RISC-V instructions corresponding to the PC value of the current cycle are accessed through the cache bus and the AXI interface to transmit the RISC-V instructions corresponding to the PC value of the current cycle to the instruction buffer unit, and read out and cache several RISC-V instructions corresponding to the PC values ​​of adjacent cycles.

5. The low-power single-issue out-of-order execution RISC-V processor according to claim 1, characterized in that: The instruction buffer unit adopts a non-compressed first-in-first-out architecture to buffer the RISC-V instructions sent by the front end of the RISC-V processor to adapt to the difference in computing speed between the front end and the back end.

6. The low-power single-issue out-of-order execution RISC-V processor according to claim 1, characterized in that: The decoding unit includes a decoding logic circuit, which is used to parse the RISC-V instructions obtained from the instruction buffer unit, obtain control information required for instruction execution, and jointly encode the control information using a one-hot code and a binary code.

7. The low-power single-issue out-of-order execution RISC-V processor according to claim 1, characterized in that: The decoding unit includes a register renaming unit, which is used to dynamically map the logical registers involved in the RISC-V instruction set to physical registers and generate access control information for the physical register stack to avoid read and write conflicts in the register data path; The register renaming unit is provided with: a physical register free list, a prediction renaming mapping table, a physical register ready list and a register allocation logic circuit; The physical register idle list is used to mark the idle state of each physical register; The predicted renaming mapping table is used to record the dynamic mapping relationship between logical registers and physical registers; The register allocation logic circuit is used to detect whether the physical register free list is available when the RISC-V instruction executes to write the destination logical register; if not, wait for the physical register to be released after the subsequent pipeline operation is completed; if so, arbitrate an idle physical register in the physical register free list through the first priority arbitration tree, allocate it as the destination physical register to the destination logical register to be written, and update the mapping relationship between the corresponding logical register and the physical register in the predicted rename mapping table; The register allocation logic circuit is further used to find out the corresponding source physical register number in the predicted rename mapping table when the RISC-V instruction executes a read source logical register, and find out the ready state of the corresponding source physical register in the physical register ready list according to the source physical register number; The register allocation logic circuit is also used to integrate the destination physical register number, source physical register number, and ready state of the source physical register corresponding to the current RISC-V instruction into the access control information for output.

8. The low-power single-issue out-of-order execution RISC-V processor according to claim 7, characterized in that: The register renaming unit is further provided with: a physical register free list checkpoint, and an architecture renaming mapping table; The physical register free list checkpoint is used to mark the current RISC-V instruction as a branch instruction, generate a branch number and back up the physical register free list when the current RISC-V instruction is a branch instruction; The register renaming unit is also used to restore the content of the physical register free list using the physical register free list checkpoint corresponding to the branch number in the next cycle when branch prediction fails, and to restore the content of the predicted renaming mapping table using the architecture renaming mapping table.

9. The low-power single-issue out-of-order execution RISC-V processor according to claim 7, characterized in that: The register allocation logic circuit also includes a register wake-up logic; The register wake-up logic is used to detect whether there is an early wake-up signal returned from the execution unit when the source physical register to be read by the current RISC-V instruction is not ready; if yes, compare the register number carried in the early wake-up signal with the source physical register number to be read by the current RISC-V instruction; if they are the same, update the source physical register to be read by the current instruction to a ready state; if they are not the same or there is no early wake-up signal, detect whether the write address of the physical register stack by the execution unit is consistent with the source physical register number to be read by the current instruction; if they are consistent, update the source physical register to be read by the current RISC-V instruction to a ready state; if they are inconsistent, wait for the source physical register to be executed; The physical register stack is used to perform a write operation on an idle destination physical register or a read operation on a ready source physical register according to the access control information.

10. The low-power single-issue out-of-order execution RISC-V processor according to claim 7, characterized in that: The first priority arbitration tree is a comparison multiplexing merging arbiter with a fixed low bit as the priority.

11. The low-power single-issue out-of-order execution RISC-V processor according to claim 1, characterized in that: The transmitting unit includes three independent parallel transmitting queues: a logic operation transmitting queue, a multiplication and division transmitting queue, and a memory access transmitting queue; each transmitting queue is a non-compressed and non-data capture queue; The transmitting unit further includes distribution logic, the distribution logic including transmit readiness logic, allocation logic, and an age arbitration tree; The transmit-ready logic is used to determine whether the current RISC-V instruction obtained from the decoding unit is ready to transmit, and when all source physical registers involved in the current RISC-V instruction are awakened, determine that the current RISC-V instruction is ready to transmit, and distribute the ready-to-transmit RISC-V instruction to one of the transmit queues according to its instruction type; The allocation logic searches for an idle item in the corresponding transmission queue through the second priority arbitration tree, and writes the ready-to-transmit RISC-V instruction into the idle item; The age arbitration tree is used to sort the RISC-V instructions in each transmission queue by age, and arbitrate the oldest instructions in each of the three transmission queues for parallel transmission.

12. The low-power single-issue out-of-order execution RISC-V processor according to claim 1, characterized in that: The execution unit is used to use an input gating circuit to receive decoding information of one or more RISC-V instructions emitted by the emission unit, assign it to a corresponding functional unit for calculation, and submit the calculation result to a register data path or a memory access path; The functional unit includes an independent arithmetic logic operation unit, a multiplication and division calculation unit and a memory access unit; the arithmetic logic operation unit is used to process the calculation of single-cycle arithmetic operation instructions and branch jump instructions; the multiplication and division calculation unit is used to process the instruction calculation of the M-type extended instruction set; the memory access unit is used to process the calculation of load instructions and storage instructions.

13. The low-power single-issue out-of-order execution RISC-V processor according to claim 12, characterized in that: The memory access path includes a non-compressed load queue and a first-in-first-out storage queue; the storage instruction is used to write data to an external device through the memory access path; the load instruction is used to read data from an external device to the physical register file through the memory access path; The memory access unit is used to sequentially execute the storage instructions in the storage queue, and to execute the load instructions in the load queue whose age is greater than the storage instructions to be retired out of order.

14. The low-power single-issue out-of-order execution RISC-V processor according to claim 13, characterized in that: The memory access path further comprises a first-level tightly coupled data cache unit; the first-level tightly coupled data cache unit is used to cache data required to be read in by a load instruction in a load queue or data required to be written out by a store instruction in a store queue.

15. The low-power single-issue out-of-order execution RISC-V processor according to claim 1, characterized in that: The retirement unit is provided with a first-in-first-out reordering cache, a branch prediction failure recovery logic and an interrupt anomaly detection logic; The retirement unit is used to retire the instructions entering the reorder cache in order, and return the accurate value of the global jump history of the retired instructions to the instruction fetch unit, and return the physical register number and register mapping relationship released by the retired instructions to the decoding unit; The retirement unit is also used to perform branch prediction failure detection and interrupt exception detection at the dequeue pointer of the reorder cache using the branch prediction failure recovery logic and interrupt exception detection logic, and flush the pipeline architecture of each level of the RISC-V processor when a branch prediction failure or interrupt exception occurs, and use the accurate value of the global jump history and the correct register mapping relationship to perform calculation recovery on the RISC-V processor.

16. An instruction processing method for RISC-V instruction set, characterized in that: Including processing input RISC-V instructions based on the seven-stage pipeline architecture of the RISC-V processor according to any one of claims 1-15.

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