A processor interrupt control device and method based on RISC-V architecture

Abstract

The present invention relates to the field of integrated circuit design, and discloses a processor interrupt control device and method based on RISC-V architecture, wherein the device includes a cross-clock domain synchronization module, an interrupt request signal capture module, an interrupt register module, an interrupt arbitration module, an interrupt vector storage module, and an arbitration result output module; through the coordination and cooperation of multiple modules, efficient arbitration of several interrupt event requests issued simultaneously by n interrupt sources can be completed in a single cycle, and multiple interrupt information winning the arbitration interrupt can be provided to the processor core at the same time. The device strictly follows the CLIC interrupt standard of the RISC-V architecture, and improves the portability, compatibility and efficiency of the software. The device can effectively handle complex interrupt scenarios, improve the interrupt processing capability of the system, reduce the consumption of transistor resources, and shorten the timing path length, and is particularly suitable for applications such as digital signal processors and microcontrollers that are sensitive to hardware resources.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a processor interrupt control device and method based on RISC-V architecture. Background Art

[0002] With the rapid development of applications such as the Internet of Things, smart homes, and automotive electronics, the demand for high-performance processors continues to increase, especially in embedded microprocessors, where the demand for efficient and reliable interrupt handling mechanisms is becoming more and more urgent. The interrupt handling mechanism refers to the interruption of the normal program execution flow in the processor, and is an asynchronous event that requires the processor to handle in a timely manner. When the system is running, if an event that requires immediate processing occurs (such as hardware failure, external device request, etc.), the interrupt handling mechanism allows the processor to suspend the execution of the current task and execute a specific interrupt service program instead. After the processing is completed, the original task will be resumed. The speed of the interrupt response directly affects the performance of the entire real-time signal chain of the processor's perception, processing, and execution of external events. The interrupt handling mechanism is an important internal mechanism of modern processors, which improves the response speed and real-time performance of the system.

[0003] The interrupt control device is an important part of the interrupt handling mechanism. When the processor is executing a task, multiple interrupt event requests may occur at the same time. The priorities of these interrupt event requests are different, and the time of occurrence is unpredictable. When multiple interrupt event requests are sent to the processor core almost at the same time, the interrupt control device is responsible for managing the interrupt event requests of these external interrupt sources. The interrupt control device needs to arbitrate and manage each interrupt event request according to the priority, enable status and threshold settings of different interrupt events to ensure that the processor core responds to the interrupt request with the highest urgency first, thereby meeting the real-time processing requirements of the processor to the greatest extent.

[0004] Faced with the diversification of applications and the increase in system complexity, existing interrupt control devices still have some problems in handling multiple interrupts, priority management, and efficient response, which limits the real-time performance and flexibility of the system. Traditional interrupt control devices mostly use fixed priority settings, and cannot dynamically adjust the priority according to actual needs. It is difficult to flexibly adjust the interrupt processing strategy or dynamically allocate interrupt resources according to different application scenarios; the configuration of interrupt event requests is relatively complex and not intuitive, which increases the difficulty of system design and maintenance, and also limits the subsequent expansion and upgrade of system functions; the interrupt nesting processing capability is insufficient, and the existing interrupt control device has limited support for interrupt nesting, and cannot effectively handle more urgent interrupt event requests that occur during the execution of the interrupt service program, affecting the real-time response capability of the system.

[0005] In the prior art, the arbitration logic of the interrupt control device is relatively complex to implement, and the multi-level combinational logic increases the timing path length of the interrupt arbitration, which limits the arbitration cycle of the interrupt control device or the overall clock frequency of the processor, which reduces the response speed of the system. In order to realize the priority arbitration, register configuration management, cross-clock domain synchronization and other functions of the interrupt event request, the existing design often requires the use of a large number of gate circuits and triggers, which significantly increases the chip area, while causing an increase in chip power consumption and cost, and becomes a bottleneck restricting system integration and cost control in resource-constrained applications. How to achieve a large number of interrupt event requests while quickly obtaining the arbitration results of the interrupt event request without significantly increasing the timing path length and chip area of ​​the processor chip has become a major technical difficulty in current processor design. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a processor interrupt control device and method based on the RISC-V architecture, so as to greatly improve the response speed of the processor to interrupt event requests, reduce the chip area of ​​the processor, and reduce the power consumption of the processor.

[0007] To achieve the above object, the technical solution of the present invention is as follows:

[0008] A processor interrupt control device based on RISC-V architecture, comprising a cross-clock domain synchronization module, an interrupt request signal capture module, an interrupt register module, an interrupt arbitration module, an interrupt vector storage module, and an arbitration result output module;

[0009] The cross-clock domain synchronization module is used to stably synchronize the interrupt request signals from the n interrupt sources that are asynchronous or in different clock domains to the clock domain of the interrupt control device;

[0010] The interrupt request signal capture module is responsible for edge detection or level sampling of n interrupt request signals synchronized from the cross-clock domain synchronization module according to the value of the interrupt trigger mode trig bit field of the interrupt attribute register in the interrupt register module;

[0011] The interrupt register module is responsible for managing and controlling the interrupt enable state, interrupt wait state, interrupt level, interrupt priority, interrupt trigger mode and interrupt hardware vectorization mode of n interrupt sources; the processor core can read and write the contents of the interrupt register module through the bus;

[0012] The interrupt arbitration module is responsible for arbitrating interrupt event requests from a number of interrupt sources in the interrupt enable and wait states issued by n interrupt sources. The module can obtain the arbitration result within one cycle. The interrupt enable state, interrupt wait state, interrupt level information, and interrupt priority information required in the arbitration process come from the interrupt register module. The interrupt threshold information required in the arbitration process comes from the interrupt CSR register of the processor core.

[0013] The interrupt vector storage module stores the entry vectors of the interrupt service program corresponding to n interrupt sources. The n interrupt vector table entries are stored continuously in the interrupt vector storage module starting from the interrupt vector base address and with a step length of four bytes. The processor core extracts the corresponding interrupt vector table entry according to the arbitrated interrupt ID, and then directly jumps to the address to execute the interrupt service program. The processor core can read and write the content in the interrupt vector storage module through the bus;

[0014] The arbitration result output module selects and outputs the interrupt information of the arbitration interrupt source according to the n-bit one-hot code signal output by the interrupt arbitration module, and outputs the obtained arbitration result to the processor core.

[0015] In the above scheme, if the interrupt trigger mode trig bit field of the interrupt attribute register is 00, the interrupt request signal capture module samples the high level from n interrupt request signals, and if the current cycle value is high, the interrupt request signal is captured;

[0016] If the interrupt trigger mode trig bit field of the interrupt attribute register is 01, the interrupt request signal capture module performs low-level sampling on n interrupt request signals, and if the current cycle value is low, the interrupt request signal is captured;

[0017] If the interrupt trigger mode trig bit field of the interrupt attribute register is 10, the interrupt request signal capture module performs rising edge detection on n interrupt request signals. When it is detected that the current cycle value is high and the previous clock cycle is low, it means that a rising edge has occurred, and the interrupt request signal is captured;

[0018] If the interrupt trigger mode trig bit field of the interrupt attribute register is 11, the interrupt request signal capture module performs falling edge detection on n interrupt request signals. When it is detected that the current cycle value is low and the previous clock cycle is high, it means that a falling edge has occurred, and the interrupt request signal is captured;

[0019] After the interrupt request signal capture module captures the interrupt request signal, the interrupt wait register of the corresponding interrupt source in the interrupt wait register group in the interrupt register module is pulled high.

[0020] In the above scheme, the interrupt register module includes an interrupt waiting register group consisting of n 8-bit interrupt waiting registers, an interrupt enable register group consisting of n 8-bit interrupt enable registers, an interrupt attribute register group consisting of n 8-bit interrupt attribute registers and an interrupt control register group consisting of n 8-bit interrupt control registers, and the n interrupt sources have corresponding 8-bit interrupt waiting registers, 8-bit interrupt enable registers, 8-bit interrupt attribute registers and 8-bit interrupt control registers.

[0021] In a further technical solution, each interrupt waiting register of the interrupt waiting register group indicates whether each interrupt is in an interrupt waiting state. The lowest bit of the interrupt waiting register, namely the interrupt waiting bit ip, is zero, indicating that there is no pending interrupt event. The lowest bit of the interrupt waiting register, namely the interrupt waiting bit ip, is one, indicating that an interrupt request is in a waiting state. After the interrupt request signal capture module captures the interrupt request signal, it will set the corresponding interrupt waiting bit to one until the corresponding interrupt is responded to and cleared after processing.

[0022] In a further technical solution, each interrupt enable register in the interrupt enable register group is responsible for controlling whether the interrupt request of the corresponding interrupt source is allowed to enter the interrupt arbitration and triggering process. When the lowest bit of the interrupt enable register, i.e., the interrupt enable bit ie, is one, the interrupt is allowed to be triggered; when the lowest bit of the interrupt enable register, i.e., the interrupt enable bit ie, is zero, even if there is an interrupt event request to be processed, it will be blocked.

[0023] In a further technical solution, each interrupt attribute register of the interrupt attribute register group is responsible for controlling the triggering mode and hardware vectorization mode of the interrupt, determining whether the interrupt is edge triggered or level triggered, and whether hardware vectorization is adopted;

[0024] The lowest bit of the interrupt attribute register, i.e., the interrupt hardware vectorization selection bit hv, is 1, indicating that hardware automatic vectorization is allowed. The hardware can select the corresponding interrupt vector address from the interrupt vector memory according to the interrupt source ID of the arbitration interrupt result.

[0025] The lowest bit of the interrupt attribute register, i.e., the interrupt hardware vectorization selection bit hv, is zero, indicating that hardware automatic vectorization is not allowed, and the hardware calculates the corresponding interrupt vector address through the interrupt service program;

[0026] The first and second bits of the interrupt attribute register are the interrupt trigger mode bit field trig. When the interrupt trigger mode bit field trig is 00, the interrupt request signal module captures the high-level interrupt signal. When the high-level interrupt signal is captured, the interrupt wait bit ip of the corresponding interrupt wait register is set to one. When the interrupt trigger mode bit field trig is 01, the interrupt request signal module captures the low-level interrupt signal. When the low-level interrupt signal is captured, the interrupt wait bit ip of the corresponding interrupt wait register is set to one. When the interrupt trigger mode bit field trig is 10, the interrupt request signal module captures the rising edge interrupt signal. When the rising edge interrupt signal is captured, the interrupt wait bit ip of the corresponding interrupt wait register is set to one. When the interrupt trigger mode bit field is 11, the interrupt request signal module captures the falling edge interrupt signal. When the falling edge interrupt signal is captured, the interrupt wait bit ip of the corresponding interrupt wait register is set to one.

[0027] In a further technical solution, each interrupt control register in the interrupt control register group is used to set the interrupt level and interrupt priority of the corresponding interrupt source, wherein the high nlbits bits are the interrupt level and the low 8-nlbits bits are the interrupt priority.

[0028] In the above scheme, the interrupt arbitration module includes a response interrupt level and priority preprocessing module, a maximum interrupt level and priority solving module, a maximum interrupt request preprocessing module, a maximum interrupt request ID arbitration module, and an interrupt threshold comparison module;

[0029] The response interrupt level and priority preprocessing module is responsible for expanding the interrupt levels and priorities of n interrupt sources into a one-hot code format and outputting the result to the highest interrupt level and priority solving module;

[0030] The highest interrupt level and priority solving module obtains the highest interrupt level and priority one-hot code result by solving the one-hot code result of the interrupt levels and priorities of n interrupt sources, and outputs it to the highest interrupt request preprocessing module;

[0031] The highest interrupt request preprocessing module sets the interrupt source with the highest interrupt level and priority among the n interrupt sources, which is in the interrupt enable and waiting state, to one, and the other positions to zero, to obtain the n-bit one-hot code form result of the highest interrupt request, and outputs it to the highest interrupt request ID arbitration module;

[0032] The highest interrupt request ID arbitration module is responsible for obtaining the n-bit one-hot code form result of the highest interrupt request with the largest ID from the n-bit one-hot code form results of the highest interrupt request, and outputting it to the interrupt threshold comparison module;

[0033] The interrupt threshold comparison module is responsible for comparing the interrupt level of the highest interrupt request with the largest ID with the interrupt threshold of the interrupt threshold register from the processor core. If the interrupt level of the highest interrupt request with the largest ID is greater than or equal to the interrupt threshold of the interrupt threshold register, the highest interrupt unique code result with the largest ID is output to the arbitration result output module.

[0034] In the above scheme, the arbitration result output module includes an arbitration interrupt ID result output module, an arbitration interrupt vector result output module, an arbitration interrupt trigger mode result output module, an arbitration interrupt vectorization mode result output module, and an arbitration interrupt level result output module;

[0035] The arbitration interrupt ID result output module is responsible for selecting and outputting the interrupt ID information of the corresponding interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module;

[0036] The arbitration interrupt vector result output module is responsible for selecting and outputting the vector entry of the interrupt service program corresponding to the interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module;

[0037] The arbitration interrupt trigger mode result output module is responsible for selecting and outputting the interrupt trigger mode of the corresponding interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module;

[0038] The arbitration interrupt vectorization mode result output module is responsible for selecting and outputting the hardware vectorization mode of the corresponding interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module;

[0039] The arbitration interrupt level result output module is responsible for selecting and outputting the interrupt level of the corresponding interrupt source according to the n-bit highest interrupt one-hot code result with the largest ID output by the interrupt arbitration module.

[0040] A processor interrupt control method based on RISC-V architecture, using a processor interrupt control device based on RISC-V architecture as described above, characterized in that it includes the following steps:

[0041] Step 1, the cross-clock domain synchronization module stably synchronizes the interrupt request signals from the asynchronous or different clock domains of n interrupt sources to the clock domain of the interrupt control device, and outputs the n interrupt request signals after the synchronized clock domain to the interrupt request signal capture module;

[0042] Step 2, the interrupt request signal capture module performs edge detection or level sampling on n interrupt request signals according to the value of the interrupt trigger mode trig bit field of the interrupt attribute register in the interrupt register module;

[0043] Step 3, the interrupt arbitration module is responsible for arbitrating the interrupt event requests of several interrupt sources in the interrupt enable and waiting state issued by n interrupt sources;

[0044] Step 4, the interrupt arbitration module outputs the n-bit highest interrupt one-hot code result with the largest ID to the arbitration result output module;

[0045] Step 5: The arbitration result output module selects and outputs the interrupt information of the arbitration interrupt source according to the n-bit one-hot code signal output by the interrupt arbitration module, and outputs the arbitration result to the processor core.

[0046] Through the above technical solution, the processor interrupt control device and method based on RISC-V architecture provided by the present invention have the following beneficial effects:

[0047] 1. This device can arbitrate and manage interrupt event requests from multiple interrupt sources simultaneously within one clock cycle, significantly improving the interrupt response speed and meeting application scenarios with high real-time requirements.

[0048] 2. The interrupt enable state, interrupt level and priority parameters of this device can be dynamically configured. Users can adjust the interrupt strategy in real time according to different application requirements, which enhances the flexibility and adaptability of the system;

[0049] 3. This device supports advanced interrupt mechanisms such as nested interrupts, interrupt tail biting and late interrupts, which can effectively handle complex interrupt scenarios and improve the system's interrupt processing capabilities;

[0050] 4. This device adopts simple interrupt arbitration logic, which reduces the consumption of transistor resources, shortens the timing path length, and reduces power consumption. It is particularly suitable for applications such as digital signal processors and microcontrollers that are sensitive to hardware resources;

[0051] 5. This device strictly follows the CLIC interrupt standard of the RISC-V architecture in key links such as interrupt register organization, interrupt triggering method, interrupt arbitration strategy, and interrupt vector processing, reducing the software adaptation workload caused by hardware differences and improving the portability, compatibility and efficiency of the software.

[0052] In summary, the interrupt control device of the present invention is superior to the existing technology in improving interrupt response speed, enhancing system flexibility, supporting complex interrupt mechanisms, reducing hardware resource consumption, and improving software adaptability, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0054] Figure 1 A schematic diagram of the structure of a processor interrupt control device based on RISC-V architecture disclosed in an embodiment of the present invention;

[0055] Figure 2 A schematic diagram of the structure of an interrupt register module disclosed in an embodiment of the present invention;

[0056] Figure 3 A schematic diagram of the structure of an interrupt arbitration module disclosed in an embodiment of the present invention;

[0057] Figure 4 It is a schematic diagram of the structure of the interrupt vector storage module disclosed in the embodiment of the present invention. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0059] The present invention provides a processor interrupt control device based on RISC-V architecture, such as Figure 1 As shown, it includes a cross-clock domain synchronization module, an interrupt request signal capture module, an interrupt register module, an interrupt arbitration module, an interrupt vector storage module, and an arbitration result output module; the functions of each module are as follows:

[0060] 1. Cross-clock domain synchronization module

[0061] The cross-clock domain synchronization module is used to stably synchronize the interrupt request signals from the asynchronous or different clock domains of n interrupt sources to the clock domain of the interrupt control device, so that the interrupt request signal is stable and reliable in the new clock domain, avoiding erroneous interrupt triggering or leaking triggering due to noise or signal glitches, ensuring reliable and accurate capture of external interrupt requests, preventing potential errors caused by metastable states, and ensuring the overall stability of the system.

[0062] 2. Interrupt request signal capture module

[0063] The interrupt request signal capture module is responsible for edge detection or level sampling of the n interrupt request signals synchronized by the cross-clock domain synchronization module according to the value of the interrupt trigger mode trig bit field of the interrupt attribute register in the interrupt register module.

[0064] If the interrupt trigger mode trig bit field of the interrupt attribute register is 00, the interrupt request signal capture module samples the high level from n interrupt request signals, and if the current cycle value is high, the interrupt request signal is captured;

[0065] If the interrupt trigger mode trig bit field of the interrupt attribute register is 01, the interrupt request signal capture module performs low-level sampling on n interrupt request signals, and if the current cycle value is low, the interrupt request signal is captured;

[0066] If the interrupt trigger mode trig bit field of the interrupt attribute register is 10, the interrupt request signal capture module performs rising edge detection on n interrupt request signals. When it is detected that the current cycle value is high and the previous clock cycle is low, it means that a rising edge has occurred, and the interrupt request signal is captured;

[0067] If the interrupt trigger mode trig bit field of the interrupt attribute register is 11, the interrupt request signal capture module performs falling edge detection on n interrupt request signals. When it is detected that the current cycle value is low and the previous clock cycle is high, it means that a falling edge has occurred, and the interrupt request signal is captured;

[0068] After the interrupt request signal capture module captures the interrupt request signal, the interrupt wait register of the corresponding interrupt source in the interrupt wait register group in the interrupt register module is pulled high.

[0069] 3. Interrupt Register Module

[0070] The interrupt register module is responsible for managing and controlling the interrupt enable state, interrupt waiting state, interrupt level, interrupt priority, interrupt trigger mode, and interrupt hardware vectorization mode of n interrupt sources, so as to support flexible adjustment of interrupt processing strategies or dynamic allocation of interrupt resources according to different application scenarios, thereby improving interrupt response efficiency, reducing software overhead, and achieving better real-time performance and flexibility. The processor core can read and write the contents of the interrupt register module through the bus.

[0071] like Figure 2 As shown, the interrupt register module includes an interrupt waiting register group, an interrupt enable register group, an interrupt attribute register group and an interrupt control register group. Each of the n interrupt sources has a corresponding 8-bit interrupt waiting register, an 8-bit interrupt enable register, an 8-bit interrupt attribute register and an 8-bit interrupt control register. The n 8-bit interrupt waiting registers constitute the interrupt waiting register group, the n 8-bit interrupt enable registers constitute the interrupt enable register group, the n 8-bit interrupt attribute registers constitute the interrupt attribute register group, and the n 8-bit interrupt control registers constitute the interrupt control register group.

[0072] 1. Interrupt wait register group

[0073] Each interrupt waiting register of the interrupt waiting register group indicates whether each interrupt is in the interrupt waiting state. The lowest bit of the interrupt waiting register, namely the interrupt waiting bit ip, is zero, indicating that there is no pending interrupt event. The lowest bit of the interrupt waiting register, namely the interrupt waiting bit ip, is one, indicating that an interrupt request is in the waiting state. After the interrupt request signal capture module captures the interrupt request signal, it will set the corresponding interrupt waiting bit to one until the corresponding interrupt is responded to and cleared after processing.

[0074] 2. Interrupt enable register group

[0075] Each interrupt enable register in the interrupt enable register group is responsible for controlling whether the interrupt request of the corresponding interrupt source is allowed to enter the interrupt arbitration and triggering process. When the lowest bit of the interrupt enable register, i.e., the interrupt enable bit ie, is one, the interrupt is allowed to be triggered; when the lowest bit of the interrupt enable register, i.e., the interrupt enable bit ie, is zero, even if there is an interrupt event request to be processed, it will be blocked.

[0076] 3. Interrupt attribute register group

[0077] Each interrupt attribute register in the interrupt attribute register group is responsible for controlling the interrupt triggering mode and hardware vectorization mode, determining whether the interrupt is edge triggered or level triggered, and whether hardware vectorization is used;

[0078] The lowest bit of the interrupt attribute register, i.e., the interrupt hardware vectorization selection bit hv, is 1, indicating that hardware automatic vectorization is allowed. The hardware can select the corresponding interrupt vector address from the interrupt vector memory according to the interrupt source ID of the arbitration interrupt result.

[0079] The lowest bit of the interrupt attribute register, i.e., the interrupt hardware vectorization selection bit hv, is zero, indicating that hardware automatic vectorization is not allowed, and the hardware calculates the corresponding interrupt vector address through the interrupt service program;

[0080] The first and second bits of the interrupt attribute register are the interrupt trigger mode bit field trig. When the interrupt trigger mode bit field trig is 00, the interrupt request signal module captures the high-level interrupt signal. When the high-level interrupt signal is captured, the interrupt wait bit ip of the corresponding interrupt wait register is set to one. When the interrupt trigger mode bit field trig is 01, the interrupt request signal module captures the low-level interrupt signal. When the low-level interrupt signal is captured, the interrupt wait bit ip of the corresponding interrupt wait register is set to one. When the interrupt trigger mode bit field trig is 10, the interrupt request signal module captures the rising edge interrupt signal. When the rising edge interrupt signal is captured, the interrupt wait bit ip of the corresponding interrupt wait register is set to one. When the interrupt trigger mode bit field is 11, the interrupt request signal module captures the falling edge interrupt signal. When the falling edge interrupt signal is captured, the interrupt wait bit ip of the corresponding interrupt wait register is set to one.

[0081] 4. Interrupt control register group

[0082] Each interrupt control register in the interrupt control register group is used to set the interrupt level and interrupt priority of the corresponding interrupt source, where the high nlbits bits are the interrupt level and the low 8-nlbits bits are the interrupt priority.

[0083] 4. Interrupt Arbitration Module

[0084] The interrupt arbitration module is responsible for arbitrating interrupt event requests from several interrupt sources in the interrupt enable and waiting states issued by n interrupt sources. The module can obtain the arbitration result within one cycle. The interrupt enable status, interrupt waiting status, interrupt level information, and interrupt priority information required in the arbitration process come from the interrupt register module, and the interrupt threshold information required in the arbitration process comes from the interrupt CSR register of the processor core.

[0085] like Figure 3 As shown, the interrupt arbitration module includes a response interrupt level and priority preprocessing module, a maximum interrupt level and priority solving module, a maximum interrupt request preprocessing module, a maximum interrupt request ID arbitration module, and an interrupt threshold comparison module.

[0086] 1. Response to interrupt level and priority preprocessing module

[0087] The response interrupt level and priority preprocessing module is responsible for expanding the interrupt levels and priorities of n interrupt sources into one-hot code form and outputting the results to the highest interrupt level and priority solving module.

[0088] 2. Maximum interrupt level and priority solving module

[0089] The highest interrupt level and priority solving module obtains the highest interrupt level and priority one-hot code result by solving the one-hot code result of the interrupt levels and priorities of n interrupt sources, and outputs it to the highest interrupt request preprocessing module.

[0090] 3. Highest interrupt request preprocessing module

[0091] The highest interrupt request preprocessing module sets the interrupt source with the highest interrupt level and priority among the n interrupt sources, which is in the interrupt enabled and waiting state, to one, and the remaining positions to zero, to obtain the n-bit one-hot code form of the highest interrupt request, and outputs it to the highest interrupt request ID arbitration module.

[0092] 4. Highest interrupt request ID arbitration module

[0093] The highest interrupt request ID arbitration module is responsible for obtaining the n-bit one-hot code form result of the highest interrupt request with the largest ID from the n-bit one-hot code form results of the highest interrupt request, and outputting it to the interrupt threshold comparison module.

[0094] 5. Interrupt threshold comparison module

[0095] The interrupt threshold comparison module is responsible for comparing the interrupt level of the highest interrupt request with the largest ID with the interrupt threshold of the interrupt threshold register from the processor core. If the interrupt level of the highest interrupt request with the largest ID is greater than or equal to the interrupt threshold of the interrupt threshold register, the highest interrupt unique code result with the largest ID is output to the arbitration result output module.

[0096] The following functional logic is realized through the coordination of the above modules:

[0097] Among the interrupt event requests of several interrupt sources in the interrupt enable and interrupt wait states, the one with a higher interrupt level wins arbitration. When the interrupt levels of several interrupt sources are the same, interrupt priority arbitration is performed. Among the interrupt event requests of several interrupt sources, the one with a higher interrupt priority wins arbitration. When the interrupt levels and interrupt priorities of several interrupt sources are the same, interrupt ID arbitration is performed. Among the interrupt event requests of several interrupt sources, the one with a larger interrupt ID wins arbitration. Finally, the interrupt event request of the interrupt source with the highest urgency is obtained. If the interrupt level of the interrupt source is greater than or equal to the interrupt threshold in the interrupt CSR from the processor core, the interrupt event request of a certain interrupt source is successfully arbitrated, and the interrupt arbitration module outputs the n-bit highest interrupt unique hot code result with the largest ID to the arbitration result output module.

[0098] 5. Interrupt vector storage module

[0099] like Figure 4 As shown, the interrupt vector storage module stores the entry vectors of the interrupt service programs corresponding to n interrupt sources. The n interrupt vector table entries are stored continuously in the interrupt vector storage module starting from the interrupt vector base address with a step length of four bytes. The processor core will extract the corresponding interrupt vector table entry according to the arbitrated interrupt ID, and then directly jump to the address to execute the interrupt service program. The processor core can read and write the contents of the interrupt vector storage module through the bus.

[0100] 6. Arbitration Result Output Module

[0101] The arbitration result output module selects and outputs the interrupt information such as the interrupt ID of the arbitration interrupt source, the vector entry of the interrupt service program, the interrupt trigger mode, the interrupt hardware vectorization mode and the interrupt level according to the n-bit unique hot code signal output by the interrupt arbitration module, and outputs the obtained arbitration result to the processor core.

[0102] The arbitration result output module includes an arbitration interrupt ID result output module, an arbitration interrupt vector result output module, an arbitration interrupt trigger mode result output module, an arbitration interrupt vectorization mode result output module, and an arbitration interrupt level result output module.

[0103] 1. Arbitration interrupt ID result output module

[0104] The arbitration interrupt ID result output module is responsible for selecting and outputting the interrupt ID information of the corresponding interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module.

[0105] 2. Arbitration interrupt vector result output module

[0106] The arbitration interrupt vector result output module is responsible for selecting and outputting the vector entry of the interrupt service program corresponding to the interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module.

[0107] 3. Arbitration interrupt trigger mode result output module

[0108] The arbitration interrupt trigger mode result output module is responsible for selecting and outputting the interrupt trigger mode of the corresponding interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module.

[0109] 4. Arbitration interrupt vectorization result output module

[0110] The arbitration interrupt vectorization mode result output module is responsible for selecting and outputting the hardware vectorization mode of the corresponding interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module.

[0111] 5. Arbitration interrupt level result output module

[0112] The arbitration interrupt level result output module is responsible for selecting and outputting the interrupt level of the corresponding interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module.

[0113] The multifunctional interrupt control device is designed with full consideration of the CLIC interrupt standard of the RISC-V architecture to ensure compatibility with the RISC-V interrupt mechanism; the interrupt request signal capture module of the device performs edge detection or level sampling according to the interrupt trigger mode trig bit field of the interrupt attribute register in the interrupt register module, and supports high level, low level, rising edge and falling edge trigger modes, which is consistent with the interrupt trigger mode description in the CLIC interrupt standard of the RISC-V architecture.

[0114] The interrupt register module of the device implements interrupt registers such as interrupt enable register, interrupt wait register, interrupt attribute register, interrupt control register corresponding to n interrupt sources, which complies with the interrupt register design requirements of the CLIC interrupt standard of the RISC-V architecture;

[0115] The interrupt arbitration module of the device implements the interrupt arbitration strategy of first performing interrupt level arbitration, then performing interrupt priority arbitration, then performing interrupt ID arbitration, and finally performing interrupt threshold comparison, which meets the sequential requirements of hierarchical arbitration of interrupt level, interrupt priority, ID to interrupt threshold of CLIC interrupt standard of RISC-V architecture;

[0116] The interrupt vector storage module in the device stores an independent interrupt vector table entry for each interrupt source hardware. When the interrupt arbitration is completed, the interrupt vector entry of the interrupt event request that won the arbitration can be quickly given, which supports the implementation of the hardware vectorization mechanism for selecting the CLIC interrupt standard of the RISC-V architecture.

[0117] In summary, the processor's multifunctional interrupt control device strictly follows the CLIC interrupt standard of the RISC-V architecture in key links such as interrupt register organization, interrupt triggering method, interrupt arbitration strategy, and interrupt vector processing, reducing the software adaptation workload caused by hardware differences and improving the software's portability, compatibility, and efficiency. The device is suitable for embedded scenarios with strict real-time requirements.

[0118] Next, the workflow of a processor multifunctional interrupt control device based on the RISC-V architecture, which is capable of simultaneously arbitrating and managing n interrupt event requests from interrupt sources in a single cycle, is introduced according to a specific embodiment of the present invention. The interrupt control device can complete the arbitration of interrupt event requests from n interrupt sources in one cycle to obtain the highest interrupt event request with the largest ID, and at the same time output interrupt information such as the interrupt ID of the arbitrated interrupt event request, the vector entry of the interrupt service program, the interrupt triggering mode, the interrupt hardware vectorization mode and the interrupt level to the processor core.

[0119] A processor interrupt control method based on RISC-V architecture, using a processor interrupt control device based on RISC-V architecture as above, comprises the following steps:

[0120] Step 1, the cross-clock domain synchronization module stably synchronizes the interrupt request signals from the asynchronous or different clock domains of n interrupt sources to the clock domain of the interrupt control device, ensuring reliable and accurate capture of external interrupt requests, and outputs the n interrupt request signals after the synchronized clock domain to the interrupt request signal capture module.

[0121] Step 2: The interrupt request signal capture module performs edge detection or level sampling on n interrupt request signals according to the value of the interrupt trigger mode trig bit field of the interrupt attribute register in the interrupt register module.

[0122] If the interrupt trigger mode trig bit field of the interrupt attribute register is 00, the interrupt request signal capture module samples the high level from n interrupt request signals, and if the current cycle value is high, the interrupt request signal is captured;

[0123] If the interrupt trigger mode trig bit field of the interrupt attribute register is 01, the interrupt request signal capture module performs low-level sampling on n interrupt request signals, and if the current cycle value is low, the interrupt request signal is captured;

[0124] If the interrupt trigger mode trig bit field of the interrupt attribute register is 10, the interrupt request signal capture module performs rising edge detection on n interrupt request signals. When it is detected that the current cycle value is high and the previous clock cycle is low, it means that a rising edge has occurred, and the interrupt request signal is captured;

[0125] If the interrupt trigger mode trig bit field of the interrupt attribute register is 11, the interrupt request signal capture module performs falling edge detection on n interrupt request signals. When it is detected that the current cycle value is low and the previous clock cycle is high, it means that a falling edge has occurred, and the interrupt request signal is captured;

[0126] After the interrupt request signal capture module captures the interrupt request signal, the interrupt wait register of the corresponding interrupt source in the interrupt wait register group in the interrupt register module is pulled high.

[0127] Step 3: The interrupt arbitration module is responsible for arbitrating interrupt event requests from a number of interrupt sources in the interrupt enable and waiting states issued by n interrupt sources.

[0128] First, the response interrupt level and priority preprocessing module is responsible for expanding the interrupt levels and priorities of n interrupt sources into one-hot code form and outputting the result to the highest interrupt level and priority solving module;

[0129] The highest interrupt level and priority solving module solves the one-hot code form results of the interrupt levels and priorities of n interrupt sources to obtain the highest interrupt level and priority one-hot code form results and outputs them to the highest interrupt request preprocessing module;

[0130] The highest interrupt request preprocessing module sets the interrupt source with the highest interrupt level and priority among the n interrupt sources, which is in the interrupt enable and waiting state, to one, and the other positions to zero, and obtains the highest interrupt request in the form of an n-bit one-hot code, which is output to the highest interrupt request ID arbitration module;

[0131] The highest interrupt request ID arbitration module is responsible for obtaining the n-bit one-hot code form result of the highest interrupt request with the largest ID from the n-bit one-hot code form result of the highest interrupt request and outputting it to the interrupt threshold comparison module;

[0132] The interrupt threshold comparison module is responsible for comparing the interrupt level of the highest interrupt request with the largest ID with the interrupt threshold of the interrupt threshold register from the processor core. If the interrupt level of the highest interrupt request with the largest ID is greater than or equal to the interrupt threshold of the interrupt threshold register, the highest interrupt unique code result with the largest ID is output to the arbitration result output module.

[0133] The following functional logic is implemented through the coordination of the above modules: among the interrupt event requests of several interrupt sources in the interrupt enable and interrupt wait states, the one with a higher interrupt level wins arbitration; when the interrupt levels of several interrupt sources are the same, interrupt priority arbitration is performed; among the interrupt event requests of several interrupt sources, the one with a higher interrupt priority wins arbitration; when the interrupt levels and interrupt priorities of several interrupt sources are the same, interrupt ID arbitration is performed; among the interrupt event requests of several interrupt sources, the one with a larger interrupt ID wins arbitration; finally, the interrupt event request of the interrupt source with the highest urgency is obtained; if the interrupt level of the interrupt source is greater than or equal to the interrupt threshold in the interrupt CSR from the processor core, the interrupt event request arbitration of a certain interrupt source succeeds.

[0134] Step 4: The interrupt arbitration module outputs the n-bit highest interrupt one-hot code result with the largest ID to the arbitration result output module.

[0135] Step 5, the arbitration result output module selects and outputs the interrupt ID of the arbitration interrupt source, the vector entry of the interrupt service program, the interrupt trigger mode, the interrupt hardware vectorization mode and the interrupt level according to the n-bit unique hot code signal output by the interrupt arbitration module, and outputs the arbitration result to the processor core.

[0136] The arbitration interrupt ID result output module is responsible for selecting and outputting the interrupt ID information of the corresponding interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module;

[0137] The arbitration interrupt vector result output module is responsible for selecting and outputting the vector entry of the interrupt service program corresponding to the interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module;

[0138] The arbitration interrupt trigger mode result output module is responsible for selecting and outputting the interrupt trigger mode of the corresponding interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module;

[0139] The arbitration interrupt vectorization mode result output module is responsible for selecting and outputting the hardware vectorization mode of the corresponding interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module;

[0140] The arbitration interrupt level result output module is responsible for selecting and outputting the interrupt level of the corresponding interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module.

[0141] Through the coordination and cooperation of the above-mentioned cross-clock domain synchronization module, interrupt request signal capture module, interrupt register module, interrupt arbitration module, interrupt vector storage module, and arbitration result output module, the interrupt control device can complete the arbitration of interrupt event requests from n interrupt sources within one cycle to obtain the highest interrupt event request with the largest ID, and at the same time output the interrupt ID of the arbitrated interrupt event request, the vector entry of the interrupt service program, the interrupt triggering mode, the interrupt hardware vectorization mode and the interrupt level and other interrupt information to the processor core, thereby completing the entire interrupt arbitration process of the interrupt event requests from n interrupt sources.

[0142] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A processor interrupt control device based on RISC-V architecture, characterized in that: It includes a cross-clock domain synchronization module, an interrupt request signal capture module, an interrupt register module, an interrupt arbitration module, an interrupt vector storage module, and an arbitration result output module; The cross-clock domain synchronization module is used to stably synchronize interrupt request signals from n interrupt sources that are asynchronous or in different clock domains to the clock domain of the interrupt control device; The interrupt request signal capture module is responsible for edge detection or level sampling of n interrupt request signals synchronized from the cross-clock domain synchronization module according to the value of the interrupt trigger mode trig bit field of the interrupt attribute register in the interrupt register module; The interrupt register module is responsible for managing and controlling the interrupt enable state, interrupt wait state, interrupt level, interrupt priority, interrupt trigger mode and interrupt hardware vectorization mode of n interrupt sources; the processor core can read and write the contents of the interrupt register module through the bus; The interrupt arbitration module is responsible for arbitrating interrupt event requests from a number of interrupt sources in the interrupt enable and wait states issued by n interrupt sources. The module can obtain the arbitration result within one cycle. The interrupt enable state, interrupt wait state, interrupt level information, and interrupt priority information required in the arbitration process come from the interrupt register module. The interrupt threshold information required in the arbitration process comes from the interrupt CSR register of the processor core. The interrupt vector storage module stores the entry vectors of the interrupt service program corresponding to n interrupt sources. The n interrupt vector table entries are stored continuously in the interrupt vector storage module starting from the interrupt vector base address and with a step length of four bytes. The processor core extracts the corresponding interrupt vector table entry according to the arbitrated interrupt ID, and then directly jumps to the address to execute the interrupt service program. The processor core can read and write the content in the interrupt vector storage module through the bus; The arbitration result output module selects and outputs the interrupt information of the arbitration interrupt source according to the n-bit one-hot code signal output by the interrupt arbitration module, and outputs the obtained arbitration result to the processor core.

2. A processor interrupt control device based on RISC-V architecture according to claim 1, characterized in that: If the interrupt trigger mode trig bit field of the interrupt attribute register is 00, the interrupt request signal capture module samples the high level from n interrupt request signals, and if the current cycle value is high, the interrupt request signal is captured; If the interrupt trigger mode trig bit field of the interrupt attribute register is 01, the interrupt request signal capture module performs low-level sampling on n interrupt request signals, and if the current cycle value is low, the interrupt request signal is captured; If the interrupt trigger mode trig bit field of the interrupt attribute register is 10, the interrupt request signal capture module performs rising edge detection on n interrupt request signals. When it is detected that the current cycle value is high and the previous clock cycle is low, it means that a rising edge has occurred, and the interrupt request signal is captured; If the interrupt trigger mode trig bit field of the interrupt attribute register is 11, the interrupt request signal capture module performs falling edge detection on n interrupt request signals. When it is detected that the current cycle value is low and the previous clock cycle is high, it means that a falling edge has occurred, and the interrupt request signal is captured; After the interrupt request signal capture module captures the interrupt request signal, the interrupt wait register of the corresponding interrupt source in the interrupt wait register group in the interrupt register module is pulled high.

3. A processor interrupt control device based on RISC-V architecture according to claim 1, characterized in that: The interrupt register module includes an interrupt waiting register group consisting of n 8-bit interrupt waiting registers, an interrupt enable register group consisting of n 8-bit interrupt enable registers, an interrupt attribute register group consisting of n 8-bit interrupt attribute registers and an interrupt control register group consisting of n 8-bit interrupt control registers. Each of the n interrupt sources has a corresponding 8-bit interrupt waiting register, 8-bit interrupt enable register, 8-bit interrupt attribute register and 8-bit interrupt control register.

4. A processor interrupt control device based on RISC-V architecture according to claim 3, characterized in that: Each interrupt waiting register of the interrupt waiting register group indicates whether each interrupt is in an interrupt waiting state. The lowest bit of the interrupt waiting register, namely the interrupt waiting bit ip, is zero, indicating that there is no pending interrupt event. The lowest bit of the interrupt waiting register, namely the interrupt waiting bit ip, is one, indicating that an interrupt request is in a waiting state. After the interrupt request signal capture module captures the interrupt request signal, it will set the corresponding interrupt waiting bit to one until the corresponding interrupt is responded to and cleared after processing.

5. A processor interrupt control device based on RISC-V architecture according to claim 3, characterized in that: Each interrupt enable register in the interrupt enable register group is responsible for controlling whether the interrupt request of the corresponding interrupt source is allowed to enter the interrupt arbitration and triggering process. When the lowest bit of the interrupt enable register, i.e., the interrupt enable bit ie, is one, the interrupt is allowed to be triggered; when the lowest bit of the interrupt enable register, i.e., the interrupt enable bit ie, is zero, even if there is an interrupt event request to be processed, it will be blocked.

6. A processor interrupt control device based on RISC-V architecture according to claim 3, characterized in that: Each interrupt attribute register of the interrupt attribute register group is responsible for controlling the triggering mode and hardware vectorization mode of the interrupt, determining whether the interrupt is edge triggered or level triggered, and whether hardware vectorization is adopted; The lowest bit of the interrupt attribute register, i.e., the interrupt hardware vectorization selection bit hv, is 1, indicating that hardware automatic vectorization is allowed. The hardware can select the corresponding interrupt vector address from the interrupt vector memory according to the interrupt source ID of the arbitration interrupt result. The lowest bit of the interrupt attribute register, i.e., the interrupt hardware vectorization selection bit hv, is zero, indicating that hardware automatic vectorization is not allowed, and the hardware calculates the corresponding interrupt vector address through the interrupt service program; The first and second bits of the interrupt attribute register are the interrupt trigger mode bit field trig. When the interrupt trigger mode bit field trig is 00, the interrupt request signal module captures the high-level interrupt signal. When the high-level interrupt signal is captured, the interrupt wait bit ip of the corresponding interrupt wait register is set to one. When the interrupt trigger mode bit field trig is 01, the interrupt request signal module captures the low-level interrupt signal. When the low-level interrupt signal is captured, the interrupt wait bit ip of the corresponding interrupt wait register is set to one. When the interrupt trigger mode bit field trig is 10, the interrupt request signal module captures the rising edge interrupt signal. When the rising edge interrupt signal is captured, the interrupt wait bit ip of the corresponding interrupt wait register is set to one. When the interrupt trigger mode bit field is 11, the interrupt request signal module captures the falling edge interrupt signal. When the falling edge interrupt signal is captured, the interrupt wait bit ip of the corresponding interrupt wait register is set to one.

7. A processor interrupt control device based on RISC-V architecture according to claim 3, characterized in that: Each interrupt control register in the interrupt control register group is used to set the interrupt level and interrupt priority of the corresponding interrupt source, wherein the high nlbits bit is the interrupt level and the low 8-nlbits bit is the interrupt priority.

8. A processor interrupt control device based on RISC-V architecture according to claim 1, characterized in that: The interrupt arbitration module includes a response interrupt level and priority preprocessing module, a maximum interrupt level and priority solving module, a maximum interrupt request preprocessing module, a maximum interrupt request ID arbitration module, and an interrupt threshold comparison module; The response interrupt level and priority preprocessing module is responsible for expanding the interrupt levels and priorities of n interrupt sources into a one-hot code format and outputting the result to the highest interrupt level and priority solving module; The highest interrupt level and priority solving module obtains the highest interrupt level and priority one-hot code result by solving the one-hot code result of the interrupt levels and priorities of n interrupt sources, and outputs it to the highest interrupt request preprocessing module; The highest interrupt request preprocessing module sets the interrupt source with the highest interrupt level and priority among the n interrupt sources, which is in the interrupt enable and waiting state, to one, and the other positions to zero, to obtain the n-bit one-hot code form result of the highest interrupt request, and outputs it to the highest interrupt request ID arbitration module; The highest interrupt request ID arbitration module is responsible for obtaining the n-bit one-hot code form result of the highest interrupt request with the largest ID from the n-bit one-hot code form results of the highest interrupt request, and outputting it to the interrupt threshold comparison module; The interrupt threshold comparison module is responsible for comparing the interrupt level of the highest interrupt request with the largest ID with the interrupt threshold of the interrupt threshold register from the processor core. If the interrupt level of the highest interrupt request with the largest ID is greater than or equal to the interrupt threshold of the interrupt threshold register, the highest interrupt unique code result with the largest ID is output to the arbitration result output module.

9. A processor interrupt control device based on RISC-V architecture according to claim 1, characterized in that: The arbitration result output module includes an arbitration interrupt ID result output module, an arbitration interrupt vector result output module, an arbitration interrupt trigger mode result output module, an arbitration interrupt vectorization mode result output module, and an arbitration interrupt level result output module; The arbitration interrupt ID result output module is responsible for selecting and outputting the interrupt ID information of the corresponding interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module; The arbitration interrupt vector result output module is responsible for selecting and outputting the vector entry of the interrupt service program corresponding to the interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module; The arbitration interrupt trigger mode result output module is responsible for selecting and outputting the interrupt trigger mode of the corresponding interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module; The arbitration interrupt vectorization mode result output module is responsible for selecting and outputting the hardware vectorization mode of the corresponding interrupt source according to the n-bit highest interrupt unique hot code result with the largest ID output by the interrupt arbitration module; The arbitration interrupt level result output module is responsible for selecting and outputting the interrupt level of the corresponding interrupt source according to the n-bit highest interrupt one-hot code result with the largest ID output by the interrupt arbitration module.

10. A processor interrupt control method based on RISC-V architecture, using a processor interrupt control device based on RISC-V architecture as claimed in any one of claims 1 to 9, characterized in that: The steps include: Step 1, the cross-clock domain synchronization module stably synchronizes the interrupt request signals from the asynchronous or different clock domains of n interrupt sources to the clock domain of the interrupt control device, and outputs the n interrupt request signals after the synchronized clock domain to the interrupt request signal capture module; Step 2, the interrupt request signal capture module performs edge detection or level sampling on n interrupt request signals according to the value of the interrupt trigger mode trig bit field of the interrupt attribute register in the interrupt register module; Step 3, the interrupt arbitration module is responsible for arbitrating the interrupt event requests of several interrupt sources in the interrupt enable and waiting state issued by n interrupt sources; Step 4, the interrupt arbitration module outputs the n-bit highest interrupt one-hot code result with the largest ID to the arbitration result output module; Step 5: The arbitration result output module selects and outputs the interrupt information of the arbitration interrupt source according to the n-bit one-hot code signal output by the interrupt arbitration module, and outputs the arbitration result to the processor core.

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