Central processing unit and I3C controller

Abstract

A central processing unit and an I3C controller are provided. The central processing unit comprises a processing module and an output module. The processing module is used for generating task groups according to execution tasks. The output module is used for outputting the task groups to the I3C controller, so that the I3C controller executes the task groups to complete task execution. The task group comprises a definition word and at least one data byte which are connected in sequence. The definition word comprises a first set byte, a second set byte, a third set byte and a fourth set byte which are sequentially connected and respectively define a first write-in quantity of the first write-in operation, a second write-in quantity of the second write-in operation, a read quantity of the read operation and a third write-in quantity of the third write-in operation. The execution task includes at least one of a first write operation, a second write operation, a read operation, and a third write operation.

Description

Technical Field

[0001] The present invention relates to I3C (Improved Inter-Integrated Circuit) technology, and in particular to a central processing unit, an I3C controller, and a method for generating and executing task groups, which can simplify the processing flow of an I3C controller and reduce the load of a central processing unit. Background Art

[0002] Generally, when designing an I3C controller, multiple combinations of operations can be implemented by sending multiple commands, or complex logic can be directly implemented in the I3C controller. Taking ENTDAA (Enter Dynamic Address Assignment) in the general command as an example, the central processing unit usually splits the ENTDAA task into multiple commands and then sends them to the I3C controller. Summary of the invention

[0003] In an embodiment, a central processing unit includes a processing module and an output module. The processing module is used to generate a task group according to an execution task. The output module is used to output the task group to an I3C controller coupled to the central processing unit, so that the I3C controller executes the task group to complete the execution task. Wherein, the task group includes a definition word and at least one data byte. At least one data byte is sequentially connected to the definition word. The definition word includes a first setting byte, a second setting byte, a third setting byte and a fourth setting byte connected in sequence. The first setting byte defines a first write quantity of a first write operation. The second setting byte defines a second write quantity of a second write operation. The third setting byte defines a read quantity of a read operation. The fourth setting byte defines a third write quantity of a third write operation. The execution task includes at least one of the first write operation, the second write operation, the read operation and the third write operation.

[0004] In an embodiment, an I3C controller includes a receiving module and an execution module. The receiving module is used to receive a task group. The execution module is used to execute the task group to complete the execution task. Wherein, the task group includes a definition word and at least one data byte. The at least one data byte is sequentially connected to the definition word. The definition word includes a first setting byte, a second setting byte, a third setting byte and a fourth setting byte that are sequentially connected. The first setting byte defines a first write quantity of a first write operation. The second setting byte defines a second write quantity of a second write operation. The third setting byte defines a read quantity of a read operation. The fourth setting byte defines a third write quantity of a third write operation. The execution task includes at least one of the first write operation, the second write operation, the read operation and the third write operation.

[0005] In an embodiment, a method for generating a task group includes: generating a definition word according to an execution task, wherein the definition word includes a first setting byte, a second setting byte, a third setting byte and a fourth setting byte connected in sequence, the first setting byte defines a first write quantity of a first write operation, the second setting byte defines a second write quantity of a second write operation, the third setting byte defines a read quantity of a read operation, the fourth setting byte defines a third write quantity of a third write operation, and the execution task includes at least one of the first write operation, the second write operation, the read operation and the third write operation; generating at least one data byte according to the execution task; concatenating at least one data byte after the definition word to generate a task group; and outputting the task group to an I3C controller so that the I3C controller executes the task group to complete the execution task.

[0006] In an embodiment, a method for executing a task group includes: receiving a task group, wherein the task group includes a definition word and at least one data byte, the at least one data byte is sequentially connected to the definition word, the definition word includes a first setting byte, a second setting byte, a third setting byte and a fourth setting byte connected in sequence, the first setting byte defines a first write quantity of a first write operation, the second setting byte defines a second write quantity of a second write operation, the third setting byte defines a read quantity of a read operation, and the fourth setting byte defines a third write quantity of a third write operation; and executing the task group to complete the execution task, wherein the execution task includes at least one of the first write operation, the second write operation, the read operation and the third write operation.

[0007] In summary, the central processing unit, I3C controller, and task grouping generation method and execution method of any embodiment can generate task groups according to the execution task or execute the task groups of the execution task, so that the central processing unit sends the instructions and data required by the I3C controller to complete the execution task to the I3C controller in a single task group at one time, so that the I3C controller completes the execution of the execution task after executing the task group. Therefore, during the process of the I3C controller executing the task group (that is, before completing the execution task), the central processing unit does not need to access the I3C controller again, thereby greatly simplifying the processing flow of the I3C controller and reducing the number of times the central processing unit waits for a reply and accesses the I3C controller (that is, reducing the intervention of the central processing unit) to reduce the load of the central processing unit.

[0008] The detailed features and advantages of the present invention are described in detail in the following embodiments, and the contents are sufficient to enable any person skilled in the relevant art to understand the technical content of the present invention and implement it accordingly. Moreover, according to the contents disclosed in this specification, the scope of the patent application and the drawings, any person skilled in the relevant art can easily understand the relevant purposes and advantages of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A schematic block diagram of an embodiment of a system.

[0010] Figure 2 A schematic diagram of an embodiment of task grouping.

[0011] Figure 3 A flowchart of an embodiment of a method for generating task groups is shown.

[0012] Figure 4 A schematic diagram of an embodiment of task grouping.

[0013] Figure 5 A flowchart of an embodiment of a method for executing task grouping is provided.

[0014] Figure 6 A schematic diagram of an embodiment of task grouping.

[0015] Figure 7 A schematic diagram of an embodiment of task grouping.

[0016] Figure 8 A schematic diagram of an embodiment of task grouping.

[0017] Fig. 9 A schematic diagram of an embodiment of task grouping. DETAILED DESCRIPTION

[0018] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and understandable, a detailed description is given below with reference to the accompanying drawings.

[0019] It should be understood that the word "comprising" used in this specification is used to indicate the existence of specific technical features, values, method steps, operation processing, elements and / or components, but does not exclude the addition of more technical features, values, method steps, operation processing, elements, components, or any combination of the above.

[0020] Figure 1 is a schematic block diagram of an embodiment of the system 100. Figure 1 The system 100 includes a central processing unit 110 and an I3C (Improved Inter-Integrated Circuit) controller 120 , and the central processing unit 110 is coupled to the I3C controller 120 .

[0021] In some embodiments, the system 100 may further include at least one I3C controller 130, an I2C (Inter-Integrated Circuit) controller 140, a memory controller 150, a direct memory access controller (DMAC) 160 or other electronic components. Here, the I3C controller 120 is a master controller, and the I3C controller 130 is a slave controller.

[0022] In some embodiments, the CPU 110, the I3C controller 120, the I3C controller 130, the I2C controller 140, the memory controller 150, and the direct memory access controller 160 may be interconnected via a bus 170 for mutual communication. In addition, the I3C controller 120, the I3C controller 130, and the I2C controller 140 may also be interconnected via an I3C bus 180.

[0023] In some embodiments, the bus 170 may adopt the Advanced Microcontroller Bus Architecture (AMBA) protocol. The bus 170 may be, for example but not limited to, an Advanced Peripheral Bus (APB), an Advanced Extensible Interface (AXI), or an Advanced High-Performance Bus (AHB). The I3C bus 180 includes a serial data (SDA) line and a serial clock (SCL) line. In addition, the central processing unit 110, the I3C controller 120, the I3C controller 130, the I2C controller 140, the memory controller 150, and the direct memory access controller 160 may be, for example but not limited to, an embedded controller (EC), a system on a chip (SoC), a central processing unit (CPU), a microcontroller (MCU), an application specific integrated circuit (ASIC), an application processor (AP), a digital signal processor (DSP), a programmable logic device (PLD), or any other suitable electronic component.

[0024] In some embodiments, the central processing unit 110 includes a processing module 111 and an output module 112. The processing module 111 is coupled to the output module 112, and the output module 112 is coupled to the I3C controller 120. The processing module 111 is used to generate a task group P1 according to the execution task M1, and transmit the task group P1 to the output module 112. The output module 112 is used to output the task group P1 to the I3C controller 120. For example, the task group P1 is transmitted to the I3C controller 120 via the bus 170.

[0025] In some embodiments, the execution task M1 may be written in a programming language, such as, but not limited to, C, C++, Verilog, machine language, or any other applicable programming language.

[0026] In some embodiments, the I3C controller 120 includes a receiving module 121 and an execution module 122. The execution module 122 is coupled to the receiving module 121, and the receiving module 121 can be coupled to the output module 112 of the central processing unit 110 through, for example but not limited to, a bus 170. The receiving module 121 is used to receive a task packet P1 from the central processing unit 110, and transmit the received task packet P1 to the execution module 122. The execution module 122 is used to execute the task packet P1 to complete the execution task M1. Here, the task packet P1 has all the instructions and data required for the I3C controller 120 to complete the execution task M1.

[0027] It is worth noting that in order to clearly illustrate the present invention, Figure 1 For simplified block diagram, only components related to the present invention are shown. Those skilled in the art should understand that the system 100, the central processing unit 110 or the I3C controller 120 may include other components for providing specific functions.

[0028] Figure 2 A schematic diagram of an embodiment of task grouping. Figure 3 FIG. 1 is a flow chart of an embodiment of a method for generating task groups. Figures 1 to 3 The CPU 110 may execute any embodiment of the method for generating the task group P1 to generate and output the task group P1 for executing the task M1 to the I3C controller 120 .

[0029] Specifically, the processing module 111 of the central processing unit 110 performs the following steps: generating a corresponding definition word W0 according to the content of the execution task M1 (step S11), generating at least one corresponding byte (hereinafter referred to as data bytes B1-BN) according to the content of the execution task M1 (step S12), and concatenating at least one data byte B1-BN after the definition word W0 to generate a task group P1 (step S13). Wherein N is a positive integer greater than or equal to 1.

[0030] In some embodiments, in step S11, the processing module 111 of the central processing unit 110 generates a definition word W0 corresponding to the operation setting of the execution task M1. At this time, in step S12, the processing module 111 of the central processing unit 110 generates at least one data byte B1-BN corresponding to the operation content (i.e., instructions and data) of the execution task M1.

[0031] In some embodiments, the CPU 110 may generate at least one data byte B1-BN in a word manner. In other words, the CPU 110 generates at least one data word W1-WM composed of at least one data byte B1-BN in step S12. Where M is a positive integer greater than or equal to 1.

[0032] In some embodiments, the definition word W0 includes a plurality of bytes connected in sequence (hereinafter referred to as setting bytes), and each data word W1-WM and the definition word W0 may have the same number of bytes. In other words, at least one data byte B1-BN is divided into data words W1-WM in sequence with the same number of bytes as the definition word W0. In some embodiments, when the number of at least one data byte B1-BN is not a multiple of the number of bytes of the definition word W0, the last data word WM is composed of data bytes and one or more preset bytes. Each preset byte may have the same or different preset values.

[0033] In some embodiments, each set byte of the definition word W0 represents a specified operation (eg, a write operation or a read operation) and indicates the total number of bytes of instructions and data of the specified operation represented by it.

[0034] In some embodiments, the definition word W0 and the data words W1-WM are serially connected, and each word (i.e., one of W0-WM) is composed of four bytes. For example, the definition word W0 may be composed of four setting bytes B01-B04, the data word W1 may be composed of data bytes B1-B4, the data word W2 may be composed of data bytes B5-B8, and so on. In some embodiments, each of the data bytes B1-BN is composed of 8 bits.

[0035] In some embodiments, the definition word W0 may be composed of four sequentially connected setting bytes B01-B04 (hereinafter referred to as the first setting byte B01, the second setting byte B02, the third setting byte B03 and the fourth setting byte B04). Here, the first setting byte B01, the second setting byte B02, the third setting byte B03 and the fourth setting byte B04 may be arranged in sequence from the lower bit to the higher bit. In some embodiments, each setting byte B01-B04 of the definition word W0 is composed of 8 bits.

[0036] In some embodiments, the first setting byte B01 defines a first write quantity for a first write operation. The second setting byte B02 defines a second write quantity for a second write operation. The third setting byte B03 defines a read quantity for a read operation. The fourth setting byte B04 defines a third write quantity for a third write operation. Specifically, the value represented by the first setting byte B01 (i.e., the first write quantity) indicates how many data bytes in the data bytes B1-BN are used to perform the first write operation. The value represented by the second setting byte B02 (i.e., the second write quantity) indicates how many data bytes in the data bytes B1-BN are used to perform the second write operation. The value represented by the third setting byte B03 (i.e., the read quantity) indicates how many bytes of data to be read by the read operation. The value represented by the fourth setting byte B04 (i.e., the third write quantity) indicates how many data bytes in the data bytes B1-BN are used to perform the third write operation.

[0037] In some embodiments, the value of at least one of the first write quantity, the second write quantity, the read quantity, and the third write quantity is not 0. In other words, executing task M1 includes at least one of the first write operation, the second write operation, the read operation, and the third write operation, so that the I3C controller 120 executes at least one of the first write operation, the second write operation, the read operation, and the third write operation when executing task group P1.

[0038] In some embodiments, the data bytes B1-BN used to perform the first write operation (hereinafter, each data byte may be referred to as the first data byte), the data bytes used to perform the second write operation (hereinafter, each data byte may be referred to as the second data byte), and the data bytes used to perform the third write operation (hereinafter, each data byte may be referred to as the third data byte) will not be overlapped and may be arranged in sequence. In other words, each of the data bytes B1-BN is only used for one of the first write operation, the second write operation, and the third write operation, and the data bytes B1-BN may be composed of the first data byte, the second data byte, and the third data byte arranged in sequence.

[0039] For example, taking the task group P1 including 4 data bytes B1 - B4 as an example, the data bytes B1 - B2 may be first data bytes respectively, the data byte B3 may be the second data byte, and the data byte B4 may be the third data byte.

[0040] In some embodiments, the central processing unit 110 may first generate and temporarily store the definition word W0 and at least one data byte B1-BN one by one, and after the definition word W0 and at least one data byte B1-BN are generated, the at least one data byte B1-BN is sequentially connected to the definition word W0, thereby forming a task group P1. However, the present invention is not limited to this. In other embodiments, the central processing unit 110 may directly generate and serially connect the definition word W0 and at least one data byte B1-BN to form a task group P1.

[0041] Figure 4 A schematic diagram of an embodiment of grouping tasks. Figure 1 and Figure 4 In some embodiments, when the total number of data bytes B1-BN is not a multiple of four, the central processing unit 110 generates additional preset bytes with preset values ​​after the data bytes B1-BN according to the insufficient number, so that the total number of data bytes B1-BN and the preset bytes can become a multiple of four to generate data words W1-WM.

[0042] For example, taking the task group P1 including ten data bytes B1-B10 as an example, the central processing unit 110 will generate two additional preset bytes D1-D2 to generate data words W1-W3 according to the data bytes B1-B10 and the preset bytes D1-D2. Among them, the data word W1 is composed of data bytes B1-B4, the data word W2 is composed of data bytes B5-B8, and the data word W3 is composed of data bytes B9-B10 and the preset bytes D1-D2. In some embodiments, the preset values ​​of the preset bytes D1-D2 can be respectively but not limited to 0 (that is, the preset bytes D1-D2 can be respectively 8'b0). However, the present invention is not limited to this. In other embodiments, the preset values ​​of the preset bytes D1-D2 may be different.

[0043] Return to Reference Figure 1 and Figure 3 In the embodiment of the method for generating task group P1, after the processing module 111 of the central processing unit 110 generates the task group P1 in step S13, the processing module 111 transmits the task group P1 to the output module 112. The output module 112 then transmits the task group P1 to the I3C controller 120 via the bus 170, so that the I3C controller 120 can execute the task group P1 to complete the corresponding execution task M1 (step S14).

[0044] Figure 5 Schematic diagram of a flow chart of an embodiment of a method for executing task grouping. Figure 1 , Figure 2 and Figure 5 The I3C controller 120 may execute any embodiment of the execution method of the task group P1. In the embodiment of the execution method of the task group P1, the I3C controller 120 uses the receiving module 121 to receive the task group P1 from the central processing unit 110 through the bus 170 (step S21). After receiving the task group P1, the receiving module 121 transmits the task group P1 to the execution module 122, so that the execution module 122 executes the task group P1 to complete the corresponding execution task M1 (step S22).

[0045] In some embodiments, after receiving the task group P1, the execution module 122 of the I3C controller 120 first reads the definition word W0 in the task group P1 to respectively know the first write quantity of the first data byte used to perform the first write operation, the second write quantity of the second data byte used to perform the second write operation, the read quantity required to read back for the read operation, and the third write quantity of the third data byte used to perform the third write operation according to the first setting byte B01, the second setting byte B02, the third setting byte B03 and the fourth setting byte B04 in the definition word W0.

[0046] Afterwards, the execution module 122 can sequentially execute a first write operation according to the first data byte of the first write quantity in the data bytes B1-BN, execute a second write operation according to the second data byte of the second write quantity in the data bytes B1-BN, execute a read operation according to the read quantity, and execute a third write operation according to the third data byte of the third write quantity in the data bytes B1-BN to complete the execution task M1.

[0047] In some embodiments, the execution module 122 may automatically send a restart (i.e., a restart condition, usually represented by "Sr") after completing the first write operation and before starting to execute the second write operation, or after completing the read operation and before starting to execute the third write operation. In addition, in some embodiments, the execution module 122 may also automatically send a restart or end (i.e., an end condition, usually represented by "P") after completing the third write operation.

[0048] In some embodiments, the execution task M1 may be a common command in a common command code (CCC) set. In addition, the processing module 111 of the central processing unit 110 may set the first setting byte B01 of the definition word W0 to 0x02 (i.e., the first write quantity is 2), so that when the execution module 122 of the I3C controller 120 executes the task group P1, the I3C controller 120 uses the data bytes B1-B2 in the data bytes B1-BN as the two first data bytes, and performs the first write operation according to the two first data bytes.

[0049] In some embodiments, the first byte of the first data byte (i.e., data byte B1) may include a broadcast address and a write bit, and the second byte of the first data byte (i.e., data byte B2) may include a general command code corresponding to the general command. In some embodiments, when the write bit is a first value, it indicates that a write operation is to be performed. And when the write bit is a second value, it indicates that a read operation is to be performed. In some embodiments, the broadcast address may be 7'h7E. The first value of the write bit may be 0 (i.e., 1'b0), and the second value of the write bit may be 1 (i.e., 1'b1). In addition, the general command code may be one of 0x00 to 0xFE.

[0050] Figure 6 A schematic diagram of an embodiment of grouping tasks. Figure 1 and Figure 6. For example, each word is composed of four bytes, the general command included in the execution task M1 is ENTDAA, and the number of slaves to be assigned addresses is 1. The processing module 111 of the central processing unit 110 can set the first setting byte B01 of the definition word W0 to 0x02 (that is, the first write quantity is 2), set the second setting byte B02 of the definition word W0 to 0x01 (that is, the second write quantity is 1), set the third setting byte B03 of the definition word W0 to 0x08 (that is, the read quantity is 8), and set the fourth setting byte B04 of the definition word W0 to 0x01 (that is, the third write quantity is 1). In addition, the processing module 111 of the central processing unit 110 generates a data word W1, that is, generates data bytes B1-B4. Here, the processing module 111 may set the data byte B1 in the data word W1 to 0xfc (i.e., {7'h7E, 1'b0}), set the data byte B2 in the data word W1 to 0x07 (i.e., the general command code of ENTDAA), set the data byte B3 in the data word W1 to 0xfd (i.e., {7'h7E, 1'b1}), and set the data byte B4 in the data word W1 to 0x47 (i.e., {7'h23, 1'b1}, where 7'h23 indicates that the allocation address assigned to the slave is 0x023). Furthermore, the processing module 111 of the central processing unit 110 concatenates the definition word W0 and the data word W1 and packages them into a task group P1, and then outputs the task group P1 to the I3C controller 120 via the output module 112.

[0051] Therefore, when the execution module 122 of the I3C controller 120 executes the task group P1, the execution module 122 first writes the data bytes B1-B2 in the data word W1 into the corresponding buffer (e.g., a dedicated write buffer) according to the first setting byte B01 of the definition word W0 (i.e., performs the first write operation), and automatically sends a restart after completing the first write operation. Afterwards, the execution module 122 writes the data byte B3 in the data word W1 into the corresponding buffer (e.g., a dedicated write buffer) according to the second setting byte B02 of the definition word W0 (i.e., performs the second write operation). Next, the execution module 122 reads back eight bytes of data from the corresponding buffer (e.g., a dedicated read buffer) according to the third setting byte B03 of the definition word W0 (i.e., performs a read operation). Afterwards, the execution module 122 writes the data byte B4 in the data word W1 into the corresponding buffer (e.g., a dedicated write buffer) according to the fourth setting byte B02 of the definition word W0 (i.e., executes the third write operation), and automatically sends the end after completing the third write operation. At this point, the I3C controller 120 completes the execution task M1 of ENTDAA specifying an allocation address to the slave.

[0052] In this way, the central processing unit 110 only needs to generate a task group P1 including two words (i.e., a definition word W0 and a data word W1) to the I3C controller 120, so that the I3C controller 120 can complete the entire ENTDAA to assign an allocation address to the execution task M1 of the slave, thereby simplifying the processing flow of the I3C controller 120 and reducing the intervention of the central processing unit 110, thereby alleviating the load of the central processing unit 110.

[0053] In some embodiments, the execution task M1 may be a write task. Here, the processing module 111 of the central processing unit 110 may set the third setting byte B03 of the definition word W0 to 0x00 (i.e., the read quantity is 0), so that when the execution module 122 of the I3C controller 120 executes the task group P1, the I3C controller 120 skips the read operation. In addition, the first byte (i.e., data byte B1) of the first data byte of the first write quantity may include a write address (i.e., the assigned address to which the slave is assigned) and a write bit having a first value.

[0054] Figure 7 A schematic diagram of an embodiment of grouping tasks. Figure 1 and Figure 7 . For example, take a write task in which each word is composed of four bytes and the execution task M1 is to write 10 bytes of data (for example, {0xaa998877665544332211}) to a slave whose write address (i.e., assigned address) is 0x23 as an example. The processing module 111 of the central processing unit 110 can set the first setting byte B01 of the definition word W0 to 0x0B (i.e., the first write quantity is 11), and set the second setting byte B02, the third setting byte B03 and the fourth setting byte B04 of the definition word W0 to 0x00 (i.e., the second write quantity, the read quantity and the third write quantity are 0 respectively). In addition, the processing module 111 of the central processing unit 110 generates three data words W1-W3, and after concatenating the definition word W0 and the data words W1-W3 and packaging them into a task group P1, transmits the task group P1 to the output module 112 for output to the I3C controller 120.

[0055] The data word W1 is composed of data bytes B1 - B4 , the data word W2 is composed of data bytes B5 - B8 , and the data word W3 is composed of three data bytes B9 - B11 and a preset byte D1 . Here, the processing module 111 may set the data byte B1 in the data word W1 to {7'h23,1'b0}, the data byte B2 in the data word W1 to 0x11, the data byte B3 in the data word W1 to 0x22, the data byte B4 in the data word W1 to 0x33, the data byte B5 in the data word W2 to 0x44, the data byte B6 in the data word W2 to 0x55, the data byte B7 in the data word W2 to 0x66, the data byte B8 in the data word W2 to 0x77, the data byte B9 in the data word W3 to 0x88, the data byte B10 in the data word W3 to 0x99, and the data byte B11 in the data word W3 to 0xaa.

[0056] Therefore, when the execution module 122 of the I3C controller 120 executes the task group P1, the execution module 122 will first write the data bytes B1-B11 in the data words W1-W3 into the corresponding buffer (e.g., a dedicated write buffer) according to the first setting byte B01 of the definition word W0 (i.e., execute the first write operation), and automatically send a restart after completing the first write operation. Afterwards, the execution module 122 will skip the second write operation, the read operation, and the third write operation according to the second setting byte B02, the third setting byte B03, and the fourth setting byte B04 of the definition word W0, and then automatically send an end. At this point, the I3C controller 120 completes this write task (i.e., completes the execution task M1).

[0057] Figure 8 A schematic diagram of an embodiment of grouping tasks. Figure 1 and Figure 8. For another example, each word is composed of four bytes and the execution task M1 is to write 1 byte of data (for example, {0x11}) to a slave whose write address (i.e., assigned address) is 0x23 and write 2 bytes of data (for example, {0xaa99}) to a slave whose write address (i.e., assigned address) is 0x25. The processing module 111 of the central processing unit 110 can set the first setting byte B01 of the definition word W0 to 0x02 (i.e., the first write quantity is 2), set the second setting byte B02 and the third setting byte B03 of the definition word W0 to 0x00 respectively (i.e., the second write quantity and the read quantity are 0 respectively), and set the fourth setting byte B04 of the definition word W0 to 0x03 (i.e., the third write quantity is 3). In addition, the processing module 111 of the CPU 110 generates two data words W1 - W2 , and after concatenating and packaging the definition word W0 and the data words W1 - W2 into a task packet P1 , transmits the task packet P1 to the output module 112 to be output to the I3C controller 120 .

[0058] The data word W1 is composed of data bytes B1-B4, and the data word W2 is composed of 1 data byte B5 and 3 preset bytes D1-D3. Here, the processing module 111 sets the data byte B1 in the data word W1 to {7'h23,1'b0}, sets the data byte B2 in the data word W1 to 0x11, sets the data byte B3 in the data word W1 to {7'h25,1'b0}, sets the data byte B4 in the data word W1 to 0x99, and sets the data byte B5 in the data word W2 to 0xaa.

[0059] Therefore, when the execution module 122 of the I3C controller 120 executes the task group P1, the execution module 122 will first write the data bytes B1-B2 in the data word W1 into the corresponding buffer (e.g., a dedicated write buffer) according to the first setting byte B01 of the definition word W0 (i.e., execute the first write operation), and automatically send a restart after completing the first write operation. Then, the execution module 122 will skip the second write operation and the read operation according to the second setting byte B02 and the third setting byte B03 of the definition word W0. After that, the execution module 122 will write the data bytes B3-B4 in the data word W1 and the data byte B5 in the data word W2 into the corresponding buffer (e.g., a dedicated write buffer) according to the fourth setting byte B04 of the definition word W0 (i.e., execute the third write operation), and automatically send an end after completing the third write operation. At this point, the I3C controller 120 completes this write task (i.e., completes the execution task M1).

[0060] In some embodiments, the execution task M1 may be a read task. Here, the processing module 111 of the central processing unit 110 may set the first setting byte B01 and the fourth setting byte B02 of the definition word W0 to 0x00 (i.e., the first write quantity and the third write quantity are 0, respectively), so that when the execution module 122 of the I3C controller 120 executes the task group P1, the I3C controller 120 skips the first write operation and the third write operation. In addition, the second data byte of the second write quantity may include a write instruction. The write instruction includes a write address (i.e., the allocation address to which the slave is assigned) and a write bit having a second value.

[0061] Fig. 9 A schematic diagram of an embodiment of grouping tasks. Figure 1 and Fig. 9 For example, when each word is composed of 4 bytes and the execution task M1 is a reading task of reading 10 bytes of data from a slave whose address (i.e., the assigned address) is 0x23, the processing module 111 of the central processing unit 110 may set the first setting byte B01 of the definition word W0 to 0x00 (i.e., the first write quantity is 0), set the second setting byte B02 of the definition word W0 to 0x01 (i.e., the second write quantity is 1), set the third setting byte B03 of the definition word W0 to 0x0a (i.e., the read quantity is 10), and set the fourth setting byte B04 of the definition word W0 to 0x00 (i.e., the third write quantity is 0). In addition, the processing module 111 of the central processing unit 110 generates a data word W1, and after concatenating the definition word W0 and the data word W1 and packaging them into a task group P1, transmits the task group P1 to the output module 112 to output to the I3C controller 120. The data word W1 is composed of a data byte B1 and three preset bytes D1-D3. Here, the processing module 111 may set the data byte B1 in the data word W1 to 0x47 (i.e., {7'h23, 1'b1}, where 7'h23 indicates that the write address is 0x23, and 1'b1 indicates a write bit with a second value).

[0062] Therefore, when the execution module 122 of the I3C controller 120 executes the task group P1, the execution module 122 will first skip the first write operation according to the first setting byte B01 of the definition word W0. Then it automatically sends a restart. After that, the execution module 122 writes the data byte B1 in the data word W1 into the corresponding buffer (for example, a dedicated write buffer) according to the second setting byte B02 of the definition word W0 (that is, performs the second write operation). Then, the execution module 122 reads back 10 bytes of data from the slave with the assigned address of 0x23 according to the third setting byte B03 of the definition word W0 (that is, performs a read operation). After that, the execution module 122 skips the third write operation according to the fourth setting byte B02 of the definition word W0, and automatically sends the end. At this point, the I3C controller 120 completes this read task (that is, completes the execution task M1).

[0063] In summary, the central processing unit 110, the I3C controller 120, and the task group generation method and execution method of any embodiment can generate a task group P1 according to the execution task M1 or execute the task group P1 of this execution task M1, so that the central processing unit 110 sends the instructions and data required by the I3C controller 120 to complete the execution task M1 to the I3C controller 120 at one time in a single task group P1, so that the I3C controller 120 completes the execution task M1 after executing this task group P1. Therefore, during the process of the I3C controller 120 executing this task group P1 (that is, before completing the execution task M1), the central processing unit 110 does not need to access the I3C controller 120 again, thereby greatly simplifying the processing flow of the I3C controller 120, and reducing the number of times the central processing unit 110 waits for a reply and accesses the I3C controller 120 (that is, reducing the intervention of the central processing unit 110), so as to reduce the load of the central processing unit 110.

[0064] Although the technical content of the present invention has been disclosed as above in the form of preferred embodiments, it is not intended to limit the present invention. Slight changes and modifications made by those skilled in the art without departing from the spirit of the present invention should all be included in the scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the attached patent application.

[0065]

Explanation of symbols

[0066] 100: System

[0067] 110: Central Processing Unit

[0068] 111: Processing module

[0069] 112: Output module

[0070] 120: I3C controller

[0071] 121: Receiving module

[0072] 122: Execution module

[0073] 130: I3C controller

[0074] 140: I2C controller

[0075] 150: Memory controller

[0076] 160: Direct Memory Access Controller

[0077] 170: Bus

[0078] 180: I3C bus

[0079] B1~BN:Data Byte

[0080] B01~B04: Setting Byte

[0081] D1~D3: Preset Byte

[0082] M1: Execute the mission

[0083] P1: Task Grouping

[0084] W0: Definition word

[0085] W1-WM: Data word

[0086] S11-S14: Steps

[0087] S21-S22: Steps

Claims

1. A central processing unit, comprising: a processing module, configured to generate a task group according to an execution task, wherein the task group includes a definition word and at least one data byte, the at least one data byte is sequentially connected to the definition word, the definition word includes a first setting byte, a second setting byte, a third setting byte and a fourth setting byte that are sequentially connected, the first setting byte defines a first write quantity of a first write operation, the second setting byte defines a second write quantity of a second write operation, the third setting byte defines a read quantity of a read operation, the fourth setting byte defines a third write quantity of a third write operation, and the execution task includes at least one of the first write operation, the second write operation, the read operation and the third write operation; as well as The output module is used for outputting the task group to an I3C controller coupled to the central processing unit, so that the I3C controller executes the task group to complete the execution task.

2. The central processing unit of claim 1 , wherein the first setting byte is used to cause the I3C controller to perform the first write operation according to a first data byte of the first write quantity in the at least one data byte, the second setting byte is used to cause the I3C controller to perform the second write operation according to a second data byte of the second write quantity in the at least one data byte, the third setting byte is used to cause the I3C controller to perform the read operation according to the read quantity, and the fourth setting byte is used to cause the I3C controller to perform the third write operation according to a third data byte of the third write quantity in the at least one data byte. 3 . The central processing unit as claimed in claim 1 , wherein the I3C controller sends a restart after completing the first write operation or the read operation. 4 . The central processing unit as claimed in claim 1 , wherein the I3C controller sends a restart or an end after completing the third write operation.

5. A central processing unit as described in claim 2, wherein when the execution task is a general command, the first write quantity is 2, wherein the first byte in the first data byte of the first write quantity includes a broadcast address and a write bit, and the second byte in the first data byte of the first write quantity includes a general command code corresponding to the general command.

6. The central processing unit of claim 5, wherein when the general command is ENTDAA, the first data byte of the first write quantity includes 0xfc and 0x07 in sequence, the second data byte of the second write quantity includes 0xfd, the read quantity is 8, and the third data byte of the third write quantity includes an allocation address. 7 . The central processing unit as claimed in claim 1 , wherein when the execution task is a write task, the read quantity is 0.

8. The central processing unit of claim 7, wherein a first byte of the first write quantity of first data bytes comprises a write address and a write bit having a first value.

9. A central processing unit as described in claim 1, wherein when the execution task is a read task, the first write number and the third write number are 0, the read number is greater than 0, and the second data byte of the second write number includes a write instruction, which includes a write address and a write bit with a second value.

10. An I3C controller, comprising: A receiving module, configured to receive a task group, wherein the task group includes a definition word and at least one data byte, the at least one data byte is sequentially connected to the definition word, wherein the definition word includes a first setting byte, a second setting byte, a third setting byte and a fourth setting byte that are sequentially connected, the first setting byte defines a first write quantity of a first write operation, the second setting byte defines a second write quantity of a second write operation, the third setting byte defines a read quantity of a read operation, and the fourth setting byte defines a third write quantity of a third write operation; as well as The execution module is used for executing the task group to complete the execution task, wherein the execution task includes at least one of the first write operation, the second write operation, the read operation and the third write operation.

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