Random hardware fault positioning method and system and storage medium

Abstract

The invention provides a random hardware fault positioning method and system and a storage medium. The method comprises the following steps: screening out a fragile unit from a circuit module of a chip; performing fault detection operation on each fragile unit based on a pre-established test simulation platform to obtain a fault detection result, and establishing a compressed sensing equation based on the fault detection result; and solving the compressed sensing equation, and positioning the fragile unit with the random hardware fault according to a solving result. According to the method, the fragile units are screened out from the microscopic perspective, then fault detection is carried out on the fragile units, the compressed sensing equation is established and solved, and then the fragile units with random hardware faults are positioned, so that the security vulnerabilities existing in the vehicle-gauge-level chip can be revealed by a small number of observation times, and the security vulnerabilities in the vehicle-gauge-level chip can be found out. An accurate evaluation result of the chip function is obtained, and the accuracy and the detection efficiency of chip detection are improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit testing technology, and in particular to a random hardware fault locating method, system and storage medium for automotive-grade chips. Background Art

[0002] The chips currently in use can be divided into military-grade, automotive-grade, industrial-grade and consumer-grade chips based on the level of the industry in which they are used. Automotive-grade chips refer to chips used in automotive control. As the intelligence of automobiles increases, the functional safety of automotive-grade chips is a key core issue in the development of automobiles.

[0003] As automotive-grade chips shift from single-function, large-size to multi-function, highly integrated, small-size, the failure rate of hardware has also increased. However, the current testing of chip functional safety is still at the macro level, and there is a lack of testing methods proposed from the micro perspective of functional safety. Therefore, the goal of accurate assessment cannot be achieved.

[0004] Therefore, the prior art needs to be further improved. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the present invention provides a method, system and storage medium for locating random hardware faults for automotive-grade chips, aiming to overcome the defect in the prior art that the functional safety of automotive-grade chips cannot be accurately tested.

[0006] The technical solution adopted by the present invention to solve the technical problem is as follows:

[0007] In the first aspect, the present application proposes a random hardware fault location method for automotive-grade chips, which includes:

[0008] Analyze the circuit structure of the automotive-grade chip to be tested and extract the circuit modules associated with the preset safety goals;

[0009] Screening out vulnerable units from the circuit module;

[0010] In the random hardware fault detection platform, the automotive-grade chip to be tested is subjected to fault detection operations to obtain the fault detection results of each vulnerable unit, and a compressed sensing equation is established based on the fault detection results;

[0011] The compressed sensing equation is solved, and the vulnerable unit where the random hardware failure occurs is located according to the solution result.

[0012] Optionally, the step of analyzing the circuit structure of the automotive-grade chip to be tested and extracting a circuit module associated with a preset safety target includes:

[0013] Determine the safety goals of the automotive-grade chip to be tested based on the chip type and chip function;

[0014] According to the safety goal, determining the calculation logic of the output signal in the automotive-grade chip to be tested;

[0015] According to the calculation logic of the output signal in the target detection automotive-grade chip, circuit information associated with the safety target is extracted from the circuit of the automotive-grade chip to be tested.

[0016] Optionally, the step of screening out fragile units from the circuit module includes:

[0017] Obtaining event symbols, logic gate symbols, and transfer symbols corresponding to the causal relationship between various events in the circuit module;

[0018] Determine the progressive relationship between logic events according to the event symbols, logic gate symbols and transfer symbols;

[0019] Establish a fault tree model based on the progressive relationship between logical events;

[0020] The vulnerable units in the circuit module are screened out based on the fault tree model.

[0021] Optionally, the step of screening out vulnerable units in the circuit module based on the fault tree model includes:

[0022] The fault tree model is solved by using Boolean operations to determine the minimum cut set of the fault tree model, and the circuit logic unit combination corresponding to the minimum cut set is used as the fragile unit.

[0023] Optionally, the step of performing a fault detection operation on the automotive-grade chip to be tested in the random hardware fault detection platform, obtaining a fault detection result of each vulnerable unit, and establishing a compressed sensing equation based on the fault detection result includes:

[0024] Build a detection platform for random hardware failures;

[0025] Perform fault injection on the automotive-grade chip to be tested on the testing platform, input a preset test vector and a test protocol, and start a test operation on the automotive-grade chip to be tested;

[0026] Obtaining an observation matrix and test results based on the test operation;

[0027] A compressed sensing equation is established according to the observation matrix and the test results.

[0028] Optionally, the step of establishing a compressed sensing equation according to the measurement matrix and the test result includes:

[0029] Generate an observation matrix according to the fault status corresponding to each vulnerable unit in the test results;

[0030] According to the observation matrix sequence obtained from multiple test results, the compressed sensing equation is established.

[0031] Optionally, the step of solving the compressed sensing equation and locating the vulnerable unit where the random hardware failure occurs according to the solution result includes:

[0032] The convex optimization method is used to solve the compressed sensing equation and obtain the sparse signal solution of the compressed sensing equation;

[0033] Determine whether a corresponding fragile unit has issued a random hardware fault according to a value corresponding to the sparse signal solution, and obtain a random hardware fault determination result;

[0034] The vulnerable unit where the fault occurs is located according to the random hardware fault determination results.

[0035] Optionally, after the step of solving the compressed sensing equation and locating the vulnerable unit where the random hardware failure occurs according to the solution result, the method further includes:

[0036] Analyze the random hardware fault determination results to identify the vulnerable units corresponding to permanent faults and the vulnerable units corresponding to transient faults;

[0037] The fragile units corresponding to permanent faults are removed from the random hardware fault judgment results to obtain the fragile units corresponding to transient faults.

[0038] In a second aspect, the present application provides a random hardware fault location system for automotive-grade chips, which includes:

[0039] The circuit analysis module is used to analyze the circuit structure of the automotive-grade chip to be tested and extract the circuit modules associated with the preset safety goals;

[0040] A vulnerable point screening module, used to screen out vulnerable units from the circuit module;

[0041] The test module is used to perform fault detection operations on the automotive-grade chip to be tested in the random hardware fault detection platform, obtain the fault detection results of each vulnerable unit, and establish a compressed sensing equation based on the fault detection results;

[0042] The fault point location module is used to solve the compressed sensing equation and locate the vulnerable unit where the random hardware failure occurs according to the solution result.

[0043] In the third aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more computer-readable programs, and the one or more computer-readable programs can be executed by one or more processors. When the computer-readable program is executed by the processor, the hardware fault location method for automotive-grade chips is implemented.

[0044] Beneficial effect: The present invention provides a method, system and storage medium for locating random hardware faults for automotive-grade chips. By analyzing the circuit structure of the automotive-grade chip to be tested, the circuit module associated with the preset safety target is extracted; the vulnerable unit is screened out from the circuit module; a fault detection operation is performed on the automotive-grade chip to be tested in the detection platform of random hardware faults to obtain the fault detection results of each vulnerable unit, and a compressed sensing equation is established based on the fault detection results, the compressed sensing equation is solved, and the vulnerable unit where the random hardware fault occurs is located according to the solution result. The present application starts from a microscopic perspective to first screen out the vulnerable units in the circuit module, and then perform fault detection on each vulnerable unit, and locates the vulnerable unit where the random hardware fault occurs based on the fault detection results. Therefore, the method of the present application can locate the security vulnerabilities existing inside the automotive-grade chip through a small number of observations, realize accurate evaluation of chip functions, and improve the accuracy and efficiency of chip detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a flowchart of the steps of a random hardware fault locating method for automotive-grade chips provided by an embodiment of the present invention;

[0046] Figure 2 is a schematic diagram of the relationship between incoherent observation and compressed sensing equation in an embodiment of the present invention;

[0047] Figure 3 is a schematic diagram of the principle of a random hardware fault detection system in an embodiment of the present invention;

[0048] Figure 4 It is a schematic diagram of the random hardware fault location result of the MCU chip in an embodiment of the present invention;

[0049] Figure 5 It is a principle structure block diagram of the random hardware fault locating system in an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the present invention clearer and more specific, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0051] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0052] With the rapid development of intelligent connected vehicles at home and abroad, the functional safety of automotive-grade chips has become a key issue in the development of intelligent connected vehicles. Since automotive-grade chips need to work under diverse pressures and dynamic environments, the temperature range can be as wide as -40 to 155°C, high vibration, dust, radiation, electromagnetic interference, etc. In addition, personal safety issues are also involved. Automotive chips have higher requirements for reliability and safety, and the general design life is 10 to 15 years. Therefore, automotive-grade chips must meet the requirements of reliability, consistency and stability. As automotive-grade chips change from traditional large size and single function to small size, high integration, high computing power and multi-function, the random hardware failure rate of automotive-grade chips has also increased, and functional safety issues are also in urgent need of improvement.

[0053] Functional safety of automotive-grade chips means that chips used in automotive electronic systems must strictly comply with a series of functional safety standards and specifications to ensure that even when random hardware failures occur inside the chip, they can still stably and reliably perform the corresponding functions, thereby effectively preventing accidents or potential dangers caused by failures. Functional safety standards and requirements usually include specifications for chip design, development, testing, and verification processes to ensure that the chip takes into account various potential failure conditions during the design phase and can maintain a high degree of reliability and safety in actual use. In order to ensure the safety of vehicle electronic systems, the international functional safety standard ISO 26262: Road vehicles—Functional safety and the national standard GB / T 34590 functional safety standard "Road vehicles—Functional safety" came into being, which clearly include chip analysis and testing requirements.

[0054] The functional safety of chips is mainly based on failures. Chip failures are mainly divided into systematic failures and random hardware failures. Among them, systematic failures refer to failures that cannot be predicted during the life cycle of the chip, and are the focus of chip functional safety analysis. Random hardware failures refer to unexpected and random hardware failures caused by factors such as physical processes or environmental stress during the hardware life cycle. The time of occurrence of this failure cannot be predicted, but it follows a certain probability distribution, such as exponential distribution. Random hardware failures are usually caused by a variety of degradation mechanisms, such as component aging, fatigue, physical degradation, and external environmental stress. Random hardware failures are mainly divided into two categories: permanent failures and transient failures. Permanent failures are usually caused by chip manufacturing process problems and physical processes, such as open circuits, short circuits, etc. Transient failures are usually caused by the chip's own packaging materials or environmental factors, such as single event effects (SEE) induced by high-energy radiation particles in the driving environment of the car, which cause bit flips. Random hardware failures are the root cause of functional safety failures in chips. Efficient security vulnerability detection methods will help identify negligence or weak links in chip functional safety design, which is of great significance for targeted security mechanism optimization and accurate and objective security assessment.

[0055] In order to accurately locate random hardware failures that may occur in automotive-grade chips, the present application provides a random fault location method, which first analyzes the circuit structure of the automotive-grade chip to be tested, maps the chip's security goals to the signals transmitted in the circuit module, screens out vulnerable units where random hardware failures may occur, injects faults into each vulnerable unit, establishes a compressed sensing equation based on the detection results, and locates the vulnerable units corresponding to the random hardware failures according to the calculation results of the compressed sensing equation, thereby evaluating the security vulnerabilities inside the chip from a microscopic perspective, providing technical support for the optimization of the chip structure and the accurate evaluation of the chip function.

[0056] The embodiments of the present invention are further described below in conjunction with the accompanying drawings.

[0057] In the first aspect, this embodiment proposes a random hardware fault location method for automotive-grade chips, such as Figure 1 ,include:

[0058] Step S1: Analyze the circuit structure of the automotive-grade chip to be tested and extract the circuit modules associated with the preset safety goals.

[0059] For the automotive-grade chip to be tested, its circuit structure is obtained and analyzed to extract the circuit modules related to the preset safety goals.

[0060] Specifically, the method of obtaining the circuit structure of the automotive-grade chip may include: searching for the product model of the automotive-grade chip to be tested, and searching for relevant information based on the product model, for example: searching for technical documents related to the automotive-grade chip from the official website of the chip manufacturer, and the technical documents contain detailed information related to the circuit structure of the chip, or browsing technical analysis, evaluation articles or related materials related to the automotive-grade chip on professional websites to obtain relevant information on the circuit structure of the automotive-grade chip. The detailed circuit structure of the chip can also be obtained by studying the circuit diagram of the automotive-grade chip and understanding the connection method and signal transmission path between the various components.

[0061] In detail, this step includes:

[0062] Step S11: Determine the safety target of the automotive-grade chip to be tested based on the chip type and chip function.

[0063] First, we need to have a detailed understanding of the type and function of the automotive-grade chip to be tested, and clarify the chip type and chip function of the automotive-grade chip. For example, the chip type of the automotive-grade chip can be computing and control chips (such as MCU chips and SOC chips), power chips (such as MOSFET chips and IGBT chips), sensor chips, or storage chips, positioning chips, etc. The functions of the chip include: data processing, storage, control, communication or perception functions.

[0064] Because automotive-grade chips need to have failure risks under extreme temperature ranges, high vibrations, and high magnetic fields. Failure risks may include: system failures, data leakage, etc., which pose threats to the safety and stability of the vehicle. Therefore, based on the type and functional characteristics of the automotive-grade chip to be tested, the possible risks of the chip in specific applications are analyzed, and the risk level is evaluated, and then the functional safety goals are determined based on the possible risks and risk levels. The safety goal can be to determine the safety integrity level, and the safety integrity level reflects the safety importance of the chip in the system. The safety goal can also be reflected by customizing safety function requirements. Safety function requirements can be: chip fault detection and response capabilities, data protection capabilities, and redundant design requirements. Determine the safety goal based on the above requirements for safety integrity levels and / or safety function requirements.

[0065] Specifically, the safety goal can be determined to be any level from ASIL-A to ASIL-D in the safety integrity level, or the safety function requirement can be the data protection capability to meet the specified requirements. In the specific implementation, the failure problem that violates the safety purpose in the circuit is regarded as the top event, and the transient fault that causes the event is regarded as the bottom event.

[0066] Step S12: Determine the calculation logic of the output signal in the automotive-grade chip to be tested according to the safety goal.

[0067] According to the determined safety goals, the calculation logic is determined from the signals output by each component in the circuit corresponding to the automotive-grade chip to be tested. Since there is a logical relationship between the signals output by each circuit module in the automotive-grade chip, it is possible to start from the top event and analyze from top to bottom, representing the previous level event with the next level until the bottom-level circuit logic is analyzed.

[0068] Step S13: according to the calculation logic of the output signal in the target detection automotive-grade chip, extract the circuit information associated with the safety target from the circuit of the automotive-grade chip to be tested.

[0069] According to the calculation logic of the output signal in the circuit, the circuit module related to the safety target is extracted from the overall circuit of the chip to obtain the circuit structure related to the top event. Since the circuit structure of the automotive-grade chip contains a part of the circuit structure that is not related to the preset safety target, in this step, the circuit information related to the set safety target can be extracted from the circuit structure based on the calculation logic of the output signal in the chip.

[0070] Step S2: Screen out fragile units from the circuit module.

[0071] Screen out vulnerable units that may fail from the extracted circuit modules. Specifically, vulnerable units refer to those logical units that are propagative in a faulty state and will directly violate the chip safety goals once a fault occurs. These units are potential threats to chip functional safety and the root cause of security vulnerabilities in the chip. Vulnerable units are based on the logical implementation level of the chip, rather than the physical circuit layout or the physical characteristics of the components themselves. From the microscopic perspective of the circuit, not all faults in the circuit will cause chip failure, and not all failures are related to vehicle safety. Whether a circuit unit is considered a vulnerable unit is closely related to its specific functional implementation, which is mainly reflected in two aspects: first, analyze whether the fault effect of the logical unit will be shielded by other logical units or system-level designs when a fault occurs, thereby avoiding fault propagation; second, evaluate whether the circuit failure caused by the unit fault is directly related to safety, that is, whether it violates the preset safety goals. Vulnerable units are the focus of testing, so identifying them in the analysis phase can achieve better testing results.

[0072] Specifically, this step includes:

[0073] Step S21: Acquire event symbols, logic gate symbols, and transfer symbols corresponding to the causal relationships between various events in the circuit module.

[0074] According to the logical relationship between the output signals of each component in the circuit module, the causal relationship between each event in the circuit module is obtained, and then the corresponding event symbol, logic gate symbol and transfer symbol are determined according to the causal relationship between each event. Event symbols are used to represent events or states occurring in the circuit. Logic gate symbols are basic elements in digital circuits and are used to represent logical operation relationships. Transfer symbols are used to represent state transfer relationships in state machines or sequential circuits.

[0075] Step S22: Determine the progressive relationship between logic events according to the event symbols, logic gate symbols and transfer symbols.

[0076] The event symbols, logic gate symbols and transfer symbols determined according to the above steps can determine the progressive relationship between logic events.

[0077] Step S23: Establish a fault tree model according to the progressive relationship between logical events.

[0078] A fault tree model is established based on the progressive relationship between logical events. Since Fault Tree Analysis (FTA) is an inverted tree-like logical causal relationship diagram, which describes the causal relationship between various events in the system through event symbols, logic gate symbols, and transfer symbols, the fault tree model can be used to reflect the fault mechanism in the chip. In the fault tree model, the event that violates the safety goal in the chip is the top event, and the vulnerable unit is the bottom event. Random hardware faults are located by finding the vulnerable units in the system that may cause violations of the safety goal.

[0079] Step S24: Screen out vulnerable units in the circuit module based on the fault tree model.

[0080] The fault tree model established in the above steps is calculated, and the fragile units in the circuit module are screened out based on the calculation results. In one implementation, the fault tree model is solved by Boolean operations to determine the minimum cut set of the fault tree model, and the combination of circuit logic units corresponding to the minimum cut set is used as the fragile unit. Since the minimum cut set of the fault tree is found by calculation, the simplest combination of the top event occurrence logic unit is determined, and the set of these simplest combinations is the fragile unit, thereby screening out the fragile units in the circuit module.

[0081] Step S3: performing a fault detection operation on each of the fragile units based on a pre-established test simulation platform to obtain a fault detection result, and establishing a compressed sensing equation based on the fault detection result.

[0082] After screening out the vulnerable units, the chip is subjected to fault detection operations using a test simulation platform, and a compressed sensing equation is established based on the test results.

[0083] Since any given matrix has a large incoherence with the random matrix, the random matrix can be used as the observation matrix to collect data in the compressed sensing technology. The random Gaussian matrix, random Bernoulli matrix and some Fourier matrices satisfy the isometry constraint.

[0084] In this embodiment, an incoherent observation model of a fragile unit is first established. The physical meaning of a mapping signal is defined in the incoherent observation model. The mapping signal includes: a signal to be measured, an observation matrix and an observation signal.

[0085] The signal to be tested is represented as X, where X is the fault state of the fragile unit inside the chip to be tested, and X is If x j =1, indicating that the vulnerable unit is a faulty unit, i.e., a security vulnerability unit. If x j =0, indicating that the fragile unit C j It is not a faulty unit, that is, the vulnerable unit is safe.

[0086] The observation matrix Φ: The elements of Φ are denoted by a ij (i∈1,2,LM,j∈1,2,LN), i represents the i-th observation, j represents the j-th vulnerable unit tested. If the coefficient a corresponding to the observation matrix ij =1, it means that the fragile unit is observed and its fault status is counted in the i-th observation result; if the coefficient a of the observation matrix ij =0, it means that this unit is not observed and its fault status will not be reflected in the i-th observation result.

[0087] Observation signal Y: Y is a column vector whose element y i (i∈1,2,...,M) represents the total number of faults corresponding to each incoherent observation, which is obtained by scanning the test results.

[0088] Since the measured signal represents the fault state of the logic unit, the measured signal x j Is a discrete signal with a 0-1 distribution, the test result y i is an integer greater than or equal to 0. The meaning of the observation matrix is ​​whether the fragile unit is observed, so the coefficients in the observation matrix are integers distributed between 0 and 1. According to the above analysis, the Bernoulli random matrix distributed between 0 and 1 satisfies the above two constraints. The lower bound of the observation matrix, i.e. the number of observations, needs to be determined by combining theory with data analysis.

[0089] In this embodiment, the concept of random measurement matrix in compressed sensing is transformed into an effective selection of test nodes in the testability design method to generate corresponding incoherent test vectors, such as Figure 2As shown, the result of each observation is used as a set of data test vectors, and the M sets of data of the Mth observation constitute a random sequence of the observation matrix. That is, each row of the observation matrix corresponds to an incoherent observation, and the result of each observation y i represents the total number of faulty units detected in the i-th observation, which can be obtained by analyzing the output test vector, where the coefficient of the incoherent observation matrix Φ is denoted by a ij , i represents the i-th observation, and j represents the j-th observed fragile unit.

[0090] If the coefficient a corresponding to the observation matrix ij =1, it means that the fragile unit is observed in the i-th observation, that is, the test vector set corresponding to this observation needs to include the test vector for testing this unit. Correspondingly, the fault state of this fragile unit will be reflected in the total number of faults y obtained in the i-th random observation i In statistics. On the contrary, if the coefficient a of the observation matrix ij = 0, it means that this fragile unit is not observed in the i-th observation, that is, the test vector set does not need to include the vector for testing this fragile unit. Correspondingly, the fault state of this fragile unit will not be reflected in the total number of faults y obtained in this observation. i In the statistics, as in the compressed sensing imaging technology, the light of this pixel is not included in the measurement value. According to the observation matrix and the M-times observation result y i , a compressed sensing equation Y=ΦX can be established.

[0091] Specifically, this step includes:

[0092] Build a detection platform for random hardware failures; inject faults into the automotive-grade chip to be tested on the detection platform, input preset test vectors and test protocols, and start the test operation on the automotive-grade chip to be tested; obtain an observation matrix and test results based on the test operation; and establish a compressed sensing equation based on the observation matrix and test results.

[0093] Combination Figure 3 As shown in the figure, first you need to build a detection platform for random hardware faults, then inject faults into the chip, observe the test results after fault injection, and establish a compressed sensing equation based on the test results. Uncover and unseal the automotive-grade chip to be tested so that soft faults can be injected. Then place the exposed automotive-grade chip to be tested safely on the compressed sensing observation platform, connect the fault injection equipment, and inject faults into the chip. At the same time, input the preset test vector and test protocol for testing, and finally establish the compressed sensing equation based on the observation matrix and test results.

[0094] Specifically, the step of establishing a compressed sensing equation according to the observation matrix and the test results includes: generating an observation matrix according to the fault state corresponding to each vulnerable unit in the test results; and establishing a compressed sensing equation according to the observation matrix sequence obtained from multiple test results. In this step, M incoherent observations are performed, and M equations can be established, that is, a compressed sensing equation can be obtained.

[0095] Step S4: Solve the compressed sensing equation and locate the vulnerable unit where the random hardware failure occurs according to the solution result.

[0096] In this step, the problem of solving the observed compressed sensing method is the process of locating random hardware faults in the automotive-grade chip to be tested. According to the solution of the compressed sensing equation calculated, the security vulnerability unit that violates the safety goal in the automotive-grade chip to be tested can be identified. Due to the sparsity and incoherence of the observed signal, a convex optimization method with high reconstruction accuracy can be used to solve the compressed sensing equation, thereby locating the random hardware faults that cause the safety goal to fail.

[0097] Specifically, the step of solving the compressed sensing equation and locating the vulnerable unit where the random hardware failure occurs according to the solution result includes:

[0098] The compressed sensing equation is solved by using a convex optimization method to obtain a sparse signal solution of the compressed sensing equation; according to the value corresponding to the sparse signal solution, it is determined whether the corresponding fragile unit has issued a random hardware fault, and a random hardware fault determination result is obtained; according to the random hardware fault determination result, the fragile unit with the fault is located. Solving the compressed sensing equation is to obtain the value of the signal to be tested X. If the value of X is 1, it means that the fragile unit will issue a random hardware fault. If the value of X is 0, it means that the fragile unit will not issue a hardware fault.

[0099] In this embodiment, the safety failure event of abnormal acceleration and deceleration of the MCU chip is taken as an example, and the feasibility of the solution is verified by simulation. The simulation tool uses VCS and the test vector generation tool uses TetraMax TM . Figure 4 The figure shows a random hardware fault location diagram of the MCU chip.

[0100] In order to more accurately locate the vulnerable unit corresponding to the random hardware failure, after the step of solving the compressed sensing equation and locating the vulnerable unit where the random hardware failure occurs according to the solution result, the method further includes:

[0101] Analyze the random hardware fault determination results to identify the vulnerable units corresponding to permanent faults and the vulnerable units corresponding to transient faults;

[0102] The fragile units corresponding to permanent faults are removed from the random hardware fault judgment results to obtain the fragile units corresponding to transient faults.

[0103] Since the random hardware fault distribution obtained under the fault injection environment includes the contribution of both permanent faults and transient faults, in order to further refine the distinction, it is necessary to test it under the condition of no fault injection using the same observation method to obtain only permanent faults. By removing permanent faults from the total random hardware fault distribution, transient faults can be accurately identified, providing solid data support and improvement direction for subsequent chip design and safety protection strategies.

[0104] The method disclosed in this embodiment establishes a fault tree model based on the possible failure modes in the automotive-grade chip, and analyzes and locates the cause of the failure in the chip based on the fault tree model.

[0105] First, according to the type and main functions of the chip, the chip's safety goals and top events (safety hazards that may be caused by the failure of the chip) are determined. Failure problems in the circuit that violate the safety goals are regarded as top events, and transient faults that cause top events are regarded as bottom events.

[0106] Secondly, analyze the circuit structure of the automotive-grade chip to be tested, and extract the circuit modules that are only related to the determined safety goals from the entire circuit of the chip.

[0107] Next, the output signal of the extracted circuit module is analyzed to establish a fault tree model. When analyzing the output signal, based on the logical relationship between the output signal and each circuit module in the circuit, starting from the top event, the previous level event is represented by the next level event from top to bottom until it is decomposed to the bottom level circuit logic unit.

[0108] Finally, an incoherent observation model of the vulnerable unit is established, and a compressed sensing equation is established based on the incoherent observation model. The vulnerable unit corresponding to the random hardware failure is located by solving the problem based on the compressed sensing method.

[0109] Specifically, the exposed integrated circuit is safely placed on the compressed sensing observation platform, connected to the fault injection device, and the chip is injected with faults. At the same time, the preset test vector and test protocol are input for testing. Finally, the compressed sensing equation can be established based on the observation matrix and the test results obtained. By performing multiple incoherent observations, multiple equations can be established, that is, a compressed sensing equation. By resolving it, random hardware failures that cause the safety goal to fail can be located.

[0110] Based on the above random hardware fault location method, this application also provides a random hardware fault location system for automotive-grade chips, such as Figure 5As shown, the random hardware fault location system includes:

[0111] The circuit analysis module 510 is used to analyze the circuit structure of the automotive-grade chip to be tested and extract the circuit modules associated with the preset safety goals; its function is as described in step S1.

[0112] The vulnerable point screening module 520 is used to screen out vulnerable units from the circuit module; its function is as described in step S2.

[0113] The test module 530 is used to perform fault detection operations on the automotive-grade chip to be tested in the random hardware fault detection platform, obtain the fault detection results of each vulnerable unit, and establish a compressed sensing equation based on the fault detection results; its function is as described in step S3.

[0114] The fault point location module 540 is used to solve the compressed sensing equation and locate the vulnerable unit where the random hardware failure occurs according to the solution result. Its function is as described in step S4.

[0115] Furthermore, the circuit analysis module includes: a safety target determination unit, a signal logic calculation unit and a circuit information extraction unit.

[0116] The safety target determination unit is used to determine the safety target of the automotive-grade chip to be tested based on the chip type and chip function.

[0117] A signal logic calculation unit is used to determine the calculation logic of the output signal in the automotive-grade chip to be tested according to the safety goal.

[0118] The circuit information extraction unit is used to extract circuit information associated with the safety target from the circuit of the automotive-grade chip to be tested according to the calculation logic of the output signal in the target detection automotive-grade chip.

[0119] Furthermore, the vulnerability screening module includes: a symbol information acquisition unit, an event logic analysis unit, a fault tree model building unit and a screening unit.

[0120] A symbol information acquisition unit, used to acquire event symbols, logic gate symbols and transfer symbols corresponding to the causal relationship between various events in the circuit module;

[0121] An event logic analysis unit, used to determine the progressive relationship between logic events according to the event symbols, logic gate symbols and transfer symbols;

[0122] A fault tree model building unit, used to build a fault tree model according to the progressive relationship between logical events;

[0123] A screening unit is used to screen out vulnerable units in a circuit module based on the fault tree model.

[0124] Further, the screening unit includes: a fault tree calculation subunit;

[0125] The fault tree calculation subunit is used to solve the fault tree model by using Boolean operations, determine the minimum cut set of the fault tree model, and use the circuit logic unit combination corresponding to the minimum cut set as the fragile unit.

[0126] Furthermore, the test module includes: a platform building unit, a test operation unit, a test result unit and an equation building unit.

[0127] A platform building unit, used to build a detection platform for random hardware failures;

[0128] The test operation unit is used to inject faults into the automotive-grade chip to be tested on the detection platform, and at the same time input preset test vectors and test protocols to start the test operation on the automotive-grade chip to be tested.

[0129] The test result unit is used to obtain the observation matrix and the test result based on the test operation.

[0130] The equation building unit is used to build a compressed sensing equation according to the observation matrix and the test result.

[0131] Furthermore, the equation construction unit includes: an observation matrix generation subunit and an equation establishment subunit.

[0132] An observation matrix generation subunit is used to generate an observation matrix according to the fault state corresponding to each vulnerable unit in the test result;

[0133] The equation building subunit is used to build a compressed sensing equation based on the observation matrix sequence obtained from multiple test results.

[0134] Furthermore, the fault point location module includes: an equation solving unit, a fault judgment unit and a vulnerable point location unit.

[0135] An equation solving unit, used for solving the compressed sensing equation by using a convex optimization method to obtain a sparse signal solution of the compressed sensing equation;

[0136] A fault judgment unit, used to determine whether a corresponding fragile unit has issued a random hardware fault according to a value corresponding to the sparse signal solution, and obtain a random hardware fault judgment result;

[0137] The vulnerable point location unit is used to locate the vulnerable unit where the fault occurs according to the random hardware fault determination result.

[0138] Optionally, the system further includes: a result analysis unit and a fault screening unit.

[0139] A result analysis unit, used to analyze the random hardware fault determination results and identify the fragile units corresponding to the permanent faults and the fragile units corresponding to the transient faults;

[0140] The fault screening unit is used to remove the fragile units corresponding to the permanent faults from the random hardware fault determination results to obtain the fragile units corresponding to the transient faults.

[0141] Based on the disclosure of the above-mentioned method and system, the present application also provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more computer-readable programs, and the one or more computer-readable programs can be executed by one or more processors. When the computer-readable program is executed by the processor, the hardware fault location method for automotive-grade chips is implemented.

[0142] Existing automotive chip detection methods mostly focus on macro testing, lacking the ability to analyze and reveal security vulnerabilities at the micro level, thus limiting targeted design and accurate safety assessment. Aiming at the problems of insufficient functional safety testing methods for automotive-grade chips and difficulty in locating random hardware faults, the present invention cleverly utilizes the sparse distribution characteristics of faulty units inside the chip, integrates compressed sensing technology and testability technology to construct an incoherent observation model, and performs incoherent observations on vulnerable units inside the chip, thereby revealing the faulty units that affect functional safety inside the chip with a small number of observations, and establishing a new method and new model for functional safety testing of automotive-grade chips.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A random hardware fault location method for automotive-grade chips, characterized in that: include: Analyze the circuit structure of the automotive-grade chip to be tested and extract the circuit modules associated with the preset safety goals; Screening out vulnerable units from the circuit module; In the random hardware fault detection platform, the automotive-grade chip to be tested is subjected to fault detection operations to obtain the fault detection results of each vulnerable unit, and a compressed sensing equation is established based on the fault detection results; The compressed sensing equation is solved, and the vulnerable unit where the random hardware failure occurs is located according to the solution result.

2. The random hardware fault location method for automotive-grade chips according to claim 1 is characterized in that: The step of analyzing the circuit structure of the automotive-grade chip to be tested and extracting the circuit module associated with the preset safety target includes: Determine the safety goals of the automotive-grade chip to be tested based on the chip type and chip function; According to the safety goal, determining the calculation logic of the output signal in the automotive-grade chip to be tested; According to the calculation logic of the output signal in the automotive-grade chip to be tested, circuit information associated with the safety target is extracted from the circuit of the automotive-grade chip to be tested.

3. The random hardware fault location method for automotive-grade chips according to claim 1 is characterized in that: The step of screening out fragile units from the circuit module comprises: Obtaining event symbols, logic gate symbols, and transfer symbols corresponding to the causal relationship between various events in the circuit module; Determine the progressive relationship between logic events according to the event symbols, logic gate symbols and transfer symbols; Establish a fault tree model based on the progressive relationship between logical events; The vulnerable units in the circuit module are screened out based on the fault tree model.

4. The method for locating hardware faults for automotive-grade chips according to claim 3, characterized in that: The step of screening out vulnerable units in the circuit module based on the fault tree model comprises: The fault tree model is solved by using Boolean operations to determine the minimum cut set of the fault tree model, and the circuit logic unit combination corresponding to the minimum cut set is used as the fragile unit.

5. The random hardware fault location method for automotive-grade chips according to claim 1 is characterized in that: The steps of performing a fault detection operation on the automotive-grade chip to be tested in the random hardware fault detection platform, obtaining the fault detection results of each vulnerable unit, and establishing a compressed sensing equation based on the fault detection results include: Build a detection platform for random hardware failures; Perform fault injection on the automotive-grade chip to be tested on the testing platform, input a preset test vector and a test protocol, and start a test operation on the automotive-grade chip to be tested; Obtaining an observation matrix and test results based on the test operation; A compressed sensing equation is established according to the observation matrix and the test results.

6. The random hardware fault location method for automotive-grade chips according to claim 5 is characterized in that: The step of establishing a compressed sensing equation according to the measurement matrix and the test result comprises: Generate an observation matrix according to the fault status corresponding to each vulnerable unit in the test results; According to the observation matrix sequence obtained from multiple test results, the compressed sensing equation is established.

7. The random hardware fault location method for automotive-grade chips according to claim 1 is characterized in that: The step of solving the compressed sensing equation and locating the vulnerable unit where the random hardware failure occurs according to the solution result comprises: The convex optimization method is used to solve the compressed sensing equation and obtain the sparse signal solution of the compressed sensing equation; Determine whether the corresponding fragile unit has issued a random hardware fault according to the value corresponding to the sparse signal solution, and obtain a random hardware fault determination result; The vulnerable unit where the fault occurs is located according to the random hardware fault determination results.

8. The random hardware fault location method for automotive-grade chips according to claim 7 is characterized in that: After the step of solving the compressed sensing equation and locating the vulnerable unit where the random hardware failure occurs according to the solution result, the method further includes: Analyze the random hardware fault determination results to identify the vulnerable units corresponding to permanent faults and the vulnerable units corresponding to transient faults; The fragile units corresponding to permanent faults are removed from the random hardware fault judgment results to obtain the fragile units corresponding to transient faults.

9. A random hardware fault location system for automotive-grade chips, characterized in that: include: The circuit analysis module is used to analyze the circuit structure of the automotive-grade chip to be tested and extract the circuit modules associated with the preset safety goals; A vulnerable point screening module, used to screen out vulnerable units from the circuit module; The test module is used to perform fault detection operations on the automotive-grade chip to be tested in the random hardware fault detection platform, obtain the fault detection results of each vulnerable unit, and establish a compressed sensing equation based on the fault detection results; The fault point location module is used to solve the compressed sensing equation and locate the vulnerable unit where the random hardware failure occurs according to the solution result.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more computer-readable programs, and the one or more computer-readable programs can be executed by one or more processors. When the computer-readable program is executed by the processor, the random hardware fault locating method for automotive-grade chips as described in any one of claims 1-8 is implemented.

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