Multi-level coverage rate collection system

Abstract

The invention relates to the technical field of chip verification, in particular to a multi-level coverage rate collection system, which determines whether a coverage rate needs to be updated by using other verification modes for a module which does not fully collect the coverage rate through a preset verification duration. The problem that the efficiency of overall chip verification is reduced due to the fact that the coverage rate collection time of the deep module is too long is avoided, and the coverage rate of the current module is updated by selecting a proper verification mode according to the module complexity of the current module and the verification environment complexity of the preset verification environment. Therefore, the flexibility and the reliability of the coverage rate collection of the deep module are improved, the efficiency of the coverage rate collection of the deep module is also effectively improved, the coverage rate of the deep module can be quickly collected, and the efficiency of chip verification is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to a multi-level coverage collection system. Background Art

[0002] In the chip verification scenario, a more complex design to be tested will contain more levels. For modules at a deeper level, if more scenarios need to be involved when collecting coverage, it will be difficult to collect all scenarios due to the deep levels and multiple instantiations. The collected coverage is difficult to meet expectations. For example, the verification of the cache module involves the status of various instructions such as reading data, writing data, and forcing writing to the next level of storage, as well as the status of hits and misses in different ways, resulting in a large number of scenarios that need to be covered in the verification of the cache module.

[0003] To address the above issues, when faced with the situation where full coverage cannot be collected for deep modules, existing methods usually require manual construction of specific stimuli to input into the top-level module of the design to be tested. However, due to the complexity of the design to be tested, manually constructing stimuli to collect coverage for deep modules takes a long time, and it is even difficult to construct effective stimuli, resulting in low chip verification efficiency.

[0004] Therefore, how to quickly collect the coverage of deep modules to improve the efficiency of chip verification has become an urgent problem to be solved. Summary of the invention

[0005] In view of the above technical problems, the technical solution adopted by the present invention is: A multi-level coverage collection system, the system comprising: a design to be verified, a processor and a memory storing a computer program, wherein the design to be verified comprises M modules {a1, a2, ..., a m , …, a M}, a m is the mth module in the design to be verified, where m is an integer in the range [1, M], and a m Corresponding to a m The level b in the design to be verified m , when the computer program is executed by a processor, the following steps are implemented: S101, verifying the design to be verified under a preset verification environment, and recording the coverage rate of each module under a preset verification time.

[0006] S102: When there is at least one module whose corresponding coverage is less than a preset coverage threshold, for any module whose coverage is less than the coverage threshold, if the level to which the current module belongs is greater than the preset level threshold, and the preset verification time satisfies the preset first condition, the module complexity corresponding to the current module is obtained.

[0007] S103: If the module complexity corresponding to the current module is less than a preset first complexity threshold, the coverage of the current module is updated using a first verification method.

[0008] S104: If the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is less than the preset second complexity threshold, the second verification method is used to update the coverage of the current module.

[0009] S105: If the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is greater than or equal to the second complexity threshold, the third verification method is used to update the coverage of the current module.

[0010] Compared with the prior art, the present invention has obvious beneficial effects. By means of the above technical solution, the multi-level coverage collection system provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects: The present invention provides a multi-level coverage collection system, the system comprising: a design to be verified, a processor and a memory storing a computer program, wherein the design to be verified comprises M modules {a1, a2, ..., a m , …, a M}, a m is the mth module in the design to be verified, where m is an integer in the range [1, M], and a m Corresponding to a m The level b in the design to be verified m, when the computer program is executed by the processor, the following steps are implemented: S101, verifying the design to be verified under a preset verification environment, and recording the coverage rate corresponding to each module under a preset verification time, S102, when there is at least one module whose corresponding coverage rate is less than a preset coverage rate threshold, for any module whose coverage rate is less than the coverage rate threshold, if the level to which the current module belongs is greater than the preset level threshold, and the preset verification time satisfies the preset first condition, then the module complexity corresponding to the current module is obtained, S103, if the module complexity corresponding to the current module is less than the preset first complexity threshold, then the coverage rate of the current module is updated using the first verification method, S104, if the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is less than the preset second complexity threshold, then the coverage rate of the current module is updated using the second verification method, S105, if the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is greater than or equal to the second complexity threshold, then the coverage rate of the current module is updated using the third verification method.

[0011] It can be seen that by pre-setting the verification time to determine whether it is necessary to use other verification methods to update the coverage of modules that have not collected full coverage, it is avoided that the coverage collection of deep modules takes too long and causes the efficiency of the overall chip verification to decrease. Moreover, according to the module complexity of the current module and the verification environment complexity of the preset verification environment, a suitable verification method is selected to update the coverage of the current module, thereby improving the flexibility and reliability of deep module coverage collection, and effectively improving the efficiency of deep module coverage collection, so that the coverage of deep modules can be collected quickly, thereby improving the efficiency of chip verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A schematic diagram of a flow chart of a computer program executed by a processor in a multi-level coverage collection system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0015] This embodiment provides a multi-level coverage collection system. Figure 1 , is a flow chart of a computer program executed by a processor in a multi-level coverage collection system provided by an embodiment of the present invention, wherein the system comprises: a design to be verified, a processor, and a memory storing the computer program, wherein the design to be verified comprises M modules {a1, a2, ..., a m , …, a M}, a m is the mth module in the design to be verified, where m is an integer in the range [1, M], and a m Corresponding to a m The level b in the design to be verified m , when the computer program is executed by a processor, the following steps are implemented: S101, verifying the design to be verified under a preset verification environment, and recording the coverage rate of each module under a preset verification time; S102, when there is at least one module whose corresponding coverage is less than a preset coverage threshold, for any module whose coverage is less than the coverage threshold, if the level to which the current module belongs is greater than the preset level threshold and the preset verification time meets the preset first condition, then obtain the module complexity corresponding to the current module; S103, if the module complexity corresponding to the current module is less than a preset first complexity threshold, update the coverage of the current module using a first verification method; S104: if the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is less than the preset second complexity threshold, then the second verification method is used to update the coverage of the current module; S105: If the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is greater than or equal to the second complexity threshold, the third verification method is used to update the coverage of the current module.

[0016] The design to be verified usually includes a top-level module, which may include several second-level modules, and each second-level module may include several third-level modules, and so on.

[0017] The preset verification environment may refer to a comprehensive test system built to ensure the correctness of the chip design, which is intended to verify whether the chip can work according to the expected functional and performance requirements through various stimulus and checking mechanisms. The preset test environment corresponds to the top-level module in the design to be verified.

[0018] The preset verification time may refer to the time from the start time point of the verification of the design to be verified to the preset time point. There may be multiple preset time points. Accordingly, the coverage rate of each module corresponding to each preset verification time may be recorded.

[0019] The coverage rate can be expressed by the ratio of the number of collected scenarios to the number of all expected scenarios. The coverage rate threshold can be used to determine whether the coverage rate collected by the corresponding module meets expectations. Normally, chip verification expects that the coverage rate collected by each module reaches 1, that is, each module can cover all corresponding scenarios.

[0020] The preset first condition can be used to determine whether the verification time of the top-level module is too long, thereby affecting the efficiency of the overall verification process.

[0021] The module complexity can be evaluated through multiple dimensions such as the number of module function points, interactivity between functions, functional scalability, the number of interface signals, interface signal types, complexity of interface protocols, data volume, data type, data storage and access methods, the number of clock domains involved, and the strictness of timing constraints. In this embodiment, the module complexity can be normalized in combination with the module complexity of each module, and the normalization can adopt a min-max normalization method.

[0022] The complexity of the verification environment can be evaluated through multiple dimensions, such as the number of verification components, the type of verification components, the number of stimulus modes, the complexity of stimulus timing, stimulus correlation, the number of checkpoints, the depth and breadth of inspection, the number of inspection methods, the number of configurable parameters, the relationship between configuration parameters, the flexibility and extensibility of configuration, etc. In this embodiment, the complexity of the verification environment can be normalized in combination with the complexity of the verification environments of other known verification environments, and the normalization can also adopt the min-max normalization method.

[0023] Specifically, when the condition that the coverage rate corresponding to at least one module is less than the preset coverage rate threshold is not satisfied, and for any module whose coverage rate is less than the coverage rate threshold, the level to which the module belongs is greater than the preset level threshold, and the preset verification time satisfies the preset first condition, the design to be verified continues to be verified under the preset verification environment.

[0024] In a specific implementation, the preset first condition is: the preset verification time length is greater than a preset verification time length threshold.

[0025] Among them, when the preset verification time is greater than the preset verification time threshold, it may mean that the verification time of the top-level module is too long, which will lead to a decrease in the efficiency of the overall verification process. It can also be considered that it is difficult to update the coverage from the verification of the top-level module.

[0026] In a specific implementation, the preset verification duration corresponds to the verification incentive quantity; Correspondingly, the preset first condition is: the preset verification time is greater than the preset verification time threshold, or the verification incentive quantity corresponding to the preset verification time is greater than the preset incentive quantity threshold.

[0027] Among them, the fact that the number of verification incentives corresponding to the preset verification time is greater than the preset incentive number threshold can also indicate that it is difficult to update the coverage from the verification of the top-level module. In this case, the modules whose coverage does not meet expectations can be independently verified, so that the coverage of such modules can reach expectations more quickly.

[0028] In a specific embodiment, a m Containing several ports, the use of the first verification method to update the coverage of the current module includes: For any port in the current module, a reference signal corresponding to the current port is configured to the current port in a mandatory manner to update the coverage of the current module.

[0029] Among them, if the module complexity corresponding to the current module is less than the preset first complexity threshold, it can be said that the design of the current module is relatively simple, and the current module can be driven by directly forcing the port signal of the current module to collect the missing scenes and improve the coverage of the current module. A group of reference signals corresponding to each port can be used to collect a missing scene.

[0030] Specifically, by forcibly specifying the port signal of the current module to drive the current module, the coverage of the current module can be quickly updated in the preset verification environment. All components in the preset verification environment can be reused, which is more reliable and only one verification database (vdb) needs to be generated.

[0031] In a specific implementation, the updating of the coverage of the current module using the second verification method includes: Constructing a module verification sequencer in the preset verification environment and defining interface components; By means of the module verification sequencer, in the preset verification environment, the reference signal corresponding to each port in the current module is assigned to the interface component; By using the interface component, the reference signal corresponding to each port in the current module is configured to the corresponding port in a mandatory designated manner to update the coverage of the current module.

[0032] Among them, the module verification sequencer can be used to assign the reference signal corresponding to each port in the current module to the interface component, and then through the interface component, the reference signal corresponding to each port in the current module is configured to the corresponding port in a forced manner.

[0033] Specifically, in a scenario where the module complexity is high and the verification environment complexity is low, that is, the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is less than the preset second complexity threshold, the scenario that the current module needs to cover is relatively complex. If the current module needs to cover many scenarios, using the first verification method to verify the current module requires forced designation operations on more ports one by one, and the flexibility and reusability of the verification are poor, which will still lead to a decrease in verification efficiency. Therefore, this embodiment defines an interface component, and through the interface component, the reference signals corresponding to each port in the current module are configured to the corresponding ports in a forced designation manner to avoid driving the current module multiple times. Compared with the first verification method, the second verification method has better reusability and randomness, and better applicability to complex scenarios and multiple scenarios, but the complexity of the verification process will also increase accordingly.

[0034] In a specific implementation, the preset verification environment corresponds to a checker; The use of the third verification method to update the coverage of the current module includes: Constructing a reference verification environment corresponding to the current module, wherein the reference verification environment includes the checker; The current module is verified under the reference verification environment to update the coverage of the current module.

[0035] The reference verification environment is for the verification of the current module. At this time, the current module is equivalent to a new design to be tested. When constructing the reference verification environment, the checker in the verification environment can be reused.

[0036] Specifically, when using the first verification method and the second verification method, the forced specified method may affect the normal functional coverage. For example, if a design error exists in a module and the scenarios of another module cannot be fully collected, the scenarios of the other module can be fully collected through the forced specified method, but it cannot guarantee that the functions of the designed test can be executed normally.

[0037] In addition, the forced designation method requires the addition of some special signal processing. For example, if the input of a module is configured through forced designation, and the module should be provided with input by another module, and the output of the module needs to be returned to the other module, special processing is required in this case, such as forcing the input of the other module to be invalid.

[0038] If the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is greater than or equal to the second complexity threshold, it can be considered that the use of a forced specified method is more likely to affect the normal function of the design to be tested. Therefore, this embodiment adopts the third verification method, that is, to build an independent reference verification environment for the current module. The reference verification environment and the preset verification environment are independent of each other and do not affect each other, so they will not affect the normal function of the design to be tested. Moreover, there is no need to perform additional processing on special signals, and the credibility of the preset verification environment can be fully guaranteed. In addition, it can be intuitively reflected whether the scene is collected through the top-level module or through the current module. The credibility of the coverage is higher, and the subsequent analysis of the design to be tested is more friendly. However, the third verification method requires additional maintenance of the reference verification environment, which increases the workload of the verification personnel, and it is necessary to move the checker, coverage group and other codes in the preset verification environment, which will also bring a certain amount of workload, and it is necessary to ensure the consistency of the reference verification environment and the preset verification environment. In addition, due to the existence of multiple verification environments, multiple verification databases need to be generated accordingly.

[0039] In a specific implementation, the preset verification environment corresponds to a checker; The use of the third verification method to update the coverage of the current module includes: Initialize the temporary level k=2 and obtain the level corresponding to the current module; If the level corresponding to the current module is less than K, determine the temporary module to which the current module belongs, and the level corresponding to the temporary module is k; Constructing a temporary verification environment corresponding to the temporary module, wherein the temporary verification environment includes the checker; Verifying the temporary module under the temporary verification environment to update the coverage of the current module, and recording the temporary coverage of the current module under the temporary verification duration; If the temporary coverage rate is less than the coverage rate threshold and the temporary verification duration satisfies the second preset condition, update k=k+1, and return to execute the step of determining the temporary module to which the current module belongs if the level corresponding to the current module is less than K.

[0040] Among them, directly adopting the method of constructing the reference verification environment corresponding to the current module to verify the current module will sacrifice the authenticity of some scenarios compared with the method of forced designation. However, the test link expects that the simulated scenarios are all real and can occur. Therefore, in this embodiment, the method of layer-by-layer verification is applied to the third verification method to retain the authenticity of the scenario as much as possible. However, this method will further increase the workload of the verification personnel.

[0041] Specifically, the condition for terminating the iteration in this embodiment is that the temporary coverage rate is greater than or equal to the coverage rate threshold. At this time, it indicates that the coverage rate of the current module has met the expectation, or the level corresponding to the current module is equal to K. At this time, it indicates that the reference verification environment corresponding to the current module has been directly constructed.

[0042] In a specific implementation manner, the second preset condition is: The temporary verification duration is greater than the preset temporary duration threshold, where the temporary duration threshold corresponding to the temporary level k = k1 is greater than the temporary duration threshold corresponding to the temporary level k = k2, k1 < k2, and both k1 and k2 are integers within the range of [2, K].

[0043] Among them, when adopting the layer-by-layer verification method, compared with directly verifying the current module, additional module verification may be added. For example, if the current module cannot collect full coverage in the modules at each level to which it belongs, it will obviously affect the overall verification efficiency. Therefore, in this embodiment, different temporary duration thresholds are set for module verification at different levels. The temporary duration threshold corresponding to the temporary level k = k1 is greater than the temporary duration threshold corresponding to the temporary level k = k2, which may mean that the deeper the level, the shorter the temporary duration threshold, so as to reduce the impact of the layer-by-layer verification method on the time-consuming of module verification.

[0044] Specifically, when adopting the layer-by-layer verification method, the implementer can also adjust the verification duration threshold to further reduce the impact of the layer-by-layer verification method on the time-consuming of module verification.

[0045] It can be seen that by presetting the verification duration to determine whether it is necessary to use other verification methods to update the coverage rate for the modules that have not collected full coverage, it avoids the decrease in the overall chip verification efficiency caused by the too long time-consuming of collecting the coverage rate of deep-layer modules. And by the module complexity of the current module and the verification environment complexity of the preset verification environment, the appropriate verification method is selected to update the coverage rate of the current module, thereby improving the flexibility and reliability of collecting the coverage rate of deep-layer modules, and also effectively improving the efficiency of collecting the coverage rate of deep-layer modules, enabling the coverage rate of deep-layer modules to be quickly collected, thus improving the chip verification efficiency.

[0046] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A multi-level coverage collection system, characterized in that: The system comprises: a design to be verified, a processor and a memory storing a computer program, wherein the design to be verified comprises M modules {a1, a2, ..., a m , …, a M }, a m is the mth module in the design to be verified, where m is an integer in the range [1, M], and a m Corresponding to a m The level b in the design to be verified m , when the computer program is executed by a processor, the following steps are implemented: S101, verifying the design to be verified under a preset verification environment, and recording the coverage rate of each module under a preset verification time; S102, when there is at least one module whose corresponding coverage is less than a preset coverage threshold, for any module whose coverage is less than the coverage threshold, if the level to which the current module belongs is greater than the preset level threshold and the preset verification time meets the preset first condition, then obtain the module complexity corresponding to the current module; S103, if the module complexity corresponding to the current module is less than a preset first complexity threshold, update the coverage of the current module using a first verification method; S104: if the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is less than the preset second complexity threshold, then the second verification method is used to update the coverage of the current module; S105: If the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is greater than or equal to the second complexity threshold, the third verification method is used to update the coverage of the current module.

2. The multi-level coverage collection system according to claim 1, characterized in that: The preset first condition is: the preset verification time length is greater than a preset verification time length threshold.

3. The multi-level coverage collection system according to claim 2, characterized in that: The preset verification time length corresponds to the verification incentive amount; Correspondingly, the preset first condition is: the preset verification time is greater than the preset verification time threshold, or the verification incentive quantity corresponding to the preset verification time is greater than the preset incentive quantity threshold.

4. The multi-level coverage collection system according to claim 1, characterized in that: a m Containing several ports, the use of the first verification method to update the coverage of the current module includes: For any port in the current module, a reference signal corresponding to the current port is configured to the current port in a mandatory manner to update the coverage of the current module.

5. The multi-level coverage collection system according to claim 4, characterized in that: The updating of the coverage of the current module by using the second verification method includes: Constructing a module verification sequencer in the preset verification environment and defining interface components; By means of the module verification sequencer, in the preset verification environment, the reference signal corresponding to each port in the current module is assigned to the interface component; By using the interface component, the reference signal corresponding to each port in the current module is configured to the corresponding port in a mandatory designated manner to update the coverage of the current module.

6. The multi-level coverage collection system according to claim 1, characterized in that: The preset verification environment corresponds to a checker; The use of the third verification method to update the coverage of the current module includes: Constructing a reference verification environment corresponding to the current module, wherein the reference verification environment includes the checker; The current module is verified under the reference verification environment to update the coverage of the current module.

7. The multi-level coverage collection system according to claim 1, characterized in that: The preset verification environment corresponds to a checker; The use of the third verification method to update the coverage of the current module includes: Initialize the temporary level k=2 and obtain the level corresponding to the current module; If the level corresponding to the current module is less than K, determine the temporary module to which the current module belongs, and the level corresponding to the temporary module is k; Constructing a temporary verification environment corresponding to the temporary module, wherein the temporary verification environment includes the checker; Verifying the temporary module under the temporary verification environment to update the coverage of the current module, and recording the temporary coverage of the current module under the temporary verification duration; If the temporary coverage rate is less than the coverage rate threshold and the temporary verification duration meets the second preset condition, then update k = k + 1, and return to execute the step of determining the temporary module to which the current module belongs if the level corresponding to the current module is less than K.

8. The multi-level coverage collection system according to claim 7, characterized in that: The second preset condition is: The temporary verification duration is greater than a preset temporary duration threshold, where the temporary duration threshold corresponding to the temporary level k = k1 is greater than the temporary duration threshold corresponding to the temporary level k = k2, k1 < k2, and both k1 and k2 are integers within the range of [2, K].

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