CAN bus semi-physical simulation method and system

Abstract

The invention relates to a CAN bus semi-physical simulation method and system, and belongs to the technical field of simulation and testing of embedded systems. A mode of combining interface physical simulation and processing logic simulation is adopted, semi-physical simulation of the CAN bus is realized, a simulation test environment of a processor consisting of upper computer software and the intelligent target board in a loop is formed, the intelligent target board based on the tight coupling architecture can be used as a target machine prototype of an embedded system, and the simulation test efficiency is improved. And a program running environment is quickly formed. In addition, compared with full-physical hardware testing, the semi-physical simulation testing scheme of the CAN bus supports simulation of terminal equipment and the CAN bus, and testing means are richer and more flexible. Compared with full-digital simulation testing and terminal equipment virtual simulation testing schemes, the semi-physical simulation of the CAN bus can realize external interface configuration through the FPGA technology, hardware fault testing conditions such as an abnormal interface and an abnormal time sequence can be constructed, and the sufficiency of software testing is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of simulation and testing of embedded systems, and in particular relates to a CAN bus semi-physical simulation method and system. Background Art

[0002] Embedded systems are widely used in safety-critical fields such as aerospace and aviation. System testing of embedded software is an important stage of embedded software testing. There are three main types of testing methods: full physical hardware system testing, semi-physical simulation testing of processors in the loop, and full digital virtual simulation testing. Full physical hardware system testing scenarios are real, run fast, and can effectively perform performance testing, but resources are limited, costs are high, and testing methods are not rich, so it is suitable for black box testing. Full digital virtual simulation testing can get rid of hardware dependence, has strong reusability, low cost, and rich testing methods, but has high requirements for CPU virtual simulation technology, especially for high-performance CPUs such as multi-core batch processing, and CPU model support is not very sound. Compared with full physical hardware system testing, semi-physical simulation testing of processors in the loop has relatively rich testing methods, is more realistic than full digital virtual simulation testing, and effectively makes up for the lack of CPU support models for full digital virtual simulation testing.

[0003] CAN bus is one of the most frequently used communication buses in embedded software systems. Therefore, in the embedded software system testing, it is necessary to adapt, transform and simulate the CAN bus. Patent CN202211415744.0 discloses a low-orbit communication satellite CAN bus terminal simulation method and system. The patent provides a CAN bus application layer communication protocol parsing and processing mechanism, and gives the data transmission format of each CAN bus terminal data packet in the simulation system at the application layer, laying the foundation for data communication for terminal device simulation. Patent CN202210796410.6 discloses a CAN bus data simulation system, which consists of a simulation unit, a control unit, a transceiver unit and Ethernet. The simulation unit simulates the data of the terminal device, and the control unit and the transceiver unit adapt to the CAN bus port to realize the virtual simulation of the CAN bus terminal device. Patent CN202310051872.X discloses a method and device for realizing a virtual 1553B bus based on TCPIP. The pure software method simulates the entire CAN bus application layer message distribution and transmission, and does not involve the specific CAN bus protocol.

[0004] The current embedded software testing environment mainly simulates the CAN bus by simulating terminal devices and data, or directly transmitting the application layer communication protocol data that skips the CAN bus. The former is high-cost and low-scalability for embedded software systems that rely on CAN bus hardware; the latter not only requires a lot of modification work for the embedded software being tested, but also fails to test the data transmission function of the CAN bus module. Summary of the invention

[0005] 1. Technical issues to be resolved

[0006] At present, the semi-physical test environment of embedded software system is limited to the simulation of CAN bus terminal equipment, and it depends on CAN bus hardware equipment, and the simulation degree is low. The present invention designs a CAN bus semi-physical simulation method and system for virtual simulation of CAN bus of embedded software system, so as to realize higher-level semi-physical simulation test of embedded software.

[0007] (II) Technical solution

[0008] In order to solve the above technical problems, the present invention provides a CAN bus semi-physical simulation method, which uses FPGA to simulate the behavior of CAN bus interface chip, realizes address mapping from target board to CAN bus interface chip, and simulates the read and write operation of CAN bus interface chip; uses host computer to run CAN bus simulation chip, realizes the connection of virtual terminal device to CAN bus, and simulates CAN bus data transmission function; FPGA simulation CAN bus chip of FPGA and CAN bus simulation chip on host computer realize read and write access mapping of internal registers or memory of CAN bus simulation chip through physical bus; FPGA simulation CAN bus chip includes target board interface mapping logic module, CAN bus simulation logic module, read and write mapping logic module, physical bus logic module, wherein CAN bus simulation logic module includes interface timing logic module, register group, receiving buffer, sending buffer, and register group includes control and status register; host computer includes virtual terminal device, CAN bus simulation chip, read and write mapping logic module, physical bus logic module, and CAN bus simulation chip includes interface management logic module, control register, status register, timing logic module, receiving buffer, and sending buffer;

[0009] The target board receives the data and transmits it to the virtual terminal device. The logic simulation process is as follows:

[0010] (1) The target board interface mapping logic module of the FPGA simulating CAN bus chip realizes the mapping relationship between the target board interface and the CAN bus simulation chip, and sets the chip select base address register and the chip select address mask register;

[0011] (2) The interface timing logic module of the FPGA simulation CAN bus chip cooperates with the interface mapping logic module of the target board to complete the reading and writing of the register group in the CAN bus simulation logic module according to the read and write enable, address and data signals, and simulate the read and write operations of the target board on the CAN bus simulation logic module;

[0012] (3) FPGA simulates the control and status registers of the CAN bus chip to simulate the CAN bus registers. The receive buffer is used to store received data, and the send buffer is used to store sent data.

[0013] (4) FPGA simulates the read-write mapping logic module of the CAN bus chip to realize the mapping between the physical bus logic module and the register group when accessing each other;

[0014] (5) The target board sends data to the FPGA. The FPGA simulates the CAN bus chip to generate an interrupt request to the host computer through the physical bus logic module, and feeds back the start and end addresses of each buffer as the interrupt vector to the host computer;

[0015] (6) The host computer responds to the interrupt and reads the data of the corresponding address through its physical bus logic module according to the offset address of the corresponding register generated by the interrupt;

[0016] (7) The read-write mapping logic module of the host computer is responsible for realizing the address mapping between its physical bus logic module and the CAN bus simulation chip, and writing the read data to the corresponding CAN simulation bus address;

[0017] (8) The control register and status register on the CAN bus simulation chip of the host computer realize CAN bus register simulation, the receiving buffer is used to store received data, and the sending buffer is used to store sent data;

[0018] (9) The CAN bus simulation chip of the host computer detects that the data is written into the receiving buffer, and after the data is written, it is transmitted from the virtual interface to the virtual terminal device.

[0019] Preferably, the CAN bus simulation chip also includes an interface management logic module and a timing logic module; the interface management logic module is used to communicate with the virtual terminal device on the host computer; the timing logic module of the CAN bus simulation chip is used to sort the data stream when outputting data, and to split the data stream whose length exceeds a preset threshold to ensure the correct timing of the transmitted data.

[0020] Preferably, a chip select base address register and a chip select address mask register are set for each chip select generated in the target board interface mapping logic module. The data of the chip select base address register and the chip select address mask register can be written and read by the host computer to complete the address mapping configuration between the target board and the FPGA simulated CAN bus chip.

[0021] Preferably, the CAN bus simulation logic module of the FPGA simulation CAN bus chip simulates the register reading and writing and data sending and receiving behaviors in the BASIC CAN working mode of the CAN bus controller SJA1000, realizes the simulation of the control register, status register, receive buffer and send buffer in the FPGA simulation CAN bus chip, and the interface of the target board interface mapping logic module of the FPGA simulation CAN bus chip corresponds to the target board terminal base address offset 0x0_0000~0x0_001F.

[0022] Preferably, the PCIE bus is set as the physical bus logic module, that is, the physical bus between the FPGA simulated CAN bus chip and the host computer, then the read-write mapping logic module of the FPGA simulated CAN bus chip is responsible for realizing the mapping of the AXI-Lite of the PCIE bus interface IP to the control register and status register access in the FPGA simulated CAN bus chip.

[0023] Preferably, in step (5), the target board performs a write operation on the control register and the status register in the FPGA simulated CAN bus chip, and after the write operation is completed, the CAN bus simulation logic module of the FPGA simulated CAN bus chip generates an interrupt request to the host computer through the physical bus logic module, and feeds back the offset address of the corresponding register generated by the interrupt to the host computer as part of the interrupt vector. In step (6), when the host computer responds to the interrupt, it reads data from the corresponding register and updates it to the corresponding register of the CAN bus simulation chip.

[0024] Preferably, when the target board updates the sending buffer, an interrupt request is not generated temporarily until the target board writes 1 to the 0th bit of the status register, and the interrupt request is generated, and the start and end of the sending buffer are used as the interrupt vector, and the host computer obtains the data in the sending buffer through the MemoryMap read operation; when the CAN bus simulation chip of the host computer sends CAN bus data to the target board, the data in the sending buffer is updated to the receiving buffer through the Memory Map write operation, and the 0th bit of the local status register and the 0th bit of the interrupt register in the status register are updated, and the data of the interrupt register in the status register is also updated to the corresponding register of the FPGA simulation CAN bus chip.

[0025] Preferably, the CAN bus simulation chip is connected to the virtual terminal device to implement the interaction of application layer protocol information through a function interface.

[0026] The present invention also provides a system for implementing the method.

[0027] The invention also provides an application of the method in simulation and testing of embedded systems.

[0028] (III) Beneficial effects

[0029] The present invention adopts a combination of interface physical simulation and processing logic simulation to achieve semi-physical simulation of the CAN bus, forming a processor in-loop simulation test environment composed of host computer software and an intelligent target board. The intelligent target board based on this tightly coupled architecture can be used as a target machine prototype of an embedded system to quickly form a program running environment. In addition, compared with full physical hardware testing, the semi-physical simulation test solution of the CAN bus supports terminal equipment and CAN bus simulation, and the testing methods are richer and more flexible; compared with full digital simulation testing and terminal equipment virtual simulation testing solutions, the semi-physical simulation of the CAN bus can realize external interface configuration through FPGA technology, and can construct hardware fault test conditions such as abnormal interfaces and abnormal timing, thereby improving the adequacy of software testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a structural diagram of the CAN bus semi-physical simulation system of the present invention;

[0031] Figure 2 It is a flow chart of the target board sending data to the virtual terminal device of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.

[0033] The present invention designs a CAN bus semi-physical simulation method and system, which is a virtual simulation method of interface simulation (FPGA) + logic simulation (host computer), FPGA is coupled to a target board, the host computer loads a virtual terminal device, and the FPGA and the host computer are mapped through a physical bus to achieve a higher level of embedded software semi-physical simulation test. The present invention semi-virtualizes the CAN bus: target board (real device) + semi-physical virtual CAN bus + terminal device (virtual device), and the target board and the virtual terminal device of the host computer communicate data through the CAN semi-physical simulation bus.

[0034] This method uses FPGA to simulate the behavior of CAN bus interface chip (docking to target board, receiving access to CAN bus on target board and sending request and data to target board), realizes address mapping from target board to CAN bus interface chip, and simulates read and write operation of CAN bus interface chip; uses host computer to run CAN bus simulation chip, realizes connection of virtual terminal device to CAN bus, and simulates CAN bus data transmission function; FPGA simulation CAN bus chip of FPGA and CAN bus simulation chip on host computer realize read and write access mapping of internal register or memory of CAN bus simulation chip through physical bus, and the specific structure is as follows: Figure 1 As shown, the FPGA simulation CAN bus chip includes the target board interface mapping logic module, CAN bus simulation logic module, read-write mapping logic module, and physical bus logic module, wherein the CAN bus simulation logic module includes the interface timing logic module, register group, receiving buffer, and sending buffer, and the register group includes control and status registers; the host computer includes the virtual terminal device, the CAN bus simulation chip, the read-write mapping logic module, and the physical bus logic module, and the CAN bus simulation chip includes the interface management logic module, control register, status register, timing logic module, receiving buffer, and sending buffer. The interface management logic module is used to communicate with the virtual terminal device on the host computer; the timing logic module is used to sort the data stream when outputting data, and to segment the longer data stream to ensure the correct timing of the transmitted data. The target board transfers the data to the FPGA simulation CAN bus chip → the CAN bus simulation chip on the host computer → the virtual terminal device on the host computer, and the reverse direction is also possible. The FPGA simulation CAN bus interface, the physical bus logic module, and the CAN bus simulation chip constitute the CAN bus semi-physical simulation chip.

[0035] refer to Figure 2 , the target board receives the data and transmits it to the virtual terminal device. The logic simulation process is as follows:

[0036] (1) The target board interface mapping logic module of the FPGA simulating CAN bus chip realizes the mapping relationship between the target board interface and the CAN bus simulation chip, and sets the chip select base address register and the chip select address mask register;

[0037] (2) The interface timing logic module of the FPGA simulation CAN bus chip cooperates with the interface mapping logic module of the target board to complete the reading and writing of the register group in the CAN bus simulation logic module according to the read and write enable, address and data signals, and simulate the read and write operations of the target board on the CAN bus simulation logic module;

[0038] (3) FPGA simulates the control and status registers of the CAN bus chip to simulate the CAN bus registers. The receive buffer is used to store received data, and the send buffer is used to store sent data.

[0039] (4) FPGA simulates the read-write mapping logic module of the CAN bus chip to realize the mapping between the physical bus logic module (i.e., the physical bus interface) and the register group when they access each other;

[0040] (5) When the target board sends data, the FPGA simulates the CAN bus chip to generate an interrupt request to the host computer through the physical bus logic module, and feeds back the start and end addresses of each buffer (receive buffer, send buffer) to the host computer as an interrupt vector;

[0041] (6) The host computer responds to the interrupt and reads the data of the corresponding address through its physical bus logic module according to the CAN bus offset address (accessing the bus through the address and then calculating the offset address: access address - base address = offset address);

[0042] (7) The read-write mapping logic module of the host computer is responsible for realizing the address mapping between its physical bus logic module and the CAN bus simulation chip, and writing the read data to the corresponding CAN simulation bus address;

[0043] (8) The control register and status register on the CAN bus simulation chip of the host computer realize CAN bus register simulation, the receiving buffer is used to store received data, and the sending buffer is used to store sent data;

[0044] (9) The CAN bus simulation chip of the host computer detects that the data is written into the data buffer, and after the data is written, it is transmitted from the virtual interface to the virtual terminal device.

[0045] The virtual terminal device of the host computer uploads data to the target board and the registers are read and written bidirectionally, and the process is similar.

[0046] This embodiment uses the 6713 model of DSP as the target board, the CAN bus controller SJA1000 as the simulation target, and the PCIE bus (physical bus logic module) as the FPGA to simulate the physical bus between the CAN bus chip and the host computer.

[0047] The target board receives the data and transmits it to the virtual terminal device:

[0048] (1) The target board interface mapping logic module realizes the mapping relationship between the DSP's EMIF interface and the FPGA simulated CAN bus chip. The DSP's target board interface mapping logic module sets a chip select base address register and a chip select address mask register for each chip select. The register data can be written and read by the host computer to complete the address mapping configuration between the DSP and the peripheral chip;

[0049] (2) The CAN bus simulation logic module of the FPGA simulation CAN bus chip simulates the register reading and writing and data transmission and reception behavior in the BASIC CAN working mode of the SJA1000, and realizes the simulation of the control register, status register, receive buffer, and send buffer in the FPGA simulation CAN bus chip. The interface of the target board interface mapping logic module of the FPGA simulation CAN bus chip corresponds to the DSP target board terminal base address offset 0x0_0000~0x0_001F;

[0050] (3) The read-write mapping logic module of the FPGA simulation CAN bus chip is responsible for implementing the mapping of the AXI-Lite of the PCIE bus interface IP to the control registers and status registers (registers of the read-write mapping logic module) in the FPGA simulation CAN bus chip;

[0051] (4) Use the PCIE bus to connect the FPGA and the host computer, and then perform the following steps:

[0052] When the DSP target board writes to the control register and status register in the FPGA simulated CAN bus chip, the CAN bus simulation logic of the FPGA simulated CAN bus chip generates an interrupt request to the host computer through the PCIE bus after the write operation is completed, and feeds back the address offset of the register generated by the interrupt to the host computer as part of the interrupt vector. When the host computer responds to the interrupt, it reads data from the corresponding register and updates it to the corresponding register of the CAN bus simulation chip; when the host computer needs to feed back information to the DSP through the control register or status register, the data of the corresponding register in the CAN bus simulation chip is written into the corresponding register of the FPGA simulated CAN bus chip through the Memory Map method of the PCIE bus;

[0053] When the DSP target board updates the send buffer, the PCIE interrupt request is not generated temporarily until the DSP writes 1 to the 0th bit of the status register. The PCIE interrupt request is generated, and the start and end of the send buffer are used as the interrupt vector. The host computer obtains the data in the send buffer through the MemoryMap read operation; when the CAN bus simulation chip of the host computer sends CAN bus data to the target board, the data in the send buffer area is updated to the receive buffer through the Memory Map write operation, and the local status register 0th bit and the interrupt register 0th bit in the status register are updated. At the same time, the data of the interrupt register in the status register is also updated to the corresponding register of the FPGA simulation CAN bus chip;

[0054] (5) The read-write mapping logic module on the host side is responsible for implementing the mapping of the AXI-Lite of the PCIE bus interface IP to the access of the status register or control register on the host side;

[0055] (6) The CAN bus simulation chip simulates the reading and writing of the status register or control register and the sending and receiving of data in the BASIC CAN working mode of SJA1000, realizing the simulation of the status register, control register and storage area;

[0056] (7) The CAN bus simulation chip is connected to the virtual terminal device and the interaction of application layer protocol information is realized through the function interface.

[0057] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A CAN bus semi-physical simulation method, characterized in that: The method utilizes FPGA to simulate the behavior of CAN bus interface chip, realizes address mapping from target board to CAN bus interface chip, and simulates the read and write operation of CAN bus interface chip; utilizes host computer to run CAN bus simulation chip, realizes the connection of virtual terminal device to CAN bus, and simulates the data transmission function of CAN bus; the FPGA simulation CAN bus chip of FPGA and the CAN bus simulation chip on host computer realize the read and write access mapping of internal register or memory of CAN bus simulation chip through physical bus; the FPGA simulation CAN bus chip includes target board interface mapping logic module, CAN bus simulation logic module, read and write mapping logic module, physical bus logic module, wherein the CAN bus simulation logic module includes interface timing logic module, register group, receiving buffer, sending buffer, and the register group includes control and status register; the host computer includes virtual terminal device, CAN bus simulation chip, read and write mapping logic module, physical bus logic module, and the CAN bus simulation chip includes interface management logic module, control register, status register, timing logic module, receiving buffer, and sending buffer; The target board receives the data and transmits it to the virtual terminal device. The logic simulation process is as follows: (1) The target board interface mapping logic module of the FPGA simulating CAN bus chip realizes the mapping relationship between the target board interface and the CAN bus simulation chip, and sets the chip select base address register and the chip select address mask register; (2) The interface timing logic module of the FPGA simulation CAN bus chip cooperates with the interface mapping logic module of the target board to complete the reading and writing of the register group in the CAN bus simulation logic module according to the read and write enable, address and data signals, and simulate the read and write operations of the target board on the CAN bus simulation logic module; (3) FPGA simulates the control and status registers of the CAN bus chip to simulate the CAN bus registers. The receive buffer is used to store received data, and the send buffer is used to store sent data. (4) FPGA simulates the read-write mapping logic module of the CAN bus chip to realize the mapping between the physical bus logic module and the register group when accessing each other; (5) The target board sends data to the FPGA. The FPGA simulates the CAN bus chip to generate an interrupt request to the host computer through the physical bus logic module, and feeds back the start and end addresses of each buffer as the interrupt vector to the host computer; (6) The host computer responds to the interrupt and reads the data of the corresponding address through its physical bus logic module according to the offset address of the corresponding register generated by the interrupt; (7) The read-write mapping logic module of the host computer is responsible for realizing the address mapping between its physical bus logic module and the CAN bus simulation chip, and writing the read data to the corresponding CAN simulation bus address; (8) The control register and status register on the CAN bus simulation chip of the host computer realize CAN bus register simulation, the receiving buffer is used to store received data, and the sending buffer is used to store sent data; (9) The CAN bus simulation chip of the host computer detects that the data is written into the receiving buffer, and after the data is written, it is transmitted from the virtual interface to the virtual terminal device.

2. The method according to claim 1, characterized in that The CAN bus simulation chip also includes an interface management logic module and a timing logic module; the interface management logic module is used to communicate with the virtual terminal device on the host computer; the timing logic module of the CAN bus simulation chip is used to sort the data stream when outputting data, and to segment the data stream whose length exceeds a preset threshold to ensure the correct timing of the transmitted data.

3. The method according to claim 1, characterized in that In the target board interface mapping logic module, a chip select base address register and a chip select address mask register are set for each chip select. The data of the chip select base address register and the chip select address mask register can be written and read by the host computer to complete the address mapping configuration between the target board and the FPGA simulated CAN bus chip.

4. The method according to claim 1, characterized in that The CAN bus simulation logic module of the FPGA simulation CAN bus chip simulates the register reading and writing and data sending and receiving behaviors of the BASIC CAN working mode of the CAN bus controller SJA1000, and realizes the simulation of the control register, status register, receive buffer and send buffer in the FPGA simulation CAN bus chip. The interface of the target board interface mapping logic module of the FPGA simulation CAN bus chip corresponds to the target board terminal base address offset 0x0_0000~0x0_001F.

5. The method according to claim 1, characterized in that set up The PCIE bus is a physical bus logic module, that is, the physical bus between the FPGA simulated CAN bus chip and the host computer. The read-write mapping logic module of the FPGA simulated CAN bus chip is responsible for implementing the mapping of the AXI-Lite of the PCIE bus interface IP to the control registers and status registers in the FPGA simulated CAN bus chip.

6. The method according to claim 1, characterized in that In step (5), the target board performs write operations on the control register and status register in the FPGA simulated CAN bus chip, and after the write operation is completed, the CAN bus simulation logic module of the FPGA simulated CAN bus chip generates an interrupt request to the host computer through the physical bus logic module, and feeds back the offset address of the corresponding register generated by the interrupt to the host computer as part of the interrupt vector. In step (6), when the host computer responds to the interrupt, it reads data from the corresponding register and updates it to the corresponding register of the CAN bus simulation chip.

7. The method according to claim 1, characterized in that When the target board updates the sending buffer, an interrupt request is not generated temporarily until the target board writes 1 to the 0th bit of the status register. The start and end of the sending buffer are used as the interrupt vector, and the host computer obtains the data in the sending buffer through the Memory Map read operation; when the CAN bus simulation chip of the host computer sends CAN bus data to the target board, the data in the sending buffer is updated to the receiving buffer through the Memory Map write operation, and the local status register 0th bit and the interrupt register 0th bit in the status register are updated. At the same time, the data of the interrupt register in the status register is also updated to the corresponding register of the FPGA simulation CAN bus chip.

8. The method according to claim 1, characterized in that The CAN bus simulation chip is connected to the virtual terminal device and the interaction of application layer protocol information is realized through the function interface.

9. A system for implementing the method according to any one of claims 1 to 8.

10. Application of the method according to any one of claims 1 to 8 in simulation and testing of embedded systems.

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