PCIe retimer, PCIe system and electronic device

Abstract

The present invention proposes a PCIe retimer, a PCIe system and an electronic device, wherein a decoding and descrambling unit receives input data of an ingress link connected thereto, performs decoding and descrambling processing, and outputs a decoding and descrambling code stream to a back end; a processing unit determines the path delay skew compensation corresponding to each path according to the output code stream of each decoding and descrambling unit, and transmits the path delay skew compensation to a de-skew unit; a de-skew unit performs de-skew processing on the decoding and descrambling code stream according to the path delay skew compensation, and outputs the de-skewed code stream to a back end; a coding and scrambling unit performs coding and scrambling processing on the received de-skewed code stream, and outputs the coding and scrambling code stream to a back end. When performing the de-skew processing, the delay skew on the entire path is taken into account, the delay skew compensation amount can be reduced, the data transmission delay can be effectively reduced, and the data transmission efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to a PCIe retimer, a PCIe system and an electronic device. Background Art

[0002] In a PCIe system where the root complex (RC) and the end point device (EP) are interconnected, when the PCIe transmission rate is greater than a certain rate, the PCIe signal is severely attenuated through the PCB routing. It is necessary to add a PCIe retimer between the root complex and the end point device to solve the signal attenuation problem.

[0003] A PCIe retimer is added to the PCIe system. The PCIe retimer receives data from the root complex, completes link decoding and descrambling, and then encodes and scrambles the link after de-skew processing, and then sends it to the terminal device through the PCIe Physical Layer (PCIe PHY for short).

[0004] In current PCIe systems, the de-skew process performed in the PCIe retimer will significantly increase system latency, affecting system interaction efficiency. Summary of the invention

[0005] The object of the present invention is to provide a PCIe retimer, a PCIe system and an electronic device to improve the above-mentioned problem.

[0006] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0007] In a first aspect, an embodiment of the present invention provides a PCIe retimer, the PCIe retimer comprising: a de-skew unit, a processing unit, N decoding and descrambling units, and N encoding and scrambling units;

[0008] The input end of the i-th decoding and descrambling unit is connected to the i-th ingress link, the output end of the i-th decoding and descrambling unit is connected to the i-th access end of the processing unit and the i-th input end of the deskewing unit, the i-th output end of the deskewing unit is connected to the input end of the i-th coding and scrambling unit, the output end of the i-th coding and scrambling unit is connected to the i-th egress link, 1≤i≤N, and the processing unit is connected to the deskewing unit;

[0009] The decoding and descrambling unit is used to receive input data from the ingress link connected thereto, perform decoding and descrambling processing, and output a decoded and descrambled code stream to the back end;

[0010] The processing unit is used to determine the path delay skew compensation corresponding to each path according to the output code stream of each decoding and descrambling unit, and transmit the path delay skew compensation to the de-skew unit, wherein the path includes 1 ingress link and 1 egress link;

[0011] The de-skew unit is used to perform de-skew processing on the decoded descrambled code stream according to the path delay skew compensation, and output the de-skewed code stream to the back end;

[0012] The coding and scrambling unit is used to perform coding and scrambling processing on the received de-skewed code stream, and output the coding and scrambling code stream to the back end.

[0013] In the embodiment of the present invention, when performing the de-skew processing, the delay skew on the entire path is taken into consideration, and the delay skew compensation amount can be reduced, which can effectively reduce the data transmission delay and improve the data transmission efficiency.

[0014] Optionally, the PCIe retimer further includes: a first link mapping unit.

[0015] The i-th output end of the de-skewing unit is connected to the i-th input end of the first link mapping unit, the i-th output end of the first link mapping unit is connected to the input end of the i-th coding scrambling unit, and the processing unit is connected to the first link mapping unit.

[0016] The processing unit is used to generate a mapping relationship set according to the output code streams of each decoding and descrambling unit, and transmit the mapping relationship set to the first link mapping unit, wherein the mapping relationship set includes N mapping relationships, the j-th mapping relationship corresponds to the j-th path, the j-th mapping relationship is a mapping relationship between the j-th ingress link and the N+1-j-th egress link sorted according to delay skew, 1≤j≤N.

[0017] The first link mapping unit is used to control the switching of its input end and output end based on the mapping relationship set, so that the input end corresponding to the jth ingress link and the output end corresponding to the N+1-jth egress link are connected, and forward the received de-skewed code stream to the back end.

[0018] It should be understood that the path delay skew of the N paths constructed based on this is more uniform, and the path delay skew compensation can be reduced, thereby reducing communication delay and improving interaction efficiency.

[0019] Optionally, the processing unit includes an inlet recording unit, an inlet sorting unit, an outlet recording unit, an outlet sorting unit and a mapping construction unit;

[0020] The ingress recording unit is connected to the ingress sorting unit, the egress recording unit is connected to the egress sorting unit, and both the ingress sorting unit and the egress sorting unit are connected to the mapping construction unit; the output end of the i-th decoding and descrambling unit is connected to the i-th access end of the ingress recording unit; the mapping construction unit is connected to the first link mapping unit;

[0021] The ingress recording unit is used to determine the delay skew of each ingress link according to the output code stream of each decoding and descrambling unit, and transmit the delay skew of each ingress link to the ingress sorting unit;

[0022] The egress recording unit is used to transmit the delay skew of each egress link to the egress sorting unit;

[0023] The ingress sorting unit is used to sort the delay skew of each ingress link;

[0024] The egress sorting unit is used to sort the delay skew of each egress link;

[0025] When the inlet sorting unit adopts ascending order, the outlet sorting unit adopts descending order; when the inlet sorting unit adopts descending order, the outlet sorting unit adopts ascending order;

[0026] The mapping construction unit is used to construct the jth ingress link in the ingress sorting unit and the jth egress link in the egress sorting unit into a jth mapping relationship, thereby generating the mapping relationship set, and transmitting the mapping relationship set to the first link mapping unit.

[0027] By sorting through the inlet sorting unit and the outlet sorting unit, the mapping relationship can be determined quickly and accurately, the efficiency of path construction can be improved, and the communication speed can be guaranteed.

[0028] Optionally, the processing unit further includes a residual value compensation unit, and the residual value compensation unit is connected to the mapping construction unit and the de-skew unit respectively;

[0029] The residual value compensation unit is used to take the minimum value of the total delay of N paths as the first reference value, wherein the total delay of the jth path is the sum of the delay skew of the ingress link and the delay skew of the egress link in the jth path;

[0030] The residual value compensation unit is used to determine the difference between the total delay of the j-th path and the first reference value as the path delay skew of the j-th path;

[0031] The residual value compensation unit is used to take the maximum value of the path delay skews of the N paths as the second reference value;

[0032] The residual value compensation unit is used to determine the difference between the second reference value and the path delay skew of the j-th path as the path delay skew compensation of the j-th path, and transmit the j-th path information to the de-skew unit, wherein the j-th path information includes the path delay skew compensation of the j-th path and the ingress link identifier in the j-th path.

[0033] Thereby, the delay of the data received by the second device is reduced as much as possible, or even to zero, so as to save the space of the corresponding de-skew buffer.

[0034] In a second aspect, an embodiment of the present invention provides a PCIe system, the PCIe system comprising a first device, a second device and the above-mentioned PCIe retimer;

[0035] The i-th output terminal of the first device is connected to the input terminal of the i-th decoding and descrambling unit through the i-th inlet link, and the i-th input terminal of the second device is connected to the output terminal of the i-th encoding and scrambling unit through the i-th outlet link;

[0036] When the first device is a root complex device, the second device is a terminal device; when the first device is a terminal device, the second device is a root complex device.

[0037] Optionally, when the PCIe retimer includes a first link mapping unit, the second device is provided with a second link mapping unit;

[0038] The i-th input terminal of the second link mapping unit is connected to the i-th egress link;

[0039] The second link mapping unit is used to control its input end and output end to perform reverse switching based on the mapping relationship set, and the reverse switching means that the switching relationship in the second link mapping unit is the reverse of the switching relationship in the first link mapping unit.

[0040] In a third aspect, an embodiment of the present invention provides an electronic device, comprising the above-mentioned PCIe system.

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 This is one of the structural schematic diagrams of the PCIe retimer provided in an embodiment of the present invention.

[0044] Figure 2 A schematic diagram of a pathway provided by an embodiment of the present invention.

[0045] Figure 3 The second structural diagram of the PCIe retimer provided in the embodiment of the present invention.

[0046] Figure 4 A schematic diagram of the structure of a processing unit provided in an embodiment of the present invention.

[0047] In the figure: 10-deskewing unit; 20-processing unit; 21-entry recording unit; 22-entry sorting unit; 23-exit recording unit; 24-exit sorting unit; 25-mapping construction unit; 26-residual value compensation unit; 30-decoding and descrambling unit; 40-coding and scrambling unit; 50-first link mapping unit; 60-first PCIe interface; 70-second PCIe interface. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0049] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0051] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0052] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0053] The embodiment of the present invention provides a PCIe retimer that can adaptively perform deskew processing, reduce system latency, and achieve the purpose of optimal deskew processing. Figure 1 , Figure 1 This is one of the structural schematic diagrams of the PCIe retimer provided in an embodiment of the present invention.

[0054] The PCIe retimer includes a de-skewing unit 10 , a processing unit 20 , N decoding and descrambling units 30 , and N encoding and scrambling units 40 .

[0055] The input end of the i-th decoding and descrambling unit 30 is connected to one end of the i-th inlet link, and the other end of the i-th inlet link is connected to the i-th output end of the first device (not shown in the figure). The output end of the i-th decoding and descrambling unit 30 is connected to the i-th access end of the processing unit 20 and the i-th input end of the deskewing unit 10, the i-th output end of the deskewing unit 10 is connected to the input end of the i-th coding and scrambling unit 40, the output end of the i-th coding and scrambling unit 40 is connected to one end of the i-th outlet link, and the other end of the i-th outlet link is connected to the i-th input end of the second device (not shown in the figure), 1≤i≤N. The processing unit 20 is connected to the deskewing unit 10.

[0056] When the first device is a root complex device (RC for short), the second device is an endpoint device (EP for short); when the first device is an endpoint device, the second device is a root complex device.

[0057] The decoding and descrambling unit 30 is used to receive input data from the ingress link connected thereto, perform decoding and descrambling processing, and output a decoded and descrambled code stream to the back end.

[0058] It should be noted that the i-th decoding and descrambling unit 30 receives the input data of the i-th ingress link and performs decoding and descrambling processing on it to obtain the decoding and descrambling code stream corresponding to the i-th ingress link. The back end of the decoding and descrambling unit 30 includes a deskewing unit 10 and a processing unit 20.

[0059] The processing unit 20 is used to determine the path delay skew compensation corresponding to each path according to the output code stream of each decoding and descrambling unit 30, and transmit the path delay skew compensation to the de-skew unit 10, wherein the path includes 1 ingress link and 1 egress link.

[0060] The path delay skew compensation is related to the delay skew of the ingress link and the delay skew of the egress link in the path. The processing unit 20 can determine the delay skew of the ingress link in each path according to the output code stream of each decoding and descrambling unit 30, and can determine the path delay skew compensation in combination with the delay skew of the corresponding egress link.

[0061] It should be noted that there are N paths in the PCIe retimer, and different paths will not share an ingress link or an egress link. The jth path may include the jth ingress link and the jth egress link sorted by position, where j represents the position sorting number of the link. The jth path may also include the jth ingress link and the N+1-jth egress link sorted by delay skew, where j represents the delay skew sorting number of the link.

[0062] Sorting by position may be but is not limited to sorting from top to bottom or from left to right, and sorting by delay skew may be sorting by delay skew in ascending or descending order.

[0063] Please refer to Figure 2 , Figure 2 Schematic diagram of a path provided by an embodiment of the present invention. Figure 2 As shown, assuming that there are 5 inlet links and 5 outlet links, the inlet links are sorted by position as A1-A2-A3-A4-A5, and the outlet links are sorted by position as B1-B2-B3-B4-B5. When the jth path includes the jth inlet link and the jth outlet link sorted by position, the inlet link A1 and the outlet link B1 form the first path, the inlet link A2 and the outlet link B2 form the second path, and so on, the inlet link A5 and the outlet link B5 form the fifth path.

[0064] like Figure 2As shown, the inlet links are sorted according to the delay skew as A2-A1-A3-A5-A4, that is, the sequence number corresponding to A1 is 2, the sequence number corresponding to A2 is 1, the sequence number corresponding to A3 is 3, the sequence number corresponding to A4 is 5, and the sequence number corresponding to A5 is 4. The outlet links are sorted according to the delay skew as B4-B2-B3-B5-B1, that is, the sequence number corresponding to B1 is 5, the sequence number corresponding to B2 is 2, the sequence number corresponding to B3 is 3, the sequence number corresponding to B4 is 1, and the sequence number corresponding to B5 is 4. It should be noted that the sorting rules of the inlet links here are the same as the sorting rules of the outlet links, and either descending or ascending order can be used. When ascending order is used, the delay skew of A2-A1-A3-A5-A4 increases in sequence, and the delay skew of B4-B2-B3-B5-B1 increases in sequence. When the jth path includes the jth ingress link and the N+1-jth egress link sorted (in ascending or descending order) according to delay skew, the ingress link A2 and the egress link B1 constitute the first path, the ingress link A1 and the egress link B5 constitute the second path, and so on, the ingress link A4 and the egress link B4 constitute the fifth path.

[0065] The de-skew unit 10 is used to perform de-skew processing on the decoded and descrambled code stream according to the path delay skew compensation, and output the de-skewed code stream to the back end.

[0066] The decoded and descrambled code stream on the j-th path is the decoded and descrambled code stream transmitted by the decoding and descrambling unit connected to the ingress link corresponding to the j-th path.

[0067] It should be noted that when the jth path includes the jth ingress link and the jth egress link sorted by position, the jth path corresponds to the jth ingress link, the jth ingress link corresponds to the jth decoding and descrambling unit, and the decoding and descrambling code stream on the jth path is the decoding and descrambling code stream transmitted by the jth decoding and descrambling unit.

[0068] When the jth path includes the jth ingress link and the (N+1-j)th egress link sorted according to the delay skew, the jth path corresponds to the jth ingress link sorted according to the delay skew.

[0069] The rear end of the de-skewing unit 10 is a coding scrambling unit 40, or a first link mapping unit 50 hereinafter.

[0070] The coding and scrambling unit 40 is used to perform coding and scrambling processing on the received de-skewed code stream, and output the coding and scrambling code stream to the back end.

[0071] In the embodiment of the present invention, when performing the de-skew processing, the delay skew on the entire path is taken into consideration, and the delay skew compensation amount can be reduced, which can effectively reduce the data transmission delay and improve the data transmission efficiency.

[0072] On the basis of the above, regarding how to further reduce the delay and improve the communication efficiency, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 3 , Figure 3 The second structural diagram of the PCIe retimer provided in the embodiment of the present invention.

[0073] The PCIe retimer further includes: a first link mapping unit 50 .

[0074] The i-th output end of the de-skew unit 10 is connected to the i-th input end of the first link mapping unit 50 , the i-th output end of the first link mapping unit 50 is connected to the input end of the i-th coding scrambling unit 40 , and the processing unit 20 is connected to the first link mapping unit 50 .

[0075] The processing unit 20 is used to generate a mapping relationship set according to the output code streams of each decoding and descrambling unit 30, and transmit the mapping relationship set to the first link mapping unit 50, wherein the mapping relationship set includes N mapping relationships, the j-th mapping relationship corresponds to the j-th path, the j-th mapping relationship is the mapping relationship between the j-th ingress link and the N+1-j-th egress link sorted according to the delay skew, 1≤j≤N.

[0076] It should be understood that the path delay skew of the N paths constructed based on this is more uniform, and the path delay skew compensation can be reduced, thereby reducing communication delay and improving interaction efficiency.

[0077] The first link mapping unit 50 is used to control the switching of its input end and output end based on the mapping relationship set, so that the input end corresponding to the jth ingress link and the output end corresponding to the N+1-jth egress link are turned on, and forward the received de-skewed code stream to the back end, where j represents the delay skew sorting number of the link.

[0078] It should be understood that after the first link mapping unit 50 switches the internal conduction relationship, the transmission path of the code stream may change. Figure 2 , the code stream corresponding to the inlet link A2 will be output from the outlet link B1. In order to ensure that the second device at the back end can receive the ordered code stream, the processing unit 20 can transmit the mapping relationship set to the second device through the code stream data before the first link mapping unit 50 switches, so that it can perform path correction based on the mapping relationship set to ensure that the transmission of the code stream data complies with the preset order.

[0079] Based on the foregoing, the embodiment of the present invention further provides an optional implementation method for how to generate a mapping relationship set, which is described below.

[0080] The processing unit 20 is used to determine the delay skew of each ingress link according to the output code streams of each decoding and descrambling unit 30 .

[0081] The processing unit 20 is configured to generate a mapping relationship set according to the delay skews of the N ingress links and the delay skews of the N egress links.

[0082] Please refer to Figure 4 , Figure 4 The schematic diagram of the structure of the processing unit provided by the embodiment of the present invention is as follows: The processing unit 20 comprises an inlet recording unit 21, an inlet sorting unit 22, an outlet recording unit 23, an outlet sorting unit 24 and a mapping construction unit 25.

[0083] The entry recording unit 21 is connected to the entry sorting unit 22, the exit recording unit 23 is connected to the exit sorting unit 24, and both the entry sorting unit 22 and the exit sorting unit 24 are connected to the mapping construction unit 25; the output end of the i-th decoding and descrambling unit 30 is connected to the i-th access end of the entry recording unit 21; the mapping construction unit 25 is connected to the first link mapping unit 50.

[0084] The ingress recording unit 21 is used to determine the delay skew of each ingress link according to the output code stream of each decoding and descrambling unit 30 , and transmit the delay skew of each ingress link to the ingress sorting unit 22 .

[0085] Because the delays between links of the PCIe retimer are inconsistent and the delays are not fixed at different PCIe rates, an ingress recording unit 21 is added to the PCIe retimer to record the delay skew of the ingress link.

[0086] Optionally, the entry recording unit 21 is used to count the target arrival time of the i-th decoding and descrambling unit 30, wherein the target arrival time is the arrival time of the target information in the output code stream; and the delay skew of each entry link is determined according to the target arrival time of each decoding and descrambling unit 30.

[0087] In an optional implementation, the delay skew of the ingress link corresponding to the earliest target arrival time is set to 0, and the delay skew of other ingress links is the difference between the target arrival time of the ingress link and the earliest target arrival time. The delay skew of the ingress link is recorded as shown in Table 1 below.

[0088] Table 1

[0089]

[0090] The egress recording unit 23 is used to transmit the delay skew of each egress link to the egress sorting unit 24 .

[0091] It should be noted that the recording of the delay skew of the egress link is similar to the recording of the delay skew of the ingress link, and will not be elaborated here.

[0092] The egress recording unit 23 may receive the delay data of the egress link transmitted by the second device, wherein the delay data of the egress link includes the delay skew of each egress link. Alternatively, the egress recording unit 23 may be configured by the user to obtain the delay skew of each egress link.

[0093] The ingress sorting unit 22 is used to sort the delay skew of each ingress link.

[0094] The egress sorting unit 24 is used to sort the delay skew of each egress link.

[0095] When the inlet sorting unit 22 arranges in ascending order, the outlet sorting unit 24 arranges in descending order; when the inlet sorting unit 22 arranges in descending order, the outlet sorting unit 24 arranges in ascending order.

[0096] Optionally, after being sorted in descending order by the entry sorting unit 22, the following delay skew sorting array of the entry link is formed: {Lane_in[a], Lane_in[b].....Lane_in[w]}, where the lane with the smallest Delta T is Lane_in[w], and the lane with the largest Delta T is Lane_in[a]. Delta T represents the delay skew of the link, and Lane_in represents the entry link.

[0097] After being sorted in ascending order by the egress sorting unit 24, the following egress link delay skew sorting array is formed: {Lane_out[p], Lane_out[q].....Lane_out[z]}, where the one with the smallest Delta T is Lane_out[p], the one with the largest Delta T is Lane_out[z], and Lane_out represents the egress link.

[0098] The mapping construction unit 25 is used to construct the jth ingress link in the ingress sorting unit 22 and the jth egress link in the egress sorting unit 24 into a jth mapping relationship, thereby generating a mapping relationship set, and transmit the mapping relationship set to the first link mapping unit 50 .

[0099] Referring to the above example, Lane_in[a] and Lane_out[p] form a path, Lane_in[b] and Lane_out[q] form a path, and so on, Lane_in[w] and Lane_out[z] form a path.

[0100] It should be noted that the jth egress link in the egress sorting unit 24 when the descending order is adopted is the same as the N+1-jth egress link in the egress sorting unit 24 when the ascending order is adopted.

[0101] In order to reduce the delay of the data received by the second device as much as possible, or even to zero, so as to save the space of its corresponding de-skew buffer, the embodiment of the present invention also provides an optional implementation method. Please continue to refer to Figure 4 In an optional implementation, the processing unit 20 further includes a residual value compensation unit 26, and the residual value compensation unit 26 is connected to the mapping construction unit 25 and the de-skew unit 10 respectively.

[0102] The residual value compensation unit 26 is used to take the minimum value of the total delays of the N paths as the first reference value, wherein the total delay of the jth path is the sum of the delay skew of the ingress link and the delay skew of the egress link in the jth path.

[0103] Please refer to the following formula: Min Delta T = min (Delta T0, Delta T1, ... Delta TN), where Min Delta T represents the first reference value, Delta Tj represents the total delay of the j-th path, 1≤j≤N.

[0104] The residual value compensation unit 26 determines the difference between the total delay of the j-th path and the first reference value as the path delay skew of the j-th path.

[0105] Please refer to the following formula: Coef Tj = Delta Tj-Min Delta T, where Coef Tj is the path delay skew of the jth path.

[0106] The residual value compensation unit 26 is used to take the maximum value of the path delay skews of the N paths as the second reference value.

[0107] Please refer to the following formula: Max Coef T=max(Coef T0, Coef T0, ...Coef TN); wherein Max Coef T is the second reference value.

[0108] The residual value compensation unit 26 is used to determine the difference between the second reference value and the path delay skew of the j-th path as the path delay skew compensation of the j-th path, and transmit the j-th path information to the de-skew unit 10, the j-th path information including the path delay skew compensation of the j-th path and the ingress link identifier in the j-th path.

[0109] Please refer to the following formula: Path delay skew compensation for the jth path = Max Coef T-Coef Tj.

[0110] It should be understood that the de-skew unit 10 can determine the corresponding port according to the ingress link identifier in the jth path, and de-skew the code stream received by the port according to the path delay skew compensation of the jth path. For example, if the ingress link identifier in the jth path is the i-th ingress link, then the de-skew unit 10 de-skews the code stream received by its i-th input terminal according to the path delay skew compensation of the j-th path. Here, i represents the position sequence number of the link, and j represents the delay skew sequence number of the link.

[0111] Please continue to refer to Figure 3 In an optional implementation, the input end of the i-th decoding and descrambling unit 30 is used to connect to the i-th ingress link through the first PCIe interface 60.

[0112] The output end of the i-th encoding and scrambling unit 40 is connected to the i-th egress link through the second PCIe interface 70 .

[0113] It should be noted that, in the drawings provided in the embodiments of the present invention, 1~N in the decoding and descrambling unit 30 represents the serial number of the decoding and descrambling unit 30; 1~N in the coding and scrambling unit 40 represents the serial number of the coding and scrambling unit 40; 1~N in the de-skew unit 10 close to the decoding and descrambling unit 30 represents the serial number of the input end of the de-skew unit 10, and 1~N in the de-skew unit 10 close to the coding and scrambling unit 40 represents the serial number of the output end of the de-skew unit 10; 1~N in the first link mapping unit 50 close to the de-skew unit 10 represents the serial number of the input end of the first link mapping unit 50, and 1~N in the first link mapping unit 50 close to the coding and scrambling unit 40 represents the serial number of the output end of the first link mapping unit 50; 1~N in the second PCIe interface 70 close to the first link mapping unit 50 represents the serial number of the input end of the second PCIe interface 70, and 1~N in the other side of the second PCIe interface 70 represents the serial number of the output end of the second PCIe interface 70.

[0114] Based on the foregoing, an embodiment of the present invention further provides a PCIe system, which includes a first device, a second device and the above-mentioned PCIe retimer.

[0115] The i-th output terminal of the first device is connected to the input terminal of the i-th decoding and descrambling unit 30 through the i-th inlet link, and the i-th input terminal of the second device is connected to the output terminal of the i-th encoding and scrambling unit 40 through the i-th outlet link.

[0116] When the first device is a root complex device, the second device is a terminal device; when the first device is a terminal device, the second device is a root complex device.

[0117] When the PCIe retimer includes the first link mapping unit 50 , the second device is provided with a second link mapping unit.

[0118] The i-th input end of the second link mapping unit is connected to the i-th egress link, and the i-th output end of the second link mapping unit is connected to the input end of the i-th decoding and descrambling unit in the second device.

[0119] Alternatively, the i-th export link is connected to the input end of the i-th decoding and descrambling unit in the second device, the output end of the i-th decoding and descrambling unit in the second device is connected to the i-th input end of the second link mapping unit, and the i-th output end of the second link mapping unit is connected to the i-th input end of the de-skew unit in the second device.

[0120] The second link mapping unit is used to control its input end and output end to perform reverse switching based on the mapping relationship set. Reverse switching means that the switching relationship in the second link mapping unit is the reverse of the switching relationship in the first link mapping unit 50 .

[0121] An example of reverse switching is given below, assuming that both the first link mapping unit 50 and the second link mapping unit have three input terminals and three output terminals. The switching relationship in the first link mapping unit 50 is that the first input terminal is connected to the second output terminal, the second input terminal is connected to the third output terminal, and the third input terminal is connected to the first output terminal. Then the switching relationship in the second link mapping unit is that the second input terminal is connected to the first output terminal, the third input terminal is connected to the second output terminal, and the first input terminal is connected to the third output terminal.

[0122] An embodiment of the present invention further provides an electronic device, which includes the above-mentioned PCIe system. The electronic device can be, but is not limited to, a mobile phone, a computer, a server, and a smart wearable device.

[0123] In summary, the embodiments of the present invention provide a PCIe retimer, a PCIe system and an electronic device, wherein a decoding and descrambling unit receives input data of an ingress link connected thereto, performs decoding and descrambling processing, and outputs a decoding and descrambling code stream to the back end; a processing unit determines the path delay skew compensation corresponding to each path according to the output code stream of each decoding and descrambling unit, and transmits the path delay skew compensation to a de-skew unit; a de-skew unit performs de-skew processing on the decoding and descrambling code stream according to the path delay skew compensation, and outputs a de-skewed code stream to the back end; a coding and scrambling unit performs coding and scrambling processing on the received de-skewed code stream, and outputs a coding and scrambling code stream to the back end. When performing the de-skew processing, the delay skew on the entire path is taken into account, the delay skew compensation amount can be reduced, the data transmission delay can be effectively reduced, and the data transmission efficiency can be improved.

[0124] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0125] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A PCIe retimer, characterized in that: The PCIe retimer includes: a de-skewing unit, a processing unit, N decoding and descrambling units, and N encoding and scrambling units; The input end of the i-th decoding and descrambling unit is connected to the i-th ingress link, the output end of the i-th decoding and descrambling unit is connected to the i-th access end of the processing unit and the i-th input end of the deskewing unit, the i-th output end of the deskewing unit is connected to the input end of the i-th coding and scrambling unit, the output end of the i-th coding and scrambling unit is connected to the i-th egress link, 1≤i≤N, and the processing unit is connected to the deskewing unit; The decoding and descrambling unit is used to receive input data from the ingress link connected thereto, perform decoding and descrambling processing, and output a decoded and descrambled code stream to the back end; The processing unit is used to determine the path delay skew compensation corresponding to each path according to the output code stream of each decoding and descrambling unit, and transmit the path delay skew compensation to the de-skew unit, wherein the path includes 1 ingress link and 1 egress link; The de-skew unit is used to perform de-skew processing on the decoded descrambled code stream according to the path delay skew compensation, and output the de-skewed code stream to the back end; The coding and scrambling unit is used to perform coding and scrambling processing on the received de-skewed code stream, and output the coding and scrambling code stream to the back end.

2. The PCIe retimer of claim 1, wherein: The PCIe retimer further includes: a first link mapping unit; The i-th output end of the de-skewing unit is connected to the i-th input end of the first link mapping unit, the i-th output end of the first link mapping unit is connected to the input end of the i-th coding scrambling unit, and the processing unit is connected to the first link mapping unit; The processing unit is used to generate a mapping relationship set according to the output code streams of each decoding and descrambling unit, and transmit the mapping relationship set to the first link mapping unit, wherein the mapping relationship set includes N mapping relationships, the jth mapping relationship corresponds to the jth path, the jth mapping relationship is a mapping relationship between the jth ingress link and the N+1-jth egress link sorted according to delay skew, 1≤j≤N; The first link mapping unit is used to control the switching of its input end and output end based on the mapping relationship set, so that the input end corresponding to the jth ingress link and the output end corresponding to the N+1-jth egress link are connected, and forward the received de-skewed code stream to the back end.

3. The PCIe retimer of claim 2, wherein: The processing unit is used to determine the delay skew of each ingress link according to the output code stream of each decoding and descrambling unit; The processing unit is used to generate the mapping relationship set according to the delay skew of N ingress links and the delay skew of N egress links.

4. The PCIe retimer of claim 3, wherein: The processing unit includes an inlet recording unit, an inlet sorting unit, an outlet recording unit, an outlet sorting unit and a mapping construction unit; The ingress recording unit is connected to the ingress sorting unit, the egress recording unit is connected to the egress sorting unit, and both the ingress sorting unit and the egress sorting unit are connected to the mapping construction unit; the output end of the i-th decoding and descrambling unit is connected to the i-th access end of the ingress recording unit; the mapping construction unit is connected to the first link mapping unit; The ingress recording unit is used to determine the delay skew of each ingress link according to the output code stream of each decoding and descrambling unit, and transmit the delay skew of each ingress link to the ingress sorting unit; The egress recording unit is used to transmit the delay skew of each egress link to the egress sorting unit; The ingress sorting unit is used to sort the delay skew of each ingress link; The egress sorting unit is used to sort the delay skew of each egress link; When the inlet sorting unit adopts ascending order, the outlet sorting unit adopts descending order; when the inlet sorting unit adopts descending order, the outlet sorting unit adopts ascending order; The mapping construction unit is used to construct the jth ingress link in the ingress sorting unit and the jth egress link in the egress sorting unit into a jth mapping relationship, thereby generating the mapping relationship set, and transmitting the mapping relationship set to the first link mapping unit.

5. The PCIe retimer of claim 4, wherein: The entry recording unit is used to count the target arrival time of the i-th decoding and descrambling unit, wherein the target arrival time is the arrival time of the target information in the output code stream; The ingress recording unit is used to determine the delay skew of each ingress link according to the target arrival time of each decoding and descrambling unit.

6. The PCIe retimer of claim 4, wherein: The processing unit further comprises a residual value compensation unit, and the residual value compensation unit is connected to the mapping construction unit and the de-skew unit respectively; The residual value compensation unit is used to take the minimum value of the total delay of N paths as the first reference value, wherein the total delay of the jth path is the sum of the delay skew of the ingress link and the delay skew of the egress link in the jth path; The residual value compensation unit is used to determine the difference between the total delay of the j-th path and the first reference value as the path delay skew of the j-th path; The residual value compensation unit is used to take the maximum value of the path delay skews of the N paths as the second reference value; The residual value compensation unit is used to determine the difference between the second reference value and the path delay skew of the j-th path as the path delay skew compensation of the j-th path, and transmit the j-th path information to the de-skew unit, wherein the j-th path information includes the path delay skew compensation of the j-th path and the ingress link identifier in the j-th path.

7. The PCIe retimer of claim 1, wherein: The input end of the i-th decoding and descrambling unit is used to connect to the i-th ingress link through the first PCIe interface; The output end of the i-th encoding and scrambling unit is connected to the i-th egress link through the second PCIe interface.

8. A PCIe system, characterized in that: The PCIe system comprises a first device, a second device, and a PCIe retimer as described in any one of claims 1 to 7; The i-th output terminal of the first device is connected to the input terminal of the i-th decoding and descrambling unit through the i-th inlet link, and the i-th input terminal of the second device is connected to the output terminal of the i-th encoding and scrambling unit through the i-th outlet link; When the first device is a root complex device, the second device is a terminal device; when the first device is a terminal device, the second device is a root complex device.

9. The PCIe system according to claim 8, wherein: When the PCIe retimer includes a first link mapping unit, the second device is provided with a second link mapping unit; The i-th input terminal of the second link mapping unit is connected to the i-th egress link; The second link mapping unit is used to control its input end and output end to perform reverse switching based on the mapping relationship set, and the reverse switching means that the switching relationship in the second link mapping unit is the reverse of the switching relationship in the first link mapping unit.

10. An electronic device, characterized in that: Includes the PCIe system described in claim 8 or 9.

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