Method, apparatus, device and storage medium for managing line interruption

Abstract

The present disclosure provides a method, device, equipment and storage medium for managing line interruption. The method comprises: obtaining a first input, a second input and a third input, wherein the first input comprises a first table and a second table, the first table is a table to be filled, and the second table comprises a first interruption information set; the second input comprises a second interruption information set for a target multi-level in a register transfer level of an integrated circuit; the third input comprises a configuration parameter; based on the first, second and third inputs, at least one output of an inspection result, a hierarchical line interruption connection result and a third table is automatically obtained, and the third table comprises an interruption mapping table obtained by updating the first table. The present disclosure can automatically generate an interruption mapping table and hierarchical front-end hardware description language connection code, and can also check each module line interruption and design file, thereby reducing the labor and time cost of manual management, and improving the efficiency and quality of external line interruption management of chip design.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a method, apparatus, device and storage medium for managing wire interrupt. BACKGROUND

[0002] Interrupt system is an important part of computer system, for example, applied in real-time control, fault handling and handshake with peripheral communication, which needs to coordinate the response and processing of various internal and external events of the system, so as to improve the multitasking processing capability of the processor and greatly improve the efficiency of the computer.

[0003] In the field of chip design, various external interrupts are usually processed. For external interrupts, according to the way of initiating interrupt, it can be divided into two types: wire signaled interrupt (WSI) and message signaled interrupt (MSI). Wire signaled interrupt refers to interrupt driven by signal line directly, and message signaled interrupt refers to interrupt driven by writing specific address and data (message) operation.

[0004] Message interrupt type interrupt can more easily realize more and more flexible interrupts, but it needs additional design to realize writing specific address and data, and the specification support of external device. Wire interrupt is the way of more traditional external devices or modules to realize interrupt, although it is not flexible enough, but it is still an important part of modern interrupt system implementation because of its simple implementation and universal support of various traditional and new external devices or modules. SUMMARY

[0005] At least one embodiment of the present disclosure provides a method for managing wire interrupt, comprising: obtaining a first input, wherein the first input comprises a first table and a second table, the first table is configured to be filled in mapping, and the second table comprises a first interrupt information set; obtaining a second input, wherein the second input comprises a second interrupt information set corresponding to a target multi-level in a register transfer level of an integrated circuit, the target multi-level comprises a plurality of levels from a top level of the register transfer level to a last level of a target wire interrupt controller in the register transfer level; obtaining a third input, wherein the third input comprises configuration parameters corresponding to the first input and / or the second input; based on the first input, the second input and the third input, automatically obtaining at least one output of a check result, a hierarchical wire interrupt connection result and a third table, wherein the check result comprises a consistency comparison result based on the first interrupt information set and the second interrupt information set, the hierarchical wire interrupt connection result comprises a wire interrupt connection code corresponding to the target multi-level, and the third table comprises an interrupt mapping table obtained by updating the first table based on the second table.

[0006] In at least one embodiment of the present disclosure, a device for managing line interruption is provided, comprising: a first input obtaining module configured to obtain a first input, wherein the first input comprises a first table and a second table, the first table is configured to be filled by mapping, and the second table comprises a first set of interruption information; a second input obtaining module configured to obtain a second input, wherein the second input comprises a second set of interruption information corresponding to a target multi-level in a register transfer level of an integrated circuit, the target multi-level comprises a plurality of levels from a top level of the register transfer level to a last level of a target line interruption controller in the register transfer level; a third input obtaining module configured to obtain a third input, wherein the third input comprises configuration parameters corresponding to the first input and / or the second input; and an output obtaining module configured to automatically obtain at least one output of a checking result, a hierarchical line interruption connection result, and a third table based on the first input, the second input, and the third input, wherein the checking result comprises a result of consistency comparison based on the first set of interruption information and the second set of interruption information, the hierarchical line interruption connection result comprises a line interruption connection code corresponding to the target multi-level, and the third table comprises an interruption mapping table obtained by updating the first table based on the second table.

[0007] In at least one embodiment of the present disclosure, an electronic device is provided, comprising: a processor and a memory, wherein the memory has stored thereon a computer program, and the computer program, when executed by the processor, implements the method for managing line interruption according to any one of the above.

[0008] In at least one embodiment of the present disclosure, a computer readable storage medium is provided, wherein the storage medium has stored thereon a computer program, and the computer program, when executed by a processor, implements the method for managing line interruption according to any one of the above. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without creative labor.

[0010] Figure 1 is a flowchart of a method for managing line interruption according to some embodiments of the present disclosure;

[0011] Figure 2 is a schematic diagram of the principle of a method for managing line interruption according to some embodiments of the present disclosure;

[0012] Figure 3 isFigure 1 A flow chart of one execution process of step S1 of the method for managing line interruption;

[0013] Figure 4 is a schematic diagram of a principle of managing line interruption according to some embodiments of the present disclosure;

[0014] Figure 5 is a schematic diagram of a register transfer level hierarchical module according to some embodiments of the present disclosure;

[0015] Figure 6 is a schematic diagram of a parameter setting example according to some embodiments of the present disclosure;

[0016] Figure 7 is a schematic diagram of a format table file example according to some embodiments of the present disclosure;

[0017] Figure 8 is a schematic diagram of a file basic information page table example according to some embodiments of the present disclosure;

[0018] Figure 9 is a schematic diagram of a first table example according to some embodiments of the present disclosure;

[0019] Figure 10 is a schematic diagram of a third table example according to some embodiments of the present disclosure;

[0020] Figure 11 is a block diagram of a device for managing line interruption according to some embodiments of the present disclosure;

[0021] Figure 12 is a structural schematic diagram of an electronic device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present disclosure.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meanings as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that the terms, such as those defined in a generally used dictionary, should be interpreted as having meanings consistent with the meanings in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense, unless the embodiments of the present disclosure explicitly define so.

[0024] The terms "first", "second", and similar terms in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "one", "a", or "the" do not denote a quantity limitation, but mean that at least one exists. Similarly, the terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Flowcharts are used in the embodiments of the present disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the preceding or subsequent steps do not necessarily proceed in sequence. Instead, various steps can be processed in reverse order or simultaneously. Meanwhile, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0025] As the scale of a designed chip becomes larger, the number of external line interrupts also becomes relatively larger. For example, in a large or advanced chip design such as a server SOC (System On Chip, which refers to a system-level chip), there are often a large number of external line interrupt sources, and these external line interrupts can be distributed in several different levels of digital implementation and then converge to an external line interrupt manager (the line interrupt manager can also be referred to as a line interrupt controller). These external line interrupts need to be correctly integrated and connected in the levels of the SOC, and the order mapping information of the external line interrupts on the input of the external line interrupt controller needs to be clearly and efficiently provided, so as to be used as a reference for subsequent simulation verification, post-silicon testing, programming guidance, and product specification writing.

[0026] The present disclosure finds that the current management method for these external line interrupts is to manually arrange the basic information of each part of the line interrupts to collect a table, and then manually connect them in the SOC design according to the table order. In this way, the sequence numbers of the connections at each level and the interrupt sequence numbers at the input end of the external line interrupt controller can already be inconsistent. This process also requires a large amount of manual and time costs, and the inconsistent connection relationship and the manual processing method are prone to errors, which need to be discovered and corrected iteratively in the subsequent verification.

[0027] For example, the current external line interrupt management is mainly manually mapped, including interrupt mapping table and Verilog Hardware Description Language (Verilog Hardware Description Language) code connection (referred to as Verilog code connection) implemented by numbers, which requires a large amount of manual and time cost, and in the project evolution process, the number, order and connection of external line interrupts are changed, in addition to the repeated consumption of manual and time, there is a high possibility of mistakes, and there is a problem of lack of effective line interrupt signal and SOC corresponding design file check.

[0028] At least one embodiment of the present disclosure provides a method for managing line interrupts, the method comprising: obtaining a first input, wherein the first input comprises a first table and a second table, the first table is configured as a table to be mapped and filled, and the second table comprises a first interrupt information set; obtaining a second input, wherein the second input comprises a second interrupt information set corresponding to a target multi-level in a register transfer level of an integrated circuit, the target multi-level comprises a plurality of levels from a top level of the register transfer level to a last level of a target line interrupt controller in the register transfer level; obtaining a third input, wherein the third input comprises configuration parameters corresponding to the first input and / or the second input; based on the first input, the second input and the third input, automatically obtaining at least one output of a check result, a hierarchical line interrupt connection result and a third table, wherein the check result comprises a consistency comparison result based on the first interrupt information set and the second interrupt information set, the hierarchical line interrupt connection result comprises a line interrupt connection code corresponding to the target multi-level, and the third table comprises an interrupt mapping table obtained by updating the first table based on the second table.

[0029] The method for managing external line interrupts of the above-mentioned embodiments of the present disclosure can automatically generate the interrupt mapping table and the hierarchical Verilog connection code of the system line interrupts, and can check the module line interrupt information and the design file thereof, thereby greatly reducing the labor and time cost of manual management, and improving the efficiency and quality of chip design external line interrupt management.

[0030] Figure 1 is a flowchart of a method for managing line interrupts according to some embodiments of the present disclosure.

[0031] For example, as shown in Figure 1 The method for managing line interrupts at least comprises steps S1-S4.

[0032] Step S1, obtaining a first input, wherein the first input comprises a first table and a second table, the first table is configured as a table to be mapped and filled, and the second table comprises a first interrupt information set.

[0033] Step S2, obtaining a second input, wherein the second input comprises a second interrupt information set corresponding to a target multi-level in a register transfer level of the integrated circuit, the target multi-level comprising a plurality of levels from a level above the target line interrupt controller in the register transfer level to a top level of the register transfer level.

[0034] Step S3, obtaining a third input, wherein the third input comprises configuration parameters corresponding to the first input and / or the second input.

[0035] Step S4, based on the first input, the second input and the third input, automatically obtaining at least one output of a checking result, a hierarchical line interrupt connection result and a third table, wherein the checking result comprises a result of consistency comparison based on the first interrupt information set and the second interrupt information set, the hierarchical line interrupt connection result comprises a line interrupt connection code corresponding to the target multi-level, and the third table comprises an interrupt mapping table obtained by updating the first table based on the second table.

[0036] The above embodiments of the present disclosure establish a set of workflows. Through the collection of line interrupt information, consistency comparison and checking of the first interrupt information set and the second interrupt information set can be realized, and a system-level line interrupt mapping table and / or a Verilog connection code file corresponding to each level can be automatically generated, so that the line interrupt connection of each level and the line interrupt connection sequence to the external line interrupt controller remain consistent, which greatly reduces the labor and time cost, and improves the efficiency and quality of chip design external line interrupt management.

[0037] In the embodiments of the present disclosure, the "line interrupt" represents a line interrupt signal, and the "interrupt information" or "line interrupt information" represents the information content corresponding to the line interrupt signal, which are consistent, for example, which can represent the attribute of each column in the table corresponding to the line interrupt signal. The first interrupt information set and the second interrupt information set represent the information content of all line interrupt signals in the corresponding table.

[0038] For example, in some examples, the integrated circuit can be a large or advanced chip design such as a server SOC, and the embodiments of the present disclosure are not limited thereto, as long as it can be applied to a chip with external line interrupts, which is not exhaustively and elaborately described herein.

[0039] For example, in some examples, in step S4, the second interrupt information set in the second input is a design file (for example, it can include one design file or a plurality of design files corresponding to related levels, which can be determined according to actual conditions) with respect to the first interrupt information set, as described below, a set of three design files corresponding to three levels of modules.

[0040] For example, in some examples, the consistency comparison between the first set of break information and the second set of break information in step S4 can include the following process or steps: checking by a script according to corresponding rules (the first filling rules and / or the second processing rules described below) to obtain a checking result, so as to ensure the consistency between the break information in the second table and the design file.

[0041] For example, in some examples, the consistency comparison between the first set of break information and the second set of break information and the checking include but are not limited to the following cases: part of the content in the first set of break information does not exist in the second set of break information (for example, the signal name in the second table is not found in the design file), or part of the content in the second set of break information does not exist in the first set of break information, or the content in the first set of break information does not conform to the corresponding rules (for example, the second table filling mistake) described below, or the first set of break information is consistent with the second set of break information. Of course, this is only an example and is not a limitation of the embodiments of the present disclosure, which can be determined according to actual conditions, which will not be enumerated and described here.

[0042] For example, in some examples, in step S4, the content inconsistent between the first set of break information and the second set of break information in the checking result will be reported as an error (ERROR) or a warning (WARNING), and then the file of the checking result will be checked again. It should be noted that the embodiments of the present disclosure do not limit the display of the error and the specific situation of the error, which will not be described here.

[0043] For example, in some examples, the method for managing the break of the present disclosure further includes: in response to the checking result being inconsistent, iteratively modifying at least one of the first input, the second input, and the third input until the checking result is consistent. For example, until there is no error or warning, that is, all errors and warnings are finally cleared, and the checking of the break is completed.

[0044] The embodiments of the present disclosure can check some potential errors or aspects inconsistent with the design in the online break integration process earlier and more easily, and improve the quality and efficiency of chip design and break management.

[0045] For example, in some examples, in response to the checking result being inconsistent, if it is found that the first input has an error, the first input is iteratively modified; if it is found that the second input has an error, the second input is iteratively modified (as described below Figure 4The operation ①) is shown. In addition, when the check result is inconsistent, the first input and the second input can also be wrong, and the probability of this case is lower than that of one of them being wrong. Of course, this is merely exemplary and is not a limitation of the embodiments of the present disclosure, as long as it is a case that causes the check result to be inconsistent, which is within the protection scope of the present disclosure, and will not be described here.

[0046] For example, in some examples, step S4 can include the following process or step: based on the first input, the second input and the third input, automatically obtaining the above-mentioned at least one output through the script program.

[0047] Figure 2 is a schematic diagram of a principle of managing line interrupts proposed by some embodiments of the present disclosure.

[0048] For example, as Figure 2 shown, in step S4, based on the first input R1, the second input R2 and the third input R3, through the script program D1, the check result C1, the hierarchical line interrupt connection result C2 and the third table (i.e. the interrupt mapping table C3 after the mapping processing is completed) can be automatically obtained.

[0049] The embodiments of the present disclosure realize the identification of the second table content and the comparison check with the design file through the script program, and can automatically generate a new interrupt mapping table and hierarchical Verilog interrupt connection language code, so that the hierarchical line interrupt connection and the sequence of the line interrupt connection to the external line interrupt controller are consistent, which can greatly reduce the time and cost, and greatly improve the efficiency and quality of external line interrupt management.

[0050] It should be noted that this is merely exemplary and is not a limitation of the embodiments of the present disclosure, for example, the output obtained in step S4 can also be only the check result, for example, when some serious errors occur during the check, the hierarchical line interrupt connection result and the third table are no longer generated, and the embodiments of the present disclosure do not limit this, which can be determined according to the actual situation, and will not be enumerated and described here.

[0051] For example, in step S2, the last level of the target line interrupt controller in the register transfer level is the last level (for example, the level u_hier2 shown below) of the level (for example, the level of the target line interrupt controller u_aplic shown below) of the target line interrupt controller itself.

[0052] For example, in some examples, the corresponding target multi-level line break connection code in the hierarchical line break connection result refers to a line break Verilog connection code file of the level generated according to each design file in the second input (RTL filelist file list described below), which conforms to the order of the line break in the break mapping table.

[0053] For example, in some examples, the third table is changed compared with the first table, and details are described below.

[0054] Figure 3 is Figure 1 A flowchart of an execution process of step S1 of the method for managing line breaks.

[0055] Figure 4 is a schematic diagram of the principle of managing line breaks according to some embodiments of the present disclosure.

[0056] For example, as Figures 3-4 shown, step S1 includes at least step S11 and step S12.

[0057] Step S11, automatically obtaining a format table file A1, wherein the format table file A1 includes the first table and at least one sample table.

[0058] Step S12, collecting line break information based on the sample table of the format table file A1, obtaining the second table, and obtaining the first input R1.

[0059] For example, as Figure 3 and Figure 4 shown, in step S11, the format table file is automatically obtained by the script program D2. For example, for the format table file, it can be understood as an initial example of a standardized format of the break table file, which is used when the project starts or there is no modified break table file that conforms to the corresponding standard of the present disclosure. The method of the embodiments of the present disclosure can quickly cut into the management of external line breaks, for example, the steps of this format table file are generally only used once at the beginning. Of course, this is only an example and is not a limitation of the embodiments of the present disclosure.

[0060] The embodiments of the present disclosure realize the automatic generation of the format table file by executing the corresponding script commands in the flow environment, thereby realizing the automatic processing of each step of the method of the present disclosure and the rapid deployment of the application, and improving the efficiency.

[0061] In the embodiments of the present disclosure, the "table" (for example, the first table, the sample table, the second table, and the file basic information page table in the present disclosure, etc.) refers to a table made into a grid according to the required content items and filled with materials such as characters or numbers respectively for statistical viewing, for example, the table can be a table in the form of Excel, of course, this is only exemplary, for example, it can also be a table in other forms, for example, Word, Access, Numbers, etc., the embodiments of the present disclosure do not limit the type or form of the table, as long as it is a table that uses a visual communication mode and can organize and arrange data, which will not be enumerated and described here.

[0062] It should be noted that, for the sake of brevity and clarity of the present description, the following will mainly be described in detail taking the Excel table as an example, but the embodiments of the present disclosure do not limit the type or form of each table, which can be determined according to actual conditions, which will not be described here.

[0063] For example, in some examples, the format table file further includes a file basic information page table, and the file basic information page table includes first table header information.

[0064] For example, in some examples, obtaining the first input further includes the following process or step: configuring the first table, the sample table, the second table, and the file basic information page table as page tables of the same table file.

[0065] For example, in some examples, in step S1, the first input R1 is a multi-page table file (such as the same table file described above), such as an xlsx table file. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0066] The embodiments of the present disclosure realize the first input through a multi-page table file, the method is simple, and the line interruption information is more conveniently and efficiently managed, which is beneficial to improve the efficiency.

[0067] Figure 5 is a constituting diagram of the register transfer level hierarchical module proposed by some embodiments of the present disclosure.

[0068] For example, in some examples, in step S2, obtaining the second input includes the following process or step S2a: based on the register transfer level (RTL) of the target line interruption controller and the integrated circuit, and according to the list rule that the register transfer level file information is listed row by row from top to bottom by the top layer until the last level of the target line interruption controller on the register transfer level, the second input is obtained.

[0069] For example, in step S2a, the register transfer level of the integrated circuit based on indicates the integrated circuit design described by the register transfer level, which can also be referred to as an RTL file.

[0070] For example, in step S2a, the second input is: based on the actual project integrated circuit (such as SOC) digital design, record the file list of each level of RTL files starting from the top module, for example, the file list can be called rtl.list (or RTL filelist). Of course, this is only exemplary and not a limitation of the embodiments of the present disclosure. The embodiments of the present disclosure do not limit the name of the file list. As long as the contents of the file list are listed line by line from top to bottom according to the level of each RTL file in the digital design and listed to the level where the target line interrupt controller that manages these line interrupts is instantiated (for example Figure 5 The RTL file of the u_hier2 layer shown in FIG. 1 is sufficient, and will not be described in detail here. It should be noted that the target line interrupt controller layer in some embodiments of the present disclosure may also be referred to as the target line interrupt controller instantiation layer, which refers to the layer above the target line interrupt controller layer itself (or the target line interrupt controller instantiation layer itself).

[0071] For example, Figure 5 As shown, the target line interrupt controller is instantiated as u_aplic, and Figure 5 In the example of register transfer level, the top module is top, middle layer u_hier1 and u_hier2, and finally the target line interrupt controller u_aplic. Figure 5 The hierarchical example shown is top.u_hier1.u_hier2.u_aplic, and the file list RTL filelist includes the RTL design files of the three layers of modules: top, u_hier1, and u_hier2. For example, there is only one corresponding design file for each of the three layers: top, u_hier1, and u_hier2. Of course, this is merely exemplary and is not a limitation of the embodiments of the present disclosure. The specific module hierarchy arrangement is determined according to the design project plan such as SOC. As long as the location of the target line interrupt controller is determined, it will not be exhaustively listed or elaborated here.

[0072] In some embodiments of the present disclosure, "module" corresponds to "Module", which refers to a set of functions implemented in a digital design, such as a PCIE module, a DRAMC module, or an interrupt controller module, or a module integrating the three modules of PCIE module, DRAMC module, and interrupt controller module, and the module integrating the three modules has more functions, such as the top mentioned above, which is a module integrating all the functions required by a chip such as SOC, and the top module will not be integrated by other design files. Therefore, each module refers to all the modules required in a chip such as SOC, and adding a specific function limitation before "module" refers to a digital design unit that specifically implements the function, and without a specific function limitation, it refers to a digital design unit that implements the function required by a certain chip.

[0073] For example, in some examples, each module (such as the intermediate layer u_hier1) has one or more sub-modules that require interrupts, and each sub-module corresponds to a line interrupt, so the line interrupt information of the level corresponding to each module includes the summary of the line interrupt information of all sub-modules under the module (each interrupt information summary signal as described below).

[0074] For example, in some examples, in step S3, the configuration parameters include control parameters in the form of key-value pairs, and the control parameters include one or more of the following: line interrupt controller module name (ARG_TARGET), top module name (ARG_TOP), and maximum number of external line interrupts required to support (ARG_WIRE_MAX).

[0075] Embodiments of the present disclosure can adapt to various system line interrupt management of different projects by parameterized setting, can meet flexible requirements, and have a wide range of applications.

[0076] Figure 6 is a schematic diagram of a parameter setting example proposed by some embodiments of the present disclosure.

[0077] For example, as Figure 6 indicated, the configuration parameters are parameter settings required by the script program (such as script program D1) when processing. For example, Figure 6 the line interrupt controller module name APLIC, the top module name demo_top, and the maximum number of external line interrupts required to support 155 in the above example. Of course, this is only an example and is not a limitation of the embodiments of the present disclosure, and it can be freely adjusted according to the actual design situation, which will not be enumerated and described here.

[0078] For example, in some examples, the SOC design target interrupt controller can only support 155 connected interrupts, while the collected interrupt demand of all modules is 170, so the program lists all the required interrupts (170) in the interrupt mapping table, and checks them with the maximum number of interrupts supported by the design (155), and an error is reported, so that the number of interrupts needs to be controlled or the design support capability needs to be modified. This is only an example and is not limited to the embodiments of the present disclosure.

[0079] For example, in some examples, when the method of managing interrupts of the present disclosure is applied to different target interrupt controllers, the interrupt controller module name in the configuration parameter is also matched with the corresponding target interrupt controller, so that all interrupts of each target interrupt controller can be managed, the application is more convenient, and it is easier to adapt to new projects.

[0080] For example, the script program of the embodiments of the present disclosure can be implemented by Python language, which is more flexible. However, the embodiments of the present disclosure are not limited to this, and the script program of the present disclosure can also be implemented by other programming languages, which will not be enumerated and described here.

[0081] Figure 7 is a schematic diagram of an example of a format table file according to some embodiments of the present disclosure.

[0082] For example, as shown in Figure 7 , the format table file A1 includes a first table (such as page table 1) and at least one sample table. For example, as shown in Figure 7 , the format table file A1 also includes a file basic information page table (such as page table 0). Some embodiments of the present disclosure can manage all interrupt information based on the format table file and generate the interrupt mapping table after mapping.

[0083] For example, as shown in Figure 7 , the page table number of the format table file A1 is set to start from 0 and be numbered in turn, and the first row and first column of the page table are marked from 1. Of course, this is only an example and is not limited to the embodiments of the present disclosure.

[0084] For example, as shown in Figure 7 , the page table name of page table 0 is Note, the page table name of page table 1 is APLIC_int_mapping, and page table 1 can also be called the interrupt mapping table before mapping filling. At least one sample table in the format table file A1 can be Figure 7The sample table in the format table file Al can also be referred to as the interrupt sub-table before filling, and thus, the line interrupt information of each module needs to be collected according to the rules or specifications (see below) from the page table 2. Of course, this is merely an example, and the format table file of the embodiments of the present disclosure is not limited to Figure 7 the example, and the page table name of the page table is not limited to Figure 7 the naming manner of the example. The embodiments of the present disclosure do not limit this, and this will not be listed and described in detail here.

[0085] For example, in some examples, the first table header information of the file basic information page table includes at least one of the following information: version, description, date, and modifier information. This facilitates the management of line interrupts and is flexible and universal. Of course, this is merely an example and is not a limitation of the embodiments of the present disclosure.

[0086] Figure 8 is a schematic diagram of an example of the file basic information page table proposed by some embodiments of the present disclosure.

[0087] For example, as shown in Figure 8 , the first table header information of the file basic information page table (such as page table 0) includes: version (revision), description (description), date (date), and modifier information (modifier).

[0088] For example, Figure 8 The file basic information page table in the example is in an initial state, which is automatically generated by the script program D2, and subsequent filling and modification can be updated according to the actual project record. Of course, this is merely an example and is not a limitation of the embodiments of the present disclosure. The first table header information of the present disclosure can also be in other forms, which will not be described here. It should be noted that the case of the table name and / or the size of the table header information in some embodiments of the present disclosure does not affect the protection scope of the present disclosure.

[0089] Figure 9 is a schematic diagram of an example of the first table proposed by some embodiments of the present disclosure. Figure 10 is a schematic diagram of an example of the third table proposed by some embodiments of the present disclosure, Figure 10 is the result of mapping and filling the table based on Figure 9 , which will be described below.

[0090] For example, in some examples, the first table to be filled in mapping includes third table header information, and the third table header information includes at least one of the following naming identification information: wire index, signal name, module name, target, description, trigger mode, pending state and configuration register address. The format and content of the first table can be automatically generated by the script program D2. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0091] For example, as shown in Figure 9 , the third table header information of the first table (such as page table 1) to be filled in mapping includes: wire index (Wire Index), signal name (Signal Name), module name (Module Name), target (Targets), description (Description), trigger mode (Source Mode), pending state (Pending Bit) and configuration register address (Aplic cfg Register (offset)). Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. For example, as shown in Figure 9 , the first table to be filled in mapping (i.e. the interrupt mapping table before mapping filling) is blank except for the third table header information.

[0092] For example, as shown in Figure 7 , the table header information of the sample table (such as page table 2) includes signal name (Signal Name), port width (PortWidth), module name (Module Name), description (Description), trigger mode (Source Mode), target (Targets) and pending state (Pending Bit). Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. For example, in some examples, the sample table is different from the first table sample table, and is not completely blank except for the corresponding table header information (i.e. except for having the corresponding table header information, there are some records), as shown in Figure 7 , which can be freely adjusted according to actual conditions, which will not be repeated here.

[0093] For example, in some examples, the line index represents the serial number of the line interrupt index, which is the identification serial number of all valid line interrupts after processing; the trigger mode includes whether the line interrupt is rising edge triggered or falling edge triggered, high level valid or low level valid, and whether enabled or not; the target represents the corresponding individual target line interrupt controller; the signal name represents the name of the line interrupt information; the module name represents the name of each module; the description represents the content of the line interrupt information; the pending state represents the state of the pending register, for example, representing the state of having a request but not yet being processed; the configuration register address represents the address and offset of the corresponding configuration register in the interrupt controller, etc.; the port width represents the width of the port (such as the port for signal connection between each two modules). For example, the register information such as the pending state and the configuration register address is determined according to the SOC address allocation, which is associated with the SOC design, and since this is not the focus of the embodiments of the present disclosure, it will not be described here. It should be noted that the above table header information and its interpretation are only exemplary and are not limited by the embodiments of the present disclosure.

[0094] For example, in some examples, in step S12, the line interrupt information collection is performed based on the sample table of the format table file A1 to obtain the second table, including the following process or step S12a: filling the sample table based on the sample table of the format table file A1 and according to the first filling rule to obtain the second table. For example, the second table header information of the second table is the same as the table header information of the sample table.

[0095] For example, in some examples, the second table includes second table header information, and the second table header information includes at least one of the following naming identification information: signal name, port width, module name, description, trigger mode, target, and pending state. For example, the second table header information of the second table can also include the clock domain (Clk Domain), or the clock domain column can be empty. Of course, this is only exemplary and is not limited by the embodiments of the present disclosure.

[0096] For example, the table header (such as the first table header information, the second table header information, and the third table header information) of some embodiments of the present disclosure can be manually adjusted for highlighting to facilitate viewing, without affecting the execution of the process of the method of managing line interrupts. For example, the table header of some embodiments of the present disclosure is named and recognized, and the embodiments of the present disclosure support adding or inserting new column information as needed without affecting the execution of the method process of the present disclosure.

[0097] For example, in some examples, in step S12a, filling in the sample table can be done manually to collect line interruption information of each module or part of the SOC system according to the example format, and to complete the sample table to obtain a second table (not shown). Thus, the second table is a standardized interruption table file collected and sorted from each module or part. For example, the table where the line interruption corresponding to each module is located is a page table in the first input (multi-page table file). Of course, this is merely exemplary and is not a limitation of the embodiments of the present disclosure.

[0098] For example, in some examples, such as Figure 10 As shown, the third table is the interrupt mapping table after mapping processing. Figure 10 is Figure 9 On the basis of the above, the content of the second table after the line interruption information collection is completed is at least partially mapped to the result obtained in the first table.

[0099] For example, in some examples, a first filling rule for filling a sample table (i.e., the interruption sub-table before starting to fill) to obtain a second table (i.e., the interruption sub-table after completing the filling) includes at least one of the following:

[0100] (1) A complete line interruption information should fill in all the information of the interruption sub-table and the columns of description, trigger mode, clock domain and suspend status in the header information (i.e., the second header information) of the interruption sub-table can be left blank.

[0101] (2) If the target column ("Targets" column) in the second header information of the interrupt subtable has multiple interrupt target destinations (e.g., APLIC, MSCP), the targets are separated by punctuation marks (e.g., semicolons). The target column is case-insensitive, and the parameter specifies the name that the script program matches during processing. This allows the target module to be named according to the project or actual situation. The target destination represents the target line interrupt controller. For example, the target destination refers to the instantiation of the target line interrupt controller.

[0102] (3) The content of the first valid interrupt in the column where the module name is located (the "Module Name" column) in the second header information of the interrupt sub-table is not empty (for example, although the script can automatically process it as the top-level module specified by the parameter, some embodiments may choose not to use it in this way), and the column where the module name is located in the second header information of the interrupt sub-table supports filling in different module names (for example, the premise is that these modules are consistent with the number of instantiations implicitly represented in the page table name); for another example, for this column, the script program will automatically use the module name filled in last time to process the subsequent empty content (that is, at least the module name of the first valid interrupt is not empty) (from the perspective of easy viewing, it is not preferred to leave it blank).

[0103] (4) The column where the port width is located ("PortWidth" column) in the second header information of the interrupt subtable supports multi-bit width interrupt signals. For example, a number greater than 1 can be filled in, or the default 1-bit signal can be left blank.

[0104] (5) For the signal name column ("SignalName" column) in the second header information of the interrupt subtable: this column supports grammatically correct signal names, and also supports blank, slash " / " and case-insensitive NA or N / A to indicate skipping the row in the table; or, case-insensitive Reserved, used for interrupt signal mapping placeholder; or, if the interrupt signal name has been determined but a placeholder needs to be mapped at a certain stage instead of the actual code connection, the prefix Reserved_ can be used.<signal_name> The interrupt signal mapping is performed in this way.

[0105] In some embodiments of the present disclosure, interrupt signal mapping placeholders represent: interrupt placeholders are performed according to the expected number of interrupt signals, allowing this line interrupt to occupy a line interrupt sequence number in advance without actually connecting the signal. In this way, during the digital design and development phase, line interrupts that have been determined but not yet implemented are pre-occupied, facilitating earlier determination or maintaining consistency and stability in the index numbers of each line interrupt throughout the entire project phase, alleviating or reducing the difficulty or modification of subsequent verification and other processes. Since this is not the focus of the embodiments described in the present disclosure, it is not elaborated here.

[0106] The first filling rule of the embodiment of the present disclosure includes the design of table content skipping and interrupt mapping placeholders in the column where the signal name is located, which can greatly improve the flexibility of filling in the interrupt sub-table and the stability of subsequent processing. Moreover, the table content skipping means directly skipping the row after the specified content is matched, so that the interrupt can be quickly deleted without changing the number of rows in the original page table, etc., which is flexible for application.

[0107] It should be noted that the above-mentioned first filling rule is merely exemplary and does not limit the embodiments of the present disclosure. As long as it meets the project requirements, it will not be exhaustively listed or elaborated here.

[0108] For example, in some examples, when the check result is inconsistent, if it is necessary to iteratively correct the first input (such as Figure 4 In operation ①), the correction requirements also follow the first filling rule described above. That is, embodiments of the present disclosure can fill in the sample table or correct the second table according to the first filling rule described above, which will not be further described here. For example, the first input in step S1 can be the uncorrected initial first input, or it can be the first input obtained after correcting the second table after verifying the inspection results. The embodiments of the present disclosure do not impose any restrictions on this, and it can be determined based on actual circumstances, which will not be further described here.

[0109] For example, in some examples, in step S4, based on the first input, the second input, and the third input, the checking result, the hierarchical interrupt connection result, and at least one output in the third table are automatically obtained, including the following process or step S4a: updating the first table based on the second table to obtain the third table.

[0110] For example, in some examples, in step S4a, the first table and the third table are page tables in the same location, but the content in the page table is changed in the third table compared with the first table, that is, the third table is obtained by filling the content in the first table except the table header.

[0111] For example, in some examples, the third table in the second table is an interrupt mapping table generated based on two interrupt sub-tables. Figure 10 The third table in the second table is an interrupt mapping table generated based on two interrupt sub-tables. Thus, the third table of the embodiments of the present disclosure not only contains interrupt information in the interrupt sub-tables, but also contains information such as the suspension state and the configuration register address and the hierarchical instantiation obtained from the design.

[0112] In some examples, the second processing rule includes the following basic rules for processing the second table and the basic rules for processing the interrupt mapping table.

[0113] For example, in some examples, the basic rule for processing the second table includes at least one of the following:

[0114] (1) judging the column of the target in the second table header information (the “Targets” column), and if there is no target line interrupt controller module name information (for example, “APLIC” information, here the parameter specifies the system line interrupt controller module name as APLIC, which is consistent with the first filling rule of the sample table), skipping.

[0115] (2) judging the column of the signal name in the table header information of the second table (the “Signal Name” column), and if it is invalid content, skipping (for example, the cases of empty, slash “ / ”, and various NA or N / A in the second table in the above Figure 7 ).

[0116] (3) judging whether the column of the module name in the second table header information of the second table (the “Module Name” column) can be found in the RTL file of the second input; if the first valid content line in the page table is empty, the top-level module name (the top-level module name specified by the configuration parameter) is used by default; if only the non-first valid line in the page table is empty, the last valid module name is used by default (here, it is preferred to follow the first filling rule without leaving empty).

[0117] (4) judging the column of port width ("PortWidth" column) in the second table header information of the second table, if it is empty or 1, then directly processing according to 1-bit signal, if it is greater than 1, then calling a function to complete the port signal expansion.

[0118] (5) judging whether the column of description ("Description" column) in the second table header information of the second table is empty, and adjusting the content of writing the interrupt mapping table according to the judgment result.

[0119] (6) judging whether the port of the column of signal name (visible below) in the second table header information of the second table can be found on the instance, if it is the top module, then judging whether the interrupt is defined in the top layer, if it does not conform to the rule, then reporting an error; at the same time, according to the port connection of the RTL design file, automatically judging the interrupt signal name of writing the interrupt mapping table and generating the hierarchical code, if the port is not connected in the design, then the port name and the connection name are used by default, if the port has a connected signal, then the signal name connected in the design is used.

[0120] For example, in some examples, the basic rules for processing the interrupt mapping table include at least one of the following:

[0121] (1) the script program D1 initializes or clears the content of all interrupt mapping tables according to the third table header information line by line; among them, the contents of the two columns of configuration register address and suspend state in the third table header information are initialized, and the other table header information columns in the third table header information are cleared.

[0122] (2) the script program D1 processes the second table (this is only exemplary) starting from the serial number 2, and checks each line in each second table according to the above-mentioned basic rules for processing the second table, and maps the interrupt information of the line that meets the condition into the interrupt mapping table line by line.

[0123] (3) in the interrupt mapping table, the content of the line index in the third table header information is automatically generated according to the serial number; the signal name, target, description and trigger mode in the third table header information are the corresponding information extracted from the second table or the default description added by the script program; in addition, the module name, configuration register address and suspend state in the third table header information are the instantiation name and hierarchical information extracted from the RTL design file by the script program, or the base address fixed as a function parameter and the line index number and design rule offset are calculated by the function of the script program according to the SOC allocation.

[0124] Embodiments of the present disclosure can implement the function of automatically generating the interrupt mapping table of the system external line interrupt manager, and can also ensure that there is only one table file managing these external line interrupt information, avoiding redundancy and confusion, and the file containing the output interrupt mapping table can also continue to be used as the input for subsequent line interrupt modification and re-examination and automatic generation of line interrupt management.

[0125] It should be noted that the above-mentioned second processing rule is only exemplary and is not limited by embodiments of the present disclosure, as long as it can achieve the writing of normal line interrupt information meeting the corresponding rule into the interrupt mapping table (for example, if it does not meet the corresponding processing rule, an error is reported), and embodiments of the present disclosure do not limit and elaborate on this.

[0126] For example, in Figure 7 In examples, the page table name of the interrupt sub-table can not be the module name, for example, the page table name can also be a collection name composed of related modules, and embodiments of the present disclosure do not limit this. For example, as shown in Figure 7 The page table name of the page table 3 is demo_ss4x3x4, and the last "x4" in the page table name of the page table 3 indicates that the module in the page table is instantiated four times, and embodiments of the present disclosure support automatic expansion of interrupt information of multi-instantiated modules through the page table name suffix "x[Num]", reducing table redundancy.

[0127] For example, for instantiation, one module (Module) can instantiate multiple instances (Instances), such as the PCIE module instantiating PCIE_1, PCIE_2, PCIE3, and PCIE4 four times on the SOC, each of which is independent and has the same function; assuming that the PCIE module has 2 line interrupts, then four instantiations require 8 line interrupts to be sent to the line interrupt controller, and the port name of each instantiation is actually the same. For this case of instantiating multiple Instances for one Module, only the instantiation number needs to be added to the interrupt sub-table name according to the format, and the program can automatically expand the page table four times for interrupt mapping processing.

[0128] For example, in some examples, step S4 can include the following processes or steps: obtaining, based on the second interrupt information set, a single-layer interrupt information summary signal corresponding to the line interrupt information of each level of the target multi-level, and modularly transmitting, from top to bottom on the register transfer level, the single-layer interrupt information summary signal corresponding to each current level of the target multi-level to the next level connected with the current level in sequence until all single-layer interrupt information summary signals of the target multi-level are collected to the target line interrupt controller, to obtain the hierarchical line interrupt connection result.

[0129] In some embodiments of the present disclosure, "modularly transmitting" refers to each current level collecting all line interrupt information corresponding to the current level and transmitting the collected line interrupt information as a whole to the next level. In some examples, all line interrupt information of the current level can be modularly transmitted to the next level by opening a port on the next level. For example, all line interrupt information of the u_hier1 layer can be transmitted to the u_hier2 layer by opening a port on the u_hier2 layer.

[0130] In some embodiments of the present disclosure, the single-layer interrupt information aggregation signal refers to all information aggregation results obtained by collecting all line interrupt information corresponding to each level. For example, the single-layer interrupt information aggregation signal refers to a file obtained by performing ordering and connection of line interrupts in each corresponding level (i.e., completing a hierarchical connection). The single-layer interrupt information aggregation signal can be a bus type signal, and the signal transmission can be achieved by opening a port on the level.

[0131] For example, in some examples, opening a port on the module level can be achieved manually. Of course, this is merely exemplary and is not a limitation of the embodiments of the present disclosure.

[0132] For example, in some examples, the above hierarchical configuration is configured to not repeat the collection, which means that each current level only collects line interrupt information that the current level itself has, and does not repeat the collection of line interrupt information that the previous level has already collected. For example, after the u_hier2 layer obtains the second-layer interrupt information aggregation signal that has been collected by the u_hier1 layer through the port, the u_hier2 layer only needs to collect all line interrupt information that the u_hier2 layer itself has to obtain the third-layer interrupt information aggregation signal, but does not need to collect the first-layer interrupt information aggregation signal. Of course, this is merely exemplary and is not a limitation of the embodiments of the present disclosure.

[0133] For example, in the example of Figure 5 In some embodiments of the present disclosure, all line interrupt information of the top layer, the u_hier1 layer, and the u_hier2 layer is aggregated to the interrupt controller u_aplic, and each of the top layer, the u_hier1 layer, and the u_hier2 layer has an RTL design file, thereby obtaining the hierarchical line interrupt connection code in the output result.

[0134] For example, in some examples, the embodiments of the present disclosure can collect all line interruption information corresponding to the top layer to obtain a first layer interruption information summary signal, send the first layer interruption information summary signal to the u_hier1 layer as a whole by opening a port on the u_hier1 layer, then collect all line interruption information corresponding to the u_hier1 layer to obtain a second layer interruption information summary signal, send the first layer interruption information summary signal and the second layer interruption information summary signal to the u_hier2 layer, then collect all line interruption information corresponding to the u_hier2 layer to obtain a third layer interruption information summary signal, and send the first layer interruption information summary signal, the second layer interruption information summary signal and the third layer interruption information summary signal to the interrupt controller u_aplic by opening a port on the interrupt controller u_aplic. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0135] For example, in some examples, the first layer interruption information summary signal, the second layer interruption information summary signal and the third layer interruption information summary signal each correspond to the RTL design files of the top, u_hier1 and u_hier2 layers described above.

[0136] For example, each of the first layer interruption information summary signal, the second layer interruption information summary signal and the third layer interruption information summary signal refers to a file obtained by ordering and connecting line interruptions in the corresponding layer, so as to obtain the final hierarchical line interruption connection code corresponding to the target multi-layer. For example, each of the first layer interruption information summary signal, the second layer interruption information summary signal and the third layer interruption information summary signal can be a bus type signal, and these bus type signals are configured to be modularly transmitted to the next layer connected with the current layer until all bus type signals reach the target line interruption controller, so as to obtain the final hierarchical line interruption connection result corresponding to the target multi-layer.

[0137] The embodiments of the present disclosure can automatically generate the corresponding RTL file list and the Verilog connection code of line interruptions in each layer corresponding to the number of layers by modularly transmitting line interruption information, the code files all conform to the ordering of line interruptions in the interruption mapping table, so as to realize port unification, facilitate information management, and very conveniently realize design integration, saving time and effort.

[0138] In some examples, the method of managing line interruptions of any of the above embodiments can be used to maintain all line interruption information of a target line interruption controller.

[0139] The script program implemented by the above embodiments of the present disclosure can quickly provide a table file applying the method according to defined specifications and rules, check the consistency of filled line interruption information and design, and adapt to various system line interruption management of different projects through parameterized setting. In addition, the script program flexibly supports information expansion of interruption sub-tables through naming matching instead of fixed row-column matching, and can automatically analyze and check the hierarchy and signal connection information of interruption signals, and has the characteristics of rich functions and flexible generalization.

[0140] For example, in some examples, for the method of managing line interruption of the present disclosure, in response to the target line interruption controller being N, the method of managing line interruption is configured to perform N times of corresponding execution according to N target line interruption controllers, where N is an integer greater than or equal to 2.

[0141] The method of managing line interruption of the embodiments of the present disclosure has strong scalability and strong universality, and has a wide application range.

[0142] For example, in some examples, the embodiments of the present disclosure also implement the method of managing line interruption multiple times by adjusting the input (for example, adjusting at least one of the first input, the second input, and the third input), such as adjusting the line interruption controller module name in the configuration parameter for different target line interruption controllers as described above. Of course, this is only an example and is not a limitation of the embodiments of the present disclosure, and can be freely adjusted as needed, which will not be enumerated and described here.

[0143] Figure 11 A block diagram of a device for managing line interruption provided by some embodiments of the present disclosure.

[0144] For example, as shown in Figure 11 The device 100 for managing line interruption provided by at least one embodiment of the present disclosure includes a first input acquisition module 110, a second input acquisition module 120, a third input acquisition module 130, and an output acquisition module 140.

[0145] The first input acquisition module 110 is configured to acquire a first input, where the first input includes a first table and a second table, the first table is configured to be a table to be filled by mapping, and the second table includes a first interruption information set.

[0146] The second input acquisition module 120 is configured to acquire a second input, where the second input includes a second interruption information set corresponding to a target multi-level in a register transfer level of an integrated circuit, and the target multi-level includes multiple levels from a level above the target line interruption controller in the register transfer level to a top level of the register transfer level.

[0147] The third input obtaining module 130 is configured to obtain a third input, where the third input includes configuration parameters corresponding to the first input and / or the second input.

[0148] The output obtaining module 140 is configured to automatically obtain at least one output of a check result, a hierarchical line interruption connection result, and a third table based on the first input, the second input, and the third input, where the check result includes a result of consistency comparison based on the first interruption information set and the second interruption information set, the hierarchical line interruption connection result includes a line interruption connection code corresponding to the target multi-level, and the third table includes an interruption mapping table obtained by updating the first table based on the second table.

[0149] It should be noted that in the embodiments of the present disclosure, the device for managing line interruptions can include more or fewer modules, and the connection relationship between the modules is not limited and can be determined according to actual needs. The specific constituting manner of each module is not limited. For the specific implementation and technical effects of the device for managing line interruptions, reference can be made to the related content of the method for managing line interruptions provided in the above embodiments of the present disclosure, which will not be described here again.

[0150] Each module in the above embodiments can be respectively configured as software, hardware, firmware, or any combination of the above, for performing a specific function. For example, these modules can correspond to a dedicated integrated circuit, a pure software code, or a combination of software and hardware modules.

[0151] It should be noted that although the device for managing line interruptions is divided into modules for performing respective processes in the above description, it is clear to those skilled in the art that the processes performed by each module can also be performed without any specific module division of the device for managing line interruptions or without clear demarcation between the modules.

[0152] Figure 12 A structural schematic diagram of an electronic device provided by at least one embodiment of the present disclosure is provided, and the electronic device 200 includes a processor 210 and a memory 220, where the memory 220 stores a computer program, and the computer program is executed by the processor 210 to implement the method for managing line interruptions of at least some embodiments of the present disclosure.

[0153] The electronic device in the embodiments of the present disclosure can include but is not limited to mobile terminals such as notebook computers, tablet computers, and the like, and fixed terminals such as desktop computers and the like. Figure 12 The electronic device shown is only an example and should not bring any limitation to the functions and use range of the embodiments of the present disclosure.

[0154] For example, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods illustrated by the flowcharts. When the computer program is executed by a processor, the method of managing a line interruption according to embodiments of the present disclosure is performed.

[0155] It should be noted that the computer-readable medium described above in the present disclosure can be a computer-readable signal medium or a computer-readable storage medium or any combination thereof. The computer-readable storage medium may, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any suitable combination thereof. More specific examples of the computer-readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In embodiments of the present disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus or device. In embodiments of the present disclosure, the computer-readable signal medium can include a data signal carried in a baseband or as a part of a carrier wave, in which a computer-readable program code is carried. Such a propagated data signal can take many forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination thereof. The computer-readable signal medium can also be any computer-readable medium that is not a computer-readable storage medium and that can be used to carry or store a program for use by or in connection with an instruction execution system, apparatus or device. The program code contained in the computer-readable medium can be transmitted by any suitable medium, including but not limited to a wire, an optical fiber, an RF (radio frequency) or the like, or any suitable combination thereof.

[0156] The computer-readable medium described above can be included in the electronic device described above; or can exist separately and not be assembled into the electronic device.

[0157] It should be noted that in embodiments of the present disclosure, the specific functions and technical effects of the electronic device 200 can refer to the description of the method of managing a line interruption above, and will not be described here.

[0158] Based on one or more embodiments of the present disclosure, a method for managing line interrupts is provided, including: obtaining a first input, wherein the first input includes a first table and a second table, the first table is configured to be filled in mapping, and the second table includes a first set of interrupt information; obtaining a second input, wherein the second input includes a second set of interrupt information corresponding to a target multi-level in a register transfer level of an integrated circuit, the target multi-level includes a plurality of levels from a top level of the register transfer level to a level of a target line interrupt controller in the register transfer level; obtaining a third input, wherein the third input includes configuration parameters corresponding to the first input and / or the second input; based on the first input, the second input, and the third input, automatically obtaining at least one of an inspection result, a hierarchical line interrupt connection result, and a third table in the third table, wherein the inspection result includes a result of consistency comparison based on the first set of interrupt information and the second set of interrupt information, the hierarchical line interrupt connection result includes a line interrupt connection code corresponding to the target multi-level, and the third table includes an interrupt mapping table obtained by updating the first table based on the second table.

[0159] For example, in the method for managing line interrupts provided by at least one embodiment of the present disclosure, obtaining the first input includes: automatically obtaining a format table file, wherein the format table file includes the first table and at least one sample table; collecting line interrupt information based on the sample table of the format table file to obtain the second table, so as to obtain the first input.

[0160] For example, in the method for managing line interrupts provided by at least one embodiment of the present disclosure, the format table file further includes a file basic information page table, and the file basic information page table includes first table header information, and the first table header information includes at least one of the following information: version, description, date, and modifier information.

[0161] For example, in the method for managing line interrupts provided by at least one embodiment of the present disclosure, obtaining the first input further includes: configuring the first table, the at least one sample table, and the file basic information page table as page tables of a same table file.

[0162] For example, in the method for managing line interrupts provided by at least one embodiment of the present disclosure, the second table includes second table header information, and the second table header information includes at least one of the following naming identification information: signal name, port width, module name, description, trigger mode, target, and suspension state.

[0163] For example, in the method for managing line interrupts provided by at least one embodiment of the present disclosure, the first table includes third table header information, and the third table header information includes at least one of the following naming identification information: line index, signal name, module name, target, description, trigger mode, suspension state, and configuration register address.

[0164] For example, in the method for managing line interruption provided in at least one embodiment of the present disclosure, the second input is obtained based on a register transfer level of the target line interruption controller and the integrated circuit, and according to a list rule that a register transfer level file information is listed row by row from top to bottom by a top layer until a last layer of the target line interruption controller on the register transfer level.

[0165] For example, in the method for managing line interruption provided in at least one embodiment of the present disclosure, the configuration parameter includes a control parameter in the form of a key-value pair, and the control parameter includes one or more of a line interruption controller module name, a module name of a top layer, and a maximum number of external line interruptions required to be supported.

[0166] For example, in the method for managing line interruption provided in at least one embodiment of the present disclosure, the at least one output of the checking result, the hierarchical line interruption connection result, and the third table is automatically obtained based on the first input, the second input, and the third input, including: based on the first input, the second input, and the third input, the at least one output is automatically obtained by a script program.

[0167] For example, in the method for managing line interruption provided in at least one embodiment of the present disclosure, the at least one output of the checking result, the hierarchical line interruption connection result, and the third table is automatically obtained based on the first input, the second input, and the third input, including: based on the second table, the first table is updated to obtain the third table.

[0168] For example, in the method for managing line interruption provided in at least one embodiment of the present disclosure, the at least one output of the checking result, the hierarchical line interruption connection result, and the third table is automatically obtained based on the first input, the second input, and the third input, including: based on the second interruption information set, a single-layer interruption information summary signal of line interruption information corresponding to each layer in the target multi-layer is obtained, and according to a rule that the single-layer interruption information summary signal corresponding to each current layer in the target multi-layer is modularly transmitted to a next layer connected with the current layer from top to bottom by a top layer on a register transfer level, sequentially, until all single-layer interruption information summary signals of the target multi-layer are collected to the target line interruption controller, to obtain the hierarchical line interruption connection result.

[0169] For example, the method for managing line interruption provided in at least one embodiment of the present disclosure further includes: in response to the checking result being inconsistent, at least one of the first input, the second input, and the third input is iteratively corrected until the checking result is consistent.

[0170] For example, in the method for managing a line interrupt provided in at least one embodiment of the present disclosure, in response to the target line interrupt controller being N, the method for managing a line interrupt is configured to be performed N times according to the N target line interrupt controllers, where N is an integer greater than or equal to 2.

[0171] Based on one or more embodiments of the present disclosure, an apparatus for managing a line interrupt is also provided, comprising: a first input obtaining module configured to obtain a first input, wherein the first input comprises a first table configured to be filled in mapping and a second table comprising a first interrupt information set; a second input obtaining module configured to obtain a second input, wherein the second input comprises a second interrupt information set corresponding to a target multi-level in a register transfer level of an integrated circuit, the target multi-level comprising a plurality of levels from a last level of a target line interrupt controller in the register transfer level to a top level of the register transfer level; a third input obtaining module configured to obtain a third input, wherein the third input comprises configuration parameters corresponding to the first input and / or the second input; and an output obtaining module configured to automatically obtain at least one output of a checking result, a hierarchical line interrupt connection result, and a third table based on the first input, the second input, and the third input, wherein the checking result comprises a result of consistency comparison based on the first interrupt information set and the second interrupt information set, the hierarchical line interrupt connection result comprises a line interrupt connection code corresponding to the target multi-level, and the third table comprises an interrupt mapping table obtained by updating the first table based on the second table.

[0172] Based on one or more embodiments of the present disclosure, an electronic device is provided, comprising a processor and a memory, wherein the memory has stored thereon a computer program, and the computer program is executed by the processor to implement the method for managing a line interrupt according to any one of the above.

[0173] Based on one or more embodiments of the present disclosure, a computer readable storage medium is provided, wherein the storage medium has stored thereon a computer program, and the computer program is executed by a processor to implement the method for managing a line interrupt according to any one of the above.

[0174] The following points need to be explained:

[0175] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0176] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined to obtain new embodiments.

[0177] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for managing line interrupts, comprising: obtaining a first input, wherein the first input comprises a first table configured as a table to be filled in mapping and a second table comprising a first set of interrupt information; obtaining a second input, wherein the second input comprises a second set of interrupt information corresponding to a target multi-level in a register transfer level of an integrated circuit, the target multi-level comprising a plurality of levels from a top level of the register transfer level down to a level of a target line interrupt controller in the register transfer level; obtaining a third input, wherein the third input comprises configuration parameters corresponding to the first input and / or the second input; automatically obtaining at least one output of a checking result, a hierarchical line interrupt connection result and a third table based on the first input, the second input and the third input, wherein the checking result comprises a result of consistency comparison based on the first set of interrupt information and the second set of interrupt information, the hierarchical line interrupt connection result comprises line interrupt connection codes corresponding to the target multi-level, and the third table comprises an interrupt mapping table obtained by updating the first table based on the second table.

2. The method of managing a line interruption of claim 1, wherein, The obtaining of the first input comprises: automatically obtaining a format table file, wherein the format table file comprises the first table and at least one sample table; collecting line interrupt information based on the sample table of the format table file to obtain the second table, so as to obtain the first input.

3. The method of managing a line interruption of claim 2, wherein, The format table file further comprises a file basic information page table, the file basic information page table comprises first table header information, and the first table header information comprises at least one of the following information: version, description, date and modifier information.

4. The method of managing a line interruption of claim 3, wherein, The obtaining of the first input further comprises: configuring the first table, the at least one sample table and the file basic information page table as page tables of a same table file. 5.The method for managing line interrupts according to any one of claims 1 to 4, wherein the second table comprises second table header information, and the second table header information comprises at least one of the following naming identification information: signal name, port width, module name, description, trigger mode, target and suspension state. 6.The method for managing line interrupts according to claim 1, wherein the first table comprises third table header information, and the third table header information comprises at least one of the following naming identification information: line index, signal name, module name, target, description, trigger mode, suspension state and configuration register address.

7. The method of managing a line interruption of claim 1, wherein, The obtaining of the second input comprises: obtaining the second input based on the target line interrupt controller and the register transfer level of the integrated circuit, and according to a list rule of listing register transfer level file information row by row from top to bottom on the register transfer level until a level of the target line interrupt controller. 8.The method for managing line interrupts according to claim 1, wherein the configuration parameters comprise control parameters in the form of key-value pairs, and the control parameters comprise one or more of the following: line interrupt controller module name, top level module name and maximum number of external line interrupts required to be supported.

9. The method of managing a line interruption of claim 1, wherein, The at least one output includes: The at least one output is obtained automatically based on the first input, the second input and the third input through a script program.

10. The method of managing a line interruption of claim 1, wherein, The at least one output includes: The first table is updated based on the second table to obtain the third table.

11. The method of managing a line interruption of claim 1, wherein, The at least one output includes: The single-layer interrupt information summary signal of the line interrupt information corresponding to each level in the target multi-level is obtained based on the second interrupt information set, and The single-layer interrupt information summary signal corresponding to each current level in the target multi-level is modularly transmitted to a next level connected with the current level from top to bottom by a top layer on the register transfer level, until all single-layer interrupt information summary signals of the target multi-level are collected to the target line interrupt controller to obtain the hierarchical line interrupt connection result.

12. The method of claim 1, further comprising: iteratively correcting at least one of the first input, the second input and the third input until the check result is consistent with the comparison in response to the check result being inconsistent with the comparison.

13. The method of managing a line interruption of claim 1, wherein, In response to the target line interrupt controller being N, the method of managing line interrupt is configured to correspondingly perform N times according to N target line interrupt controllers, where N is an integer greater than or equal to 2.

14. An apparatus for managing line interrupt, comprising: a first input obtaining module configured to obtain a first input, wherein the first input includes a first table and a second table, the first table is configured to be a table to be filled in mapping, and the second table includes a first interrupt information set; a second input obtaining module configured to obtain a second input, wherein the second input includes a second interrupt information set corresponding to a target multi-level in a register transfer level of an integrated circuit, and the target multi-level includes a plurality of levels from a last level of a target line interrupt controller in the register transfer level to a top level of the register transfer level; a third input obtaining module configured to obtain a third input, wherein the third input includes configuration parameters corresponding to the first input and / or the second input; an output obtaining module, configured to automatically obtain at least one output of a check result, a hierarchical line interruption connection result, and a third table based on the first input, the second input, and the third input, wherein the check result comprises a result of consistency comparison based on the first interruption information set and the second interruption information set, the hierarchical line interruption connection result comprises a line interruption connection code corresponding to the target multi-level, and the third table comprises an interruption mapping table obtained based on updating the first table by using the second table.

15. An electronic device comprising: a processor and a memory, wherein the memory has stored thereon a computer program, and the computer program is executed by the processor to implement the method in any one of claims 1 to 13.

16. A computer readable storage medium, wherein, the storage medium has stored thereon a computer program, and the computer program is executed by the processor to implement the method in any one of claims 1 to 13.

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