Cluster construction method, market information data processing method and device and electronic equipment
By building a cluster of FPGA acceleration cards and using multiple FPGA acceleration cards for cascading processing, the performance bottleneck problem of a single FPGA acceleration card when processing large-scale market data is solved, and efficient and flexible market data processing is achieved to adapt to the complex and changeable market environment.
Patent Information
- Application Number
- CN202411840649.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-03-28
AI Technical Summary
A single FPGA acceleration card is prone to performance bottlenecks when processing large-scale, complex and changeable market data, and hardware upgrades require time and cost, and cannot respond to demand changes in real time.
By cascading multiple FPGA acceleration cards through cascading channels to form a cluster, each FPGA acceleration card establishes a communication connection with the server through the PCIe interface, and uses multiple FPGA acceleration cards to coordinate the market data to output the target market data.
It realizes efficient processing of large-scale and complex and variable market data, improves overall system performance, and has the ability to flexibly adjust the allocation of hardware resources to adapt to the needs of different application scenarios.
Smart Images
Figure CN119719007A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of computer and communication technology, and relates to a cluster construction method, a market data processing method and device, and an electronic device. Background Art
[0002] With the rapid development of programmatic trading, participants in the securities market are increasingly dependent on real-time, accurate and extremely short-delay market data. This trading strategy usually relies on fast-response algorithms to capture price changes, and even a small price advantage may be the key to profitability. Therefore, exchanges, trading platforms and technology providers are working hard to improve the speed and reliability of data transmission to meet millisecond or even nanosecond latency requirements. High-performance hardware facilities, optimized data processing pipelines and efficient communication protocols have become important links in achieving low-latency market services.
[0003] Currently, FPGA (Field-Programmable Gate Array) chips are gradually becoming dominant in low-latency market data processing. The advantage of FPGA is that it can provide customized computing power and high-speed data stream processing capabilities through hardware-level programming. Since the FPGA architecture can directly map the algorithm logic and reduce the overhead between software levels, it means that data can be processed and forwarded faster at the hardware level, thereby significantly reducing latency. In addition, FPGA also has good parallelism and reconfigurability, and can adapt to the ever-changing market environment and complex trading strategy requirements.
[0004] Although FPGA performs well in low-latency data processing due to its high performance and flexibility, it still has certain limitations. On the one hand, each FPGA chip has a fixed resource pool, which determines the maximum concurrent data flow and throughput it can support. If the amount of data is too large or the data source increases dramatically, exceeding the processing capacity of a single card, performance bottlenecks may occur. In addition, hardware upgrades also require time costs and do not respond to changes in demand in real time. Summary of the invention
[0005] The purpose of this application is to provide a cluster construction method, a market data processing method and device, and an electronic device, which are used to solve the performance bottleneck problem faced by a single FPGA acceleration card in the prior art when processing large-scale, complex and changeable market data.
[0006] In a first aspect, the present application provides a method for constructing an FPGA acceleration card cluster, comprising: cascading multiple FPGA acceleration cards through a cascade channel, wherein each of the FPGA acceleration cards is equipped with at least two market data input interfaces, and each of the market data input interfaces is used to obtain market data from different network links; the cascade channel is used to transmit the cascade data generated by the FPGA acceleration card of the previous level to the FPGA acceleration card of the current level; each of the FPGA acceleration cards establishes a communication connection with a server through a PCIe interface; the server is used to send the configuration items obtained by accessing the configuration register to the corresponding FPGA acceleration card; in the FPGA acceleration card of the current level, the market data and the cascade data of the previous level are processed based on the configuration items to obtain the cascade data of the current level.
[0007] In an implementation of the first aspect, cascading multiple FPGA acceleration cards through a cascade channel includes serial connection, parallel connection, and serial-parallel mixed connection.
[0008] In an implementation of the first aspect, the market data and the cascade data of the previous level are processed based on the configuration item to obtain the cascade data of the current level, including:
[0009] Decoding the market data to obtain decoded market data;
[0010] Filtering the cascade data of the previous level to obtain filtered cascade data;
[0011] Performing optimal processing on the decoded market data and the filtered cascade data to obtain optimal market data;
[0012] The output format of the market optimization data is adjusted based on the configuration item.
[0013] In an implementation of the first aspect, performing optimal processing on the decoded market data and the filtered cascade data to obtain the optimal market data includes:
[0014] Get the timestamp field t in the decoded market data 1i , where i∈[1,n], n represents the number of market data input interfaces equipped by the FPGA acceleration card at the current level;
[0015] Obtaining the timestamp field t2 in the filtered cascade data;
[0016] t 1i Compare with the size of t2;
[0017] If 1i >t2, then t1i The corresponding decoded market data is used as the market preferred data;
[0018] If 1i <t2, the filtered cascade data is used as the market optimization data.
[0019] In an implementation of the first aspect, adjusting the output format of the market optimization data based on the configuration item includes:
[0020] Determine whether the FPGA acceleration card at the current level is the FPGA acceleration card at the last level;
[0021] If yes, adjusting the cascade data of the current level into a customer data format based on the configuration item, and outputting the cascade data in the customer data format as target market data;
[0022] Otherwise, the cascade data of the current level is adjusted to a cascade output format based on the configuration item, and the cascade data having the cascade output format is input to the FPGA acceleration card of the next level.
[0023] In a second aspect, the present application provides a market data processing method, including: constructing an FPGA acceleration card cluster according to any of the methods described above; the FPGA acceleration card cluster includes multiple cascaded FPGA acceleration cards; obtaining market data from multiple network links; the number of the network links matches the number of the FPGA acceleration cards in the FPGA acceleration card cluster; distributing the market data to each of the FPGA acceleration cards in the FPGA acceleration card cluster; and using multiple FPGA acceleration cards to collaboratively process the market data to output one channel of target market data.
[0024] In a third aspect, the present application provides a market data processing device, including: a cluster construction module, used to construct an FPGA acceleration card cluster according to the method described in any one of the above items; the FPGA acceleration card cluster includes multiple cascaded FPGA acceleration cards; a data acquisition module, used to obtain market data from multiple network links; the number of network links matches the number of FPGA acceleration cards in the FPGA acceleration card cluster; a data distribution module, used to distribute the market data to each of the FPGA acceleration cards in the FPGA acceleration card cluster; a data processing module, used to use multiple FPGA acceleration cards to collaboratively process the market data to output one channel of target market data.
[0025] In an implementation of the third aspect, multiple FPGA acceleration cards are cascaded through a cascade channel, and the cascade channel is used to transmit the cascade data generated by the FPGA acceleration card of the previous level to the FPGA acceleration card of the current level; each FPGA acceleration card establishes a communication connection with the server through a PCIe interface; and the server is used to send the configuration items obtained by accessing the configuration register to the corresponding FPGA acceleration card.
[0026] In an implementation of the third aspect, the FPGA acceleration card includes:
[0027] A market data decoding module, used to decode the market data to obtain decoded market data;
[0028] A cascade filtering module, used for filtering the cascade data of the previous level to obtain filtered cascade data;
[0029] A market optimization module, used for performing optimization processing on the decoded market data and the filtered cascade data to obtain market optimization data;
[0030] An output configuration module is used to adjust the output format of the market optimization data based on the configuration items.
[0031] In a fourth aspect, the present application provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program stored in the memory, so that the electronic device performs any of the methods described above.
[0032] As described above, the cluster construction method, market data processing method and device, and electronic device described in this application realize the networking operation of multiple FPGA acceleration cards by constructing an FPGA acceleration card cluster, thereby being able to effectively cope with large-scale and complex market data processing tasks. In addition, this application has the ability to flexibly adjust the hardware resource configuration of the FPGA acceleration card according to the actual application scenario, thereby realizing the flexible deployment of the FPGA acceleration card cluster and significantly improving the overall system performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 Shown is a schematic structural diagram of a mobile terminal described in the present application in one embodiment.
[0034] Figure 2 Shown is a flowchart of an embodiment of the FPGA acceleration card cluster construction method described in this application.
[0035] Figure 3 Shown is a schematic diagram of the structure of the FPGA acceleration card cluster described in this application in one embodiment.
[0036] Figure 4 Shown is a schematic diagram of the structure of the FPGA acceleration card cluster described in this application in another embodiment.
[0037] Figure 5 Shown is a schematic diagram of the structure of the FPGA acceleration card cluster described in this application in another embodiment.
[0038] Figure 6 Shown is a flowchart of another embodiment of the FPGA acceleration card cluster construction method described in this application.
[0039] Figure 7 Shown is a flowchart of filtering cascade data in one embodiment of the FPGA acceleration card cluster construction method described in this application.
[0040] Figure 8 Shown is a flowchart of adjusting the output format of market optimization data in one embodiment of the FPGA acceleration card cluster construction method described in this application.
[0041] Fig. 9 Shown is a flow chart of a market data processing method described in this application in one embodiment.
[0042] Fig.10 Shown is a schematic diagram of the structure of the market data processing device described in this application in one embodiment.
[0043] Fig.11 Shown is a schematic diagram of the structure of the FPGA acceleration card described in this application in one embodiment.
[0044] Fig.12 Shown is a schematic structural diagram of an electronic device described in this application in an embodiment. DETAILED DESCRIPTION
[0045] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
[0046] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application, and thus the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.
[0047] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.
[0048] The following embodiments of the present application provide a cluster construction method, a market data processing method and device, and an electronic device. By constructing an FPGA accelerator card cluster, the present application realizes the networking operation of multiple FPGA accelerator cards, thereby being able to effectively cope with large-scale and complex market data processing tasks. In addition, the present application has the ability to flexibly adjust the hardware resource configuration of the FPGA accelerator card according to the actual application scenario, thereby realizing the flexible deployment of the FPGA accelerator card cluster and significantly improving the overall system performance.
[0049] The cluster construction method and market data processing method provided in the embodiment of the present application can be run in a mobile terminal, a computer terminal or similar device. Taking running on the mobile terminal as an example, Figure 1 The hardware structure block diagram of the mobile terminal described in this application is shown. Figure 1 As shown, the mobile terminal may include: a processor and a memory, the processor may be a central processing unit, and the memory is used to store data. Figure 1 The mobile terminal in the figure is only used as an example and does not limit the specific structure of the mobile terminal.
[0050] Optionally, the mobile terminal may further include: a communication transmission device and an input and output device.
[0051] Optionally, the memory may be used to store computer programs, such as software programs and modules of application software, and the memory may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory may further include a memory remotely arranged relative to the processor, and these remote memories may be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
[0052] Optionally, the communication transmission device can be used to receive or send data via a network, which may include a wireless network provided by a communication provider of the mobile terminal. The communication transmission device may include a NIC (Network Interface Controller) that can be connected to other network devices through a base station so as to communicate with the Internet.
[0053] The technical solutions in the embodiments of the present application will be described in detail below in conjunction with the drawings in the embodiments of the present application.
[0054] See also Figure 2 , which is a flow chart of the FPGA acceleration card cluster construction method described in this application in one embodiment. Figure 2 As shown, an embodiment of the present application provides a method for constructing an FPGA acceleration card cluster, including the following steps S100 to S300.
[0055] In step S100, multiple FPGA acceleration cards are cascaded through a cascade channel.
[0056] Specifically, each of the FPGA acceleration cards is equipped with at least two market data input interfaces, and each of the market data input interfaces is used to obtain market data from different network links.
[0057] The cascade channel is used to transmit the cascade data generated by the FPGA acceleration card at the previous level to the FPGA acceleration card at the current level.
[0058] In an embodiment of the present application, each FPGA accelerator card in the FPGA accelerator card cluster can be regarded as an independent computing unit. This means that each FPGA accelerator card can independently undertake specific market data processing tasks. In addition, the present application can build a more powerful computing platform by cascading multiple FPGA accelerator cards to process larger or more complex and changeable market data, which can not only increase the overall computing power, but also improve the fault tolerance of the system. For example, when an FPGA accelerator card fails, other FPGA accelerator cards that are working normally can still continue to provide computing power, thereby reducing the potential threat of single point failures to the stability of the entire cluster.
[0059] To simplify the management and deployment process, all FPGA accelerator cards can use the same firmware and be configured to execute the same functions or algorithms.
[0060] It should be noted that the number of FPGA accelerator cards in the FPGA accelerator card cluster can be dynamically adjusted according to the size of hardware resources and the scale of market data to be processed to achieve on-demand configuration. For example, if 5 FPGA accelerator cards have been deployed in the FPGA accelerator card cluster, and each FPGA accelerator card can receive 4 channels of market data, the maximum processing capacity of the FPGA accelerator card cluster is 20 channels of market data. Users can appropriately increase or decrease the number of FPGA accelerator cards according to actual needs to adjust the scale of the FPGA accelerator card cluster.
[0061] In one embodiment of the present application, cascading multiple FPGA acceleration cards through a cascade channel includes serial connection, parallel connection, and serial-parallel mixed connection.
[0062] See also Figure 3 , which is a schematic diagram of the structure of the FPGA acceleration card cluster described in this application in one embodiment. Figure 3 As shown, the FPGA acceleration card cluster includes three components, namely, FPGA acceleration card A, FPGA acceleration card B and FPGA acceleration card C, wherein FPGA acceleration card A, FPGA acceleration card B and FPGA acceleration card C are connected in series.
[0063] Specifically, FPGA accelerator card A is provided with two market data input interfaces A1 and A2, FPGA accelerator card B is provided with two market data input interfaces B1 and B2, and FPGA accelerator card C is provided with two market data input interfaces C1 and C2. FPGA accelerator card A and FPGA accelerator card B are connected via a cascade channel a, one end of the cascade channel a is the cascade data output interface of FPGA accelerator card A, and the other end is the cascade data input interface of FPGA accelerator card B. FPGA accelerator card B and FPGA accelerator card C are connected via a cascade channel b, one end of the cascade channel b is the cascade data output interface of FPGA accelerator card B, and the other end is the cascade data input interface of FPGA accelerator card C. FPGA accelerator card C is provided with a cascade data output interface for outputting target market data.
[0064] See also Figure 4 , which is a schematic diagram of the structure of the FPGA acceleration card cluster described in this application in another embodiment. Figure 4 As shown, the FPGA acceleration card cluster includes three components, namely, FPGA acceleration card A, FPGA acceleration card B and FPGA acceleration card C, wherein FPGA acceleration card A, FPGA acceleration card B and FPGA acceleration card C are connected in series and parallel.
[0065] Specifically, FPGA accelerator card A is provided with two market data input interfaces A1 and A2, FPGA accelerator card B is provided with two market data input interfaces B1 and B2, and FPGA accelerator card C is provided with two market data input interfaces C1 and C2. FPGA accelerator card A and FPGA accelerator card C are connected via a cascade channel a, one end of the cascade channel a is the cascade data output interface of FPGA accelerator card A, and the other end is the first cascade data input interface of FPGA accelerator card C. FPGA accelerator card B and FPGA accelerator card C are connected via a cascade channel b, one end of the cascade channel b is the cascade data output interface of FPGA accelerator card B, and the other end is the second cascade data input interface of FPGA accelerator card C. FPGA accelerator card C is provided with a cascade data output interface for outputting target market data.
[0066] See also Figure 5 , which is a schematic diagram of the structure of the FPGA acceleration card cluster described in this application in another embodiment. Figure 5 As shown, the FPGA acceleration card cluster includes four components, namely, FPGA acceleration card A, FPGA acceleration card B, FPGA acceleration card C and FPGA acceleration card D. Among them, FPGA acceleration card A, FPGA acceleration card B, FPGA acceleration card C and FPGA acceleration card D are connected in series and parallel.
[0067] Specifically, FPGA accelerator card A is provided with two market data input interfaces A1 and A2, FPGA accelerator card B is provided with two market data input interfaces B1 and B2, FPGA accelerator card C is provided with two market data input interfaces C1 and C2, and FPGA accelerator card D is provided with two market data input interfaces D1 and D2. FPGA accelerator card A and FPGA accelerator card D are connected through a cascade channel a, one end of the cascade channel a is the cascade data output interface of FPGA accelerator card A, and the other end is the first cascade data input interface of FPGA accelerator card D. FPGA accelerator card C and FPGA accelerator card B are connected through a cascade channel c, one end of the cascade channel c is the cascade data output interface of FPGA accelerator card C, and the other end is the cascade data input interface of FPGA accelerator card B. FPGA accelerator card B and FPGA accelerator card D are connected through a cascade channel b, one end of the cascade channel b is the cascade data output interface of FPGA accelerator card B, and the other end is the second cascade data input interface of FPGA accelerator card D. FPGA accelerator card D is provided with a cascade data output interface for outputting target market data.
[0068] In step S200, each of the FPGA acceleration cards establishes a communication connection with the server through a PCIe interface.
[0069] Specifically, the server is used to send the configuration items obtained by accessing the configuration register to the corresponding FPGA acceleration card.
[0070] In the embodiment of the present application, the configuration register is an external configuration component independent of the FPGA acceleration card cluster, and its function is to store a series of specific configuration items. The configuration items are used to adjust the hierarchical properties of the FPGA acceleration card in the FPGA acceleration card cluster. Figure 3 As shown in the figure, when the configuration value of FPGA accelerator card A is set to 0, FPGA accelerator card A is defined as the starting-level accelerator card; if the configuration value of FPGA accelerator card B is set to 1, it indicates that FPGA accelerator card B is an intermediate-level accelerator card under FPGA accelerator card A; similarly, if the configuration value of FPGA accelerator card C is also set to 1, it indicates that FPGA accelerator card C belongs to the last-level accelerator card in the entire accelerator card cluster.
[0071] In this implementation, by setting configuration items for the FPGA accelerator card, the role and status of each FPGA accelerator card in the entire cluster architecture can be flexibly defined and adjusted.
[0072] In step S300, in the FPGA acceleration card of the current level, the market data and the cascade data of the previous level are processed based on the configuration items to obtain the cascade data of the current level.
[0073] In an embodiment of the present application, the "current level" FPGA acceleration card is located at the second level or above in the FPGA acceleration card cluster by default, which means that before the current level FPGA acceleration card, there is at least one previous level FPGA acceleration card, and the previous level FPGA acceleration card is used to provide cascade data to the current level FPGA acceleration card.
[0074] In the FPGA acceleration card at the starting level, the market data is input through the market data input interface; the market data is processed based on the configuration items to obtain the cascade data of the starting level; and the cascade data of the starting level is sent to the FPGA acceleration card at the next level through the cascade data output interface.
[0075] In the intermediate-level FPGA acceleration card, the market data is input through the market data input interface; the cascade data of the previous level is input through the cascade data input interface; the market data and the cascade data of the previous level are processed based on the configuration items to obtain the cascade data of the current level; and the cascade data of the current level is sent to the next-level FPGA acceleration card through the cascade data output interface.
[0076] And so on, until the FPGA acceleration card at the last level outputs the cascade data, and the cascade data at the last level is used as the target market data.
[0077] See also Figure 6 , which is a flow chart of another embodiment of the method for constructing a FPGA acceleration card cluster described in this application. Figure 6 As shown, the market data and the cascade data of the previous level are processed based on the configuration item to obtain the cascade data of the current level, including: decoding the market data to obtain decoded market data; filtering the cascade data of the previous level to obtain filtered cascade data; performing optimal processing on the decoded market data and the filtered cascade data to obtain market optimal data; and adjusting the output format of the market optimal data based on the configuration item.
[0078] It should be noted that there are no specific restrictions or requirements on the way of decoding the market data in the embodiment of the present application. In other words, no matter what method is used to decode the market data, as long as the relevant conditions and requirements of the present application are met, it can be applied to the present application.
[0079] See also Figure 7 , which is a flowchart of filtering cascade data in an embodiment of the FPGA acceleration card cluster construction method described in this application. Figure 7 As shown, the present application filters the cascade data of the previous level to obtain the filtered cascade data including: extracting feature quantities from the cascade data of the previous level; comparing the extracted feature quantities with the standard feature quantities to determine whether the extracted feature quantities are consistent with the standard feature quantities; if so, retaining the cascade data of the previous level for subsequent optimization processing; otherwise discarding the cascade data of the previous level.
[0080] In the embodiment of the present application, the filtering step is used to identify and eliminate non-node data to ensure that the data stream input to the current-level FPGA acceleration card only contains cascade data that meets the preset standards.
[0081] In this implementation, a filtering mechanism is used to effectively distinguish which cascade data meets the standards, while excluding other data that does not meet the standards. This not only optimizes the data processing flow, but also plays a key protective role, preventing non-compliant data from interfering with the normal operation of the FPGA accelerator card or causing potential security risks.
[0082] In one embodiment of the present application, the decoded market data and the filtered cascade data are optimally processed to obtain the optimal market data, including: obtaining the timestamp field t in the decoded market data 1i, where i∈[1,n], n represents the number of market data input interfaces equipped by the FPGA acceleration card at the current level; obtaining the timestamp field t2 in the filtered cascade data; and performing a 1i and t2; if t 1i >t2, then t 1i The corresponding decoded market data is used as the market optimization data; if t 1i <t2, the filtered cascade data is used as the market optimization data.
[0083] In actual applications, market data from different data sources may be transmitted through multiple network links. Since the performance and latency of each network link may be different, the time when the market data finally arrives at each FPGA accelerator card may vary.
[0084] In the embodiment of the present application, one channel of target market data is determined based on the time priority principle. This process not only improves the efficiency of data processing, but also ensures the timeliness and accuracy of information acquisition.
[0085] See also Figure 8 , which is a flow chart showing the method for constructing a FPGA acceleration card cluster described in this application, in one embodiment, adjusting the output format of the market optimization data. Figure 8 As shown, adjusting the output format of the market preferred data based on the configuration item includes: determining whether the FPGA acceleration card of the current level is the FPGA acceleration card of the last level; if so, adjusting the cascade data of the current level to the customer data format based on the configuration item, and outputting the cascade data with the customer data format as the target market data; otherwise, adjusting the cascade data of the current level to the cascade output format based on the configuration item, and inputting the cascade data with the cascade output format to the FPGA acceleration card of the next level.
[0086] In the embodiment of the present application, the position of the component determines the data output format of the FPGA accelerator card. Specifically, the cascaded data output by the initial and intermediate FPGA accelerator cards adopts the cascaded output format, which can ensure that the data is efficiently and consistently transmitted between different FPGA accelerator cards; while the cascaded data output by the last FPGA accelerator card adopts the customer data format, which is convenient for the end user or application to directly use the data.
[0087] It should be noted that the protection scope of the FPGA acceleration card cluster construction method described in the embodiment of the present application is not limited to the execution order of the steps listed in this embodiment. All solutions implemented by adding, reducing or replacing steps in the prior art based on the principles of the present application are included in the protection scope of the present application.
[0088] See also Fig. 9 , which is a flow chart of the market data processing method described in this application in one embodiment. Fig. 9 As shown, an embodiment of the present application provides a market data processing method, including the following steps S400 to S700.
[0089] In step S400, an FPGA acceleration card cluster is constructed according to the method described in steps S100 to S300.
[0090] Specifically, the FPGA acceleration card cluster includes a plurality of cascaded FPGA acceleration cards. Each of the FPGA acceleration cards is equipped with at least two market data input interfaces, and each of the market data input interfaces is used to obtain market data from different network links.
[0091] In step S500, market data is obtained from multiple network links.
[0092] Specifically, the number of the network links matches the number of the FPGA accelerator cards in the FPGA accelerator card cluster. For example, when 20 channels of market data to be processed are obtained from the network link, 5 FPGA accelerator cards can be deployed in the FPGA accelerator card cluster according to demand, and each FPGA accelerator card is used to receive 4 channels of market data.
[0093] In step S600, the market data is distributed to each of the FPGA acceleration cards in the FPGA acceleration card cluster.
[0094] In step S700, the market data is collaboratively processed using a plurality of the FPGA acceleration cards to output one channel of target market data.
[0095] exist Figure 3 In the embodiment shown, after completing the market data processing, FPGA accelerator card A will pass the cascade data to FPGA accelerator card B. Subsequently, FPGA accelerator card B processes the received market data and cascade data, and further passes the obtained new cascade data to FPGA accelerator card C. Finally, the cascade data output by FPGA accelerator card C is used as the target market data. In this process, parallel processing of market data is achieved between FPGA accelerator cards A, B and C.
[0096] It should be noted that the protection scope of the market data processing method described in the embodiment of the present application is not limited to the execution order of the steps listed in this embodiment. All solutions implemented by adding, reducing or replacing steps in the prior art based on the principles of the present application are included in the protection scope of the present application.
[0097] See also Fig.10, which is a schematic diagram of the structure of the market data processing device described in this application in one embodiment. Fig.10 As shown, an embodiment of the present application provides a market data processing device, including a cluster construction module, a data acquisition module, a data distribution module and a data processing module.
[0098] The cluster building module is used to build an FPGA acceleration card cluster according to the method described in steps S100 to S300 above; the FPGA acceleration card cluster includes multiple cascaded FPGA acceleration cards.
[0099] The data acquisition module is used to acquire market data from multiple network links; the number of the network links matches the number of the FPGA acceleration cards in the FPGA acceleration card cluster.
[0100] The data distribution module is used to distribute the market data to each of the FPGA acceleration cards in the FPGA acceleration card cluster.
[0101] The data processing module is used to utilize a plurality of the FPGA acceleration cards to collaboratively process the market data to output one channel of target market data.
[0102] It should be noted that the structures and principles of the cluster construction module, data acquisition module, data distribution module and data processing module in the embodiment of the present application correspond one-to-one to the steps in the above-mentioned market data processing method, so they will not be repeated here.
[0103] In one embodiment of the present application, a plurality of the FPGA acceleration cards are cascaded via a cascade channel, and the cascade channel is used to transmit the cascade data generated by the FPGA acceleration card of the previous level to the FPGA acceleration card of the current level.
[0104] In one embodiment of the present application, each of the FPGA acceleration cards establishes a communication connection with the server via a PCIe interface; the server is used to send the configuration items obtained by accessing the configuration register to the corresponding FPGA acceleration card.
[0105] See also Fig.11 , which is a schematic diagram of the structure of the FPGA acceleration card described in this application in one embodiment. Fig.11 As shown, the FPGA acceleration card includes a market decoding module, a cascade filtering module, a market optimization module and an output configuration module.
[0106] The market data decoding module is used to decode the market data to obtain decoded market data.
[0107] The cascade filtering module is used to filter the cascade data of the previous level to obtain filtered cascade data.
[0108] The market optimization module is used to perform optimization processing on the decoded market data and the filtered cascade data to obtain market optimization data.
[0109] The output configuration module is used to adjust the output format of the market optimization data based on the configuration items.
[0110] exist Figure 3 In the embodiment shown, first, FPGA accelerator card A receives two channels of market data A1 and A2. A1 and A2 are decrypted by the market decoding module respectively, and the decoded market data a1 and a2 are output. Then the a1 and a2 data enter the market optimization module, and the market optimization data a_sel with the advantage in time is selected. Then a_sel enters the output configuration module. Since FPGA accelerator card A is not the last level of the FPGA accelerator card cluster, the output configuration should be a cascade output format, so that a_sel outputs A_out to the next level FPGA accelerator card B in a cascade output format.
[0111] Similarly, FPGA accelerator card B receives two channels of market data B1 and B2, as well as cascade data A_out from FPGA accelerator card A. B1 and B2 are decrypted by the market decoding module, and the decoded market data b1 and b2 are output. Then b1, b2 and A_out enter the market optimization module together, and the market optimization data b_sel with superior time is selected. After that, b_sel enters the output configuration module. Since FPGA accelerator card B is not the last level of the cascade cluster, the output configuration should also be in the cascade output format. In this way, b_sel outputs B_out to the next level FPGA accelerator card C in the cascade output format.
[0112] Finally, FPGA accelerator card C receives two channels of market data C1 and C2, as well as the cascaded data B_out from component B. C1 and C2 are decrypted by the market decoding module, and the decoded market data c1 and c2 are output. Then c1, c2 and B_out enter the market optimization module together, and the market optimization data c_sel with superior time is selected. After that, c_sel enters the output configuration module. At this time, FPGA accelerator card C is already the last level of the cluster. The output configuration of FPGA accelerator card C should be the customer data format, and finally C_out is output to the customer in the customer data format.
[0113] It should be noted that the market data processing device provided in the embodiment of the present application can implement the market data processing method described in the present application, but the implementation device of the market data processing method described in the present application includes but is not limited to the structure of the market data processing device listed in the present embodiment. All structural deformations and replacements of the prior art made according to the principles of the present application are included in the protection scope of the present application.
[0114] See also Fig.12 , which is a schematic diagram of the structure of an electronic device described in this application in one embodiment. Fig.12 As shown, an embodiment of the present application provides an electronic device, including a memory and a processor.
[0115] The memory is used to store computer programs.
[0116] The processor is used to execute the computer program stored in the memory so that the electronic device executes any one of the above methods.
[0117] In the several embodiments provided in the present application, it should be understood that the disclosed system, device or method can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules / units is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules or units, which can be electrical, mechanical or other forms.
[0118] The modules / units described as separate components may or may not be physically separated, and the components displayed as modules / units may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules / units may be selected according to actual needs to achieve the purpose of the embodiments of the present application. For example, the functional modules / units in the various embodiments of the present application may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.
[0119] Those of ordinary skill in the art should further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0120] The present application embodiment also provides a computer-readable storage medium. A person of ordinary skill in the art can understand that all or part of the steps in the method for implementing the above embodiment can be completed by a program to instruct the processor, and the program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state hard disk, a magnetic tape, a floppy disk, an optical disc, and any combination thereof. The above storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a digital video disc (DVD)), or a semiconductor medium (e.g., a solid-state hard disk (SSD)), etc.
[0121] The present application embodiment may also provide a computer program product, the computer program product including one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the process or function described in the embodiment of the present application is generated in whole or in part. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer or data center.
[0122] When the computer program product is executed by a computer, the computer executes the method described in the above method embodiment. The computer program product may be a software installation package, and when the above method is required, the computer program product may be downloaded and executed on a computer.
[0123] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.
[0124] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.
Claims
1. A method for constructing an FPGA acceleration card cluster, characterized in that: include: Cascading multiple FPGA acceleration cards through a cascading channel, wherein each of the FPGA acceleration cards is equipped with at least two market data input interfaces, each of which is used to obtain market data from different network links; the cascading channel is used to transmit the cascade data generated by the FPGA acceleration card of the previous level to the FPGA acceleration card of the current level; Establishing a communication connection between each FPGA acceleration card and a server through a PCIe interface; the server is used to send the configuration items obtained by accessing the configuration register to the corresponding FPGA acceleration card; In the FPGA acceleration card of the current level, the market data and the cascade data of the previous level are processed based on the configuration items to obtain the cascade data of the current level.
2. The method according to claim 1, characterized in that Cascading multiple FPGA acceleration cards through cascading channels includes serial connection, parallel connection, and serial-parallel mixed connection.
3. The method according to claim 1, characterized in that The market data and the cascade data of the previous level are processed based on the configuration item to obtain the cascade data of the current level, including: Decoding the market data to obtain decoded market data; Filtering the cascade data of the previous level to obtain filtered cascade data; Performing optimal processing on the decoded market data and the filtered cascade data to obtain optimal market data; The output format of the market optimization data is adjusted based on the configuration item.
4. The method according to claim 3, characterized in that The decoded market data and the filtered cascade data are optimally processed to obtain market optimal data including: Get the timestamp field t in the decoded market data 1i , where i∈[1,n], n represents the number of market data input interfaces equipped by the FPGA acceleration card at the current level; Obtaining the timestamp field t2 in the filtered cascade data; t 1i Compare with the size of t2; If 1i >t2, then t 1i The corresponding decoded market data is used as the market preferred data; If 1i <t2, the filtered cascade data is used as the market optimization data.
5. The method according to claim 3, characterized in that: Adjusting the output format of the market optimization data based on the configuration item includes: Determine whether the FPGA acceleration card at the current level is the FPGA acceleration card at the last level; If yes, adjusting the cascade data of the current level into a customer data format based on the configuration item, and outputting the cascade data in the customer data format as target market data; Otherwise, the cascade data of the current level is adjusted to a cascade output format based on the configuration item, and the cascade data having the cascade output format is input to the FPGA acceleration card of the next level.
6. A market data processing method, characterized in that: include: Constructing an FPGA acceleration card cluster according to the method described in any one of claims 1 to 5; the FPGA acceleration card cluster comprises a plurality of cascaded FPGA acceleration cards; Acquire market data from a plurality of network links; the number of the network links matches the number of the FPGA acceleration cards in the FPGA acceleration card cluster; Distribute the market data to each of the FPGA acceleration cards in the FPGA acceleration card cluster; The market data is collaboratively processed using a plurality of the FPGA acceleration cards to output a channel of target market data.
7. A market data processing device, characterized in that: include: A cluster building module, used to build an FPGA acceleration card cluster according to any one of the methods of claims 1 to 5; The FPGA acceleration card cluster includes multiple cascaded FPGA acceleration cards; A data acquisition module, used to acquire market data from a plurality of network links; the number of the network links matches the number of the FPGA acceleration cards in the FPGA acceleration card cluster; A data distribution module, used to distribute the market data to each of the FPGA acceleration cards in the FPGA acceleration card cluster; The data processing module is used to utilize a plurality of the FPGA acceleration cards to collaboratively process the market data to output a channel of target market data.
8. The device according to claim 7, characterized in that Multiple FPGA acceleration cards are cascaded through a cascade channel, and the cascade channel is used to transmit the cascade data generated by the FPGA acceleration card of the previous level to the FPGA acceleration card of the current level; each FPGA acceleration card establishes a communication connection with the server through the PCIe interface; the server is used to send the configuration items obtained by accessing the configuration register to the corresponding FPGA acceleration card.
9. The device according to claim 8, characterized in that The FPGA acceleration card includes: A market data decoding module, used to decode the market data to obtain decoded market data; A cascade filtering module, used for filtering the cascade data of the previous level to obtain filtered cascade data; A market optimization module, used for performing optimization processing on the decoded market data and the filtered cascade data to obtain market optimization data; An output configuration module is used to adjust the output format of the market optimization data based on the configuration items.
10. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program stored in the memory so as to enable the electronic device to execute the method according to any one of claims 1 to 6.