Integrated intelligent platform based on FPGA and embedded system

Abstract

The invention discloses an integrated intelligent platform based on an FPGA (Field Programmable Gate Array) and an embedded system, which comprises a core processing unit and a peripheral expansion circuit unit, the core processing unit comprises an FPGA unit and a dual-processor unit, and the dual-processor unit comprises two embedded processors which are interactively controlled. The FPGA unit is in bus connection with the two embedded processors of the dual-processor unit and performs data interaction with the two embedded processors of the dual-processor unit; the two embedded processors of the FPGA unit and the dual-processor unit are respectively provided with an external communication interface and a peripheral expansion circuit unit, and data exchange and control between the core processing unit and external equipment are realized through the peripheral expansion circuit unit. According to the invention, hardware bus connection and data interaction between the double processor units and the FPGA unit can be realized, and meanwhile, interaction control between the double processor units can be realized through bus connection, so that systematic teaching experiments can be conveniently carried out.

Description

Technical Field

[0001] The present invention relates to the technical field of educational equipment, and in particular to an integrated intelligent platform based on FPGA and embedded system. Background Art

[0002] The teaching content of colleges and vocational schools in computer and electronic information majors revolves around core courses such as microcomputer principles and interfaces, computer systems, and embedded development. These courses have high requirements for students' hardware and software knowledge, and are highly integrated with theory and practice. The teaching effect is directly restricted by laboratory conditions and learning resources. In the training process, different courses are distributed at different stages of learning, and there is a lack of connection between the contents. It is difficult for students to understand the connection between different course contents and how to apply them in professional fields during the learning process. Therefore, it is necessary to build a systematic experimental platform that supports multiple teaching contents. Most of the common experimental platforms on the market currently only target individual teaching contents, and lack the cross-integration of relevant professional knowledge in the field. Or the experimental content in the experimental platform is relatively single, involving only some knowledge points, and lacks an integrated teaching experimental platform that can run through the content of related professional courses. Summary of the invention

[0003] The purpose of the present invention is to provide an integrated intelligent platform based on FPGA and embedded system, which can enable students to learn the principles and applications of FPGA, single-chip microcomputer and embedded system in a simple and easy-to-understand way, and at the same time, enable students to gradually form a complete concept from hardware development to software development, improve students' practical operation ability and comprehensive application and innovative development of knowledge points.

[0004] The technical solution adopted by the present invention is: An integrated intelligent platform based on FPGA and embedded system includes a core processing unit and a peripheral expansion circuit unit. The core processing unit includes an FPGA unit and a dual processor unit. The dual processor unit includes two interactively controlled embedded processors. The FPGA unit is respectively connected to the two embedded processor buses of the dual processor unit and exchanges data. The FPGA unit and the two embedded processors of the dual processor unit are respectively provided with respective external communication interfaces and peripheral expansion circuit units. Data exchange and control between the core processing unit and external devices are realized through the peripheral expansion circuit unit.

[0005] Specifically, the experimental platform is powered by DC 12V and adopts a dual processor unit platform plus a programmable logic unit (FPGA) architecture. Both dual processor units can realize hardware bus connection and data interaction with high-performance programmable logic chips. At the same time, the two embedded processors exchange data through communication methods such as Ethernet, RS485 bus, and CAN bus to conduct relevant experiments. The overall architecture of the present invention is in a mesh form, and each core unit can be independent and interactive. The peripheral expansion circuit unit is interconnected with the core processing unit through a standard interface to realize data exchange and control between the core processing unit and the peripheral module.

[0006] Furthermore, the two embedded processors of the FPGA unit and the dual processor unit are both provided with debugging and downloading program interfaces, so that the management personnel can update and maintain the two embedded processors of the FPGA unit and the dual processor unit.

[0007] Furthermore, the FPGA unit and the dual processor unit are respectively connected to corresponding storage units.

[0008] Furthermore, the two embedded processors of the dual processor unit can control the function implementation of the peripheral expansion circuit unit of the FPGA unit through a bus or other means; the two embedded processors of the dual processor unit are used as FPGA unit signal source input tools to carry out basic functional experiments in conjunction with digital logic.

[0009] Furthermore, the two embedded processors are interactively controlled via Ethernet, RS485 bus or CAN bus.

[0010] Furthermore, one of the embedded processors in the dual-processor unit adopts Rockchip's flagship AIoT chip RK3588 platform, supports 8GB LPDDR memory, and supports 32GB eMMC storage; the external communication interface of one of the embedded processors in the dual-processor unit includes 1 Type-C USB with OTG download interface, 1 USB to TTL debugging interface, 2 USB2.0 interfaces, 2 USB3.0 interfaces, 1 RS485 interface, and 2 Ethernet interfaces; The communication bus between one of the embedded processors of the dual processor unit and the FPGA includes 1 RS485 bus, 1 SPI bus, 1 PCIe bus, 1 I2C bus, 2 GPIO interfaces, and 3 PWM interfaces; The communication interface between one embedded processor of the dual processor unit and the other embedded processor includes one RS485 bus and one CAN bus; The external devices connected to one of the embedded processors of the dual-processor unit include a MIPI LCD screen, a MIPI camera, an HDMI video output interface, an M.2 interface 5G communication module, an M.2 interface NVMe hard disk, 4 LED indicator lights, a reset button, a Maskrom download button, a Recovery download button, and a Wi-Fi / BT module that supports an SDIO interface.

[0011] Specifically, the RK3588 processor unit can carry out typical application experiments in communication, control, and measurement based on the Linux operating system. In addition, its 8-core 64-bit CPU, 4-core GPU, and AI accelerator NPU can support mainstream deep learning frameworks and AI-related experiments; Furthermore, the other embedded processor of the dual processor unit adopts an onboard high-performance 32-bit processor STM32F407. The external communication interface of the other embedded processor of the dual processor unit includes 1 USB to TTL debugging interface and 1 Ethernet interface; The communication bus between the other embedded processor of the dual processor unit and the FPGA unit includes 1 RS485 bus, 1 FSMC bus, 1 I2C bus, 1 SPI bus, 3 GPIO interfaces, and 3 PWM interfaces; The other embedded processor of the dual processor unit is connected with an external storage unit, including 16MB of SerialFlash memory and 1MB of SRAM.

[0012] The external devices of the other embedded processor of the dual processor unit include LED indicator, reset button, function button, 3*3 matrix keyboard, light sensor, 5V power supply actuator, relay; Specifically, the other embedded processor of the dual processor unit supports JTAG debugging; supports ADC sampling experiments; supports PWM basic experiments; supports 1-channel DAC output; supports GPIO, I2C, and UART expansion interface experiments.

[0013] Specifically, the onboard high-performance 32-bit processor STM32F407 is an ARM embedded unit. The ARM embedded unit supports basic peripheral development experiments of microcontrollers, including UART experiments, GPIO experiments, ADC data acquisition experiments of photosensors, PWM control breathing light experiments, SPI reading and writing Flash experiments, I2C reading and writing EEPROM experiments, Ethernet communication experiments, etc. It also supports the transplantation and development of operating systems such as FreeRTOS and RT-thread.

[0014] Furthermore, the FPGA unit uses the XC7A75T high-performance chip, and is connected to the two embedded processor buses and interacts with data through FSMC, RS485, PCIe, SPI, I2C, GPIO, and PWM interfaces. When conducting digital logic circuit experiments, both embedded processors can be used as signal source input tools to cooperate with the FPGA unit (programmable logic unit) to conduct basic function experiments and function expansion.

[0015] The external devices of the FPGA unit include OLED LCD screen, 3 groups of red, yellow and green lights, 1 group of 6-digit 8-segment digital tubes, 3 function buttons, 1 group of stepper motors, 1 relay control, 8-channel data acquisition DI interfaces, 8-channel device control DO interfaces, 6 groups of RS232 expansion interfaces and 2 groups of RS485 expansion interfaces.

[0016] Specifically, the FPGA unit can use hardware description language to program the FPGA, realize specific circuit design and hardware functions, and learn knowledge points such as microcomputer principles and interfaces, and the basics of digital circuits; the RK3588 processor unit of the first platform can carry out typical application experiments in communication, control, and measurement based on the Linux operating system. In addition, its 8-core 64-bit CPU, 4-core GPU and AI accelerator NPU can support mainstream deep learning frameworks and AI-related experiments; the ARM embedded unit of the second platform supports basic microcontroller peripheral development experiments, including UART experiments, GPIO experiments, ADC data acquisition experiments of photosensors, PWM control breathing light experiments, SPI reading and writing Flash experiments, I2C reading and writing EEPROM experiments, Ethernet communication experiments, etc., and also supports the transplantation and development of operating systems such as FreeRTOS and RT-thread.

[0017] The present invention adopts the above technical scheme, the core processing unit and the peripheral circuit unit are integrated on the same PCB board, and the transparent acrylic board is covered to protect the experimental platform PCB board. The relevant interfaces are all connected by KF2EDG 3.81MM plug-in PCB terminals, which can effectively avoid the problems of wrong connection, poor contact, loose pins, etc. of the pin arrangement wiring, and are convenient for systematic teaching experiments. Compared with other types of experimental platforms, the core units of this experimental platform can be developed and studied as independent modules, and can also communicate with each other through bus and other methods to control peripheral interfaces and devices to realize related functions. The more abundant external interfaces and experimental modules of this experimental platform overcome the shortcomings of the lack of onboard functional module resources of the existing teaching experimental platform circuit board, and can provide comprehensive experimental program development examples. While learning the principles and applications of FPGA, single-chip microcomputer, and embedded system in a simple way, it can also enable students to gradually form a complete concept from hardware development to software development, improve students' practical operation ability and comprehensive application and innovative development of knowledge points. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments; Figure 1 This is a schematic diagram of the structure of an integrated intelligent platform based on FPGA and embedded system of the present invention; Figure 2 A schematic diagram of the communication connection between the FPGA unit and the dual processor platform of the present invention; Figure 3 A schematic diagram of the communication interface between the FPGA unit of the present invention and an external device; Figure 4 A schematic diagram of a communication interface between a first platform of a dual-processor and an external device of the present invention; Figure 5 It is a schematic diagram of the communication interface between the second platform of the dual processor and an external device of the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0020] like Figures 1 to 5 As shown in one, the present invention discloses an integrated intelligent platform based on FPGA and embedded system, including a core processing unit and a peripheral expansion circuit unit, the core processing unit includes an FPGA unit and a dual processor unit, the dual processor unit includes two interactively controlled embedded processors, the FPGA unit is respectively connected to the two embedded processor buses of the dual processor unit and exchanges data; the FPGA unit and the two embedded processors of the dual processor unit respectively have their own external communication interface and peripheral expansion circuit unit, and data exchange and control between the core processing unit and external devices are realized through the peripheral expansion circuit unit.

[0021] Furthermore, the two embedded processors of the FPGA unit and the dual processor unit are both provided with debugging and downloading program interfaces, so that the management personnel can update and maintain the two embedded processors of the FPGA unit and the dual processor unit.

[0022] Furthermore, the FPGA unit and the dual processor unit are respectively connected to corresponding storage units.

[0023] Furthermore, the two embedded processors of the dual processor unit can control the function implementation of the peripheral expansion circuit unit of the FPGA unit through a bus or other means; the two embedded processors of the dual processor unit are used as FPGA unit signal source input tools to carry out basic functional experiments in conjunction with digital logic.

[0024] Furthermore, the two embedded processors are interactively controlled via Ethernet, RS485 bus or CAN bus.

[0025] The overall architecture is as follows Figure 1 As shown, the overall architecture of the present invention is in a mesh form, and each core unit can be independent and interactive.

[0026] The specific structure of the present invention is described in detail below. For the convenience of representation, one of the embedded processors in the dual processor unit is called a first platform processor unit, and the other embedded processor in the dual processor unit is called a second processor unit.

[0027] The FPGA unit communicates and interacts with the first platform processor unit through 3-way PWM, 2-way GPIO, SPI bus, I2C bus, RS485 bus, and PCIe bus. The first platform processor unit can control the peripheral expansion circuit unit functions of the FPGA unit through the bus and other means. The FPGA unit communicates and interacts with the second platform processor unit through 3-way PWM, 3-way GPIO, FSMC bus, RS485 bus, SPI bus, and I2C bus. The second platform processor unit can control the peripheral expansion circuit unit functions of the FPGA unit through the bus and other means. Both the first and second platform processor units can be used as FPGA unit signal source input tools to conduct basic functional experiments in conjunction with digital logic. The first platform and the second platform processor units can communicate through RS485 bus, CAN bus, Ethernet interface, etc. The communication connection between the FPGA unit and the dual processor platform is as follows: Figure 2 shown.

[0028] The FPGA unit is based on the XC7A75T high-performance chip, and can download chip firmware and debug development through the JTAG interface. Its extended 6-way RS232 communication interface is connected to the 12 I / Os of the FPGA chip, and the extended 2-way RS485 communication interface is connected to the 6 I / Os of the FPGA chip. The 16 I / Os of the FPGA chip are used as 8-way DI interfaces and 8-way DO interfaces, which can be connected to the switch quantity sensor for data acquisition. The peripheral expansion circuit unit of the FPGA unit includes an OLED display screen module, which includes an SH1106 chip and an OLED screen. The SH1106 chip communicates and controls the display with the FPGA chip through the SPI interface. The peripheral expansion circuit unit of the FPGA unit includes a group of 6-bit 8-segment digital tube modules, which are connected to the 6 I / Os of the FPGA chip through 6 groups of AP2301GN MOS tubes. The peripheral expansion circuit unit of the FPGA unit includes a relay module, which is connected to 1 I / O pin of the FPGA chip through the S8050 transistor drive circuit for actuator access and control. The peripheral expansion circuit unit of the FPGA unit includes three groups of red, yellow and green light modules, which are respectively connected to the nine I / O lines of the FPGA chip, and can realize the logical control content of experiments such as traffic lights through programming. The peripheral expansion circuit unit of the FPGA unit includes a stepper motor control interface module, which is connected to the three I / O lines of the FPGA chip, and is connected to the stepper motor driver after optical coupling isolation, so that the stepper motor can be controlled through the FPGA unit. The peripheral expansion circuit unit of the FPGA unit includes a function key module, which includes three keys and is connected to the three I / O lines of the FPGA chip. The external devices of the FPGA unit and the communication interface are as follows: Figure 3 shown.

[0029] The processor unit of the first platform is based on Rockchip's flagship AIoT chip RK3588, which includes a USB to TTL interface for debugging and development and a Type-C USB interface with OTG download function. The corresponding mode is entered through buttons such as the reset button, Maskrom download button, and Recovery download button. The peripheral expansion circuit of the first platform processor unit includes a dual 1000M Ethernet interface module, which adopts the RTL8211F-CG driver chip and is connected to the RK3588 chip through the GMAC interface to realize high-speed Ethernet frame transmission; the peripheral expansion circuit of the first platform processor unit includes an M.2 interface supporting a 5G communication module, which is connected to the RK3588 chip through a USB 3.0 interface; the peripheral expansion circuit of the first platform processor unit includes an M.2 interface supported by the RK3588 chip through a PCIe bus; the peripheral expansion circuit of the first platform processor unit includes a Wi-Fi / BT module, which includes an AW-CM256SM module, an SMA interface RF antenna, a 37.4MHz crystal oscillator and other parts, which is connected to the RK3588 chip through an SDIO bus, and can realize wireless network data communication through Wi-Fi and Bluetooth; the peripheral expansion circuit of the first platform processor unit includes 4 LED indicator lights, of which 3 LED indicator lights are connected to the RK3588 chip through a GPIO interface. MIPI LCD screen and MIPI camera can be connected to the first platform processor unit through MIPI interface to collect and display image data; the communication interface of the first platform processor unit also includes PCIe bus, RS485 bus, CAN bus, I2C bus, SPI bus, USB 2.0 interface, USB3.0 interface, PWM interface, HDMI interface. Figure 4 shown.

[0030] The second platform processor unit is based on the high-performance 32-bit processor STM32F407, and firmware burning and debugging are carried out through the JTAG interface and the USB to TTL interface. The storage unit of the second platform processor unit includes 1MB SRAM, EEPROM and 16MB Flash flash memory module, wherein the EEPROM unit adopts 24C02 chip, reads and writes through the I2C bus, and the Flash module adopts W25Q128FV chip, reads and writes through the SPI bus. The external expansion circuit of the second platform processor unit includes a photosensitive sensor, which adopts the LXD-GB5 sensor and performs data acquisition through the ADC method of the STM32F407 chip. The external expansion circuit of the second platform processor unit includes a DAC interface, and the PA5 pin of the STM32F407 chip outputs a DAC signal through the TLV9001IDBVR operational amplifier. The external expansion circuit of the second platform processor unit includes a breathing light module, which is connected to the PF10 pin of the STM32F407 chip, and the lighting and extinguishing of the breathing light can be controlled by a PWM signal. The external expansion circuit of the second platform processor unit includes a relay interface, which can be connected to a power switch control type actuator, and the opening and closing of the relay is controlled by the PF8 pin of the STM32F407 chip. The external expansion circuit of the second platform processor unit includes a 100M Ethernet interface module, which uses a LAN8720A driver chip and is connected to the STM32F407 chip through a MAC interface to realize Ethernet wired communication. The external expansion circuit of the second platform processor unit includes a 3*3 matrix keyboard, which is connected to the PE2, PG6, PC7, PC8, PC9, and PG7 pins of the STM32F407 chip, and reads keyboard input through the GPIO interface. The communication interface of the second platform processor unit also includes CAN bus, RS485 bus, I2C bus, SPI bus, and FSMC bus, among which the CAN bus interface uses the TJA1040T chip and the RS485 bus interface uses the SIT3485E chip. The external devices and communication interfaces of the dual-processor second platform are as follows: Figure 5 shown.

[0031] The power module of this experimental platform has multiple power supply circuits. The external 12V DC regulated power supply provides 4.0V, 3.3V, 5.0V, 1.8V and other working voltages through the MP8759 chip, NB680GD chip, SY8104I chip and SY8859QWC chip of the power module. These different voltages will supply power to the PMIC of the core processor unit and the power supply pins of other chips, modules, sensors and interfaces to ensure that the relevant modules can work normally.

[0032] As a teaching experiment platform, this experimental platform has more external devices and external communication interfaces. The FPGA unit supports OLED LCD screen display, 8-way DI interface data acquisition, 8-way DO interface device control, three groups of red, yellow and green light control, 3 groups of digital tube control, 3-way function buttons, 1 group of stepper motor control, and 1-way relay control; the RK3588 unit of the first dual-processor platform supports MIPI LCD screen, MIPI camera, HDMI video output interface, 5G communication module, M.2 interface hard disk, LED light, button, WiFi / BT module, dual 1000M Ethernet communication; the STM32F407 unit of the second dual-processor platform supports photosensitive sensors, DAC, EERPROM, SRAM, FLASH storage, breathing lights, buttons, matrix keyboards, Ethernet, and relay control. These core units and external devices cover teaching contents such as FPGA control, single-chip microcomputer development, embedded development, and artificial intelligence.

[0033] This experimental platform achieves full control of the experimental platform resources through the software system. The software system is divided into two levels, the underlying driver layer and the upper application layer. The driver layer includes driver function libraries based on XC7A75T chips, STM32F407 chips, RK3588 chips and their external devices. The driver layer directly controls the hardware and provides a calling interface to the upper software; the application layer software calls the driver layer software interface to achieve control of the hardware, which is convenient for students to learn and innovate.

[0034] The present invention focuses on realizing an integrated intelligent platform integrating FPGA, single-chip microcomputer and embedded system. In addition to the common use method of using FPGA unit as an interactive control channel between dual-processor platform and peripheral circuit, each unit can also be used alone to realize the corresponding peripheral function, and the dual-processing platform can be a communication object to realize relevant teaching content. In the communication structure, in addition to the internal communication mode of each unit through direct connection, the present invention also has two communication modes of Wi-Fi / BT and Ethernet that can communicate externally with other related modules. In addition to the common SPI interface, USB interface, CAN interface, and IIC interface, the present invention also includes more abundant GPIO interface, RS485 interface, PWM interface, FSMC interface, PCIe interface, HDIM interface, Type-C USB interface, and MIPI interface.

[0035] The present invention adopts the above technical solution, the core processing unit and the peripheral circuit unit are integrated on the same PCB board, and the transparent acrylic board is covered to protect the experimental platform PCB board. The relevant interfaces are connected using KF2EDG 3.81MM plug-in PCB terminals, which can effectively avoid the problems of wrong connection, poor contact, loose pins, etc. of the pin arrangement method, and is convenient for systematic teaching experiments. The present invention adopts a dual-processor platform and FPGA chip architecture, and the system architecture is more flexible. Each unit can interact with other units and can also be used as a separate platform. Both dual-processor units can realize hardware bus connection and data interaction with the FPGA unit. At the same time, the dual-processor units can also realize interactive control through bus connection.

[0036] Compared with other types of experimental platforms, the core units of this experimental platform can be developed and studied as independent modules, and can also communicate with each other through buses and other means to control peripheral interfaces and devices to realize related functions. This experimental platform has more abundant external interfaces and experimental modules, which overcomes the shortcomings of the lack of onboard functional module resources of the circuit board of the existing teaching experimental platform. It can provide comprehensive experimental program development examples. While learning the principles and applications of FPGA, single-chip microcomputers, and embedded systems in an easy-to-understand way, it can also enable students to gradually form a complete concept from hardware development to software development, improve students' practical operation ability and the comprehensive application and innovative development of knowledge points.

[0037] Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians of the art without making creative work are within the scope of protection of the present application.

Claims

1. An integrated intelligent platform based on FPGA and embedded system, characterized by: It includes a core processing unit and a peripheral expansion circuit unit. The core processing unit includes an FPGA unit and a dual processor unit. The dual processor unit includes two interactively controlled embedded processors. The FPGA unit is respectively connected to the two embedded processor buses of the dual processor unit and exchanges data. The FPGA unit and the two embedded processors of the dual processor unit respectively have their own external communication interfaces and peripheral expansion circuit units. Data exchange and control between the core processing unit and external devices are realized through the peripheral expansion circuit unit.

2. The integrated intelligent experimental platform based on FPGA and embedded system according to claim 1, characterized in that: The FPGA unit and the two embedded processors of the dual processor unit are both provided with debugging and downloading program interfaces, so that the management personnel can update and maintain the two embedded processors of the FPGA unit and the dual processor unit.

3. The integrated intelligent platform based on FPGA and embedded system according to claim 1, characterized in that: The FPGA unit and the dual processor unit are connected to corresponding storage units respectively; another embedded processor of the dual processor unit is connected to an external storage unit, and the external storage unit includes a 16MB Serial Flash memory and a 1MB SRAM.

4. The integrated intelligent platform based on FPGA and embedded system according to claim 1, characterized in that: The two embedded processors of the dual processor unit can both control the function realization of the peripheral expansion circuit unit of the FPGA unit; the two embedded processors of the dual processor unit serve as the signal source input tool of the FPGA unit and cooperate with digital logic to carry out basic functional experiments.

5. The integrated intelligent platform based on FPGA and embedded system according to claim 1, characterized in that: The two embedded processors interact and control via Ethernet, RS485 bus or CAN bus.

6. The integrated intelligent platform based on FPGA and embedded system according to claim 1, characterized in that: One of the embedded processors in the dual-processor unit uses Rockchip's flagship AIoT chip RK3588 platform, and the other embedded processor in the dual-processor unit uses the onboard high-performance 32-bit processor STM32F407.

7. The integrated intelligent platform based on FPGA and embedded system according to claim 1, characterized in that: The communication bus between one of the embedded processors of the dual processor unit and the FPGA unit includes 1 RS485 bus, 1 SPI bus, 1 PCIe bus, 1 I2C bus, 2 GPIO interfaces, and 3 PWM interfaces; The communication bus between another embedded processor of the dual processor unit and the FPGA unit includes 1 RS485 bus, 1 FSMC bus, 1 I2C bus, 1 SPI bus, 3 GPIO interfaces, and 3 PWM interfaces.

8. The integrated intelligent platform based on FPGA and embedded system according to claim 1, characterized in that: The external communication interfaces of one of the embedded processors of the dual-processor unit include 1 Type-C USB with OTG download interface, 1 USB to TTL debugging interface, 2 USB2.0 interfaces, 2 USB3.0 interfaces, 1 RS485 interface, and 2 Ethernet interfaces; The external devices connected to one of the embedded processors of the dual-processor unit include a MIPI LCD screen, a MIPI camera, an HDMI video output interface, an M.2 interface 5G communication module, an M.2 interface NVMe hard disk, 4 LED indicator lights, a reset button, a Maskrom download button, a Recovery download button, and a Wi-Fi / BT module that supports an SDIO interface.

9. The integrated intelligent platform based on FPGA and embedded system according to claim 1, characterized in that: The external communication interface of the other embedded processor of the dual processor unit includes 1 USB to TTL debugging interface and 1 Ethernet interface; The external devices of the other embedded processor of the dual processor unit include LED indicator lights, reset buttons, function buttons, 3*3 matrix keyboard, light sensor, 5V power supply actuator, relay, 1 DAC output and GPIO, I2C, UART expansion interface.

10. The integrated intelligent platform based on FPGA and embedded system according to claim 1, characterized in that: The FPGA unit uses the XC7A75T high-performance chip, which is connected to the two embedded processor buses and interacts with data through FSMC, RS485, PCIe, SPI, I2C, GPIO, and PWM interfaces; The external devices of the FPGA unit include OLED LCD screen, 3 groups of red, yellow and green lights, 1 group of 6-digit 8-segment digital tubes, 3 function buttons, 1 group of stepper motors, 1 relay control, 8-channel data acquisition DI interfaces, 8-channel device control DO interfaces, 6 groups of RS232 expansion interfaces and 2 groups of RS485 expansion interfaces.

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