PAD multiplexing device for system-on-chip

Abstract

The invention discloses a PAD multiplexing device for a system-on-chip. The PAD multiplexing device comprises a processor, a register module, a signal selection module and a plurality of PAD modules. The register module comprises a plurality of register units, and effective state values or ineffective state values are configured through one register unit connected with the signal selection module for a plurality of function modes of the PAD module. And aiming at each output function mode supported by the PAD module, the processor is respectively provided with an output signal channel connected to the signal selection module, and the output signal channel is used for outputting a processor signal. And aiming at each function mode of input supported by the PAD module, the processor is respectively provided with an input signal channel connected with the signal selection module. And the signal selection module is connected with each PAD module, and the signal selection module controls the signal output of the corresponding output signal channel and / or the signal input of the input signal channel according to the state value output by the register module, so that multiplexing of the PAD modules can be realized, and one PAD module can support multiple functional modes.

Description

Technical Field

[0001] The present technology relates to the field of chip design, and in particular to a PAD multiplexing device for a system-level chip. Background Art

[0002] With the rapid development of information technology, the demand for high-performance processors is growing. Benefiting from the improvement of process technology, the architecture of large CPUs has become more and more complex, and the design and packaging technology of multi-core processors and multi-die has matured and has been widely used in the semiconductor industry.

[0003] Among them, SoC chip (system-on-chip) is an important component of CPU. As the functions of SoC chip become more and more complex, the number of PAD pins required is also increasing. However, due to the actual design cost and chip size, the number of PADs of a SoC chip is often limited, and far less than the number required to achieve the functions. In addition, it is necessary to consider the multi-function implementation and control in different scenarios. Therefore, in the design of chip PAD, it is necessary to consider achieving as many functions as possible with a limited number of PADs, and ensure the efficiency and accuracy of the design implementation. Summary of the invention

[0004] The present application aims to provide a PAD multiplexing device for a system-level chip, which can solve the technical problem of realizing as many functions as possible when the number of PADs is limited.

[0005] To achieve the above-mentioned object, the present application provides a PAD multiplexing device for a system-level chip, comprising a processor, a register module, a signal selection module and several PAD modules, wherein the PAD module comprises multiple PAD units;

[0006] The register module comprises a plurality of register units, and a valid state value or an invalid state value is configured for each of the plurality of functional modes of the PAD unit through one of the register units connected to the signal selection module, wherein a valid state value is configured for one functional mode of the PAD unit, and invalid state values ​​are configured for other functional modes;

[0007] For each of the functional modes supported by the PAD unit, the processor stores the corresponding interface signal information and respectively configures an output signal channel connected to the signal selection module, the output signal channel being used to output the processor signal;

[0008] For each of the functional modes of the PAD unit supporting input, the processor respectively configures an input signal channel connected to the signal selection module;

[0009] The signal selection module is connected to each of the PAD units, and controls the signal output of the corresponding output signal channel and / or the signal input of the input signal channel according to the state value of the PAD unit in each functional mode output by the register module.

[0010] The PAD multiplexing device of the present application includes multiple PAD units. For a PAD unit, a valid state value is configured for one of the register units, and an invalid state value is configured for the other register units, and the signal selection module controls the signal output of the corresponding output signal channel and / or the signal input of the input signal channel according to the state values ​​of the functional mode, thereby realizing the multiplexing of a PAD unit in different scenarios and improving the multiplexing rate of the PAD unit. In addition, since the change of the state value of the functional mode can be achieved through the configuration register, and the output signal channel of the processor and the input signal channel of the processor can be achieved by modifying the corresponding configuration information in the processor, the PAD multiplexing device only needs to modify the corresponding configuration information when modifying its behavior, which reduces the later maintenance cost and the difficulty of cross-departmental cooperation.

[0011] Optionally, the output signal channel includes a first output signal channel and a second output signal channel, the first output signal channel is used to output a first signal, the second output signal channel is used to output a second signal, the first signal is an enable signal of the second signal, and the signal outputs of the first output signal channel and the second output signal channel are controlled by the state value of the same functional mode output by the register module.

[0012] Optionally, the signal selection module includes an output signal selection module;

[0013] For one of the PAD units, the output signal selection module includes a plurality of functional output AND gates, and two input ends of the functional output AND gates are respectively connected to one of the register units and the output signal channel corresponding to the register unit.

[0014] Optionally, the output signal selection module further performs an OR operation on the results of the function outputs and gate outputs in different function modes.

[0015] Optionally, the signal selection module includes an input signal selection module;

[0016] For one of the PAD units, the input signal selection module includes a plurality of function input AND gates, two input ends of the function input AND gates are respectively connected to one of the register units and the PAD unit, and an output end is connected to one of the input signal channels;

[0017] and / or,

[0018] For one of the PAD units, the input signal selection module includes a plurality of functional input OR gates, one input end of the functional input OR gate is connected to the PAD unit, the other input end is connected to the output end of a functional input NOT gate, the output end is connected to one of the input signal channels, and the input end of the functional input NOT gate is connected to one of the register units corresponding to the input signal channel.

[0019] Optionally, it also includes a decoding module; at least one of the PAD units is used as a test PAD unit to receive an external test device signal; the decoding module is connected to the test PAD unit and the signal selection module, and the decoding module is used to convert the test device signal input by the test PAD unit into a test control signal, wherein the test control signal includes status signals of multiple test modes, and for at least some of the PAD units other than the test PAD unit, the status signal of one of the test modes is a valid status value, and the status signals of other test modes are invalid status values.

[0020] Optionally, the test control signal also includes a test enable signal in different modes;

[0021] For each of the test modes of the PAD unit, the decoding module is configured to connect to the enable signal channel of the signal selection module respectively;

[0022] For each of the test modes of the PAD unit, the processor respectively configures a test signal channel connected to the signal selection module, wherein the test signal channel is used to transmit a test signal;

[0023] The signal selection module controls signal transmission of the corresponding test signal channel according to the state value of the PAD unit in each test mode.

[0024] Optionally, the test control signal further includes a test mode enable signal for the PAD unit;

[0025] When the test mode enable signal is valid, the corresponding PAD unit is used to transmit the test signal.

[0026] Optionally, the signal selection module includes an output signal selection module, and the test signal channel includes a test output signal channel;

[0027] For one of the PAD units, the output signal selection module includes a plurality of function output AND gates and test output AND gates, wherein two input ends of the function output AND gate are respectively connected to one of the register units and the output signal channel corresponding to the register unit; one input end of the test output AND gate is connected to a signal channel corresponding to a state signal of the test mode, and the other end is connected to an enable signal channel or the test output signal channel corresponding to the enable signal channel;

[0028] For one of the PAD units, the output signal selection module performs an OR operation on the results of the function outputs and gate outputs in different function modes to obtain a function output result, and also performs an OR operation on the results of the test outputs and gate outputs in different test modes to obtain a test output result, and selects one of the function output result and the test output result for output.

[0029] Optionally, the test control signal further includes a selection signal, and the output signal selection module further includes a selector;

[0030] For one of the PAD units, the two input ends of the selector are respectively connected to a signal channel corresponding to the functional output result and a signal channel corresponding to the test output result, and the selection end is connected to a signal channel corresponding to the selection signal;

[0031] The selector selects a signal received by one of the input terminals to output according to the state value of the selection terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a schematic diagram of the structure of the PAD multiplexing device according to an embodiment of the present application.

[0033] Figure 2 This is a schematic diagram of the structure of the output signal module of the embodiment of the present application.

[0034] Figure 3 This is a schematic diagram of the structure of the input signal module of an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to explain the technical content, structural features, achieved objectives and effects of the present application in detail, the following is a detailed description in conjunction with the implementation methods and the accompanying drawings.

[0036] See also Figure 1The present application discloses a PAD multiplexing device for a system-level chip, including a processor 1, a register module 2, a signal selection module 3 and a plurality of PAD modules 4, wherein the PAD module 4 includes a plurality of PAD units 43. The register module 2 includes a plurality of register units 21, and a valid state value or an invalid state value is configured for each of the plurality of functional modes of the PAD unit 43 through a register unit 21 connected to the signal selection module 3, wherein a valid state value is configured for one functional mode of the PAD unit 43, and an invalid state value is configured for other functional modes. For each functional mode that supports output of the PAD unit 43, the processor 1 stores the corresponding interface signal information and respectively configures an output signal channel 51 connected to the signal selection module 3, and the output signal channel 51 is used to output the signal of the processor 1. For each functional mode that supports input of the PAD unit 43, the processor 1 configures an input signal channel 52 connected to the signal selection module 3. The signal selection module 3 is connected to each PAD unit 43 , and controls the signal output of the corresponding output signal channel 51 and / or the signal input of the input signal channel 52 according to the state value of the PAD unit 43 in each functional mode output by the register module 2 .

[0037] Among them, each register unit 21 of the register module 2 is connected to the signal selection module 3 through the corresponding register signal channel 22, and the signal selection module 3 is connected to the PAD unit 43 through the PAD signal channel 41. The register signal channel 22 is used to output a valid state value or an invalid state value from the register unit 21 to the signal selection module 3, and the PAD signal channel 41 is used to output the signal of the output signal channel 51 from the signal selection module 3 to the PAD unit 43, or to input the signal of the PAD unit 43 to the signal selection module 3, and the signal selection module 3 then inputs the signal to the processor 1 through the input signal channel 52. The PAD unit 43 is connected to the input port or output port signal of other devices through the corresponding PAD, and is used to send the signal of the output signal channel 51 to the input port of other devices or receive the signal of the output port of other devices and input it to the signal selection module 3.

[0038] It can be understood that only some of the PAD units 43 may be connected to the signal selection module 3 .

[0039] The PAD multiplexing device of the present application configures a valid state value for one register unit 21 of a PAD unit 43, and configures invalid state values ​​for other register units 21. The signal selection module 3 controls the signal output of the corresponding output signal channel 51 and / or the signal input of the input signal channel 52 according to the corresponding state value of each functional mode, thereby realizing the multiplexing of a PAD unit 43 in different scenarios and improving the multiplexing rate of the PAD unit 43. In addition, since the change of the state value of the functional mode can be realized by configuring the register unit 21, and the output signal channel 51 of the processor 1 and the input signal channel 52 of the processor 1 can be realized by modifying the corresponding configuration information in the processor 1, the PAD multiplexing device only needs to modify the corresponding configuration information when modifying its behavior, which reduces the later maintenance cost and the difficulty of cross-departmental cooperation.

[0040] See also Figure 1 In some embodiments, the output signal channel 51 includes a first output signal channel 511 and a second output signal channel 512, the first output signal channel 511 is used to output a first signal, the second output signal channel 512 is used to output a second signal, the first signal is an enable signal of the second signal, and the signal outputs of the first output signal channel 511 and the second output signal channel 512 are controlled by the state value of the same functional mode output by the register module 2.

[0041] The PAD unit 43 responsible for the output signal of the peripheral device involved in the present application includes a first port and a second port, wherein the second port can only output the signal of the second port (output to PAD and output to the outside through PAD) when the signal of the first port is valid, and the first port is not limited. When in use, the first signal of the processor 1 can be sent to the first port of the PAD unit 43, and the second signal can be sent to the second port of the PAD unit 43. In other words, if the processor 1 communicates with the PAD unit 43 according to the TX-RX communication protocol, the first signal is the TXEN signal and the second signal is the TX signal. It can be understood that the specific form of the PAD unit 43 is not limited, and the PAD unit 43 can also be designed to control the output of several other port signals by one port, or the sending of the second port message is not limited by the first port. Accordingly, there can be multiple output signal channels 51, and it is not limited to only the first output signal channel 511 and the second output signal channel 512.

[0042] See also Figure 1 and Figure 2In some embodiments, the signal selection module 3 includes an output signal selection module 31. For one PAD unit 43, the output signal selection module 31 includes a plurality of functional output AND gates 311. The two input ends of the functional output AND gate 311 are respectively connected to a register unit 21 and an output signal channel 51 corresponding to the register unit 21.

[0043] The output signal channel 51 corresponding to the register unit 21 is the output signal channel 51 that can send a signal to the PAD unit 43 when the register unit 21 sends a valid state value to the signal selection module 3 .

[0044] Specifically, the output signal selection module 31 further performs an OR operation on the results of the output of each function output and the gate 311 in different function modes to output a signal corresponding to the function mode whose state value is a valid state value.

[0045] See also Figure 1 and Figure 3 In some embodiments, the signal selection module 3 includes an input signal selection module 32. For one PAD unit 43, the input signal selection module 32 includes a plurality of function input AND gates 321, two input ends of the function input AND gate 321 are respectively connected to a register unit 21 and the PAD unit 43, and the output end is connected to an input signal channel 52.

[0046] For a PAD unit 43, the input signal selection module 32 includes a plurality of functional input OR gates 322, one input end of the functional input OR gate 322 is connected to the PAD unit 43, the other input end is connected to the output end of a functional input NOT gate 323, the output end is connected to an input signal channel 52, and the input end of the functional input NOT gate 323 is connected to a register unit 21 corresponding to the input signal channel 52.

[0047] Among them, when the register unit 21 sends a signal "0" to the function input AND gate 321, the output of the function input AND gate 321 is always "0", and the input signal is invalid at this time. When the register unit 21 sends a signal "0" to the function input NOT gate 323, the output of the function input OR gate 322 is always "1", and the input signal is invalid at this time.

[0048] Optionally, the input enable signal (RXEN) between the processor 1 and the PAD unit 43 may be directly set inside the processor 1 , and the configuration register of the processor 1 controls whether the receiving port corresponding to the input signal receives the signal.

[0049] See also Figure 1In some embodiments, the PAD multiplexing device of the present application further includes a decoding module 6. At least one PAD unit 43 is used as a test PAD unit 43 to receive an external test device signal; the decoding module 6 is connected to the test PAD unit 43 and the signal selection module 3, and the decoding module 6 is used to convert the test device signal input by the test PAD unit 43 into a test control signal, and the test control signal includes a plurality of test mode status signals, for at least part of the PAD units 43 except the test PAD unit 43, the status signal of one test mode is a valid state value, and the status signals of other test modes are invalid state values, and the status signal of the test mode is sent from the decoding module 6 to the signal selection module 3 through the test state signal channel 61, and the test PAD unit 43 sends the external test device signal to the decoding module 6 through the test device signal channel 42.

[0050] After being connected to the test PAD unit 43 , the external test equipment can send the test equipment signal to the PAD multiplexing device according to the JTAG (Joint Test Action Group) protocol.

[0051] Specifically, the test control signal also includes a test enable signal in different modes. For each test mode of the PAD unit 43, the decoding module 6 is respectively configured with a test mode enable signal channel 53 connected to the signal selection module 3. For each test mode of the PAD unit 43, the processor 1 is respectively configured with a test signal channel 54 connected to the signal selection module 3, and the test signal channel 54 is used to transmit the test signal. The signal selection module 3 controls the signal transmission of the corresponding test signal channel 54 according to the state value of the PAD unit 43 in each test mode.

[0052] When testing the PAD multiplexing device, an external testing device sends a test control signal to control the signal selection module 3 to control the signal of the PAD unit 43 under test. If the received signal does not meet expectations, it can be determined that the PAD multiplexing device has an abnormality. At the same time, it can also be confirmed which modules have an abnormality based on the signal of the PAD unit 43 under test. The specific testing method is a technical means well known to people in this field and will not be repeated here.

[0053] Furthermore, the test control signal also includes a test mode enable signal for the PAD unit 43. When the test mode enable signal is valid, the corresponding PAD unit 43 is used to transmit the test signal.

[0054] See also Figure 1 and Figure 2, further, the signal selection module 3 includes an output signal selection module 31, and the test signal channel 54 includes a test output signal channel 541; for a PAD unit 43, the output signal selection module 31 includes a plurality of function output AND gates 311 and a test output AND gate 313, and the two input ends of the function output AND gate 311 are respectively connected to a register unit 21 and an output signal channel 51 corresponding to the register unit 21. One input end of the test output AND gate 313 is connected to a signal channel corresponding to a state signal of a test mode, and the other end is connected to a test mode enable signal channel 53 or a test output signal channel 541. For a PAD unit 43, the output signal selection module 31 performs an OR operation on the output results of each function output AND gate 311 in different function modes to obtain a function output result, and also performs an OR operation on the output results of each test output AND gate 313 in different test modes to obtain a test output result, and selects one of the function output result and the test output result for output, so as to ensure that the PAD unit 43 does not receive a signal of another mode when it is in one mode (test mode or function mode).

[0055] Among them, performing an OR operation to obtain a functional output result or a test output result can be implemented by an OR gate logic unit. Taking two functional output AND gates 311 and two test output AND gates 313 as examples, the output ends of the two functional output AND gates 311 are connected to the two input ends of a functional output OR gate 312, and the output ends of the two test output AND gates 313 are connected to the input ends of a test output OR gate 314, then the functional output OR gate 312 outputs the functional output results of the two functional output AND gates 311, and the test output OR gate 314 outputs the test output results of the two test output AND gates 313, and the functional output OR gate 312 or the test output OR gate 314 can also be connected to a new OR gate to form a cascade circuit, so as to achieve the results of each functional output AND gate 311 outputting an OR operation to obtain a functional output result and the results of each test output AND gate 313 outputting an OR operation to obtain a test output result, and the method of constructing a cascade circuit is a technical means well known to those skilled in the art, and will not be repeated.

[0056] More specifically, the test control signal also includes a selection signal, and the output signal selection module 31 also includes a selector 315. For a PAD unit 43, the two input terminals of the selector 315 are respectively connected to a signal channel corresponding to a functional output result and a signal channel corresponding to a test output result. The selection terminal is connected to the decoding module 6 through a selection signal channel 62 to receive the selection signal. The selector 315 selects the signal output received by one of the input terminals according to the state value of the selection terminal. For example, when the state value of the selection terminal is "1", the selector 315 selects to output the test output result, and when the state value of the selection terminal is "0", it selects to output the functional output result. The value of the selection signal can be set to "0" or "1" according to actual needs. Of course, the above examples are only for the convenience of understanding and cannot be understood as limitations on the present application.

[0057] Optionally, a multiplexer 7 is provided on the test output signal channel 541 and the second output signal channel 512, and the multiplexer 7 selects one of the signals of the test output signal channel 541 and the second output signal channel 512 for output according to a selection signal.

[0058] Optionally, the output signal selection module 31 includes a first output signal selection module 316 and a second output signal selection module 317. The first output signal selection module 316 is used to receive the first signal and the test mode enable signal, and output the functional output result corresponding to each first signal or the test output result corresponding to the test mode enable signal, and the second output signal selection module 317 is used to receive the second signal and the test signal, and output the functional output result corresponding to each second signal or the test output result corresponding to the test signal.

[0059] See also Figure 3 Specifically, the signal selection module 3 also includes an input signal selection module 32 , and the test signal channel 54 includes a test input signal channel 542 .

[0060] For one PAD unit 43 , the input signal selection module 32 includes a plurality of function input AND gates 321 , two input ends of the function input AND gate 321 are respectively connected to a register unit 21 and the PAD unit 43 , and the output end is connected to an input signal channel 52 .

[0061] For a PAD unit 43, the input signal selection module 32 includes a plurality of functional input OR gates 322, one input end of the functional input OR gate 322 is connected to the PAD unit 43, the other input end is connected to the output end of a functional input NOT gate 323, the output end is connected to an input signal channel 52, and the input end of the functional input NOT gate 323 is connected to a register unit 21 corresponding to the input signal channel 52.

[0062] For a PAD unit 43, the input signal selection module 32 includes a plurality of test input AND gates 324, the two input ends of the test input AND gate 324 are respectively connected to a test status signal channel 61 of a test mode status signal and the PAD unit 43, and the output end is connected to a test input signal channel 542 of a test input signal corresponding to the status signal.

[0063] For a PAD unit 43, the input signal selection module 32 includes a plurality of test input OR gates 325, one input end of the test input OR gate 325 is connected to the PAD unit 43, and the other input end is connected to the output end of a test input NOT gate 326, the input end of the test input NOT gate 326 is connected to the test status signal channel 61 corresponding to the status signal of the test mode, and the output end of the test input OR gate 325 is connected to the test input signal channel 542 of the input signal corresponding to the status signal.

[0064] The input signal corresponding to the state signal is the input signal controlled by the state signal. Only when the state signal is valid can the input signal be input from the test input signal channel 542 to the processor 1.

[0065] In some embodiments, the processor 1 sends configuration information to the register module 2 via an Advanced Peripheral Bus (APB) signal line, and the register module 2 configures the behavior of the corresponding register unit 21 according to the configuration information.

[0066] In some embodiments, the register module 2 is also connected to the PAD module 4 via a configuration signal line 23 (register filed to padattribute), and the signal of the configuration signal line 23 is used to configure relevant attributes of the PAD module 4 through the register field, such as the correspondence between the PAD unit 43 and the register unit 21.

[0067] The following is a brief description of the design steps of the PAD multiplexing device:

[0068] S1. Determine the function mode, test mode and corresponding interface signal name, input / output direction and invalid state value of each PAD unit 43, and summarize them in a configuration file.

[0069] S2. Determine the type of each PAD unit 43 and its corresponding interface signal.

[0070] S3. Write a script to generate RTL code using the configuration file as the input source. The script content includes the interface signal declaration required by the Verilog module, the address allocation declaration of the PAD cell control register, the configuration register control logic, the mode selection logic, and the signal generation logic in the input and output directions of each PAD in each functional mode and test mode.

[0071] S4. Execute the script with the configuration file as input source to output a register table. The register table is used as part of the design implementation solution document and is used to simulate and verify the PAD multiplexing device.

[0072] This design step is based on the front-end design requirements and hardware implementation limitations. When the number of PAD modules in the chip is limited, multiple functional modes can be reused. At the same time, the configuration file combined with the script implementation method improves the design versatility and efficiency. When there is a need for modification and maintenance in the later stage, you only need to modify the configuration file content to update the design code, reducing the later maintenance cost. In addition, when reviewing and verifying the design of the PAD reuse device, you only need to start with the configuration file, which makes the later design review more efficient and facilitates the synchronization of design verification requirements.

[0073] The above disclosure is only a preferred example of the present application and cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are all within the scope covered by the present application.

Claims

1. A PAD multiplexing device for a system-level chip, characterized in that: It includes a processor, a register module, a signal selection module and a PAD module, wherein the PAD module includes a plurality of PAD units; The register module comprises a plurality of register units, and a valid state value or an invalid state value is configured for each of the plurality of functional modes of the PAD unit through one of the register units connected to the signal selection module, wherein a valid state value is configured for one functional mode of the PAD unit, and invalid state values ​​are configured for other functional modes; For each of the functional modes supported by the PAD unit, the processor stores the corresponding interface signal information and respectively configures an output signal channel connected to the signal selection module, the output signal channel being used to output the processor signal; For each of the functional modes of the PAD unit supporting input, the processor respectively configures an input signal channel connected to the signal selection module; The signal selection module is connected to each of the PAD units, and controls the signal output of the corresponding output signal channel and / or the signal input of the input signal channel according to the state value of the PAD unit in each functional mode output by the register module.

2. The PAD multiplexing device according to claim 1, characterized in that: The output signal channel includes a first output signal channel and a second output signal channel, the first output signal channel is used to output a first signal, the second output signal channel is used to output a second signal, the first signal is an enable signal of the second signal, and the signal outputs of the first output signal channel and the second output signal channel are controlled by the state value of the same functional mode output by the register module.

3. The PAD multiplexing device according to claim 1, characterized in that: The signal selection module includes an output signal selection module; For one of the PAD units, the output signal selection module includes a plurality of functional output AND gates, and two input ends of the functional output AND gates are respectively connected to one of the register units and the output signal channel corresponding to the register unit.

4. The PAD multiplexing device according to claim 3, characterized in that: The output signal selection module also performs an OR operation on the results of the function outputs and gate outputs in different function modes.

5. The PAD multiplexing device according to claim 1, characterized in that: The signal selection module includes an input signal selection module; For one of the PAD units, the input signal selection module includes a plurality of function input AND gates, two input ends of the function input AND gates are respectively connected to one of the register units and the PAD unit, and an output end is connected to one of the input signal channels; and / or, For one of the PAD units, the input signal selection module includes a plurality of functional input OR gates, one input end of the functional input OR gate is connected to the PAD unit, the other input end is connected to the output end of a functional input NOT gate, the output end of the functional input OR gate is connected to one of the input signal channels, and the input end of the functional input NOT gate is connected to one of the register units corresponding to the input signal channel.

6. The PAD multiplexing device according to claim 1, characterized in that: Also includes a decoding module; At least one of the PAD units is used as a test PAD unit to receive an external test equipment signal; The decoding module is connected to the test PAD unit and the signal selection module, and the decoding module is used to convert the test equipment signal input by the test PAD unit into a test control signal, wherein the test control signal includes status signals of multiple test modes, and for at least some of the PAD units other than the test PAD unit, the status signal of one of the test modes is a valid status value, and the status signals of the other test modes are invalid status values.

7. The PAD multiplexing device according to claim 6, characterized in that: The test control signal also includes a test enable signal in different modes; For each of the test modes of the PAD unit, the decoding module is configured to connect to the enable signal channel of the signal selection module respectively; For each of the test modes of the PAD unit, the processor respectively configures a test signal channel connected to the signal selection module, wherein the test signal channel is used to transmit a test signal; The signal selection module controls signal transmission of the corresponding test signal channel according to the state value of the PAD unit in each test mode.

8. The PAD multiplexing device according to claim 7, characterized in that: The test control signal also includes a test mode enable signal for the PAD unit; When the test mode enable signal is valid, the corresponding PAD unit is used to transmit the test signal.

9. The PAD multiplexing device according to claim 7, characterized in that: The signal selection module includes an output signal selection module, and the test signal channel includes a test output signal channel; For one of the PAD units, the output signal selection module includes a plurality of functional output AND gates and a plurality of test output AND gates, wherein two input ends of the functional output AND gate are respectively connected to one of the register units and the output signal channel corresponding to the register unit; one input end of the test output AND gate is connected to a state signal channel corresponding to a state signal of the test mode, and the other input end is connected to one of the enable signal channels or the test output signal channel corresponding to the enable signal channel; For one of the PAD units, the output signal selection module performs an OR operation on the results of the function outputs and gate outputs in different function modes to obtain a function output result, performs an OR operation on the results of the test outputs and gate outputs in different test modes to obtain a test output result, and selects one of the function output result and the test output result for output.

10. The PAD multiplexing device according to claim 9, characterized in that: The test control signal further includes a selection signal, and the output signal selection module further includes a selector; For one of the PAD units, the two input ends of the selector are respectively connected to the channel corresponding to the functional output result and the channel corresponding to the test output result, and the selection end of the selector is connected to the channel corresponding to the selection signal; The selector selects and outputs a signal received by one of the input terminals of the selector according to a state value of the selection terminal.

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