Circuit board jointed board design method, electronic equipment and computer readable storage medium

Abstract

The invention discloses a circuit board jointed board design method, electronic equipment and a computer readable storage medium, the circuit board jointed board design method is used for generating a set file, and the method comprises the following steps: obtaining a target design file; the target design file comprises a unit appearance layer file and a jointed board layer file. And calculating unit region data of the jointed board layer file based on the unit feature of the unit appearance layer file. And performing functional area identification on the jointed board layer file to obtain functional area data, and performing graph construction on the functional area data to obtain a functional area graph. The method comprises the following steps: performing v-cut area identification on a jointed board layer file to obtain v-cut area data, and constructing the v-cut area data to obtain a v-cut layer; generating a set file based on the functional area graph and the v-cut layer; wherein the set file is used for circuit board splicing. According to the scheme, design steps can be fully simplified, design efficiency is improved, and the research and development cycle of products is shortened.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board processing, and in particular to a circuit board panel design method, electronic equipment and computer-readable storage medium. Background Art

[0002] PCB panelization is the process of combining multiple PCB units (usually of the same or similar design) in a certain arrangement to form a larger overall design (panel) for processing in the same production batch. PCB panelization can improve production efficiency, reduce material waste and reduce manufacturing costs.

[0003] In the prior art, based on the initial design file, which includes a unit shape layer file and a panel layer file, manual panelization is required in the engineering production software. Manual panelization requires a large amount of coordinate calculation and data calculation, and manual calculation is time-consuming, that is, the prior panelization design efficiency is low. Summary of the invention

[0004] The main purpose of the present invention is to propose a circuit board panel design method, an electronic device and a computer-readable storage medium, aiming to solve the technical problem of low efficiency in circuit board panel design.

[0005] To achieve the above object, a first aspect of the present invention provides a circuit board panel design method for generating a set file. The circuit board panel design method includes the following steps:

[0006] Obtaining a target design file; wherein the target design file includes a unit shape layer file and a panel layer file;

[0007] Calculate the unit area data of the panel layer file based on the unit features of the unit shape layer file;

[0008] Performing functional area identification on the panel layer file to obtain functional area data, and performing graphic construction on the functional area data to obtain a functional area graphic;

[0009] Performing v-cut area identification on the panel layer file to obtain v-cut area data, and constructing the v-cut area data to obtain a v-cut layer;

[0010] The set file is generated based on the functional area graphics and the v-cut layer; wherein the set file is used for circuit board panelization.

[0011] In some embodiments, before obtaining the target design file, the method further includes:

[0012] Determine whether the initial design file contains the unit shape layer file and the panel layer file;

[0013] If both the unit shape layer file and the panel layer file exist, and the unit shapes of the unit shape layer file and the panel layer file are consistent, the initial design file is confirmed as the target design file.

[0014] In some embodiments, the number of the unit features is multiple, and the calculating of the unit area data of the panel layer file based on the unit features of the unit outline layer file includes:

[0015] Calculating the position information of each unit feature to obtain unit position feature data;

[0016] Combine a plurality of the unit position feature data to obtain the unit area data of the panel layer file.

[0017] In some embodiments, after calculating the unit area data of the panel layer file based on the unit features of the unit outline layer file, the method further includes:

[0018] The non-target data of the unit area data is filtered to obtain the target data; wherein the non-target data includes non-unit data and annotation description data.

[0019] In some embodiments, the performing v-cut area identification on the panel layer file to obtain v-cut area data includes:

[0020] Search the v-cut field of the panel layer file;

[0021] The angle data and position data of the v-cut are obtained based on the v-cut field information.

[0022] In some embodiments, constructing the v-cut area data to obtain a v-cut layer includes:

[0023] Performing information verification on the v-cut area data to obtain v-cut information;

[0024] Verify the outline frame of the panel layer file to obtain the panel outline frame;

[0025] The v-cut layer is generated based on the v-cut information and the panel outline frame.

[0026] In some embodiments, the number of the units is multiple, and the generating the set file based on the functional area graphics and the v-cut layer includes:

[0027] Arrange the position of each of the units to obtain a unit area;

[0028] Based on the unit area, a non-unit area is obtained;

[0029] A process edge outline frame is configured for the non-unit area.

[0030] In some embodiments, after generating the set file based on the functional area graphic and the v-cut layer, the method further includes:

[0031] Adding optical points to the circuit, and adding windows to the solder mask layer for the optical points;

[0032] Generate a process edge, add a positioning hole to the drilling layer of the process edge, and add a window to the positioning hole in the solder mask layer;

[0033] A copper layer is laid according to the outer contour of the process edge; wherein the copper layer is spaced apart from both the unit area and the v-cut area.

[0034] A second aspect of the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the circuit board panelization design method described in the above embodiment when executing the computer program.

[0035] A third aspect of the present invention provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the circuit board panelization design method described in the above embodiment is implemented.

[0036] Compared with the prior art, the beneficial effects of the present invention include:

[0037] In the technical solution of the present invention, a circuit board panelization design method is used to generate a set file, and the circuit board panelization design method includes the following steps: obtaining a target design file. The target design file includes a unit shape layer file and a panelization layer file. The unit area data of the panelization layer file is calculated based on the unit features of the unit shape layer file. The functional area of ​​the panelization layer file is identified to obtain the functional area data, and the functional area data is graphically constructed to obtain the functional area graphics. The v-cut area of ​​the panelization layer file is identified to obtain the v-cut area data, and the v-cut area data is constructed to obtain the v-cut layer. A set file is generated based on the functional area graphics and the v-cut layer. The set file is used for circuit board panelization. Compared with the prior art solution of using manual calculation to design circuit board panels, firstly, this solution can provide a systematic process, from obtaining the target file to generating the set file, which can fully simplify the design steps, improve the design efficiency, and shorten the product development cycle. Secondly, through step-by-step identification and construction, the accuracy of each data and area can be ensured, and the errors that may occur in the design process can be reduced. Then, through graphical construction, visual support can be provided for circuit board panelization design. Moreover, the set file generated by this solution contains detailed design information, which can directly support circuit board manufacturing and reduce the risk of production errors. In addition, this solution can flexibly adapt to different circuit board design requirements and standards, and adapt to various types of circuit board assembly designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0039] Figure 1 is a flow chart of a circuit board panel design method in one embodiment of the present invention;

[0040] Figure 2 It is a partial flow chart of a circuit board panel design method in a specific embodiment of the present invention;

[0041] Figure 3 It is a partial flow chart of a circuit board panel design method in a specific embodiment of the present invention;

[0042] Figure 4 Schematic diagram of the effect of the initial design file in one embodiment of the present invention; wherein the black wireframe indicates the unit outer shape layer, and the red wireframe indicates the panel layer;

[0043] Figure 5It is a schematic diagram of the effect of the set file in one embodiment of the present invention; wherein the green wireframe indicates the panel, and the cyan square indicates the copper plating layer.

[0044] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0046] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0048] PCB panelization is the process of combining multiple PCB units (usually of the same or similar design) in a certain arrangement to form a larger overall design (panel) for processing in the same production batch. PCB panelization can improve production efficiency, reduce material waste and reduce manufacturing costs.

[0049] In the prior art, based on the initial design file, which includes the unit shape layer file and the panel layer file, manual panelization is required in the engineering production software. Manual panelization requires a large amount of coordinate calculation and data calculation, and manual calculation is time-consuming, that is, the existing panelization design efficiency is low. Specifically, relevant personnel need to design a complete set file based on the initial design file, and make v-cut layers, drilling layers, circuit optical points, solder mask optical point openings, and panel shape frames based on the information in the panel layer file.

[0050] In view of this, the first embodiment of the present invention proposes a circuit board panel design method, which is used to generate a set file to improve the efficiency of panel design. Figures 1 to 5 The circuit board panel design method of the present application is introduced. Specifically, refer to Figure 1 , the circuit board panel design method includes the following steps:

[0051] S101: Obtain a target design file; wherein the target design file includes a unit shape layer file and a panel layer file.

[0052] It can be understood that the target design file can be obtained by design software or a third party (provided by the customer), and the embodiment of the present application does not limit the acquisition method.

[0053] Reference Figure 4 For example, a unit outline file (also referred to as an outline file of a single PCB unit) can define the shape, size or layout of a single PCB (printed circuit board) unit. For example, the boundaries of the PCB unit, hole information (such as the location and diameter of the drill hole on the PCB unit) and other features can be defined. Other features may include pads, lines or solder resist layers.

[0054] Exemplarily, the panel layer file can define the layout of the entire panel, including the arrangement position, direction and other features of multiple PCB units on the panel. For example, the panel layer file includes the position and direction of each PCB unit on the panel, the path and angle of the v-cut, the drilling position and diameter on the panel, the border of the panel, the positioning holes, etc.

[0055] Need explanation, see Figure 4 , the unit outline layer file can provide the shape and size information of each unit in the circuit board. Figure 5 , while the panel layer file can provide the overall layout and structure of the splicing. The unit shape layer file combined with the panel layer file can ensure the integrity of the design.

[0056] S102: Calculate the unit area data of the panel layer file based on the unit features of the unit shape layer file.

[0057] It can be understood that the unit features of the unit outline layer file may include parameters such as the boundary, shape and size information of the functional model, etc. The unit area data of the panel layer file may include the overall layout and structure of the panel.

[0058] This step can use the existing unit shape layer file to automatically extract and calculate the relevant unit area data through data processing, which can improve the efficiency of panel design. It can also accurately reflect the actual situation of circuit board splicing and optimize subsequent designs.

[0059] S103: Perform functional area identification on the panel layer file to obtain functional area data, perform graphic construction on the functional area data to obtain functional area graphics.

[0060] Exemplarily, the functional area may include a power area, a signal processing area, a connection area, etc. The functional area data may include the area size, shape, position, and the circuit function carried by the area.

[0061] This step can ensure the functionality and manufacturability of the circuit board by accurately identifying the functional areas. Building corresponding graphics based on the functional area data can provide visual support for subsequent design verification and actual production, and enable designers to intuitively understand the structure of the circuit board.

[0062] S104: Perform v-cut area identification on the panel layer file to obtain v-cut area data, construct the v-cut area data to obtain a v-cut layer.

[0063] It should be noted that v-cut area recognition refers to the detection and identification of areas that need v-cut processing in the panel layer file. The v-cut manufacturing process forms a V-shaped groove on the circuit board to fold or split the circuit board at a predetermined position, which is convenient for subsequent processing and assembly.

[0064] Exemplarily, the v-cut area data may include parameters such as the position, shape, and depth of the v-cut area, which may provide a basis for subsequent processing and manufacturing.

[0065] This step can clarify the cutting position and cutting shape, ensuring that the subsequent segmentation operation can proceed smoothly, thereby reducing material waste and processing errors, thereby reducing overall production costs and ensuring product quality.

[0066] S105: Generate a set file based on the functional area graphics and the v-cut layer; wherein the set file is used for circuit board assembly.

[0067] Reference Figure 5 It can be understood that the functional area graph is a graph formed by identifying and constructing the functional areas in the board layer file. This part of the graph can intuitively display the different functional areas of the circuit board, including the power area, signal processing area, and connection area.

[0068] It should be noted that the v-cut layer refers to the design layer that contains the identifiable v-cut area and its processing instructions. The v-cut layer can provide necessary information for cutting during the circuit board manufacturing process to ensure that it can perform v-cut processing at the correct position.

[0069] It should be noted that the set file is a configuration file for circuit board panelization, which usually contains the required design parameters and instructions to guide the manufacturing equipment to complete the relevant panelization operations. In circuit board design and manufacturing, the set file can provide circuit board layout information, functional areas, v-cut instructions, etc.

[0070] This step can provide necessary instructions and data support for the manufacture of circuit board panels, help manufacturing equipment to plan production processes more efficiently, improve material and resource utilization, and reduce waste during cutting and processing.

[0071] In the technical solution of the present invention, a circuit board panelization design method is used to generate a set file, and the circuit board panelization design method includes the following steps: obtaining a target design file. The target design file includes a unit shape layer file and a panelization layer file. The unit area data of the panelization layer file is calculated based on the unit features of the unit shape layer file. The functional area of ​​the panelization layer file is identified to obtain the functional area data, and the functional area data is graphically constructed to obtain the functional area graphics. The v-cut area of ​​the panelization layer file is identified to obtain the v-cut area data, and the v-cut area data is constructed to obtain the v-cut layer. A set file is generated based on the functional area graphics and the v-cut layer. The set file is used for circuit board panelization. Compared with the prior art solution of using manual calculation to design circuit board panels, firstly, this solution can provide a systematic process, from obtaining the target file to generating the set file, which can fully simplify the design steps, improve the design efficiency, and shorten the product development cycle. Secondly, through step-by-step identification and construction, the accuracy of each data and area can be ensured, and the errors that may occur in the design process can be reduced. Then, through graphical construction, visual support can be provided for circuit board panelization design. Moreover, the set file generated by this solution contains detailed design information, which can directly support circuit board manufacturing and reduce the risk of production errors. In addition, this solution can flexibly adapt to different circuit board design requirements and standards, and adapt to various types of circuit board assembly designs.

[0072] In some embodiments, before obtaining the target design file, the method further includes:

[0073] S201: Determine whether the initial design file contains a unit shape layer file and a panel layer file.

[0074] This step can add prerequisites for obtaining the target design file, ensure the integrity of the basic data required for subsequent steps, effectively reduce design errors caused by missing or inconsistent files, and enhance the accuracy and reliability of the entire design process.

[0075] S202: If both the unit shape layer file and the panel layer file exist, and the unit shapes of the unit shape layer file and the panel layer file are consistent, the initial design file is confirmed as the target design file.

[0076] This step verifies that the unit appearance between the two files is consistent, which helps eliminate possible design errors and reduce risks in the production stage.

[0077] In some embodiments, the number of unit features is multiple, and the unit area data of the panel layer file is calculated based on the unit features of the unit shape layer file, including:

[0078] S301: Calculate the position information of each unit feature to obtain unit position feature data.

[0079] In this step, the system can calculate the detailed position information of each unit feature to ensure the accurate position of each unit feature, so as to reduce the potential error in the subsequent panelization process. Processing multiple unit features enables this method to adapt to complex circuit board design requirements and is suitable for circuit boards of various specifications and configurations. It should be noted that the position of each unit feature is determined by its absolute coordinates or relative coordinates on the circuit board.

[0080] S302: Combine multiple unit position feature data to obtain unit area data of the panel layer file.

[0081] In this step, after combining the position feature data of each unit, the unit area data of the generated panel layer file can be easily checked and modified later, ensuring that each step of the design has a clear basis. By providing comprehensive unit area data, the degree of automation in the manufacturing process can be improved, manual intervention can be reduced, and overall production efficiency can be improved.

[0082] In some embodiments, after calculating the unit area data of the panel layer file based on the unit features of the unit outline layer file, the method further includes:

[0083] S401: Filter non-target data of unit area data to obtain target data; wherein the non-target data includes non-unit data and annotation data.

[0084] In this step, unnecessary or irrelevant information can be removed through the filtering mechanism, and data related to the final target design can be retained, which can ensure that subsequent operations are more efficient and centralized. It should be noted that non-unit data includes other information or data that does not belong to any specific functional unit in the circuit board design, and this part of the data is not required in the panel design. The annotation data includes descriptive text or marks about the design, and this data is redundant data in the specific data of the panel layer.

[0085] In some embodiments, performing v-cut area identification on the panel layer file to obtain v-cut area data includes:

[0086] S501: Search the v-cut field of the panel layer file.

[0087] In this step, the field search method can be used to efficiently and accurately extract v-cut related information from complex panel layer files to ensure the integrity and accuracy of the design data.

[0088] S502: Obtain the angle data and position data of the v-cut based on the v-cut field information.

[0089] In this step, by extracting angle data and position data based on the information in the v-cut field, the system can accurately define the specific parameters of the cutting, which helps to achieve a fast and accurate production process.

[0090] In some embodiments, the v-cut area data is constructed to obtain a v-cut layer, including:

[0091] S601: Verify the v-cut area data to obtain v-cut information.

[0092] In this step, the data in the v-cut area is verified to ensure that the obtained data is valid and accurate, and the verified v-cut information is extracted for use.

[0093] S602: Check the outline frame of the panel layer file to obtain the panel outline frame.

[0094] Exemplarily, the outer shape frame may be the boundary shape of the circuit board. By checking and extracting the specific outer shape frame information of the panel, it can be ensured that it is consistent with the design requirements.

[0095] S603: Generate a v-cut layer based on the v-cut information and the panel outline frame.

[0096] In this step, the v-cut layer can be used in subsequent production and cutting processes to ensure that the design requirements are achieved.

[0097] In some embodiments, the number of units is multiple, and a set file is generated based on the functional area graphics and the v-cut layer, including:

[0098] S701: Arrange the position of each unit to obtain the unit area.

[0099] This step involves arranging and organizing the positions of each functional unit. By arranging the positions of each unit, the specific area of ​​this unit on the circuit board can be defined to ensure that the board can be laid out efficiently and accurately.

[0100] S702: Based on the unit area, obtain the non-unit area.

[0101] In this step, based on the defined unit areas, the areas on the circuit board that do not contain any units can be inferred, and these areas can be non-unit areas.

[0102] S703: Configure a process edge outline frame for the non-unit area.

[0103] In this step, you can define a process border for the non-unit area. The process border can be used to specify the process requirements and reserved areas of the non-unit area during the manufacturing process to ensure smooth production.

[0104] This solution can achieve efficient circuit board layout planning by managing the arrangement of multiple unit positions, ensuring the effectiveness and practicality of circuit board design. By clearly distinguishing between unit areas and non-unit areas, the design can be systematized, which is helpful for subsequent production and assembly configuration.

[0105] In some embodiments, after generating a set file based on the functional area graphic and the v-cut layer, the method further includes:

[0106] S801: Add optical points to the circuit and add windows to the solder mask layer for the optical points.

[0107] In this step, the optical point can be used to identify or monitor the position and status of functional components, improving the visibility of the circuit board during subsequent testing and assembly. Adding windows for the optical point in the solder mask layer means punching holes in the solder mask layer (usually used to protect the solder joints on the circuit board) to enable the optical point to work effectively and ensure normal optical recognition.

[0108] S802: Generate a process edge, add positioning holes to the drilling layer of the process edge, and add windows to the positioning holes in the solder mask layer.

[0109] In this step, a drilling layer is added for the generated process edge (defining the manufacturing boundary and process requirements), and positioning holes are added on this layer. Positioning holes are used to provide accurate alignment references during the manufacturing process, which helps to ensure the accurate installation of circuit board components. Similar to optical points, windows are also added to the solder mask layer for positioning holes so that the positioning holes can be correctly identified and used during the manufacturing and assembly process.

[0110] S803: Laying a copper layer according to the outline of the process edge; wherein the copper layer is spaced apart from the unit area and the v-cut area.

[0111] After creating the outline, you can define the electrical paths and connection points of the circuit board by laying copper layers to ensure the realization of electrical performance. When laying copper layers, ensure that they are spaced from the unit area and v-cut area to reduce interference, ensure signal integrity, and ensure a reasonable cutting process.

[0112] This solution introduces optical points, positioning holes and electrical layer spacing design, which can enhance the manufacturability, testability and functional integration of the circuit board.

[0113] Reference Figure 3 and Figure 4 , the following introduces a circuit board panel design method in a specific embodiment of the present application.

[0114] S901: Reference Figure 4 , determine whether the initial design file has a unit shape layer file and a panel layer file; if both the unit shape layer file and the panel layer file exist, and the unit shapes of the unit shape layer file and the panel layer file are consistent, then the initial design file is confirmed as the target design file.

[0115] S902: Obtain target design files; wherein the target design files include unit shape layer files and panel layer files.

[0116] S903: Calculate the position information of each unit feature to obtain unit position feature data; combine multiple unit position feature data to obtain unit area data of the panel layer file.

[0117] S904: Filter the non-target data of the unit area data to obtain the target data; wherein the non-target data includes non-unit data and annotation description data.

[0118] S905: Perform functional area recognition on the panel layer file to obtain functional area data, perform graphic construction on the functional area data to obtain functional area graphics.

[0119] S906: Search the v-cut field of the panel layer file; obtain the angle data and position data of the v-cut based on the v-cut field information.

[0120] S907: Verify the v-cut area data to obtain v-cut information; verify the outline frame of the panel layer file to obtain the panel outline frame; generate the v-cut layer based on the v-cut information and the panel outline frame.

[0121] S908: Reference Figure 5 , generating a set file based on the functional area graphics and the v-cut layer; wherein, arranging the position of each of the units to obtain a unit area; obtaining a non-unit area based on the unit area; and configuring a process edge outline frame for the non-unit area.

[0122] S909: Reference Figure 5, add optical points to the circuit, and add windows for the optical points in the solder mask layer; generate process edges, add positioning holes to the drilling layer of the process edges, and add windows for the positioning holes in the solder mask layer; lay the copper layer according to the outline of the process edge; wherein the copper layer is spaced from the unit area and the v-cut area.

[0123] It should be noted that in some embodiments, the processing steps of the above embodiments can be automatically executed to ensure the efficiency of the operation. In other embodiments, the generated set files and data can be verified to ensure the accuracy and consistency of all layers and processing data.

[0124] The second aspect of the present invention proposes an electronic device, which includes a memory and a processor, wherein the memory stores a computer program, and the processor implements the above-mentioned circuit board panel design method when executing the computer program. The electronic device may include any intelligent terminal such as a laptop computer, a desktop computer, a tablet computer or a car computer. The electronic device of this scheme can implement the circuit board panel design method of the above-mentioned embodiment, can fully simplify the design steps, improve the efficiency of circuit board panel design, shorten the product development cycle, and adapt to different circuit board design requirements and standards.

[0125] The processor can be implemented as a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0126] The memory can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory, and the processor is called to execute the circuit board panel design method of the embodiment of this application.

[0127] It can be understood that the electronic device may also include an input / output interface, a communication interface and a bus. The input / output interface is used to realize information input and output. The communication interface is used to realize the communication interaction between the device and other devices. Communication can be realized through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). The bus transmits information between the various components of the device (such as processor, memory, input / output interface and communication interface). The processor, memory, input / output interface and communication interface realize communication connection with each other inside the device through the bus.

[0128] The third aspect embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the circuit board panelization design method of the above embodiment, which can fully simplify the design steps, improve the efficiency of circuit board panelization design, shorten the product development cycle, and adapt to different circuit board design requirements and standards.

[0129] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0130] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0131] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0132] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0133] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0134] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0135] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0136] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0137] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0138] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0139] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0140] The non-Company software tools or components appearing in the embodiments of this application are for illustrative purposes only and do not represent actual use.

[0141] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A circuit board panel design method for generating a set file, characterized in that: The circuit board panel design method comprises the following steps: Obtaining a target design file; wherein the target design file includes a unit shape layer file and a panel layer file; Calculate the unit area data of the panel layer file based on the unit features of the unit shape layer file; Performing functional area identification on the panel layer file to obtain functional area data, and performing graphic construction on the functional area data to obtain a functional area graphic; Performing v-cut area identification on the panel layer file to obtain v-cut area data, and constructing the v-cut area data to obtain a v-cut layer; The set file is generated based on the functional area graphics and the v-cut layer; wherein the set file is used for circuit board panelization.

2. The circuit board panel design method according to claim 1, characterized in that: Before obtaining the target design file, the method further includes: Determine whether the initial design file contains the unit shape layer file and the panel layer file; If both the unit shape layer file and the panel layer file exist, and the unit shapes of the unit shape layer file and the panel layer file are consistent, the initial design file is confirmed as the target design file.

3. The circuit board panel design method according to claim 1, characterized in that: The number of the unit features is multiple, and the unit area data of the panel layer file is calculated based on the unit features of the unit outline layer file, including: Calculating the position information of each unit feature to obtain unit position feature data; Combine the plurality of unit position feature data to obtain the unit area data of the panel layer file.

4. The circuit board panel design method according to claim 3, characterized in that: After calculating the unit area data of the panel layer file based on the unit features of the unit outer shape layer file, the method further includes: The non-target data of the unit area data is filtered to obtain the target data; wherein the non-target data includes non-unit data and annotation description data.

5. The circuit board panel design method according to claim 1, characterized in that: The step of performing v-cut area identification on the panel layer file to obtain v-cut area data includes: Search the v-cut field of the panel layer file; The angle data and position data of the v-cut are obtained based on the v-cut field information.

6. The circuit board panel design method according to claim 1, characterized in that: The v-cut area data is constructed to obtain a v-cut layer, including: Performing information verification on the v-cut area data to obtain v-cut information; Verify the outline frame of the panel layer file to obtain the panel outline frame; The v-cut layer is generated based on the v-cut information and the panel outline frame.

7. The circuit board panel design method according to claim 1, characterized in that: The number of the units is multiple, and the generating of the set file based on the functional area graphics and the v-cut layer includes: Arrange the position of each of the units to obtain a unit area; Based on the unit area, a non-unit area is obtained; A process edge outline frame is configured for the non-unit area.

8. The circuit board panel design method according to claim 7, characterized in that: After generating the set file based on the functional area graph and the v-cut layer, the method further includes: Adding optical points to the circuit, and adding windows to the solder mask layer for the optical points; Generate a process edge, add a positioning hole to the drilling layer of the process edge, and add a window to the positioning hole in the solder mask layer; A copper layer is laid according to the outer contour of the process edge; wherein the copper layer is spaced apart from both the unit area and the v-cut area.

9. An electronic device, characterized in that The electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the circuit board panelization design method described in any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the circuit board panelization design method described in any one of claims 1 to 8 is implemented.

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