Peripheral interface testing method of chip and related equipment

Abstract

The invention provides a peripheral interface testing method of a chip and related equipment. The method comprises the following steps: in response to a received first instruction of an upper computer, writing data of a first data volume into a memory space of a peripheral interface; and in response to a received second instruction of the upper computer, reading the data in the memory space and writing the data into a target file, wherein the data written into the target file is discarded; obtaining the read-write duration of the data; and determining the transmission speed of the interface based on the read-write duration and the first data volume.

Description

Technical Field

[0001] The present disclosure relates to the field of chip verification, and in particular to a chip peripheral interface testing method and related equipment. Background Art

[0002] In the design and verification process of SoC (System on Chip) chips, when the simulation environment in the design verification phase is usually transitioned to the actual test phase of the automated test equipment (ATE), the simulation files created by the designer are often targeted at specific simulation tools and formats. The automated test equipment system may require test programs in different formats or instruction sets. Moreover, once the test program is compiled and deployed on the ATE, it is difficult to change the register settings of the device under test (DUT) if it needs to be modified during test development. These make the conversion between the simulation and ATE platforms complex and the register configuration inflexible, resulting in a long test development cycle and low iteration efficiency. Summary of the invention

[0003] The present invention discloses a chip peripheral interface testing method and related equipment to solve technical problems such as the conversion complexity between peripheral interface test simulation and ATE platform, the inflexibility of register configuration, the long test development cycle and the low iteration efficiency to a certain extent.

[0004] In a first aspect of the present disclosure, a method for testing a peripheral interface of a chip is provided, comprising:

[0005] In response to receiving a first instruction from the host computer, writing a first amount of data into the memory space of the peripheral interface; and

[0006] In response to receiving a second instruction from the host computer, reading the data in the memory space and writing the data into a target file; wherein the data written into the target file is discarded;

[0007] Obtaining the reading and writing time of the data;

[0008] A transmission speed of the interface is determined based on the read / write duration and the first data volume.

[0009] In a second aspect of the present disclosure, a peripheral interface testing device for a chip is provided, comprising:

[0010] A processing module, configured to write a first amount of data into the memory space of the peripheral interface in response to receiving a first instruction from the host computer; and to read the data in the memory space and write the data into a target file in response to receiving a second instruction from the host computer; wherein the data written into the target file is discarded;

[0011] The acquisition module is used to obtain the reading and writing time of the data

[0012] A speed module is used to determine the transmission speed of the interface based on the read and write duration and the first data volume.

[0013] In a third aspect of the present disclosure, an electronic device is provided, comprising one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method described in the first aspect.

[0014] According to a fourth aspect of the present disclosure, a non-volatile computer-readable storage medium containing a computer program is provided. When the computer program is executed by one or more processors, the processors execute the method described in the first aspect.

[0015] In a fifth aspect of the present disclosure, a computer program product is provided, comprising computer program instructions, which, when executed on a computer, enable the computer to execute the method described in the first aspect.

[0016] From the above description, it can be seen that the peripheral interface testing method and related equipment of a chip provided by the present invention can efficiently test the peripheral interface of the chip based on a host computer and a memory read and write test tool. Compared with the traditional ATE system-based testing method, it is lower in cost and can better support third-party testing organizations to perform functional testing and performance evaluation on the peripheral interface of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 Schematic diagram of a peripheral interface testing system for a chip according to an embodiment of the present disclosure.

[0019] Figure 2 The figure is a schematic diagram of the principle of the peripheral interface testing system of the chip according to the embodiment of the present disclosure.

[0020] Figure 3 The figure is a flow chart of a peripheral interface testing method of a chip according to an embodiment of the present disclosure.

[0021] Figure 4 Schematic diagram of a peripheral interface testing device for a chip according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0023] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0024] In the design and verification process of SoC (System on Chip) chips, the DDR4 interface is a key high-speed data transmission channel, and its performance and stability are directly related to the operating efficiency of the entire system. Designers usually use EDA (Electronic Design Automation) tools to create a detailed simulation environment to fully verify the functions of the chip before it is taped out. These simulation files not only contain the operating logic of the chip's internal structure and peripheral interfaces, but also involve the simulation of various register configurations, aiming to reproduce the data interaction process in real working scenarios. However, when the simulation environment in the design verification phase is transitioned to the actual test phase of ATE (Automatic Test Equipment), the EDA simulation files created by designers are often targeted at specific simulation tools and formats, while the ATE system may require test programs in different formats or instruction sets. Converting these high-level simulation models into test programs that ATE can recognize is not only time-consuming but also prone to errors, especially when it comes to complex DDR4 interface control logic. At the same time, once the test program is compiled and deployed on ATE, any subsequent adjustments to the internal registers of the DUT (Device Under Test) become extremely difficult. When the test work is performed by a third-party test organization, the design simulation files are often difficult to share, which will limit the test organization's ability to optimize the test plan. These problems together lead to longer test development and optimization cycles and reduce overall test efficiency. The need to quickly respond to market and technological changes requires that the test verification process has higher flexibility and maintainability. Therefore, how to reduce the conversion complexity between peripheral interface test simulation and ATE platform, improve the flexibility of register configuration, shorten the test development cycle and improve iteration efficiency have become technical problems that need to be solved urgently.

[0025] In view of this, the embodiments of the present disclosure provide a chip peripheral interface testing method and related equipment. Based on the host computer and memory read and write test tools, the chip peripheral interface is efficiently tested, which is lower in cost than the traditional ATE system-based testing method, and can better support third-party testing agencies to perform functional testing and performance evaluation on the chip peripheral interface.

[0026] See also Figure 1 , Figure 1 A schematic diagram of a chip peripheral interface testing system according to an embodiment of the present disclosure is shown. Figure 1In the example, chip U1 is connected to the host computer through the network port, and is connected to the peripheral interface (such as DDR4 interface chips U12, U14, U15, and U16) through the interface BANK 504. The data bus bandwidth between chip U1 and the peripheral interface is 64 bits, with double-edge transmission. Chip U1 provides clock and control signals to the peripheral interface through the clock address line and control line. Through the external DDR4 chip, the host computer software can be controlled to perform DDR4 tests, and read and write data tests can be performed in DDR4. The time used for reading and writing and the size of the data read and written can be obtained respectively, and the read and write speed test results can be calculated, and the test results can be sent to the host computer, and a test log can be generated.

[0027] See also Figure 2 , Figure 2 A schematic diagram showing the principle of a chip peripheral interface testing system according to an embodiment of the present disclosure is shown. Figure 2 In the test, the host computer supplies power to the test system through the PCIE interface, and clicks the DDR4 interface in the host computer software to test. To start the test, you can first apply for a storage space of the first data volume (for example, 1G size) in DDR4, and randomly write the first data volume into this space. After the writing is completed, read the written data. Get the time used for writing and reading, calculate the transmission speed, and send the result to the host computer through the serial port.

[0028] See also Figure 3 , Figure 3 A schematic flow chart of a chip peripheral interface testing method according to an embodiment of the present disclosure is shown. The chip peripheral interface testing method according to an embodiment of the present disclosure can be deployed on a chip. Figure 3 In the embodiment, the chip peripheral interface testing method 300 may further include the following steps.

[0029] In step S310, in response to receiving a first instruction from a host computer, data of a first data volume is written into the memory space of the peripheral interface.

[0030] The first instruction may point to an instruction for writing data to the memory space of the peripheral interface, and the first instruction may include at least one of the following: the written data and the written memory space address. The peripheral interface may be connected to the chip to implement an interface for the chip to communicate with the outside. For example, the peripheral interface may be a DDR4 chip.

[0031] In some embodiments, writing a first amount of data into the memory space of the peripheral interface includes: generating random data of the first amount of data, and writing the random data into the memory space.

[0032] Specifically, a storage space of a first data volume (for example, 1G in size) may be applied for in DDR4, and data of the first data volume may be randomly written into the space.

[0033] In some embodiments, before responding to receiving the first instruction, the method further includes:

[0034] In response to receiving a system startup instruction of the chip, a kernel is copied to the peripheral interface; and the kernel mounts a root file system of the chip.

[0035] Specifically, the system running on the chip may be a Linux system. After the Linux system is started, the kernel will be copied to the DDR4 through the boot loader. After the kernel is started, the root file system will be mounted before the corresponding DDR4 test program can be executed. Therefore, while testing the DDR4 transmission speed, there will be the overhead of the Linux system running other processes.

[0036] In some embodiments, the method 300 further includes: obtaining electrical energy from the host computer via a power supply interface to provide an operating voltage for the chip.

[0037] Specifically, Figure 2 The power supply interface may be a PCIE interface, and the host computer supplies power to the test system through the PCIE interface, which may trigger the DDR4 interface in the host computer software to perform a test.

[0038] In step S320, in response to receiving a second instruction from the host computer, the data in the memory space is read and written into a target file; wherein the data written into the target file is discarded.

[0039] Specifically, the theoretical operating speed of the DDR4 interface is 1200MHz, the data bus bandwidth is 64 bits, and the transmission is double-edge, so the theoretical data transmission speed of DDR4 is 1200*64*2=153600Mbps. Since the system board runs the Linux system, and the Linux system will copy the kernel to DDR4 through the boot loader after startup, the root file system will be mounted after the kernel starts, and then the corresponding DDR4 test program can be executed. Therefore, while testing the DDR4 transmission rate, there will be the overhead of the Linux system running other processes. The execution code of the time test instruction can specifically include:

[0040] #time dd if= / dev / me of= / dev / nul bs=1024k count=1024

[0041] 1024+0records in

[0042] 1024+0records out

[0043] Among them, time is the tool command for testing time, with an accuracy of ms. dd is a tool for reading and writing memory. if= / dev / mem means that data will be read from / dev / mem, which is a character device that provides access to the entire physical memory. of= / dev / null means that data will be written to / dev / null, which is an empty device, equivalent to a "trash can" that discards all data written to its device. bs represents the number of blocks in bytes, and count represents the number of blocks copied, so bs=1024k, count=1024 means that 1024k*1024=1G of data will be copied.

[0044] In step S330, the reading and writing duration of the data is obtained.

[0045] The read / write duration may refer to the duration used to write a preset amount of data in DDR4. For example, apply for a 1G storage space in DDR4 and randomly write 1G data into the space. Wait until the writing is complete, and then read the written data. Obtain the time used for writing and reading, calculate the transmission speed, and send the result to the host computer through the serial port.

[0046] In some embodiments, obtaining the reading and writing duration of the data includes:

[0047] Testing the execution time of executing the first instruction and the second instruction based on the time test instruction;

[0048] The execution duration is determined as the read and write duration.

[0049] The execution time of the second instruction may refer to the time taken to read from and write to / dev / null in DDR4.

[0050] Specifically, the output of the execution time test instruction may include:

[0051] real 0m0.933s

[0052] user 0m0.005s

[0053] sys 0m0.928s

[0054] Among them, real can refer to the total CPU time consumed from the start to the completion of instruction execution. This time includes the actual CPU time used when the process is executed, the time the process spends blocking (such as waiting for I / O operations to complete), and the time consumed by other processes (Linux is a multi-process system, and other processes may occupy the CPU during execution).

[0055] In some embodiments, the execution time of executing the second instruction based on the time test instruction test includes:

[0056] In response to executing the time test instruction, outputting the processor consumption time and kernel call time of executing the second instruction;

[0057] The execution time of the second instruction is obtained based on the sum of the processor consumption time and the kernel call time.

[0058] Specifically, in the output of the execution time test instruction, the user can use the CPU time consumed by the process to execute the current instruction. This time only refers to the CPU time actually used when the current instruction process is executed, and does not include the time used by other processes and the time when the current process is blocked.

[0059] sys can be used to calculate the CPU time consumed by the process to execute the current instruction in kernel mode, that is, the CPU time consumed by executing kernel system calls.

[0060] Therefore, the test time should be user+sys time. / dev / mem is a device that can directly access physical memory. Data cannot be written to it at will, otherwise the entire running system may crash. The test tool used obtains the DDR4 read data rate.

[0061] In step S340, the transmission speed of the interface is determined based on the read / write duration and the first data volume.

[0062] Specifically, the transmission speed of the interface can be obtained based on the first data volume divided by the read / write time.

[0063] In some embodiments, a test duration consumed by reading a second amount of data via the peripheral device interface is tested based on the time test instruction;

[0064] Determining a test speed of the time test instruction based on the test duration and the second data volume;

[0065] The test speed is determined to meet a preset accuracy based on a reference speed to determine the validity of the time test instruction.

[0066] Specifically, the time test instruction can be used to test the time taken to read 64M, 128M, 256M, 512M, and 1024M respectively, minus the time consumption caused by external factors such as the Linux system (calculated based on 94% of the consumption), and the calculation formula is: The test results can reach about 90%±5% of the theoretical value. It can be seen that the test results of the time test instruction meet the preset accuracy of 90%±5%, indicating that the test results of the time test instruction are valid data.

[0067] In some embodiments, the method 300 further includes: sending the transmission speed to the host computer.

[0068] Specifically, the test results can be sent to a host computer and a test log can be generated.

[0069] It can be seen that according to the method of the embodiment of the present invention, the DDR4 interface of the SoC chip can be efficiently tested based on the host computer and the memory read and write test tool. Compared with the traditional ATE system-based testing method, it is lower in cost and can better support third-party testing agencies to perform functional testing and performance evaluation on the DDR4 interface of the SoC chip.

[0070] It should be noted that the method of the embodiment of the present disclosure can be performed by a single device, such as a computer or a server. The method of the present embodiment can also be applied in a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present disclosure, and the multiple devices will interact with each other to complete the described method.

[0071] It should be noted that the above describes some embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0072] Based on the same technical concept, corresponding to any of the above-mentioned embodiments and methods, the present disclosure also provides a peripheral interface test device for a chip, see Figure 4 , the peripheral interface test device of the chip comprises:

[0073] A processing module, configured to write a first amount of data into the memory space of the peripheral interface in response to receiving a first instruction from the host computer; and to read the data in the memory space and write the data into a target file in response to receiving a second instruction from the host computer; wherein the data written into the target file is discarded;

[0074] The acquisition module is used to obtain the reading and writing time of the data

[0075] A speed module is used to determine the transmission speed of the interface based on the read and write duration and the first data volume.

[0076] For the convenience of description, the above device is described by dividing it into various modules according to its functions. Of course, when implementing the present disclosure, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0077] The device of the above embodiment is used to implement the peripheral interface testing method of the corresponding chip in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0078] Based on the same technical concept, corresponding to any of the above-mentioned embodiment methods, the present disclosure also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the peripheral interface testing method of the chip described in any of the above embodiments.

[0079] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0080] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the chip peripheral interface testing method described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0081] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0082] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present disclosure difficult to understand, the known power / ground connections to the integrated circuit (IC) chips and other components may or may not be shown in the provided figures. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present disclosure difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present disclosure will be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it is apparent to those skilled in the art that the embodiments of the present disclosure can be implemented without these specific details or with changes in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0083] Although the present disclosure has been described in conjunction with specific embodiments of the present disclosure, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0084] The embodiments of the present disclosure are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A chip peripheral interface testing method, comprising: In response to receiving a first instruction from the host computer, writing a first amount of data into the memory space of the peripheral interface; as well as In response to receiving a second instruction from the host computer, reading the data in the memory space and writing the data into a target file; wherein the data written into the target file is discarded; Obtaining the reading and writing time of the data; A transmission speed of the interface is determined based on the read / write duration and the first data volume.

2. The method according to claim 1, wherein Get the read and write duration of the data, including: Testing the execution time of executing the first instruction and the second instruction based on the time test instruction; The execution duration is determined as the read and write duration.

3. The method according to claim 2, wherein: Testing the execution time of executing the second instruction based on the time test instruction includes: In response to executing the time test instruction, outputting the processor consumption time and kernel call time of executing the second instruction; The execution time of the second instruction is obtained based on the sum of the processor consumption time and the kernel call time.

4. The method according to claim 1, wherein Writing a first amount of data into the memory space of the peripheral interface includes: Generate a first data amount of random data, and write the random data into the memory space.

5. The method according to claim 1, before responding to receiving the first instruction, further comprising: In response to receiving a system startup instruction of the chip, copying a kernel to the peripheral interface; The kernel mounts the root file system of the chip.

6. The method according to claim 2, further comprising: Testing the test time consumed by reading the second data amount of data via the peripheral interface based on the time test instruction; Determining a test speed of the time test instruction based on the test duration and the second data volume; The test speed is determined to meet a preset accuracy based on a reference speed to determine the validity of the time test instruction.

7. The method according to claim 1, further comprising: Obtaining electrical energy from the host computer via a power supply interface to provide an operating voltage for the chip; And / or, sending the transmission speed to the host computer.

8. A peripheral interface test device for a chip, comprising: A processing module, configured to write a first amount of data into the memory space of the peripheral interface in response to receiving a first instruction from the host computer; and in response to receiving a second instruction from the host computer, reading the data in the memory space and writing the data into a target file; wherein the data written into the target file is discarded; The acquisition module is used to obtain the reading and writing time of the data A speed module is used to determine the transmission speed of the interface based on the read and write duration and the first data volume.

9. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 7 when executing the program.

10. A non-volatile computer-readable storage medium containing a computer program, characterized in that: When the computer program is executed by one or more processors, the processors are caused to perform the method according to any one of claims 1 to 7.

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