Chip access verification method, electronic equipment and medium

Abstract

The invention relates to the technical field of chips, in particular to a chip access verification method, electronic equipment and a medium, and the method comprises the following steps: S1, obtaining a chip access verification configuration table; step S2, analyzing the chip access verification configuration table to obtain E0n and Emn corresponding to each Un; s3, generating an mth verification sequence template Fmn corresponding to the Un based on the E0n and the Emn corresponding to each Un; s4, randomly adding data and addresses in the Fmn, and generating an mth verification sequence Qmn corresponding to the Un; and S5, based on the Qmn, testing excitation is input to the chip access from a port between the Un and the chip access, the chip access is verified, and if all Qmn corresponding to all Un passes verification, verification of the chip access is passed. The chip access verification efficiency is improved, and the chip access verification cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip path verification method, electronic equipment and medium. Background Art

[0002] Existing chip designs usually include chip pathways and multiple functional units connected to the chip pathways. Commonly used chip pathways include Network-on-Chip (NoC), which is an internal communication method for integrated circuits and is suitable for highly complex System-on-Chip (SoC) with multiple processor cores, memory modules, and other functional units (such as DSP, GPU, various peripheral interfaces, etc.). In the prior art, if the chip pathway is to be verified, it is necessary to verify the chip pathway one by one based on each functional unit connected to the chip pathway, which has low verification efficiency and high verification cost. Therefore, how to improve the chip pathway verification efficiency and reduce the chip pathway verification cost has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The present invention aims to provide a chip path verification method, electronic equipment and medium, which improve the chip path verification efficiency and reduce the chip path verification cost.

[0004] According to a first aspect of the present invention, a chip path verification method is provided, comprising:

[0005] Step S1, obtain the chip path verification configuration table {E1, E2, ..., E n ,...,E N}, where E n The nth functional unit U connected to the chip path n The corresponding verification configuration information, n ranges from 1 to N, N is the total number of functional units connected to the chip path, E n =(E0 n ,E1 n ,E2 n ,...,E m n ,...,E M n ), E0 n For U n The corresponding shared configuration information, E m n For U n The configuration information of the corresponding m-th verification sequence template, where the value of m ranges from 1 to M, where M is the total number of verification templates, and the shared configuration information is the configuration information required by all M verification templates;

[0006] Step S2: parse the chip path verification configuration table to obtain each U n Corresponding E0 n and E m n ;

[0007] Step S3: Based on each U n Corresponding E0 n and E m n Generate U n The corresponding mth verification sequence template F m n ;

[0008] Step S4: m n Randomly add data and addresses to generate U n The corresponding mth verification sequence Q m n ;

[0009] Step S5: Based on Q m n From U n The port between the U and the chip path inputs the test stimulus to the chip path to verify the chip path. n All corresponding Q m n If all are verified, the chip path verification is passed.

[0010] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0011] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0012] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the chip path verification method, electronic device and medium provided by the present invention can achieve considerable technical advancement and practicality, and have wide industrial utilization value, and at least have the following beneficial effects:

[0013] The embodiment of the present invention pre-generates the configuration information required for the verification sequence template by setting a chip path verification configuration table, then generates a verification sequence template corresponding to each functional unit connected to the chip path based on the verification sequence template and the chip path verification configuration table, and then generates a corresponding test stimulus based on the verification sequence template to verify the chip path, thereby improving the chip path verification efficiency and accuracy and reducing the chip path verification cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A flow chart of a chip path verification method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0017] The embodiment of the present invention provides a chip path verification method, such as Figure 1 As shown, including:

[0018] Step S1, obtain the chip path verification configuration table {E1, E2, ..., E n ,...,E N}, where E n The nth functional unit U connected to the chip path n The corresponding verification configuration information, n ranges from 1 to N, N is the total number of functional units connected to the chip path, E n =(E0 n ,E1 n ,E2 n ,...,E m n ,...,E M n ), E0 n For U n The corresponding shared configuration information, E m n For U nThe configuration information of the corresponding m-th verification sequence template, where the value of m ranges from 1 to M, M is the total number of verification templates, and the shared configuration information is the configuration information required by all M verification templates.

[0019] Among them, the chip path is used to build the interconnection between the functional units of the chip, and the chip path can be specifically an on-chip network, etc. The chip path verification configuration table pre-sets the verification configuration information corresponding to all the functional units connected to the chip path. By setting shared configuration information, it is possible to reduce repeated processing of the same information, avoid errors, and improve the efficiency and accuracy of chip path verification.

[0020] Step S2: parse the chip path verification configuration table to obtain each U n Corresponding E0 n and E m n .

[0021] Specifically, the chip path verification configuration table can be parsed based on a preset script, and the preset script can be a python script. The chip path verification configuration table is parsed based on the preset script to obtain each U n Corresponding E0 n and E m n , which can further improve the efficiency of chip path verification.

[0022] Step S3: Based on each U n Corresponding E0 n and E m n Generate U n The corresponding mth verification sequence template F m n .

[0023] It should be noted that based on the shared configuration information E0 n , and U n The configuration information E of the corresponding mth verification sequence template m n Can determine U n The corresponding data structure of the mth verification sequence template generates U n The corresponding mth verification sequence template F m n .

[0024] Step S4: m n Randomly add data and addresses to generate U n The corresponding mth verification sequence Q m n .

[0025] It should be noted that when the mth verification sequence template F m n After generation, press F m n Configuration in F m n Randomly add data and addresses to generate U n The corresponding mth verification sequence Q m n , which can be achieved through the U mounted on the chip path n A corresponding sequencer is generated, and the sequencer may specifically be a Universal Verification Methodology (UVM) verification component.

[0026] Step S5: Based on Q m n From U n The port between the U and the chip path inputs the test stimulus to the chip path to verify the chip path. n All corresponding Q m n If all are verified, the chip path verification is passed.

[0027] It should be noted that the specific U mounted on the chip path n The corresponding driving component transmits the test stimulus to the chip path, and then based on the U mounted on the chip path n The corresponding monitoring component obtains the result output by the chip path and compares it with the preset result, thereby realizing the chip path based on U n For verification, the driving component and the monitoring component are verification components.

[0028] As an embodiment, the shared configuration information includes one or more of the following configuration information: interface clock, number of ports, data bit width, boundary alignment, early response, receiving end read address interleaving, mixed sending of write data and address channel, guaranteed request response, narrow channel trigger request, and support for receiving incomplete response time. It should be noted that the interface clock, number of ports, and data bit width are commonly used configuration information and usually need to be set. Boundary alignment, early response, receiving end read address interleaving, mixed sending of write data and address channel, guaranteed request response, narrow channel trigger request, and support for receiving incomplete response time are configured according to specific application requirements.

[0029] As an embodiment, the M verification sequence templates include a read operation verification sequence template, a write operation verification sequence template, an atomic operation verification sequence template, a burst operation verification sequence template, and an outstanding operation verification sequence template. Among them, in computer memory and storage systems, Burst operation is an efficient data access mode. When the system requests to read or write data from a series of consecutive addresses in the memory, it only needs to specify the starting address and burst length (BurstLength), and subsequent data accesses will be automatically performed in sequence, reducing the address signal and control overhead required for each access and improving the transmission speed. Outstanding operations refer to transactions that have been initiated but not yet completed or responded to. It should be noted that each U n At least corresponding to one of the read operation and the write operation, the atomic operation, the burst operation, and the Burst operation are all implemented based on the read and / or write operation.

[0030] As an embodiment, the configuration information of the read operation verification sequence template includes a typical read request length, an atypical read request maximum length, and an atypical read request minimum length, wherein a typical read request refers to a preset conventionally implemented read request, and an atypical read request refers to a preset unconventionally implemented read request.

[0031] As an embodiment, the configuration information of the write operation verification sequence template includes a typical write request length, a maximum length of an atypical write request, and a minimum length of an atypical write request; wherein a typical write request refers to a preset conventionally implemented write request, and an atypical write request refers to a preset unconventionally implemented write request.

[0032] As an embodiment, the configuration information of the atomic operation verification sequence template includes the custom interface information supported by the atomic operation, and the configuration information of the burst operation verification sequence template includes the trigger identification of the group that only supports the incremental mode. The configuration information of the outstanding operation verification sequence template includes the maximum number of outstanding writes supported, the maximum ID count of write requests, the maximum number of outstanding reads supported, the maximum ID count of read requests, the maximum number of outstanding data network control hubs supported, and the width of the AXI protocol ID.

[0033] As an embodiment, the configuration information of the atomic operation verification sequence template is a first identifier or a second identifier, the first identifier indicates support, and the second identifier indicates non-support. It should be noted that if the configuration information of the atomic operation verification sequence template is the second identifier, it means that there is no need to generate an atomic operation verification sequence template.

[0034] As an embodiment, the configuration information of the burst operation verification sequence template is the first identifier or the second identifier. It should be noted that if the configuration information of the burst operation verification sequence template is the second identifier, it means that there is no need to generate the burst operation verification sequence template.

[0035] As an embodiment, the configuration information of the read operation verification sequence template is all second identifiers or all specific values. When the configuration information of the read operation verification sequence template is all specific values, it indicates that the read operation function is supported, and each configuration information is set with a specific value.

[0036] As an embodiment, the configuration information of the write operation verification sequence template is all second identifiers or all specific values. When the configuration information of the write operation verification sequence template is all specific values, it indicates that the write operation function is supported, and each configuration information is set with a specific value.

[0037] It should be noted that at least one of the configuration information of the read operation verification sequence template and the configuration information of the write operation verification sequence template is not entirely the second identifier, that is, based on U n The verification of the chip path has at least one of the read operation and the write operation functions.

[0038] As an embodiment, the maximum unfinished number of write supports and the maximum ID count of write requests in the configuration information of the outstanding operation verification sequence template are all second identifiers or all specific values, the maximum unfinished number of read supports and the maximum ID count of read requests in the configuration information of the outstanding operation verification sequence template are all second identifiers or all specific values, and the maximum unfinished number of data network control hubs and the width of AXI protocol IDs in the configuration information of the outstanding operation verification sequence template are specific values. It can be understood that the outstanding operation can only support functions related to read operations, or only support functions related to write operations, or support both read operations and write operations.

[0039] As an embodiment, step S3 includes:

[0040] Step S31: Determine U n The corresponding E m n Are all second identifiers? If so, do not generate U n The corresponding mth verification sequence template, otherwise, execute step S32.

[0041] It should be noted that if E m n If all are second identifiers, it means that Un The function corresponding to the mth verification sequence template, therefore, does not need to generate U n The corresponding mth verification sequence template.

[0042] Step S32: Based on U n Corresponding E0 n and E m n The configuration information of the second identifier is not generated U n The corresponding mth verification sequence template F m n .

[0043] U n The corresponding mth verification sequence Q m n It may be one or more, U n The number of ports between the chip and the channel may also be one or more. When all ports are one, the number of ports is based on a Q m n Delivers a test stimulus to a port.

[0044] As an example, U n The corresponding Q m n There are multiple,U n There are one or more ports between the chip path and the chip path, and the step S5 includes:

[0045] Step S51: Based on multiple Q m n Generate a test stimulus input sequence P according to the preset stimulus input sequence m n .

[0046] The specific preset stimulus input sequence is set according to the verification stage of the chip path and the verification requirements of the chip path, which may be multiple Q-based m n Generate test stimulus input sequence P m n , or it may be based on multiple Q m n Cross-generate test stimulus input sequence P m n .

[0047] Step S52: According to P m n The order of n Each port between the chip paths sends a test stimulus to verify the chip paths.

[0048] Through step S52, Un The multiple ports between the chip paths are in a mirrored relationship, that is, the test stimulus of each port interface is always consistent.

[0049] As an example, U n The corresponding Q m n There are multiple,U n There are multiple ports between the chip and the channel, and step S5 includes:

[0050] Step C51: n The ports between the chip paths are divided into f(n) groups {R1 n ,R2 n ,...,R i n ,...,R f(n) n}, R i n For U n Corresponding to the i-th group of ports, each R i n Include at least one port.

[0051] It should be noted that, in step C51, U n The ports between the chip paths are divided into multiple groups.

[0052] Step C52: Based on one or more U n The corresponding Q m n For each R i n Generate the corresponding test stimulus input sequence PR according to the corresponding preset stimulus input sequence i n .

[0053] It should be noted that, in step C52, a corresponding test stimulus input sequence is generated for each group of ports.

[0054] Step C53: Based on each R i n Corresponding PR i n Parallel to each R i n The chip path is verified by sending test stimulus in.

[0055] It should be noted that step C53 can realize the U n Parallel verification of corresponding groups of ports.

[0056] Through the above different embodiments, the chip path can be verified in different scenarios, thereby achieving comprehensive verification of the chip path.

[0057] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0058] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0059] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0060] The embodiment of the present invention pre-generates the configuration information required for the verification sequence template by setting a chip path verification configuration table, then generates a verification sequence template corresponding to each functional unit connected to the chip path based on the verification sequence template and the chip path verification configuration table, and then generates a corresponding test stimulus based on the verification sequence template to verify the chip path, thereby improving the chip path verification efficiency and accuracy and reducing the chip path verification cost.

[0061] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A chip path verification method, characterized in that: include: Step S1, obtain the chip path verification configuration table {E1, E2, ..., E n ,...,E N }, where E n The nth functional unit U connected to the chip path n The corresponding verification configuration information, n ranges from 1 to N, N is the total number of functional units connected to the chip path, E n =(E0 n ,E1 n ,E2 n ,...,E m n ,...,E M n ), E0 n For U n The corresponding shared configuration information, E m n For U n The configuration information of the corresponding m-th verification sequence template, where the value of m ranges from 1 to M, where M is the total number of verification templates, and the shared configuration information is the configuration information required by all M verification templates; Step S2: parse the chip path verification configuration table to obtain each U n Corresponding E0 n and E m n ; Step S3: Based on each U n Corresponding E0 n and E m n Generate U n The corresponding mth verification sequence template F m n ; Step S4: m n Randomly add data and addresses to generate U n The corresponding mth verification sequence Q m n ; Step S5: Based on Q m n From U n The port between the U and the chip path inputs the test stimulus to the chip path to verify the chip path. n All corresponding Q m n If all are verified, the chip path verification is passed.

2. The method according to claim 1, characterized in that The shared configuration information includes one or more of interface clock, port number, data bit width, boundary alignment, early response, receiving end read address interleaving, mixed sending of write data and address channels, guaranteed request response, narrow channel trigger request, and support for receiving incomplete response time configuration information.

3. The method according to claim 1, characterized in that The M verification sequence templates include a read operation verification sequence template, a write operation verification sequence template, an atomic operation verification sequence template, a burst operation verification sequence template, and an outstanding operation verification sequence template.

4. The method according to claim 3, characterized in that The configuration information of the read operation verification sequence template includes a typical read request length, a maximum length of an atypical read request, and a minimum length of an atypical read request; The configuration information of the write operation verification sequence template includes a typical write request length, a maximum length of an atypical write request, and a minimum length of an atypical write request; The configuration information of the atomic operation verification sequence template includes the atomic operation support custom interface information; The configuration information of the burst operation verification sequence template includes the flag that only the incremental mode group trigger is supported; The configuration information of the outstanding operation verification sequence template includes the maximum outstanding number of writes supported, the maximum ID count of write requests, the maximum outstanding number of reads supported, the maximum ID count of read requests, the maximum outstanding number of data network control hub support, and the width of the AXI protocol ID.

5. The method according to claim 4, characterized in that The configuration information of the atomic operation verification sequence template is a first identifier or a second identifier, the first identifier indicates support, and the second identifier indicates non-support; The configuration information of the burst operation verification sequence template is the first identifier or the second identifier; The configuration information of the read operation verification sequence template is all the second identifier or all the specific numerical values, the configuration information of the write operation verification sequence template is all the second identifier or all the specific numerical values, and at least one of the configuration information of the read operation verification sequence template and the configuration information of the write operation verification sequence template is not all the second identifier; The maximum incomplete number of writes supported and the maximum ID count of write requests in the configuration information of the outstanding operation verification sequence template are all second identifiers or all specific values, the maximum incomplete number of reads supported and the maximum ID count of read requests in the configuration information of the outstanding operation verification sequence template are all second identifiers or all specific values, and the maximum incomplete number of data network control center supported and the width of AXI protocol ID in the configuration information of the outstanding operation verification sequence template are specific values.

6. The method according to claim 5, characterized in that The step S3 comprises: Step S31: Determine U n The corresponding E m n Are all second identifiers? If so, do not generate U n The corresponding mth verification sequence template, otherwise, execute step S32; Step S32: Based on U n Corresponding E0 n and E m n The configuration information of the second identifier is not generated U n The corresponding mth verification sequence template F m n .

7. The method according to claim 5, characterized in that U n The corresponding Q m n There are multiple,U n There are one or more ports between the chip path and the chip path, and the step S5 includes: Step S51: Based on multiple Q m n Generate a test stimulus input sequence P according to the preset stimulus input sequence m n ; Step S52: According to P m n The order of n Each port between the chip paths sends a test stimulus to verify the chip paths.

8. The method according to claim 5, characterized in that U n The corresponding Q m n There are multiple,U n There are multiple ports between the chip and the channel, and step S5 includes: Step C51: n The ports between the chip paths are divided into f(n) groups {R1 n ,R2 n ,...,R i n ,...,R f(n) n }, R i n For U n Corresponding to the i-th group of ports, each R i n Include at least one port; Step C52: Based on one or more U n The corresponding Q m n For each R i n Generate the corresponding test stimulus input sequence PR according to the corresponding preset stimulus input sequence i n ; Step C53: Based on each R i n Corresponding PR i n Parallel to each R i n The chip path is verified by sending test stimulus in.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method of any one of the preceding claims 1-8.

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