PCB (Printed Circuit Board) packaging structure for improving performance of large-size QFN (Quad Flat No-lead) chip and design method thereof

Abstract

The invention provides a PCB (Printed Circuit Board) packaging structure for improving the performance of a large-size QFN (Quad Flat No-lead) chip and a design method of the PCB packaging structure, which are characterized in that hot bonding pads of PCB packaging are uniformly divided into n bonding pad arrays, and power supply wires penetrate through gaps among the hot bonding pads of TOP layers and connect power supply pins dispersed on four sides, and a power supply plane of a net structure is formed; and meanwhile, a backflow path is prevented from being cut off when a power line is routed on the bottom layer, so that the chip has a good and complete GND plane on the bottom layer, and finally high-performance stable operation of the chip on the PCB with a two-layer board structure is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic packaging, and in particular relates to a PCB packaging structure for improving the performance of a large-size QFN chip and a design method thereof. Background Art

[0002] With the development of semiconductor technology, the importance of chip packaging technology in the chip industry chain has been further demonstrated. QFN is one of the most popular packaging technologies at present. Many packaging factories have already achieved large-scale mass production of QFN products with a size of 12.3mmX12.3mm, more than 400 wire bonds, multiple die stacking, and 6-layer wire bonding. In recent years, with the improvement of QFN packaging technology and changes in market demand, large-size QFN with thermal pads has gradually replaced ordinary BGA packaging. Some high-performance processors such as video surveillance chips have also begun to switch from the previous high-cost BGA to QFN packaging to achieve low cost.

[0003] These high-performance processor chips require more power paths and lower core voltage, so the requirements for ground plane design are very high. To meet high performance requirements, the chip PCB design uses a four-layer or above structure to ensure the integrity of the power and ground planes.

[0004] However, the application market of QFN packaged chip products pursues the ultimate cost advantage, requiring the use of a two-layer board design in PCB design. High-performance processor chips have many IO pins, and the pins of the chip core power supply and IO power supply are scattered. There are pins arranged in the four directions of the package. Because of its large DIE size, the base island (that is, the thermal pad on the package) of its frame design must be larger than the die size requirement. As a result, in the package pin structure, the gap between the thermal pad and the surrounding pins is not enough to connect the core power pins scattered on the four sides of the chip through the PCB routing of the TOP layer (the welding surface of the chip), and it is even more impossible to form a power plane. If the power routing changes layers and passes through the bottom layer below the base island to connect the power pins in other directions, it will cause the ground plane to be split, resulting in an incomplete ground plane.

[0005] Therefore, when this kind of high-performance processor chip with large-size QFN package is laid out and routed on a 2-layer board, due to the influence of its package pin structure and the scattered arrangement of power pins, there is no relatively complete power and ground plane, which leads to the high-performance processor's main frequency not being able to be increased in performance.

[0006] In addition, commonly used technical terms include:

[0007] QFN: Quad Flat No-Lead, is a leadless flat package, which is a surface mount technology used for packaging of integrated circuits.

[0008] BGA: Ball Grid Array Package, is a ball grid array packaging technology, which is a surface mount technology used for integrated circuit packaging. Many CPUs, motherboard south and north bridge chips use BGA packaging.

[0009] PCB: Printed Circuit Board, also known as printed circuit board, is a carrier for electrical connections between electronic components. Summary of the invention

[0010] In order to solve the above problems, the purpose of this application is to: through a method of changing the PCB packaging structure of a large-size QFN chip, the thermal pads of the PCB package are evenly divided into an array of multiple pads, and the gaps between the thermal pads of the TOP layer are used to realize that the power line passes through the gaps and connects the power pins scattered on the four sides, and a power plane with a mesh structure can be formed. Therefore, when a high-performance processor chip with a large-size QFN package adopts a 2-layer PCB design, the power line uses the gaps between the PCB package thermal pad arrays to greatly increase the TOP layer routing, so that the ground plane of the bottom layer is more complete, thereby improving the performance of the high-performance processor on the 2-layer PCB structure.

[0011] Specifically, the present invention provides a design method for a PCB packaging structure for improving the performance of a large-size QFN chip, the design method comprising the following steps:

[0012] S1, selecting a pad array of n rows and n columns according to the specific pad size of the large-size QFN package, where n is a positive integer ≥ 2;

[0013] S2, the pad array spacing design rule meets the requirements of the printed circuit board PCB process for the spacing between the line and the pad and the current overcurrent capacity of the power line, that is, the pad array spacing S is greater than or equal to the line width W of the power line plus 2 times the safety spacing d:

[0014] S≥W+2×d Formula (1);

[0015] S3, the relationship between the side length ɑ of a single pad in an n-row n-column pad array and the original thermal pad length L of the chip package is designed according to the following formula:

[0016]

[0017] S4, according to the specifically obtained pad array of n rows and n columns, the pad array spacing S and the side length ɑ of a single pad, the positional relationship of each pad with a pad gap is obtained to perform PCB packaging design.

[0018] The matrix structure in step S1 includes: n=2, 2X2, i.e., a matrix structure of 2 rows and 2 columns; n=3, 3X3, i.e., a matrix structure of 3 rows and 3 columns.

[0019] The step S2 further comprises:

[0020] The factory printed circuit board PCB process can achieve a safe distance between the line and the pad of 4mil, and a safe distance between the copper and the pad of 8mil;

[0021] The relationship between the current passing through the PCB power line, the cross-sectional area of ​​the line, and the temperature rise is as follows:

[0022] I=KΔT 0.44 A 0.725 Formula (3),

[0023] Where, I: maximum allowable current; K: correction factor, which is 0.024 when the copper wire is in the inner layer and 0.048 when it is in the outer layer; ΔT: temperature rise relative to the environment, expressed in degrees Celsius; A: trace cross-sectional area, which is the product of the trace width and the PCB copper thickness, in square mil, 1mil = 0.0254mm;

[0024] When the PCB copper thickness is measured in ounces, 1oz = 35um.

[0025] Assume that the QFN chip has 128 pins, a package size of 12.3 mm x 12.3 mm, a pin pitch of 0.4 mm, and a thermal pad of 8 x 8 mm;

[0026] If the chip power supply through the gap of the pad array requires a current capacity of 500mA, the copper thickness of the PCB surface is 1 / 2oz, and the temperature rise ΔT = 3 degrees, according to the relationship between line width, copper thickness, temperature rise and current (3), the line width of the power line W ≈ 19mil;

[0027] According to formula (1), the pad array spacing S ≥ 27mil≈0.7mm;

[0028] The thermal pad of the PCB package is designed into a 3X3 pad matrix PCB package structure;

[0029] According to formula (2), a single pad constituting the pad matrix can be designed as a square pad with a side length of no more than 2.2 mm.

[0030] The design method evenly divides the thermal pads of the PCB package into an array of n pads, and utilizes the gaps between the thermal pads of the TOP layer to allow the power line to pass through the gaps and connect the power pins scattered on the four sides, thereby forming a power plane with a mesh structure; at the same time, it avoids the power line cutting the return path when routing on the bottom layer, so that the chip has a good and complete GND plane on the bottom layer, and finally realizes high-performance and stable operation of the chip on the PCB with a two-layer board structure.

[0031] The present application also relates to a PCB packaging structure for improving the performance of a large-size QFN chip, wherein the packaging structure is obtained according to any of the above-mentioned design methods, and the packaging structure comprises:

[0032] The thermal pads of the PCB package are evenly divided into an array of n pads. The gaps between the thermal pads of the TOP layer are used to allow the power line to pass through the gaps in the pad array to connect the power pins scattered on the four sides, thereby making the ground plane of the bottom layer more complete.

[0033] The QFN packaged chip product adopts a 2-layer board design in PCB design, the pins of the chip core power supply and the pins of the IO power supply are dispersed, and the pins are arranged in the four directions of the package.

[0034] Therefore, the advantages of the present application are: the present application is a QFN packaging structure and design method that evenly divides the thermal pads of the PCB package into an array of multiple pads, so that the power pins distributed around the package can use the gaps in the pad array to route out, improving the GND splitting caused by the wiring at the bottom, greatly improving the ground plane of the chip on the PCB with a 2-layer board structure, and ultimately achieving high-performance and stable operation of a large-size QFN packaged chip on a PCB with a 2-layer board structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present invention, constitute a part of this application, and do not constitute a limitation of the present invention.

[0036] Figure 1 It is a flow chart of the present application method.

[0037] FIG2(1) is a schematic diagram of the relationship curve of the current (A) passing through a 0.5 oz copper clad thickness PCB involved in the present application.

[0038] FIG2(2) is a schematic diagram of the relationship curve of the current (A) passing through a PCB with a copper cladding thickness of 1 oz involved in the present application.

[0039] Figure 3 It is a comparison diagram of the original PCB package and the PCB package with a pad array structure. DETAILED DESCRIPTION

[0040] In order to more clearly understand the technical content and advantages of the present invention, the present invention is now further described in detail in conjunction with the accompanying drawings.

[0041] The present application relates to a packaging structure and a design method for evenly dividing the thermal pads of a PCB package into an array of multiple pads, so that the power line can pass through the gaps in the pad array to connect the power pins scattered on the four sides, so that the ground plane of the bottom layer is more complete. According to the specific pad size of the large-size QFN package, a 2X2 (2 rows and 2 columns) matrix structure, a 3X3 (3 rows and 3 columns) matrix structure or a pad array with more rows and columns (n ​​rows and n columns) is selected.

[0042] like Figure 1 As shown, the design method of the PCB packaging structure for improving the performance of large-size QFN chips includes the following steps:

[0043] S1, selecting a pad array of n rows and n columns according to the specific pad size of the large-size QFN package, where n is a positive integer ≥ 2;

[0044] S2, the pad array spacing design rule meets the requirements of the printed circuit board PCB process for the spacing between the line and the pad and the current overcurrent capacity of the power line, that is, the pad array spacing S is greater than or equal to the line width W of the power line plus 2 times the safety spacing d:

[0045] S≥W+2×d Formula (1);

[0046] S3, the relationship between the side length ɑ of a single pad in an n-row n-column pad array and the original thermal pad length L of the chip package is designed according to the following formula:

[0047]

[0048] Generally, the PCB process of printed circuit boards in factories can achieve a safe spacing of 4 mil between wires and pads, and a safe spacing of 8 mil between copper and pads. In PCB design, the power supply can connect different component pins of the same power supply network together through copper or wire. That is, if the power supply routing method is different, the corresponding d in formula (1) is different.

[0049] Figure 2(1)(2) is a schematic diagram of the PCB line width, copper thickness, temperature rise and current involved. The relationship curves between the temperature rise and current of PCB traces of different widths under 1 / 2oz (left Figure 2(1)) and 1oz (right Figure 2(2)) PCB copper thickness are shown. The relationship between the current passing through the PCB power trace and the trace cross-sectional area (the product of the line width and the PCB copper foil thickness) and the temperature rise are expressed as follows:

[0050] I=KΔT 0.44 A0.725 Formula (3)

[0051] I: Maximum allowable current

[0052] K: Correction coefficient. Generally, it is 0.024 when the copper wire is in the inner layer and 0.048 when it is in the outer layer.

[0053] ΔT: Temperature rise relative to the environment (℃)

[0054] A: Cross-sectional area of ​​the trace, unit: square mil, 1mil = 0.0254mm

[0055] Generally, the PCB copper thickness is measured in ounces (oz), 1oz = 35um.

[0056] The relationship between the side length ɑ of a single pad in an n-row and n-column pad array and the original thermal pad length L of the chip package can be designed according to the following formula:

[0057]

[0058] S4, according to the specifically obtained pad array of n rows and n columns, the pad array spacing S and the pad side length ɑ, the positional relationship of each pad with a pad gap is obtained to perform PCB packaging design.

[0059] The design method evenly divides the thermal pads of the PCB package into an array of n pads, and utilizes the gaps between the thermal pads of the TOP layer to allow the power line to pass through the gaps and connect the power pins scattered on the four sides, thereby forming a power plane with a mesh structure; at the same time, it avoids the power line cutting the return path when routing on the bottom layer, so that the chip has a good and complete GND plane on the bottom layer, and finally realizes high-performance and stable operation of the chip on the PCB with a two-layer board structure.

[0060] Take a large-size 128-pin QFN chip model X2670 produced by Beijing Ingenic Integrated Circuit Co., Ltd. (Ingenic for short) as an example. Its package size is 12.3mmX12.3mm, the pin spacing is 0.4mm, and the thermal pad is 8X8mm. If the chip power supply through the gap of the pad array requires a current capacity of 500mA, the PCB surface copper thickness is 1 / 2oz, and the temperature rise ΔT = 3 degrees, according to the relationship between line width, copper thickness, temperature rise and current (3), the power line width W≈19mil. According to formula (1), the pad array spacing S≥27mil≈0.7mm.

[0061] The thermal pad of the PCB package is designed as a PCB package structure of a 3X3 pad matrix. According to formula (2), the individual pads constituting the pad matrix can be designed as square pads with a side length of no more than 2.2 mm.

[0062] like Figure 3 As shown, Figure 3 The left picture is the original PCB package. Figure 3 The right picture in the figure is a PCB package with a pad array structure. This pad array structure allows the power pins around the chip to use the gaps between the pads to route the wires, forming a mesh structure of power routing on the TOP layer to realize the power plane. At the same time, it avoids the power line routing on the bottom layer cutting the return path, so that the chip has a good and complete GND plane on the bottom layer, and finally realizes high-performance and stable operation of the chip on the 2-layer PCB structure.

[0063] When using the original PCB package layout and routing performance on a 2-layer PCB, the maximum stable operating frequency of X2670 can only reach 600MHz. However, when it is replaced with a PCB package layout and routing using a pad array structure, its stable operating frequency reaches 900MHz, and its performance is greatly improved.

[0064] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A design method for a PCB packaging structure for improving the performance of a large-size QFN chip, characterized in that: The design method The following steps are involved: S1, selecting a pad array of n rows and n columns according to the specific pad size of the large-size QFN package, where n is a positive integer ≥ 2; S2, the pad array spacing design rule meets the requirements of the printed circuit board PCB process for the spacing between the line and the pad and the current overcurrent capacity of the power line, that is, the pad array spacing S is greater than or equal to the line width W of the power line plus 2 times the safety spacing d: S≥W+2×d Formula (1); S3, the relationship between the side length ɑ of a single pad in an n-row n-column pad array and the original thermal pad length L of the chip package is designed according to the following formula: S4, according to the specifically obtained pad array of n rows and n columns, the pad array spacing S and the side length ɑ of a single pad, the positional relationship of each pad with a pad gap is obtained to perform PCB packaging design.

2. The design method of a PCB packaging structure for improving the performance of a large-size QFN chip according to claim 1, characterized in that: The matrix structure in step S1 includes: n=2, 2X2, i.e., a matrix structure with 2 rows and 2 columns; n=3, 3X3, i.e., a matrix structure with 3 rows and 3 columns.

3. The design method of a PCB packaging structure for improving the performance of a large-size QFN chip according to claim 1, characterized in that: The step S2 further comprises: The factory printed circuit board PCB process achieves a safe distance between the line and the pad of 4mil, and a safe distance between the copper and the pad of 8mil; The relationship between the current passing through the PCB power line, the cross-sectional area of ​​the line, and the temperature rise is as follows: I=KΔT 0.44 A 0.725 Equation (3), Where, I: maximum allowable current; K: correction factor, which is 0.024 when the copper wire is in the inner layer and 0.048 when it is in the outer layer; ΔT: temperature rise relative to the environment, expressed in degrees Celsius; A: trace cross-sectional area, which is the product of the trace width and the PCB copper thickness, in square mil, 1mil = 0.0254mm; When the PCB copper thickness is measured in ounces, 1oz = 35um.

4. The method for designing a PCB packaging structure for improving the performance of a large-size QFN chip according to claim 3, characterized in that: Assume that the QFN chip has 128 pins, a package size of 12.3 mm x 12.3 mm, a pin pitch of 0.4 mm, and a thermal pad of 8 x 8 mm; If the chip power supply through the gap of the pad array requires a current capacity of 500mA, the copper thickness of the PCB surface is 1 / 2oz, and the temperature rise ΔT = 3 degrees, according to the relationship between line width, copper thickness, temperature rise and current (3), the line width of the power line W ≈ 19mil; According to formula (1), the pad array spacing S ≥ 27mil≈0.7mm; The thermal pad of its PCB package is designed into a PCB package structure of a 3X3 pad matrix; According to formula (2), a single pad constituting the pad matrix can be designed as a square pad with a side length of no more than 2.2 mm.

5. The design method of a PCB packaging structure for improving the performance of a large-size QFN chip according to claim 1, characterized in that: The design method evenly divides the thermal pads of the PCB package into an array of n pads, and utilizes the gaps between the thermal pads of the TOP layer to allow the power line to pass through the gaps and connect the power pins scattered on the four sides, thereby forming a power plane with a mesh structure; at the same time, it avoids the power line cutting the return path when routing on the bottom layer, so that the chip has a good and complete GND plane on the bottom layer, and finally realizes high-performance and stable operation of the chip on the PCB with a two-layer board structure.

6. A PCB packaging structure for improving the performance of a large-size QFN chip, characterized in that: The packaging structure is obtained according to the design method according to any one of claims 1 to 5 above, and the packaging structure includes: The thermal pads of the PCB package are evenly divided into an array of n pads. The gaps between the thermal pads of the TOP layer are used to allow the power line to pass through the gaps in the pad array to connect the power pins scattered on the four sides, thereby making the ground plane of the bottom layer more complete.

7. The PCB packaging structure for improving the performance of large-size QFN chips according to claim 6, characterized in that: The QFN packaged chip product adopts a two-layer board design in PCB design, and the pins of the chip core power supply and the IO power supply are dispersed and arranged in the four directions of the package.

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