Flip-chip bonding column placing method of superconducting quantum chip

Abstract

The invention discloses a method for placing a flip-chip bonding column of a superconducting quantum chip, and belongs to the field of superconducting quantum chip design, and the method comprises the steps: carrying out the fine processing of a layout boundary, the interior and boundary of a placed module unit, and a grid where a placed wire is located, marking a special grid type, and employing a secondary placement strategy. The flip-chip welding column placing flexibility and the space utilization rate can be improved while high efficiency and high precision are guaranteed. The method is efficient, accurate and flexible, the chip design quality and production efficiency can be remarkably improved, and the blank that an existing commercial EDA tool temporarily has no inverted column full-automatic layout function is filled.

Description

Technical Field

[0001] The present invention belongs to the field of superconducting quantum chip design, and more specifically, relates to a method for placing flip-chip solder columns of a superconducting quantum chip. Background Art

[0002] During the manufacturing process of superconducting quantum chips, flip-chip solder columns are placed in the idle areas to improve the integrity of the power supply and the mechanical strength of the chip. Flip-chip solder columns are not only used to achieve the reliability of the internal electrical connection of the chip, but also to enhance the mechanical strength and heat dissipation performance of the chip. Due to the complexity of chip design and the tiny size, the number of flip-chip solder columns is often very large, and the accuracy and efficiency of their placement directly affect the overall performance and production cost of the chip. Therefore, how to efficiently and accurately place flip-chip solder columns in the idle area of ​​the chip is an important factor affecting chip design and production quality.

[0003] During the placement of flip chip solder pillars, there is a significant difference between traditional manual placement methods and modern electronic design automation (EDA) tool placement methods.

[0004] The manual placement method of flip-chip solder pillars mainly relies on the designer's experience and manual operation. The advantage of this method is that the designer can flexibly adjust the placement of the flip-chip pillars according to the actual situation to cope with complex and special layout requirements. However, the manual placement method also has many disadvantages:

[0005] 1. Slow speed: Since the inverted columns need to be placed manually one by one, the speed of manual placement is relatively slow. Especially when there are a large number of inverted columns, the placement process is extremely time-consuming.

[0006] 2. Low precision: Manual operation inevitably involves human errors, and the placement of the inverted pillars may deviate, affecting the electrical performance and mechanical strength of the chip.

[0007] 3. Poor consistency: Different designers have different operating habits and experience levels, resulting in poor placement consistency, making it difficult to ensure that the inverted column placement of each chip is completely consistent.

[0008] 4. Low efficiency: Manual placement requires designers to repeatedly adjust and check, and the overall efficiency is low, which is difficult to meet the needs of large-scale production.

[0009] Compared with manual placement, the EDA tool placement method utilizes computer algorithms and automation technology to greatly improve the efficiency and accuracy of inverted pillar placement. It only requires inputting parameters such as the layout of the board and the safe spacing for inverted pillar placement. The main advantages of the EDA tool placement method include:

[0010] 1. Fast speed: EDA tools can complete the placement of a large number of inverted pillars in a short time. Through algorithm optimization, the tool can complete the precise placement of thousands of inverted pillars in a few seconds.

[0011] 2. High precision: EDA tools can ensure the accurate position of each inverted column through precise calculation and control, significantly reducing human errors.

[0012] 3. Strong consistency: Automated tools can ensure that the results of each placement are completely consistent and are not affected by human factors, thereby improving the quality consistency of the chip.

[0013] 4. High flexibility: Modern EDA tools are highly flexible and can automatically adjust the placement of inverted pillars according to different layout requirements and design rules to meet the requirements of complex designs.

[0014] 5. In addition, EDA tools can also combine a variety of optimization strategies, such as processing the layout through a grid partitioning model, flexibly adjusting the grid size, and marking the grid type to improve the efficiency and rationality of inverted pillar placement. In contrast, manual placement often seems to be incapable of doing so when faced with complex layouts and a large number of inverted pillars, making it difficult to ensure the quality and efficiency of the overall design.

[0015] In the process of flip-chip solder column placement, the technical challenges mainly lie in how to balance speed and accuracy, how to efficiently use space in complex layouts, and how to ensure the flexibility and consistency of the placement process. Although the traditional manual placement method is flexible, it is inefficient and has large errors; while the EDA tool placement method is fast and accurate, it still has certain technical difficulties when dealing with complex boundaries and irregular layouts. Summary of the invention

[0016] In view of the above defects or improvement needs of the prior art, the present invention provides a method for placing flip-chip solder pillars of a superconducting quantum chip, which can improve the flexibility of placement and space utilization while ensuring high efficiency and high precision.

[0017] To achieve the above object, according to a first aspect of the present invention, a method for placing flip-chip solder pillars of a superconducting quantum chip is provided, comprising:

[0018] S1, gridding the layout to be processed, and marking the type of each grid according to its location;

[0019] Among them, the types of the grids where the boundaries of the layout to be processed and the grids where the boundaries of the placed module units in the layout to be processed are all boundary grids; the types of the grids where the placed lines in the layout to be processed and the grids in the placed module units are occupied grids; the types of the grids whose distances from the boundary of the layout to be processed are less than the first safety spacing and the types of the grids whose distances from the boundary of the placed module units are not less than the second safety spacing are all grids within the safety spacing; the types of the remaining grids are all free grids;

[0020] S2, with the goal of maximizing the number of flip-chip solder pillars that can be placed, scan each free grid G ​​row by row i , with G i As a reference, align the lower left corner vertex of the flip-chip solder column with G i After the lower left corner vertex of the flip-chip solder column overlaps, it is determined whether the grids occupied by the flip-chip solder column are all free grids. If so, the corresponding horizontal placement can be performed, the placement position coordinates of the flip-chip solder column are recorded, and the grid type of the grid occupied by the flip-chip solder column is updated. If not, the grid type of the grid occupied by the flip-chip solder column is updated with G. i As a reference, align the lower left corner vertex of the flip-chip solder column after tilting with G i After the lower left corner vertex of the grid coincides, determine whether the grids occupied by the tilted flip-chip solder column are all free grids. If so, the corresponding tilted placement can be performed, and the placement position coordinates and tilt angle of the flip-chip solder column are recorded, and the grid type of the grid occupied by the flip-chip solder column is recorded. Otherwise, the grid is skipped until all free grids are scanned to obtain the coordinate set and tilt angle of the flip-chip solder column that can be placed.

[0021] According to a second aspect of the present invention, there is provided an electronic device, comprising: a computer-readable storage medium and a processor;

[0022] The computer-readable storage medium is used to store executable instructions;

[0023] The processor is used to read the executable instructions stored in the computer-readable storage medium and execute the method as described in the first aspect.

[0024] According to a third aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to cause a processor to execute the method as described in the first aspect.

[0025] According to a fourth aspect of the present invention, there is provided a computer program product, comprising a computer program or instructions, wherein when the computer program or instructions are executed by a processor, the method according to the first aspect is implemented.

[0026] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0027] The present invention provides a method for placing flip-chip solder columns for superconducting quantum chips, which performs fine processing on the grids where the layout boundaries, the interior and boundaries of the placed module units, and the placed wires are located, marks special grid types, and adopts a secondary placement strategy, which can improve the flexibility and space utilization of flip-chip solder column placement while ensuring high efficiency and high precision. The method is efficient, accurate and flexible, and can significantly improve the quality and production efficiency of chip design, filling the gap that existing commercial EDA tools do not have a fully automatic layout optimization function for flip-chip columns. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A flow chart of a method for placing flip-chip solder pillars for a superconducting quantum chip provided by an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of a layout space after preprocessing the boundaries of a layout and the boundaries of placed module units provided in an embodiment of the present invention;

[0030] Figure 3 A schematic diagram of a layout space after preprocessing the internal grid of a module unit where components have been placed, provided in an embodiment of the present invention;

[0031] Figure 4 A schematic diagram of the layout space after the inverted columns provided in the embodiment of the present invention are placed;

[0032] Figure 5 A schematic diagram of horizontal placement of an inverted column provided in an embodiment of the present invention;

[0033] Figure 6 A schematic diagram of the inclined placement of an inverted column provided in an embodiment of the present invention;

[0034] Figure 7 A schematic diagram of secondary placement provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0036] The embodiment of the present invention provides a method for placing flip-chip solder pillars of a superconducting quantum chip. The process of placing the flip-chip pillars is as follows: Figure 1 As shown, including:

[0037] S1, gridding the layout to be processed, and marking the type of each grid according to its location;

[0038] Among them, the types of the grids where the boundaries of the layout to be processed and the grids where the boundaries of the placed module units in the layout to be processed are all boundary grids; the types of the grids where the placed lines in the layout to be processed and the grids in the placed module units are occupied grids; the types of the grids whose distances from the boundary of the layout to be processed are less than the first safety spacing and the types of the grids whose distances from the boundary of the placed module units are not less than the second safety spacing are all grids within the safety spacing; the types of the remaining grids are all free grids;

[0039] S2, with the goal of maximizing the number of flip-chip solder pillars that can be placed, scan each free grid G ​​row by row i , with G i As a reference, align the lower left corner vertex of the flip-chip solder column with G i After the lower left corner vertex of the flip-chip solder column overlaps, it is determined whether the grids occupied by the flip-chip solder column are all free grids. If so, the corresponding horizontal placement can be performed, the placement position coordinates of the flip-chip solder column are recorded, and the grid type of the grid occupied by the flip-chip solder column is updated. If not, the grid type of the grid occupied by the flip-chip solder column is updated with G. i As a reference, align the lower left corner vertex of the flip-chip solder column after tilting with G i After the lower left corner vertex of coincides, determine whether the grids occupied by the tilted flip-chip solder column are all free grids. If so, the corresponding tilted placement can be performed, the placement position coordinates and tilt angle of the flip-chip solder column are recorded, and the grid type of the grid occupied by the flip-chip solder column is updated. Otherwise, the grid is skipped until all free grids are scanned to obtain the coordinate set and tilt angle of the flip-chip solder column that can be placed.

[0040] First, the layout to be processed in the plan is divided into a series of grids of equal size. The size of the grid determines the number of grids in the control layout. The type of each grid is marked. For example, a flag can be set for the grid to indicate the type of the corresponding grid. Different flags indicate the type of the current grid, such as an idle grid, an occupied grid, a grid within a safe spacing, an idle grid, etc.

[0041] Specifically, the boundaries of the layout are processed, and the grids where the boundaries are located and the grids within the first safety distance from the boundaries are marked as corresponding types, which are used for boundary judgment in the subsequent placement process; the boundaries of the module units that have been placed in the layout are processed, and the grids where the unit boundaries are located and the grids within the safety distance are marked as corresponding types, which are used for boundary judgment in the subsequent placement process, such as Figure 2 As shown;

[0042] Process the grid inside the placed module unit and mark all the grids inside the unit as the corresponding type for grid type judgment in the subsequent placement process, such as Figure 3 As shown; wherein, preferably, in order to speed up the preprocessing process, a breadth-first traversal is used to process the grid inside the placed module unit.

[0043] Then, the flip-chip solder column is placed in the placeable area in the layout (that is, the area where the free grid is located). Due to the irregular module boundaries in the layout, a single placement method may result in space waste and fail to fully utilize the layout space. Therefore, a secondary placement method is adopted, that is, the placeable area is secondary processed, and the placement is performed in two ways, horizontally and tilted, in order to fully utilize the placement space. Among them, when scanning each row of free grids, it is prioritized to determine whether the flip-chip column can be placed horizontally. Finally, the placement coordinates are output according to the specified requirements. The layout space after the flip-chip column is placed is as follows: Figure 4 shown.

[0044] Among them, by designing visualization tools, the current layout area information can be saved in bmp file format at different stages of the program processing process.

[0045] The method provided by the present invention is further described below by means of mathematical modeling: Abstract modeling is performed on the chip inverted pillar placement problem, and a corresponding basic mathematical model is established.

[0046] 1. Problem Modeling

[0047] 1.1 Input Definition

[0048] · Plane layout, size is W×H;

[0049] ·Inverted column size s×s;

[0050] The set of placed module units E = {e j}, each module unit is an irregular polygon, consisting of a vertex set {(x j1 ,y j1 ),(x j2 ,y j2 ),…,(x jn ,y jn )}The polygonal area formed by connecting the end to the end;

[0051] Network set W = {w k}, each network is a line w connected by multiple points in sequence k ={(x k1 ,y k1 ),(x k2 ,y k2 )…,(x kt ,y kt )}constitute;

[0052] The safety distance d1 between the inverted column and the layout boundary, and the safety distance d2 between the inverted column and the boundary of the placed component module unit;

[0053] · Grid size g×g; in order to maximize the number of inverted columns, the area of ​​the grid is usually set smaller than the area of ​​the inverted column. For example, the side length of the inverted column is generally 20 times the side length of the grid;

[0054] ·The rotation angle θ of the inverted column, (θ∈{0,45}).

[0055] 1.2 Output Definition

[0056] The coordinate set of the inverted column placement S = {(x1,y1),(x2,y2),....(x m ,y m )}

[0057] 1.3 Constraints

[0058] Inverted columns cannot overlap with existing components and networks.

[0059] A safe distance must be maintained between the inverted column and existing components and networks

[0060] The inverted column cannot exceed the boundary of the plane layout

[0061] 1.4 Objective Function

[0062] Maximize the number of inverted columns placed m

[0063] 2. Mathematical Model

[0064] 2.1 Meshing model

[0065] Divide the layout P into grids of equal size, each grid size is g×g, where g is used to control the number and size of grids and can be set according to actual conditions. The smaller the g value, the higher the calculation accuracy, but at the same time, the calculation efficiency must still be taken into account.

[0066] 2.2 Grid Logo

[0067] Each grid G i It has a flag bit b, which is used to indicate the state of the grid. The flag bit uses bit operations to accelerate the judgment. For example:

[0068] b=0: free grid

[0069] b=1:boundary grid

[0070] b=2:grid within safety distance

[0071] b=3: Occupancy grid

[0072] 2.3 Boundary Processing

[0073] The boundaries of the layout are processed, and the grids at the boundaries and the grids within the safety interval are marked as corresponding types b=1 and b=2 respectively.

[0074] 2.4 Component Processing

[0075] For each element e j , mark the grid it occupies and the grid within the safety interval as the corresponding type b j =3 and b j =2.

[0076] 2.5 Placement method

[0077] Two placement methods (tilted or horizontal) are used to place the inverted pillars on the pre-processed layout.

[0078] For each placement method: For each free grid G i (ie b i =0), to determine whether it meets the conditions for placing an inverted column.

[0079] If the conditions are met, the inverted column is placed in the grid and the corresponding flag is updated.

[0080] Among them, when scanning each row of free grids, first determine whether it can be placed horizontally. If so, place it horizontally and update the corresponding flag, record the position coordinates of the inverted column when it is placed horizontally, otherwise determine whether it can be placed obliquely. If so, place it obliquely and update the corresponding flag, record the position coordinates and inclination angle of the inverted column when it is placed obliquely, otherwise skip, until all free grids are scanned to obtain the coordinate set and inclination angle of the inverted column. Accordingly, it can be understood that if a certain inverted column does not have an inclination angle, the placement method of the inverted column is horizontal placement.

[0081] The results of using only the horizontal or inclined placement method and the horizontal and inclined placement methods proposed by the present invention are as follows: Figures 5 to 7 shown.

[0082] The method provided by the present invention can place as many inverted columns as possible by defining a specific placement process through grid division, marking grid type status, and scanning idle grids.

[0083] An embodiment of the present invention provides an electronic device, characterized by comprising: a computer-readable storage medium and a processor;

[0084] The computer-readable storage medium is used to store executable instructions;

[0085] The processor is used to read the executable instructions stored in the computer-readable storage medium and execute the method described in any of the above embodiments.

[0086] An embodiment of the present invention provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to execute the method described in any of the above embodiments.

[0087] An embodiment of the present invention provides a computer program product, including a computer program or instructions, wherein the computer program or instructions implement the method described in any of the above embodiments when executed by a processor.

[0088] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for placing flip-chip solder pillars of a superconducting quantum chip, characterized in that: include: S1, gridding the layout to be processed, and marking the type of each grid according to its location; Among them, the types of the grids where the boundaries of the layout to be processed and the grids where the boundaries of the placed module units in the layout to be processed are all boundary grids; the types of the grids where the placed lines in the layout to be processed and the grids in the placed module units are occupied grids; the types of the grids whose distances from the boundary of the layout to be processed are less than the first safety spacing and the types of the grids whose distances from the boundary of the placed module units are not less than the second safety spacing are all grids within the safety spacing; the types of the remaining grids are all free grids; S2, with the goal of maximizing the number of flip-chip solder pillars that can be placed, scan each free grid G ​​row by row i , with G i As a reference, align the lower left corner vertex of the flip-chip solder column with G i After the lower left corner vertex of the flip-chip solder column overlaps, it is determined whether the grids occupied by the flip-chip solder column are all free grids. If so, the corresponding horizontal placement can be performed, the placement position coordinates of the flip-chip solder column are recorded, and the grid type of the grid occupied by the flip-chip solder column is updated. If not, the grid type of the grid occupied by the flip-chip solder column is updated with G. i As a reference, align the lower left corner vertex of the flip-chip solder column after tilting with G i After the lower left corner vertex of coincides, determine whether the grids occupied by the tilted flip-chip solder column are all free grids. If so, the corresponding tilted placement can be performed, the placement position coordinates and tilt angle of the flip-chip solder column are recorded, and the grid type of the grid occupied by the flip-chip solder column is updated. Otherwise, the grid is skipped until all free grids are scanned to obtain the coordinate set and tilt angle of the flip-chip solder column that can be placed.

2. The method according to claim 1, characterized in that The grids in the placed module units are traversed using a breadth-first traversal method to mark the grid types.

3. The method according to claim 1 or 2, characterized in that In step S2, the angle of the inclined placement is 45 degrees.

4. The method according to claim 1, characterized in that The grid area is smaller than the area of ​​the flip-chip solder pillar.

5. An electronic device, characterized in that: include: A computer readable storage medium and a processor; The computer-readable storage medium is used to store executable instructions; The processor is used to read the executable instructions stored in the computer-readable storage medium and execute the method according to any one of claims 1 to 4.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to execute the method according to any one of claims 1 to 4.

7. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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