A rule-based automatic layout method for PCB functional modules

Abstract

The application discloses a kind of automatic layout methods of rule-based PCB function module, belong to PCB layout design technical field, including steps: reading relevant data and carrying out writing;The type of function module of automatic layout is identified, and according to module type, the multi-terminal network of principle drawing data is split;According to the network after splitting and the layout device definition layout priority of function module type;Construct the surface layer of layout result Liable to be wired quantization index;Establish the mixed variable multi-objective optimization model for the automatic layout of module device, the Pareto optimal solution set of the model is solved using multi-objective optimization algorithm, and according to layout preference, the global layout result of PCB function module is selected;Global layout result is legalized and post-processing.The application uses the above-mentioned automatic layout method, and high-quality module automatic layout result is obtained by automatic optimization of Liable to be wired, to further improve the accuracy and beauty of device layout position.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of PCB layout design, and in particular to a rule-based automatic layout method of a PCB functional module. BACKGROUND

[0002] In the PCB physical design process, PCB layout design is the most important. The PCB layout result will have a significant impact on the downstream processes of physical design such as routing and simulation, and good PCB layout design is the basis for the PCB circuit to be in good working condition.

[0003] Due to the large number of PCB design scenarios, the complex geometry and electrical constraints in different scenarios bring great difficulties to the modeling of automatic layout. In the traditional design process, experienced layout engineers use EDA software to perform manual layout design. The repeated design of modules with the same or similar components in PCB and the repeated iteration of the physical design process consume a lot of manpower and resources. The automatic layout algorithm of the functional module can free the layout engineers from the repetitive labor with low technical content and improve the efficiency of PCB layout and even the entire design process.

[0004] Although large EDA software contains related functions for automatic layout of PCB, these software only place components one by one according to the network connection relationship, or establish a simple optimization layout model for solving according to the netlist data and component specification data. The automatic layout result cannot meet the complex geometric and electrical constraints in the corresponding scene, and the accuracy of the component layout position is poor. At present, the design of the PCB automatic layout algorithm mostly adopts the technical route of VLSI layout planning: using B*-tree or sequence to construct a combinatorial optimization model for automatic layout based on compact layout coding, and then using an efficient intelligent optimization algorithm for solving. However, the performance of the combinatorial optimization model solving algorithm will decrease sharply with the increase of the scale, and the layout based on compact coding is difficult to handle the complex geometric constraints in the layout scene, resulting in that the quality of the automatic layout result is difficult to meet the demand. SUMMARY

[0005] The purpose of the present application is to provide a rule-based automatic layout method of a PCB functional module to solve the problems mentioned in the background.

[0006] To achieve the above purpose, the present application provides a rule-based automatic layout method of a PCB functional module, which is realized by five modules of network splitting module based on schematic diagram, network and component priority definition module, surface layer routability modeling module, mixed decision variable optimization modeling and solving module, and automatic layout DFM rule optimization module.

[0007] The specific steps of the automatic layout method are as follows:

[0008] Step S1: reading the type, size and pin data of the automatic layout component, writing into the "Module_BasicInfo.txt" file; reading the netlist information, writing the network connection relationship and network attribute into the "Net_Info.txt" file; reading the schematic structured data, writing the component and pin data into the "Schematic_Info.txt" file; reading the DFM rule data, storing into the "DFM_Rule.txt" file; the network connection data includes network connection relationship, network attribute and the like;

[0009] Step S2: reading the type data of the component from the "Module_BasicInfo.txt" file, identifying the function module type according to the IC component type; reading the netlist information and schematic data, calling the network splitting module based on the schematic to split the netlist according to the function module type, writing the function module type and the netlist splitting result into the "Net_Info.txt" file;

[0010] Step S3: reading the module and netlist information, calling the network and component priority definition module to define the network and component priority according to the function module type, and writing into the file respectively;

[0011] Step S4: reading the layout component information and netlist information, using the surface layer routability modeling module to construct the surface layer routability quantization index;

[0012] Step S5: reading the network and component priority data, calling the mixed decision variable optimization modeling and solving module to construct the mixed variable multi-objective optimization model and solve to obtain the automatic optimization layout result, and then storing the automatic optimization layout result into the file;

[0013] Step S6: reading the module global layout and DFM rule data, calling the automatic layout DFM rule optimization module to legalize and optimize the layout result, and writing the layout result into the file;

[0014] Step S7: reading the layout result from the file, converting the layout result into the layout file data format used by the user according to the user demand.

[0015] Preferably, step S2 is specifically:

[0016] Step S21: reading the netlist information and schematic structured data from the "Net_BasicInfo.txt" and "Schematic_Info.txt" files respectively, and inputting into the function module type;

[0017] Step S22: parsing the component name and connection point coordinate data from the schematic structured data, and matching the related network from the netlist information;

[0018] Step S23: According to the association relationship between the main IC device and the auxiliary device in the netlist information, the related devices are located from the pins of the main IC device, and the clustering algorithm is used to group the layout auxiliary devices according to the connection point coordinates of the auxiliary devices in the schematic diagram and the pin coordinates of the IC device;

[0019] Step S24: Each pin of the main IC device and the corresponding grouped auxiliary device are traversed, the grouped devices are sorted according to the pin coordinates of the main IC device in the schematic diagram and the connection point coordinates of the auxiliary device in the schematic diagram, and a plurality of two-terminal networks after splitting are obtained according to the sorting result;

[0020] Step S25: The netlist information after splitting is stored in the "Net_Info.txt" file.

[0021] Preferably, step S3 is specifically:

[0022] Step S31: The module and netlist information is read from the "Module_BasicInfo.txt" and "Net_Info.txt" files respectively, and the functional module type is transmitted;

[0023] Step S32: According to the module type and network type, the network connection priority is defined;

[0024] Step S33: According to the device type and the associated network type, the device priority is defined;

[0025] Step S34: According to the module type, network type and device type, the priority of the device placement direction is defined;

[0026] Step S35: The network priority and device priority are written into the "Net_Priority.txt" and "Module_Priority.txt" files respectively.

[0027] Preferably, step S4 is specifically:

[0028] Step S41: The layout device and netlist information are read from the "Module_BasicInfo.txt" and "Net_Info.txt" files respectively, and the functional module type is transmitted;

[0029] Step S42: The netlist information is matched according to the device information, and the network connection between the main chip device and the auxiliary device, and the network connection between the auxiliary devices are identified;

[0030] Step S43: According to the position of IC device pins on the IC device, the IC device pins are fan-out to the device periphery by disorder escape; According to the position of the attached device in the network, the pins connected to the IC device are escaped and fan-out to the side of the IC device by using the ordered escape algorithm;

[0031] Step S44: The fan-out sequence of the IC device is matched with the fan-out sequence position of the attached device, and the quantified index of the surface routability is defined by the matching result;

[0032] Step S45: The quantified index is calculated according to the device placement information and is transmitted to the mixed decision variable optimization modeling and solving module.

[0033] Preferably, step S5 is specifically:

[0034] Step S51: The layout device and netlist information are read from the "Module_BasicInfo.txt" and "Net_Info.txt" files, the network and device priority data are read from the "Net_Priority.txt" and "Module_Priority.txt" files, and the layout preference information is input;

[0035] Step S52: The layout quality quantified index is constructed with the rotation angle vector Θ, the horizontal coordinate vector X and the vertical coordinate vector Y of all modules as independent variables: the surface routability modeling module is called to construct the routability quantified index N(Θ,X,Y); according to the network and device priority data, the line length index L(Θ,X,Y), the layout area index S(Θ,X,Y) and the overlap constraint index O(Θ,X,Y) of automatic layout are constructed;

[0036] Step S53: A mixed variable constraint multi-objective optimization model is established with the device rotation direction and coordinate as the decision variable, the routability, the line length and the layout area as the objective function, and the overlap area as the constraint:

[0037]

[0038] Step S54: An efficient mixed variable multi-objective optimization problem solving optimization model is used to obtain the Pareto optimal solution set NS of the multi-objective optimization model:

[0039] NS={(Θ1,X1,Y1),(Θ2,X2,Y2),…,(Θ n ,X n ,Y n )};

[0040] Step S55: It is judged whether there is a layout preference; if there is a layout preference, go to step S56; if there is no layout preference, go to step S57;

[0041] Step S56: Determine the weight vector K of the optimization target according to the layout preference, construct the metric index for evaluating the non-dominated solution in NS, and get the automatic optimization layout result from the Pareto optimal solution set, go to step S58. Specifically, the metric index for evaluating the non-dominated solution in NS is:

[0042] f(N(Θ,X,Y),L(Θ,X,Y),S(Θ,X,Y),K);

[0043] Step S57: Select the layout scheme corresponding to the Knee point from the Pareto frontier as the automatic optimization layout result, and go to step S58.

[0044] Step S58: Store the automatic optimization layout result in the "Global_Placement.txt" file.

[0045] Preferably, step S6 is specifically:

[0046] Step S61: Read the module layout and DFM rule data from "Global_Placement.txt" and "DFM_Rule.txt" respectively, and pass in the module type information.

[0047] Step S62: Determine the module layout post-processing principle according to the module data, and judge whether it is a heterogeneous layout of the main IC device and the auxiliary device; if it is a heterogeneous layout, go to step S63; if it is not a heterogeneous layout, go to step S64.

[0048] Step S63: Legalize the layout result according to the heterogeneous layout rule and DFM setting data, and go to step S67.

[0049] Step S64: Judge whether it is a single main IC device module layout or a multi-main IC device module layout scenario; if it is a single main IC device module layout, go to step S65; if it is not a single main IC device module layout, go to step S66.

[0050] Step S65: According to the single main IC device functional module layout principle, perform the module layout post-processing centered on the main IC device on the module layout result, and go to step S67.

[0051] Step S66: According to the multi-main IC device functional module layout principle, perform the post-processing process centered on the main IC device and the mutual coordination of each main IC and auxiliary device on the module layout result, and go to step S67.

[0052] Step S67: Write the layout result into the "Placement.txt" file, and convert the layout result into the layout file data format used by the user according to the user's needs.

[0053] Therefore, the application adopts the automatic layout method of the rule-based PCB function module as described above, and has the following beneficial effects:

[0054] (1) The automatic layout result of the function module device is quickly generated based on the existing layout data file, and can be imported into common PCB design EDA software, thereby greatly reducing the workload of engineers in the repeated design of the function module in the PCB layout design, and improving the PCB layout design efficiency;

[0055] (2) The application relates to the modeling, solving and simulation technology of the complex optimization problem of the PCB automatic layout, and specifically relates to an automatic layout method of circuit devices according to designed circuit data, which can be used for the automatic layout of devices in the repeated design of PCB modules with the same or similar functions;

[0056] (3) The application can automatically place the main devices and the auxiliary devices of the composed function module according to the device properties and the netlist data of the module, so as to realize the automatic layout of the function module, greatly improve the repeated design efficiency of the function module in the PCB, and shorten the PCB physical design process;

[0057] (4) The application uses the efficient optimization technology of the complex optimization model, and proposes an automatic layout technology for the repeated design scene of the function module in the PCB, which can realize the automatic layout of the function module according to the network connection data, the module device parameters, the schematic diagram and the design intention of the experienced layout engineer, and greatly improve the design efficiency of the PCB.

[0058] The technical solutions of the application will be further described in detail below with reference to the drawings and embodiments. DESCRIPTION OF DRAWINGS

[0059] Figure 1 It is a module structure block diagram of the embodiment of the application;

[0060] Figure 2 It is a flowchart of an automatic layout method of a rule-based PCB function module of the embodiment of the application;

[0061] Figure 3 It is a flowchart of step S2 of the embodiment of the application;

[0062] Figure 4 It is a flowchart of step S3 of the embodiment of the application;

[0063] Figure 5 It is a flowchart of step S4 of the embodiment of the application;

[0064] Figure 6 It is a flowchart of step S5 of the embodiment of the application;

[0065] Figure 7 Flow chart for step S6 of the embodiment of the present application;

[0066] Reference signs

[0067] 101, automatic layout data preprocessing stage; 102, module automatic optimization layout stage; 103, automatic layout post-processing stage; 104, network splitting module based on schematic diagram; 105, network and device priority definition module; 106, surface layer wireability modeling module; 107, mixed decision variable optimization modeling and solving module; 108, automatic layout DFM rule optimization module. DETAILED DESCRIPTION

[0068] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art without creative work based on the embodiments in the present application belong to the scope of protection of the present application.

[0069] It should be noted that: similar reference signs and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0070] EMBODIMENT

[0071] As shown in the drawings, Figure 1 The present application provides an automatic layout method of a rule-based PCB functional module, which contains three stages: an automatic layout data preprocessing stage 101, a module automatic optimization layout stage 102 and an automatic layout post-processing stage 103. The method is realized through five modules: a network splitting module based on schematic diagram 104, a network and device priority definition module 105, a surface layer wireability modeling module 106, a mixed decision variable optimization modeling and solving module 107 and an automatic layout DFM rule optimization module 108. Among them, the main key technologies of the preprocessing stage of the automatic layout data are realized by the network splitting module based on schematic diagram 104 and the network and device priority definition module 105; the module automatic optimization layout stage 102 is realized by the surface layer wireability modeling module 106 and the mixed decision variable optimization modeling and solving module 107; and the post-processing stage of the automatic layout is realized by the automatic layout DFM rule optimization module 108.

[0072] As Figure 2 shown, the method comprises the following steps:

[0073] Step S1: reading the type, size and pin data of the automatic layout component, and writing them into the "Module_BasicInfo.txt" file; reading the netlist information, and writing the network connection relationship and network attribute into the "Net_Info.txt" file; reading the schematic structural data, and writing the component and pin data into the "Schematic_Info.txt" file; reading the DFM rule data, and storing them into the "DFM_Rule.txt" file.

[0074] Step S2: reading the type data of the component from the "Module_BasicInfo.txt" file, and identifying the function module type according to the IC component type; reading the netlist information and schematic data, and calling the network splitting module 104 based on the schematic to split the netlist according to the function module type, and writing the function module type and the netlist splitting result into the "Net_Info.txt" file.

[0075] Step S3: reading the module and netlist information, and calling the network and component priority definition module 105 to define the network and component priority according to the function module type, and writing them into the file respectively.

[0076] Step S4: reading the layout component information and netlist information, and using the surface layer routability modeling module 106 to construct the surface layer routability quantization index.

[0077] Step S5: reading the network and component priority data, calling the mixed decision variable optimization modeling and solving module 107 to construct the mixed variable multi-objective optimization model and solve it to obtain the automatic optimization layout result, and then storing the automatic optimization layout result into the file.

[0078] Step S6: reading the module global layout and DFM rule data, calling the automatic layout DFM rule optimization module 108 to legalize and optimize the layout result, and writing the layout result into the file.

[0079] Step S7: reading the layout result from the file, and converting the layout result into the layout file data format used by the user for convenience of importing into the PCB design EDA software used by the user.

[0080] In this embodiment, as Figure 3 shown, step S2 specifically comprises:

[0081] Step S21: read the netlist information and schematic structured data from the "Net_BasicInfo.txt" and "Schematic_Info.txt" files respectively, and pass into the functional module type.

[0082] Step S22: parse the device name and connection point coordinate data from the schematic structured data, and match the related network from the netlist information.

[0083] Step S23: start from the pin of the main IC device, locate the related device according to the association relationship between the main IC device and the auxiliary device in the netlist information, and group the layout auxiliary device according to the connection point coordinate of the auxiliary device in the schematic and the pin coordinate of the IC device by using the clustering algorithm.

[0084] Step S24: traverse each pin of the main IC device and the corresponding grouped auxiliary device, sort the grouped device according to the pin coordinate of the main IC device in the schematic and the connection point coordinate of the auxiliary device in the schematic, and obtain the split multiple two-terminal networks according to the sorting result.

[0085] Step S25: store the split netlist information into the "Net_Info.txt" file.

[0086] The multi-terminal network splitting module 104 based on the schematic realizes the multi-terminal network splitting based on the parseable schematic data, reduces the network connection representation and the degree of freedom of the device position by reducing the number of devices / pins in the network, and greatly improves the accuracy of the device position in the automatic layout design.

[0087] In the embodiment, as shown in FIG. 3, step S3 specifically includes: Figure 4

[0088] Step S31: read the module and netlist information from the "Module_BasicInfo.txt" and "Net_Info.txt" files respectively, and pass into the functional module type.

[0089] Step S32: define the network connection priority according to the module type and the network type.

[0090] Step S33: define the device priority according to the device type and the associated network type.

[0091] Step S34: define the priority of the device placement orientation according to the module type, the network type and the device type.

[0092] Step S35: write the network priority and the device priority into the "Net_Priority.txt" and "Module_Priority.txt" files respectively. ​

[0093] The network and device priority defining module 105 defines the priority according to the network connection attribute in the functional module, realizes the optimal placement of the layout device based on the priority, and obtains the automatic layout result conforming to the physical design rule.

[0094] In the embodiment, as shown in Figure 5 , the step S4 is specifically:

[0095] Step S41: read the layout device and netlist information from the "Module_BasicInfo.txt" and "Net_Info.txt" files, respectively, and input the functional module type. The layout device information is the IC device pin information.

[0096] Step S42: match the netlist information according to the device information, identify the network connection of the main chip device and the auxiliary device, and the network connection between the auxiliary devices.

[0097] Step S43: according to the position of the IC device pin on the IC device, perform disordered escape, and fan out the IC device pin to the periphery of the device; according to the placement position of the auxiliary device in the network, group the auxiliary device, and use the ordered escape algorithm to escape and fan out the pin connected with the IC device to one side of the IC device.

[0098] Step S44: group and match the fan-out sequence of the IC device and the fan-out sorting position of the auxiliary device, and define the quantization index of the surface routability through the matching result.

[0099] Step S45: calculate the quantization index according to the device placement information, and pass it to the mixed decision variable optimization modeling and solving module 107.

[0100] For the surface routing demand of the functional module, the surface routability modeling module 106 constructs a low-complexity routability quantitative modeling strategy, and obtains a high-quality automatic layout result of the module through automatic optimization of the routability.

[0101] In the embodiment, as shown in Figure 6 , the step S5 is realized by the mixed decision variable optimization modeling and solving module 107, and specifically:

[0102] Step S51: read the layout device and netlist information from the "Module_BasicInfo.txt" and "Net_Info.txt" files, and read the network and device priority data from the "Net_Priority.txt" and "Module_Priority.txt" files, and input the layout preference information.

[0103] Step S52: Construct layout quality quantitative indicators using the rotation angle vector Θ, the horizontal coordinate vector X, and the vertical coordinate vector Y of all modules as independent variables: call the surface routability modeling module 106 to construct the routability quantitative indicator N(Θ,X,Y); based on the network and device priority data, construct the automatic layout line length indicator L(Θ,X,Y), layout area indicator S(Θ,X,Y), and overlap constraint indicator O(Θ,X,Y).

[0104] Step S53: Establish a mixed variable constraint multi-objective optimization model with the device rotation direction and coordinates as decision variables, routability, line length and layout area as objective functions, and overlap area as a constraint:

[0105]

[0106] Step S54: Utilize the efficient mixed variable multi-objective optimization problem to solve the optimization model and obtain the Pareto optimal solution set NS of the multi-objective optimization model:

[0107] NS={(Θ1,X1,Y1),(Θ2,X2,Y2),…,(Θ n ,X n ,Y n )}.

[0108] Step S55: Determine whether there is a layout preference; if there is a layout preference, go to step S56; if there is no layout preference, go to step S57.

[0109] Step S56: Determine the weight vector K of the optimization target based on the layout preference, and construct a metric to evaluate the non-dominated solutions in NS. Obtain the automatic optimization layout result from the Pareto optimal solution set, and go to step S58. Specifically, the metric for evaluating the non-dominated solutions in NS is:

[0110] f(N(Θ,X,Y),L(Θ,X,Y),S(Θ,X,Y),K).

[0111] Step S57: Select the layout solution corresponding to the Knee point from the Pareto frontier as the automatic optimization layout result, and go to step S58.

[0112] Step S58: Save the automatic optimization layout result into the "Global_Placement.txt" file.

[0113] In this embodiment, if Figure 7 As shown, step S6 is implemented by the automatic layout DFM rule optimization module 108, specifically:

[0114] Step S61: read in module layout and DFM rule data from "Global_Placement.txt" and "DFM_Rule.txt" respectively, and pass in module type information.

[0115] Step S62: determine module layout post-processing principles according to module data, judge whether it is a main IC device and an auxiliary device out-of-plane layout; if it is an out-of-plane layout, go to step S63; if it is not an out-of-plane layout, go to step S64.

[0116] Step S63: according to the out-of-plane layout rule and the DFM setting data, the layout result is legalized, and goes to step S67.

[0117] Step S64: judge whether it is a single main IC device module layout or a multi-main IC device module layout scene; if it is a single main IC device module layout, go to step S65; if it is not a single main IC device module layout, go to step S66.

[0118] Step S65: according to the single main IC device functional module layout principle, the module layout result is processed with the main IC device as the center, and goes to step S67.

[0119] Step S66: according to the multi-main IC device functional module layout principle, the module layout result is processed with the main IC device as the center, and each main IC and auxiliary device is mutually coordinated, and goes to step S67.

[0120] Step S67: write the layout result into the "Placement.txt" file, and convert the layout result into the layout file data format used by the user according to the user's needs.

[0121] The automatic layout DFM rule optimization module 108 adopts a device coordinate continuous movement strategy for complex irregular layout area constraints, and combines the disturbance of the module orientation to further optimize the layout result; for different scenes such as main IC device and auxiliary device out-of-plane layout, single main IC device single surface layout and multi-main IC device module layout, a layout legalization and optimization strategy is designed for the layout module type.

[0122] Therefore, the automatic layout method of the PCB functional module based on the rule is adopted, a mixed decision variable optimization model is established for the layout optimization problem, and an efficient solving algorithm is designed to realize the automatic layout of the module device. The modeling and optimization method can adapt to complex geometric constraints in different layout scenes, and can be customized for different PCB manufacturing processes and technical requirements for automatic layout of functional modules.

[0123] It should be pointed out finally that the above examples are only used to illustrate the technical solutions of the present application but not to limit it, and although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present application can still be modified or replaced equivalently, and these modifications or equivalent replacements should not make the modified technical solutions deviate from the spirit and scope of the technical solutions of the present application.

Claims

1. A method for automatic layout of a rule-based PCB functional module, characterized in that: The automatic layout method is realized through a schematic-based network splitting module, a network and device priority definition module, a surface routability modeling module, a mixed decision variable optimization modeling and solving module and an automatic layout DFM rule optimization module; The automatic layout method comprises the following specific steps: Step S1: reading the type, size and pin data of the automatic layout components and devices, and writing them into a "Module_BasicInfo.txt" file; reading the netlist information, and writing the network connection relationship and network attributes into a "Net_Info.txt" file; reading the schematic structured data, and writing the device and pin data into a "Schematic_Info.txt" file; and reading the DFM rule data, and storing them into a "DFM_Rule.txt" file; Step S2: reading the type data of the components and devices from the "Module_BasicInfo.txt" file, and identifying the function module type according to the IC device type; reading the netlist information and schematic data, and calling the schematic-based network splitting module to split the netlist according to the function module type, and writing the function module type and the netlist splitting result into the "Net_Info.txt" file; Step S3: reading the function module and netlist information, and calling the network and device priority definition module to define the network and device priority according to the function module type, and writing them into the file respectively; Step S4: reading the layout device information and the netlist information, and using the surface routability modeling module to construct the surface routability quantitative index; Step S5: reading the network and device priority data, calling the mixed decision variable optimization modeling and solving module to construct a mixed variable multi-objective optimization model and solve it to obtain the automatic optimization layout result, and then storing the automatic optimization layout result into the file; Step S6: reading the function module global layout and DFM rule data, calling the automatic layout DFM rule optimization module to legalize and optimize the layout result, and writing the layout result into the file; Step S7: reading the layout result from the file, and converting the layout result into the layout file data format used by the user according to the user demand.

2. The method of claim 1, wherein: Step S2 specifically comprises: Step S21: reading the netlist information and schematic structured data from the "Net_BasicInfo.txt" and "Schematic_Info.txt" files respectively, and inputting the function module type; Step S22: parsing the device name and connection point coordinate data from the schematic structured data, and matching the related network from the netlist information; Step S23: starting from the IC device pin, positioning the related devices according to the association relationship between the IC device and the auxiliary device in the netlist information, and using the clustering algorithm to group the layout auxiliary devices according to the auxiliary device connection point coordinates and the IC device pin coordinates in the schematic; Step S24: traversing each IC device pin and corresponding grouped attached device, sorting the grouped device according to IC device pin coordinates in the schematic diagram and attached device connection point coordinates in the schematic diagram, and obtaining the split multiple two-terminal networks according to the sorting result; Step S25: storing the split netlist information in the "Net_Info.txt" file.

3. The method of claim 1, wherein: the rule-based automatic layout of a PCB functional module is based on a set of rules. Step S3 is specifically: Step S31: reading the functional module and netlist information from the "Module_BasicInfo.txt" and "Net_Info.txt" files respectively, and inputting the functional module type; Step S32: defining the network connection priority according to the functional module type and network type; Step S33: defining the device priority according to the device type and associated network type; Step S34: defining the priority of the device placement orientation according to the functional module type, network type and device type; Step S35: writing the network priority and device priority into the "Net_Priority.txt" and "Module_Priority.txt" files respectively.

4. The method of claim 1, wherein: Step S4 is specifically: Step S41: reading the layout device information and netlist information from the "Module_BasicInfo.txt" and "Net_Info.txt" files respectively, and inputting the functional module type; Step S42: matching the netlist information according to the layout device information, identifying the network connection between the IC device and the attached device, and the network connection between the attached devices; Step S43: performing disordered escape according to the position of the IC device pin on the IC device, and fanning out the IC device pin to the device around; grouping the attached devices according to the placement position of the attached devices in the network, and using the escape algorithm to perform ordered escape and fan out the pin connected with the IC device to the side of the IC device; Step S44: grouping and matching the fan-out sequence of the IC device and the fan-out sorting position of the attached device, and defining the quantification index of the surface routability through the matching result; Step S45: calculating the quantification index according to the device placement information, and passing it to the mixed decision variable optimization modeling and solving module.

5. The method of claim 1, wherein: the rule-based automatic layout of a PCB functional module is based on a set of rules. Step S5 is specifically: Step S51: reading the layout device and netlist information from the "Module_BasicInfo.txt" and "Net_Info.txt" files, and reading the network and device priority data from the "Net_Priority.txt" and "Module_Priority.txt" files, and inputting the layout preference information; Step S52: construct layout quality quantization index with rotation angle vector of all modules as independent variable , horizontal coordinate vector , and vertical coordinate vector ; call surface routability modeling module to construct routability quantization index ; construct line length index, layout area index, and overlap constraint index of automatic layout according to network and device priority data , , and ;​​ Step S53: establishing a mixed variable constraint multi-objective optimization model with device rotation direction and coordinates as decision variables, routability, line length and layout area as objective functions, and overlapping area as constraints: ； Step S54: using the efficient mixed variable multi-objective optimization problem solving optimization model, obtaining the Pareto optimal solution set of the multi-objective optimization model NS : ； wherein Pareto optimal solution set of a multi-objective optimization model NS in group solution; Step S55: determining whether there is a layout preference; If there is a layout preference, go to step S56; If there is no layout preference, go to step S57; Step S56: Determine the weight vector of the optimization target according to the layout preference , construct a metric index for evaluating the non-dominated solution in NS The metric index for evaluating the non-dominated solution in NS is: ； Step S57: Select the layout solution corresponding to the knee point from the Pareto frontier as the automatic optimization layout result, and go to step S58; Step S58: Save the automatic optimization layout result into the "Global_Placement.txt" file.

6. The method of claim 1, wherein: Step S6 is specifically as follows: Step S61: Read module layout and DFM rule data from "Global_Placement.txt" and "DFM_Rule.txt" respectively, and pass in module type information; Step S62: Determine the module layout post-processing principle based on the module data to determine whether the IC device and the auxiliary device are arranged on different planes; if so, go to step S63; if not, go to step S64; Step S63: Legalize the layout result according to the different-plane layout rules and DFM setting data, and go to step S67; Step S64: Determine whether it is a single IC device module layout or a multi-IC device module layout scenario; if it is a single IC device module layout, go to step S65; if it is not a single IC device module layout, go to step S66; Step S65: According to the principle of single IC device functional module layout, perform module layout post-processing centered on the IC device on the module layout result, and then go to step S67; Step S66: Based on the principle of multi-IC device functional module layout, the module layout result is subjected to a post-processing process with the IC device as the center and the various IC devices and auxiliary devices cooperating with each other, and then the process goes to step S67; Step S67: Write the layout result into the "Placement.txt" file, and convert the layout result into the layout file data format used by the user according to the user's needs.

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