Static hiding method and electronic device for Latch PUF unit circuit in chip

Abstract

The present invention discloses a static concealment method and electronic device for a Latch PUF unit circuit in a chip. The method comprises: using the Verilog language to instantiate standard cells corresponding to an inverter, a buffer, a first multiplexer, a second multiplexer, a first NAND gate, and a second NAND gate; generating a circuit netlist for the Latch PUF unit circuit based on the standard cells; placing each standard cell based on the circuit netlist, interconnecting and routing each standard cell, and performing instruction adjustment after the interconnection routing to obtain a Latch PUF unit circuit; and randomly placing multiple Latch PUF unit circuits in a chip layout according to random coordinates. The method of the present invention can effectively eliminate the circuit characteristics and image characteristics of the Latch PUF, thereby reducing the possibility of being identified or located by an attacker and improving the security of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a static hiding method for a Latch PUF (Physical Unclonable Functions) unit circuit in a chip, a computer-readable storage medium, and an electronic device. Background Art

[0002] A physically unclonable function (PUF) generates keys by exploiting the inherent random process variations that occur during the integrated circuit manufacturing process. This uncontrollable variation gives PUF security properties such as unpredictability and unclonability, making it a promising hardware-based solution for chip-level secure key generation.

[0003] In related technologies, current PUF circuit designs require highly symmetrical placement and wiring to achieve good bias characteristics, resulting in significant layout and image features in chip images. These significant layout and image features make the chip's PUF circuit vulnerable to attackers, posing a significant security risk. Specifically, after obtaining the chip, attackers can use reverse engineering techniques such as chip delamination and circuit extraction to obtain the chip's complete layout and circuits, making it easy to locate the PUF circuit. Subsequently, semi-invasive techniques such as focused ion beam or fault injection can be used to obtain the PUF key, resulting in poor chip security. Summary of the Invention

[0004] The present invention aims to solve, at least to some extent, one of the technical problems in the related art. To this end, the first object of the present invention is to propose a static hiding method for the Latch PUF unit circuit in a chip. By randomizing the position of the featureless Latch PUF unit circuit, multiple Latch PUF unit circuits are randomly distributed among a large number of standard digital cells, effectively eliminating the circuit characteristics and image characteristics of the Latch PUF. This makes it difficult for attackers to locate the Latch PUF unit circuit through image characteristics, reducing the possibility of being identified or located by attackers and improving the security of the chip.

[0005] A second object of the present invention is to provide a computer-readable storage medium.

[0006] A third object of the present invention is to provide an electronic device.

[0007] To achieve the above-mentioned purpose, an embodiment of the first aspect of the present invention proposes a static hiding method for a Latch PUF unit circuit in a chip, wherein the chip includes a plurality of the Latch PUF unit circuits, and the Latch PUF unit circuit includes an inverter, a buffer, a first multiplexer, a second multiplexer, a first NAND gate, and a second NAND gate, wherein the transmission path from the buffer to the first multiplexer is a first path, the transmission path from the buffer to the second multiplexer is a second path, the transmission path from the first multiplexer to the first NAND gate is a third path, the transmission path from the second multiplexer to the second NAND gate is a fourth path, the transmission path from the output end of the second NAND gate to the input end of the first NAND gate is a fifth path, and the transmission path from the output end of the first NAND gate to the input end of the second NAND gate is a sixth path; the method includes: using Verilog language to respectively instantiate the standard cells corresponding to the inverter, the buffer, the first multiplexer, the second multiplexer, the first NAND gate, and the second NAND gate; generating the Latch according to each of the standard cells. A circuit netlist of a PUF unit circuit; placing each of the standard cells based on the circuit netlist, interconnecting and routing the standard cells, and adjusting instructions after the interconnection and routing to obtain the Latch PUF unit circuit, wherein the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path; and randomly placing multiple Latch PUF unit circuits on a chip layout according to random coordinates.

[0008] According to the static hiding method of the Latch PUF unit circuit in a chip according to an embodiment of the present invention, first, the standard cells corresponding to the inverter, the buffer, the first multiplexer, the second multiplexer, the first NAND gate, and the second NAND gate are respectively instantiated using the Verilog language; then, a circuit netlist of the Latch PUF unit circuit is generated based on the standard cells, and based on the circuit netlist, each standard cell is placed, and interconnections are performed between the standard cells. After the interconnections are performed, instructions are adjusted to obtain the Latch PUF unit circuit, so that the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path; finally, multiple Latch PUF unit circuits are randomly placed in the chip layout according to random coordinates. Therefore, this method randomizes the position of featureless Latch PUF unit circuits, and randomly distributes multiple Latch PUF unit circuits in a large number of standard digital units, effectively eliminating the circuit characteristics and image characteristics of Latch PUF. This makes it difficult for attackers to locate the Latch PUF unit circuit through image characteristics, reduces the possibility of being identified or located by attackers, and improves the security of the chip.

[0009] In addition, the static concealment method of the Latch PUF unit circuit in the chip according to the above embodiment of the present invention may also have the following additional technical features:

[0010] According to an embodiment of the present invention, placing the standard cells includes: placing the standard cells symmetrically.

[0011] According to one embodiment of the present invention, the standard cells are symmetrically placed, including: placing the standard cell of the first NAND gate and the standard cell of the second NAND gate in a mirror-symmetrical manner, and determining an axis of symmetry; placing the standard cell of the first multiplexer below the standard cell of the first NAND gate along the axis of symmetry, and mirror-placing the standard cell of the second multiplexer below the standard cell of the second NAND gate along the axis of symmetry, with the standard cell of the first multiplexer and the standard cell of the second multiplexer being mirror-symmetrical; and placing the standard cell of the buffer below the standard cell of the second multiplexer along the axis of symmetry.

[0012] According to one embodiment of the present invention, interconnection routing is performed between each of the standard cells and instruction adjustment is performed after the interconnection routing, including: automatic layout and routing between each of the standard cells; and instruction adjustment of each path based on the length of each path after automatic layout and routing, so that the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path.

[0013] According to one embodiment of the present invention, a plurality of LatchPUF unit circuits are randomly placed in a chip layout according to random coordinates, including: obtaining a unit height, an area of ​​a NAND gate, an area of ​​a multiplexer, and an area of ​​a buffer of a standard unit in a process library file; determining a width of the NAND gate according to the area of ​​the NAND gate and the unit height; determining a width of the multiplexer according to the area of ​​the multiplexer and the unit height; determining a width of the buffer according to the area of ​​the buffer and the unit height; obtaining a placement spacing, a width, and boundary coordinates of WellTap units in a chip; inputting the unit height, the width of the NAND gate, the width of the multiplexer, the width of the buffer, the placement spacing, the width, and the boundary coordinates of the WellTap units into a preset algorithm to randomly generate a plurality of random coordinates; and placing a plurality of Latch PUF unit circuits in a chip layout according to the plurality of random coordinates.

[0014] According to one embodiment of the present invention, the width of the NAND gate is determined by the following formula:

[0015]

[0016] Among them, W ND is the width of the NAND gate, A ND is the area of ​​the NAND gate, H cell is the unit height.

[0017] According to one embodiment of the present invention, the width of the multiplexer is determined by the following formula:

[0018]

[0019] Among them, W MUX is the width of the multiplexer, A MUX is the area of ​​the multiplexer, H cell is the unit height.

[0020] According to one embodiment of the present invention, the width of the buffer is determined by the following formula:

[0021]

[0022] Among them, W BUF is the width of the buffer, A BUF is the area of ​​the buffer, H cell is the unit height.

[0023] To achieve the above objectives, a second embodiment of the present invention provides a computer-readable storage medium storing a static hiding program for a latch PUF unit circuit in a chip. When the static hiding program for the latch PUF unit circuit in the chip is executed by a processor, the above-mentioned static hiding method for the latch PUF unit circuit in the chip is implemented.

[0024] According to the computer-readable storage medium of an embodiment of the present invention, the static concealment method of the Latch PUF unit circuit in the chip can effectively eliminate the circuit characteristics and image characteristics of the Latch PUF, making it difficult for attackers to locate the Latch PUF unit circuit through image characteristics, thereby reducing the possibility of being identified or located by attackers and improving the security of the chip.

[0025] To achieve the above objectives, the third aspect of the present invention proposes an electronic device, comprising: a memory and a processor, wherein the memory stores a program that can be run on the processor, and when the processor executes the program, it implements the static hiding method of the Latch PUF unit circuit in the above-mentioned chip.

[0026] In electronic devices according to embodiments of the present invention, the aforementioned static concealment method for the Latch PUF unit circuit in the chip can effectively eliminate the circuit and image features of the Latch PUF, making it difficult for attackers to locate the Latch PUF unit circuit through image features. This reduces the possibility of being identified or located by attackers and improves chip security.

[0027] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Flowchart of a static concealment method of a Latch PUF unit circuit in a chip according to an embodiment of the present invention;

[0029] Figure 2 A Latch PUF unit circuit according to an embodiment of the present invention and its equivalent circuits in different modes;

[0030] Figure 3 Schematic diagram of a transmission path of a Latch PUF unit circuit according to one embodiment of the present invention;

[0031] Figure 4 Schematic diagram of the placement of a Latch PUF unit circuit according to one embodiment of the present invention;

[0032] Figure 5 Schematic diagram of a Latch PUF unit circuit after automatic wiring according to one embodiment of the present invention;

[0033] Figure 6 A schematic diagram of a Latch PUF unit circuit after optimized wiring according to one embodiment of the present invention;

[0034] Figure 7 is a schematic diagram of a WellTap unit in a chip according to one embodiment of the present invention;

[0035] Figure 8 The effective placement area of ​​the Latch PUF unit circuit according to one embodiment of the present invention is

[0036] Figure 9 Schematic diagram of the overall layout of a chip after random placement of Latch PUF unit circuits according to one embodiment of the present invention;

[0037] Figure 10 FIG. 4 is a block diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0039] The following describes a static hiding method for a Latch PUF unit circuit in a chip, a computer-readable storage medium, and an electronic device proposed in embodiments of the present invention with reference to the accompanying drawings.

[0040] Physically unclonable functions (PUFs) exploit the inherent random process variations that occur during integrated circuit manufacturing to generate secret keys. This uncontrollable variation gives PUFs security properties such as unpredictability and unclonability, making them a promising hardware-based solution for secure, chip-level key generation. Current PUF circuit designs require highly symmetrical placement and routing to achieve good biasing characteristics, resulting in significant layout and image features in chip images. These distinct layout and image features make the chip's PUF circuitry vulnerable to attack, posing a significant security risk. Specifically, after obtaining a chip, an attacker can use reverse engineering techniques such as chip stripping and circuit extraction to obtain the complete chip layout and circuitry, making it easy to locate the PUF circuitry. Subsequently, semi-invasive techniques such as focused ion beams or fault injection can be used to obtain the PUF secret key. Therefore, achieving complete PUF anonymity requires not only obfuscating the use of the PUF secret key but also concealing the PUF circuitry.

[0041] After obtaining a chip, an attacker can use reverse engineering techniques such as chip stripping and circuit extraction to obtain the chip's complete layout and circuitry, making it easy to locate the PUF circuit. Subsequently, semi-invasive techniques such as focused ion beam or fault injection can be used to obtain the PUF key. To mitigate these vulnerabilities, various protection strategies have been proposed. For example, a collaborative fuzzification scheme is adopted, which uses virtual hole technology to implement fuzzy logic gates for logical fuzzification. However, this scheme still distributes channel-based PUFs in an orderly manner on the chip. Compared with standard logic gates, virtual holes have a larger area, allowing attackers to locate them through computer vision technology; another example is an obfuscation cell (OC) composed of inverters and multiplexers. The chip-dependent license is generated by the PUF response based on the OC configuration to prevent image processing-based reverse engineering and protect third-party IP cores. However, this scheme only performs multi-layer obfuscation on the PUF key without hiding the PUF circuit. Therefore, the PUF circuit still has unique characteristics, allowing attackers to easily locate them, thereby obtaining the PUF key and then tracing it to the license; another example is the use of combining the PUF response with a finite state machine (finite state machine). This method integrates the inherent PUF response into the FSM, restricting the execution of the hardware IP to specific FPGAs and enforcing paid device licenses, thereby protecting the IP core. However, attackers can still locate the PUF based on its unique characteristics, obtain the key through physical attacks, and use the obtained PUF key to enable the FSM to function properly, thereby cracking the entire security chip. Therefore, to fully conceal the PUF, the key is not only to obfuscate the use of the PUF key, but also to hide the PUF circuit.

[0042] To achieve stealth, PUF circuits must be implemented using standard cells, which should be randomly distributed on the chip, hiding the PUF cells within a large number of standard cells and obscuring their signature. However, some existing PUFs, such as arbiter PUFs, RO PUFs, and SRAM PUFs, cannot eliminate their signature even when implemented using standard cells. Arbiter PUFs require a large number of multiplexers for path switching and D-type flip-flops at the end of the circuit for arbitration, creating a distinct signature on the chip and making them easily identifiable by attackers. Similarly, the ring oscillator in the RO PUF consists of neatly arranged inverters, making it equally distinctive. While SRAM PUFs can be reused with SRAM, the unique characteristics of SRAM and its bus structure make it easy for attackers to locate them. Once an attacker successfully locates the PUF circuit, they can extract the key at a low cost through invasive attacks. Therefore, the fundamental reason why these standard cell-based PUFs cannot be concealed is that they cluster many identical standard cells together. Therefore, in order to achieve the concealment of PUF circuits, PUF units must be composed of a small number of standard units, and their aggregation should be avoided.

[0043] To address this issue, this paper proposes a static anonymity method based on Latch PUF. First, the featureless Latch PUF unit circuit consists of only six standard cells to eliminate the circuit characteristics of the PUF. Second, the featureless Latch PUF units are randomly distributed throughout the digital chip layout, rather than clustered together, to eliminate the PUF's image characteristics.

[0044] Figure 1 4 is a flow chart of a static concealment method of a Latch PUF unit circuit in a chip according to an embodiment of the present invention.

[0045] like Figure 2As shown in FIG. , in one embodiment of the present invention, a chip includes multiple Latch PUF unit circuits, each comprising an inverter, a buffer BUFFER, a first multiplexer MUX1, a second multiplexer MUX2, a first NAND gate NAND1, and a second NAND gate NAND2. Both the first multiplexer MUX1 and the second multiplexer MUX2 are controlled by a mode control signal MODE, which switches the Latch PUF unit circuit between two operating modes: a latch unit and a latch PUF. When MODE is "1," OUT equals the input signal IN. Subsequently, when MODE is "0" and PUF_EN is "1," the featureless Latch PUF functions as a latch unit, storing the previous input signal IN. When MODE is "0" and PUF_EN is "0," OUT outputs data that is no longer latched and remains constant at "1," preparing for key generation within the Latch PUF. Subsequently, when MODE is "0" and PUF_EN is "1," the circuit operates as a latch PUF, and OUT is determined by the drive capabilities of the first and second NAND gates, NAND1 and NAND2. If NAND1 has a stronger drive capability, OUT is "1"; otherwise, OUT outputs "0."

[0046] Among them, such as Figure 3 As shown, the transmission path from the buffer BUFFER to the first multiplexer MUX1 is the first path Path1, the transmission path from the buffer BUFFER to the second multiplexer MUX2 is the second path Path2, the transmission path from the first multiplexer MUX1 to the first NAND gate NAND1 is the third path Path3, the transmission path from the second multiplexer MUX2 to the second NAND gate NAND2 is the fourth path Path4, the transmission path from the output end of the second NAND gate NAND2 to the input end of the first NAND gate NAND1 is the fifth path Path5, and the transmission path from the output end of the first NAND gate NAND1 to the input end of the second NAND gate NAND2 is the sixth path Path6.

[0047] like Figure 1 As shown, the static concealment method of the Latch PUF unit circuit in the chip of the embodiment of the present invention may include the following steps:

[0048] S1, using Verilog language to respectively instantiate standard cells corresponding to the inverter, the buffer, the first multiplexer, the second multiplexer, the first NAND gate, and the second NAND gate.

[0049] S2, generating a circuit netlist of the Latch PUF unit circuit based on each standard unit.

[0050] S3, based on the circuit netlist, placing each standard cell, interconnecting and routing each standard cell, and adjusting instructions after the interconnection and routing to obtain a Latch PUF unit circuit, wherein the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path.

[0051] S4 randomly places multiple Latch PUF unit circuits on the chip layout according to random coordinates.

[0052] Specifically, to accurately place the digital circuit of the featureless latch PUF unit, the inverter, buffer (BUFFER), multiplexer (MUX), and NAND gate standard cells in the HJ 180nm standard cell library are first instantiated using the Verilog hardware description language. The register transfer level (RTL) code is then synthesized through Design Compile to generate a circuit netlist. Finally, based on the resulting circuit netlist, the various standard cells are placed in Innovus, and interconnections are routed between the standard cells. After the interconnection routing, the lengths of the paths are adjusted based on the interconnection routing results, that is, the lengths of the various paths. This ensures that the length of the first path Path1 is equal to the length of the second path Path2, the length of the third path Path3 is equal to the length of the fourth path Path4, and the length of the fifth path Path5 is equal to the length of the sixth path Path6, thereby obtaining the latch PUF unit circuit. This alignment helps prevent additional, predictable differences caused by mismatched interconnection lengths within the featureless latch PUF unit circuit, thereby achieving the placement and routing of the featureless latch PUF circuit. In the same way, multiple LatchPUF unit circuits are obtained, and then the multiple LatchPUF unit circuits are randomly placed in the chip layout according to the random coordinates in the chip.

[0053] Therefore, the static hiding method of the Latch PUF unit circuit in the embodiment of the present invention randomizes the position of the featureless Latch PUF unit circuit, and randomly distributes multiple Latch PUF unit circuits in a large number of standard digital units, effectively eliminating the circuit characteristics and image characteristics of the Latch PUF. This makes it difficult for attackers to locate the Latch PUF unit circuit through image characteristics, reduces the possibility of being identified or located by attackers, and improves the security of the chip.

[0054] According to an embodiment of the present invention, placing each standard cell includes: placing each standard cell symmetrically.

[0055] Furthermore, according to one embodiment of the present invention, the standard cells are symmetrically placed, including: placing the standard cell of the first NAND gate and the standard cell of the second NAND gate in a mirror-symmetrical manner, and determining the axis of symmetry; placing the standard cell of the first multiplexer below the standard cell of the first NAND gate along the axis of symmetry, and mirror-placing the standard cell of the second multiplexer below the standard cell of the second NAND gate along the axis of symmetry, and the standard cell of the first multiplexer and the standard cell of the second multiplexer are mirror-symmetrical; and placing the standard cell of the buffer below the standard cell of the second multiplexer along the axis of symmetry.

[0056] Specifically, if Figure 3 As shown in the figure, when the featureless Latch PUF unit circuit is used as a Latch PUF, it is necessary to ensure that the length of the first path Path1 is equal to the length of the second path Path2, the length of the third path Path3 is equal to the length of the fourth path Path4, and the length of the fifth path Path5 is equal to the length of the sixth path Path6. This alignment helps prevent additional, predictable differences due to the mismatch of the interconnection trace lengths within the featureless Latch PUF unit. To achieve this, the standard cells in the Latch PUF unit circuit should be placed symmetrically. Figure 4 As shown, the standard cells of the first NAND gate NAND1 and the second NAND gate NAND2 are placed in mirror symmetry. Similarly, the standard cells of the first multiplexer MUX1 are placed below the standard cells of the first NAND gate NAND1 along the symmetry axis, and the standard cells of the second multiplexer MUX2 are mirrored and placed below the standard cells of the second NAND gate NAND2 along the symmetry axis. The standard cells of the first multiplexer MUX1 and the standard cells of the second multiplexer MUX2 are mirrored. Due to the limitations of the placement grid, the buffer BUFFER cannot be placed symmetrically below along the same symmetry axis. Therefore, the buffer BUFFER is placed below MUX2, close to the right side of the symmetry axis. Figure 4 The placement shown ensures that the interconnect trace lengths between standard cells are as consistent as possible, minimizing the impact of path variations on the key.

[0057] According to one embodiment of the present invention, interconnection routing is performed between various standard cells and instruction adjustment is performed after the interconnection routing, including: automatic layout and routing between various standard cells; and instruction adjustment of each path based on the length of each path after the automatic layout and routing, so that the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path.

[0058] For example, after the standard cells in the featureless Latch PUF unit circuit are placed, automatic layout and routing will be performed between the standard cells. Figure 5 As shown in the figure, only the path lengths of the third path Path3 and the fourth path Path4 are equal, while the path lengths of the first path Path1 and the second path Path2, as well as the fifth path Path5 and the sixth path Path6, are inconsistent. To resolve the path length difference between the first path Path1 and the second path Path2, first use the deleteNet command to delete the second path Path2 routing between the buffer BUFFER and the second multiplexer MUX2. Then, use the editSelectVia command to select the via Via in the second multiplexer MUX2, and then use the editMove command to move the via Via upward to compensate for the path length difference between the first path Path1 and the second path Path2. Finally, use the editAddRoute command to reroute the second path Path2, changing the path lengths of the first path Path1 and the second path Path2 from 5.78μm and 5.16μm to a uniform 5.78μm, making their lengths equal. To resolve the path length difference between the fifth path Path5 and the sixth path Path6, the deleteNet command is initially used to delete the existing routing of the fifth path Path5; then the editAddRoute command is used to mirror the path direction of the sixth path Path6 to reroute the fifth path Path5. As a result, the path lengths of the fifth path Path5 and the sixth path Path6 are modified from 3.04μm and 5.28μm respectively to the same 5.28μm, thus achieving equal path lengths. The optimized routing results are shown in the figure below. Figure 6 The same steps are applied to other featureless Latch PUF units to ensure that the length of the first path Path1 of all units is equal to the length of the second path Path2, the length of the third path Path3 is equal to the length of the fourth path Path4, and the length of the fifth path Path5 is equal to the length of the sixth path Path6.

[0059] It should be understood that there may be certain differences in the interconnection routing between the various standard cells of different Latch PUF units. After automatic layout and routing between the various standard cells, the instructions for each path are adjusted according to the length of each path after automatic layout and routing, so that the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path.

[0060] According to one embodiment of the present invention, multiple Latch PUF unit circuits are randomly placed in a chip layout according to random coordinates, including: obtaining the unit height, area of ​​a NAND gate, area of ​​a multiplexer, and area of ​​a buffer of a standard cell in a process library file; determining the width of the NAND gate according to the area and unit height of the NAND gate; determining the width of the multiplexer according to the area and unit height of the multiplexer; determining the width of the buffer according to the area and unit height of the buffer; obtaining the placement spacing and width of WellTap units in the chip, and the boundary coordinates of the WellTap units; inputting the unit height, width of the NAND gate, width of the multiplexer, width of the buffer, placement spacing and width of the WellTap units, and boundary coordinates of the WellTap units into a preset algorithm to randomly generate multiple random coordinates; and placing multiple Latch PUF unit circuits in the chip layout according to the multiple random coordinates.

[0061] According to one embodiment of the present invention, the width of the NAND gate is determined by the following formula:

[0062]

[0063] Among them, W ND is the width of the NAND gate, A ND is the area of ​​the NAND gate, H cell is the unit height.

[0064] According to one embodiment of the present invention, the width of the multiplexer is determined by the following formula:

[0065]

[0066] Among them, W MUX is the width of the multiplexer, A MUX is the area of ​​the multiplexer, H cell is the unit height.

[0067] According to one embodiment of the present invention, the width of the buffer is determined by the following formula:

[0068]

[0069] Among them, W BUF is the width of the buffer, A BUF is the area of ​​the buffer, H cell is the unit height.

[0070] Specifically, during chip planning, WellTap cells are first placed at fixed intervals to prevent latching. Therefore, when randomly placing featureless Latch PUF cells, they should be avoided in areas where WellTap cells are already present. To this end, the PUF cell placement problem is transformed into a mathematical problem of finding the coordinates of the largest reachable area under given boundary constraints.

[0071] Specifically, based on the process library file, the unit height H of the standard unit can be obtained cell , and the area sizes of NAND gate, multiplexer MUX and buffer BUFFER are A ND 、A MUX and A BUF , from which we can deduce the width W of the NAND gate ND , the width W of the multiplexer MUX MUX and the width W of BUFFER BUF .

[0072] Further, if Figure 7 As shown, the WellTap units are staggered in the chip layout, with a spacing of S WT , width W WT To facilitate layout, the featureless Latch PUF unit circuit is randomly placed in the space between any two WellTap units, such as Figure 8 As shown. Set the unit height H cell , the width of the NAND gate W ND , the width of the multiplexer W MUX , buffer width W BUF 、WellTap unit placement spacing S WT , width W WT The boundary coordinates of the WellTap unit are input into the preset algorithm to randomly generate multiple random coordinates, wherein the boundary coordinates of the WellTap unit can be the coordinates (X1, Y1) of the lower left WellTap unit and the coordinates (X2, Y2) of the upper right WellTap unit; the coordinates (X1, Y1) of the first NAND gate NAND1 can be obtained by performing calculations using the preset algorithm. ND1 , Y ND1 ), the coordinate of the second NAND gate NAND2 (X ND2 , Y ND2 ), the coordinates of the first multiplexer MUX1 (X MUX1 , Y MUX1 ), the coordinates of the second multiplexer MUX2 (X MUX2 , Y MUX2 ), the coordinates of the buffer BUFFER (X BUF， YBUF ).

[0073] For example, the codes of the preset algorithm are specifically shown in Table 1.

[0074] Table 1

[0075]

[0076]

[0077] The following is a text description of the code:

[0078] For loop i = 0, ..., N means looping the following content N times to generate N coordinates that meet the standards;

[0079] First, for i=1; for the coordinates (X ND1 , Y ND1 ), (X ND2 , Y ND2 ), (X MUX1 , Y MUX1 ), (X MUX2 , Y MUX2 ), (X BUF， Y BUF ) is initialized to 0, 0;

[0080] Then make a while judgment, (X ND1 , X ND2 , X MUX1 , X MUX2 , X BUF <X1 or> X2)or(Y ND1 , Y ND2 , Y MUX1 , Y MUX2 , Y BUF <Y1 or> Y2) Only when the X coordinates of these coordinates are less than X1 or greater than X2, or the Y coordinates are less than Y1 or greater than Y2, perform the following operations, and then divide them into three cases to judge W ND , W MUX , W MUX Which one is the largest? In different situations, different formulas can be used to generate coordinates. The largest one is W. ND For example, use the int(rand(a, b)) function to generate random integers in the range (a, b) to generate the required N, A; then according to rand(X1+N*W WT +(N-1)*S WT , X1+N*W WT +N*S WT -2*W ND) Generate the X coordinate of MUX1;

[0081] Then, the corresponding coordinates of NAND1, NAND2, MUX1, MUX2, and BUFFER are generated according to the following formulas. ND1 , Y ND1 ), (X ND2 , Y ND2 ), (X MUX1 , Y MUX1 ), (X MUX2 , Y MUX2 ), (X BUF， Y BUF ) are all within the range of (X1, X2) and the Y coordinates are all within the range of (Y1, Y2), the coordinates X that meet the requirements will be obtained. ND1 , Y ND1 ), (X ND2 , Y ND2 ), (X MUX1 , Y MUX1 ), (X MUX2 , Y MUX2 ), (X BUF， Y BUF ), and then enter the next cycle i=i+1; when i=N cycles are completed, N groups of coordinates that meet the requirements can be obtained.

[0082] Use this algorithm to randomly generate N sets of coordinates for N featureless Latch PUF cell circuits. Then, use the placeInstance command to place the cells accordingly, and use the set_dont_touch command to ensure that these cells remain unchanged during the placement and routing optimization process.

[0083] Figure 9 The overall layout after all digital cells are placed is shown, where the featureless Latch PUF cell circuit is highlighted in red. It can be observed that the placement of standard cells in each featureless Latch PUF cell circuit is the same as Figure 4 By randomizing the locations of the featureless Latch PUF cells, they are distributed among a large number of standard digital cells, effectively eliminating their layout characteristics and reducing the possibility of being identified or located by an attacker.

[0084] By adopting a symmetrical placement strategy for standard cells within the featureless Latch PUF unit circuit, optimizing the routing between standard cells, and randomly placing the featureless Latch PUF unit circuit, the Latch PUF can be hidden in a large number of digital standard cells, eliminating the circuit and image features of the Latch PUF.

[0085] The embodiment of the present invention integrates the proposed featureless Latch PUF and implements chip tape-out and testing using the HJ standard 0.18μm CMOS process. Each chip contains 32 featureless Latch PUF units. It can be found that the image features of the Latch PUF are successfully eliminated, making it difficult for attackers to locate the Latch PUF units through image features.

[0086] In summary, according to the static hiding method of the Latch PUF unit circuit in the chip of the embodiment of the present invention, the standard cells corresponding to the inverter, the buffer, the first multiplexer, the second multiplexer, the first NAND gate, and the second NAND gate are first instantiated using the Verilog language; then, a circuit netlist of the Latch PUF unit circuit is generated according to the standard cells, and based on the circuit netlist, each standard cell is placed, and interconnection routing is performed between each standard cell, and instruction adjustment is performed after the interconnection routing to obtain the Latch PUF unit circuit, so that the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path; finally, multiple Latch PUF unit circuits are randomly placed in the chip layout according to random coordinates. Therefore, this method randomizes the position of featureless Latch PUF unit circuits, and randomly distributes multiple Latch PUF unit circuits in a large number of standard digital units, effectively eliminating the circuit characteristics and image characteristics of Latch PUF. This makes it difficult for attackers to locate the Latch PUF unit circuit through image characteristics, reduces the possibility of being identified or located by attackers, and improves the security of the chip.

[0087] Corresponding to the above embodiment, the present invention further proposes a computer-readable storage medium.

[0088] A computer-readable storage medium according to an embodiment of the present invention stores a static concealment program for a latch PUF unit circuit in a chip. When the static concealment program for the latch PUF unit circuit in the chip is executed by a processor, the static concealment method for the latch PUF unit circuit in the chip is implemented.

[0089] According to the computer-readable storage medium of an embodiment of the present invention, the static concealment method of the Latch PUF unit circuit in the chip can effectively eliminate the circuit characteristics and image characteristics of the Latch PUF, making it difficult for attackers to locate the Latch PUF unit circuit through image characteristics, thereby reducing the possibility of being identified or located by attackers and improving the security of the chip.

[0090] Corresponding to the above embodiment, the present invention further provides an electronic device.

[0091] Figure 10 FIG. 4 is a block diagram of an electronic device according to an embodiment of the present invention.

[0092] like Figure 10 As shown, the electronic device 100 of an embodiment of the present invention includes: a memory 110 and a processor 120. The memory 110 stores a program that can be run on the processor 120. When the processor 120 executes the program, the static hiding method of the Latch PUF unit circuit in the chip is implemented.

[0093] In electronic devices according to embodiments of the present invention, the aforementioned static concealment method for the Latch PUF unit circuit in the chip can effectively eliminate the circuit and image features of the Latch PUF, making it difficult for attackers to locate the Latch PUF unit circuit through image features. This reduces the possibility of being identified or located by attackers and improves chip security.

[0094] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0095] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0096] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0097] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0098] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0099] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A static hiding method for a Latch PUF unit circuit in a chip, characterized in that: The chip includes a plurality of Latch PUF unit circuits, each Latch PUF unit circuit including an inverter, a buffer, a first multiplexer, a second multiplexer, a first NAND gate, and a second NAND gate, wherein a transmission path from the buffer to the first multiplexer is a first path, a transmission path from the buffer to the second multiplexer is a second path, a transmission path from the first multiplexer to the first NAND gate is a third path, a transmission path from the second multiplexer to the second NAND gate is a fourth path, a transmission path from the output end of the second NAND gate to the input end of the first NAND gate is a fifth path, and a transmission path from the output end of the first NAND gate to the input end of the second NAND gate is a sixth path; the method includes: Instantiate standard cells corresponding to the inverter, the buffer, the first multiplexer, the second multiplexer, the first NAND gate, and the second NAND gate respectively using Verilog language; Generating a circuit netlist of the Latch PUF unit circuit according to each of the standard cells; Based on the circuit netlist, placing each of the standard cells, performing interconnection routing between each of the standard cells, and performing instruction adjustment after the interconnection routing, so as to obtain the Latch PUF unit circuit, wherein the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path; A plurality of Latch PUF unit circuits are randomly placed on a chip layout according to random coordinates.

2. The static hiding method of the Latch PUF unit circuit in the chip according to claim 1, characterized in that: Placing each of the standard cells includes: The standard cells are placed symmetrically.

3. The static hiding method of the Latch PUF unit circuit in the chip according to claim 2, characterized in that: The standard units are symmetrically placed, including: Placing the standard unit of the first NAND gate and the standard unit of the second NAND gate in mirror symmetry, and determining an axis of symmetry; Placing the standard cell of the first multiplexer below the standard cell of the first NAND gate along the symmetry axis, and placing a mirror image of the standard cell of the second multiplexer below the standard cell of the second NAND gate along the symmetry axis, with the standard cell of the first multiplexer and the standard cell of the second multiplexer being mirror-symmetrical; The standard cell of the buffer is placed below the standard cell of the second multiplexer along the symmetry axis.

4. The static hiding method of the Latch PUF unit circuit in the chip according to claim 3, characterized in that: Performing interconnection routing between the standard cells and performing instruction adjustment after the interconnection routing, including: Performing automatic layout and routing between each of the standard cells; According to the length of each path after automatic layout and routing, instructions are adjusted for each path so that the length of the first path is equal to the length of the second path, the length of the third path is equal to the length of the fourth path, and the length of the fifth path is equal to the length of the sixth path.

5. The static hiding method of the Latch PUF unit circuit in the chip according to claim 1, characterized in that: A plurality of Latch PUF unit circuits are randomly placed on a chip layout according to random coordinates, including: Get the unit height, NAND gate area, multiplexer area, and buffer area of ​​the standard cell in the process library file; determining a width of the NAND gate according to the area of ​​the NAND gate and the unit height; determining a width of the multiplexer according to an area of ​​the multiplexer and the unit height; determining a width of the buffer according to an area of ​​the buffer and the unit height; Obtaining the placement spacing and width of the WellTap units in the chip and the boundary coordinates of the WellTap units; Inputting the unit height, the width of the NAND gate, the width of the multiplexer, the width of the buffer, the placement spacing and width of the WellTap unit, and the boundary coordinates of the WellTap unit into a preset algorithm to randomly generate a plurality of random coordinates; A plurality of the Latch PUF unit circuits are placed on a chip layout according to the plurality of random coordinates.

6. The static hiding method of the Latch PUF unit circuit in the chip according to claim 5, characterized in that: The width of the NAND gate is determined by the following formula: Among them, W ND is the width of the NAND gate, A ND is the area of ​​the NAND gate, H cell is the unit height.

7. The static hiding method of the Latch PUF unit circuit in the chip according to claim 5, characterized in that: The width of the multiplexer is determined by the following formula: Among them, W MUX is the width of the multiplexer, A MUX is the area of ​​the multiplexer, H cell is the unit height.

8. The static hiding method of the Latch PUF unit circuit in the chip according to claim 5, characterized in that: The width of the buffer is determined by the following formula: Among them, W BUF is the width of the buffer, A BUF is the area of ​​the buffer, H cell is the unit height.

9. A computer-readable storage medium, characterized in that A static hiding program of a latch PUF unit circuit in a chip is stored thereon. When the static hiding program of the latch PUF unit circuit in the chip is executed by a processor, the static hiding method of the latch PUF unit circuit in a chip according to any one of claims 1 to 8 is implemented.

10. An electronic device, characterized in that: include: A memory and a processor, wherein the memory stores a program that can be run on the processor, and when the processor executes the program, the static hiding method of the Latch PUF unit circuit in the chip according to any one of claims 1 to 8 is implemented.

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