Automatic wiring method for electronic design automation (EDA) circuit schematic diagram display

Abstract

The invention discloses an automatic wiring method for electronic design automation (EDA) circuit schematic diagram display, which comprises the following steps of: S1, acquiring a connection relation and a coordinate set of components, and dividing hierarchical channels for the components; s2, sorting the connection relation and the coordinate set, finding two farthest points to determine a transverse path of the bus, classifying coordinate points to determine a longitudinal range of the bus, determining tracks which do not conflict with each other as longitudinal paths, and determining a bus path by combining the transverse path and the longitudinal paths; s3, determining a branching path from the bus to each pin according to the abscissa of the longitudinal path in the hierarchical channel and the coordinate of each pin; and S4, obtaining the longitudinal range of the hierarchical channel, comparing the longitudinal range of the hierarchical channel with the longitudinal range of the bus, determining the longitudinal path of the branch, integrating the transverse path and the branch path to each pin, and determining the overall path of the branch. Compared with the prior art, the utilization space of the channels is optimized, intersection is reduced, the wiring sequence is standardized, and wiring is more compact and attractive.

Description

Technical Field

[0001] The invention relates to the field of electronic automation design, in particular to an automatic wiring method for EDA circuit principle diagram display. Background Art

[0002] The circuit diagram display function plays a vital role in EDA (Electronic Design Automation) software design. EDA software is usually used to design, simulate and verify electronic circuits, and the circuit diagram display function is one of the main interfaces for users to interact with circuit design. It not only makes the circuit design process more intuitive and efficient, but also allows engineers to visually check the circuit design so that they can promptly discover and fix errors in the design process, helping them achieve the accuracy, reliability and maintainability of circuit design. Automatic wiring is a key step in circuit diagram display. Circuit wiring reflects the connection relationship and signal direction of the circuit component ports. In complex designs, a large number of wirings are usually required to be drawn. Therefore, efficient automatic wiring methods can shorten the wiring time and reduce the observation cost of engineers. At the same time, when designing the automatic wiring method of the circuit diagram, certain specific rules and constraints must be met according to the actual application background to ensure the rationality and practicality of the wiring.

[0003] At present, the common automatic routing technologies used for circuit diagram display include channel algorithms and heuristic search algorithms. There are also automatic routing methods that consider integrating different algorithms. [1] proposed to divide the routing process into horizontal channels and vertical channels, use heuristic search algorithms to allocate horizontal channels, and use dynamic perception search technology to allocate vertical channels, making full use of circuit layout information to reduce the search process; [2] proposed an algorithm for arranging lines between channels, which focuses on the areas between levels and avoids the overlap of horizontal lines by splitting vertical lines. However, in actual large-scale and complex circuits, there are cross-level lines and feedback lines, so additional constraints need to be added to optimize the direction of the lines; [3] proposed the process of layout and routing of the entire circuit schematic, and used the idea of ​​common vertical lines to allocate multiple through lines for the routing part, and proposed a column gap compression algorithm based on the greedy algorithm to reduce the distance between columns and improve the aesthetics of the circuit diagram. Similarly, this routing algorithm only focuses on the direction of the lines between channels, and does not explain the global routing in detail.

[0004] However, the above algorithm only considers the connection path, and does not consider the relationship between the bus and the branch line. It is simply a connection from one port to another, and then the entire path is represented by the bus. However, in actual circuits, some pins are connected to branch lines. For example, there is a bus called addr[3:0], and pins are p1 and p2. p1 is connected to branch line addr[0], and p2 is connected to branch line addr[1]. That is, p1 is connected to bit 0 of bus addr, and p2 is connected to bit 1 of bus addr. The above algorithm does not consider how to distinguish between the bus path and the branch line path, but will represent the entire path with bus addr[3:0]. This is not clear for circuit representation and is not conducive to circuit designers analyzing circuits.

[0005] Therefore, there is an urgent need for an automatic wiring method for EDA circuit schematic display, which has the characteristics of beautiful appearance, fast layout speed and no line overlap. Summary of the invention

[0006] In view of the problems existing in the prior art, the present invention discloses an automatic wiring method for EDA circuit schematic display, comprising:

[0007] Step S1: Read the design file of the circuit to be analyzed, obtain the connection relationship of all components and the corresponding coordinate set, and lay out the components in layers and divide the hierarchical channels;

[0008] Step S2: sorting the connection relationships of all components and the corresponding coordinate sets, finding the two coordinate points with the farthest distance to determine the horizontal path of the bus, and then classifying the coordinate points according to the hierarchical channels to determine the vertical range of the bus, and at the same time sorting the vertical range to determine the non-conflicting tracks as the vertical path of the bus, and combining the horizontal path and the vertical path of the bus to determine the bus path;

[0009] Step S3: determining a branching path from the bus to each pin according to the horizontal coordinate of the vertical path of the bus path in the hierarchical channel and the coordinates of the pins of each component;

[0010] Step S4: According to the coordinate set corresponding to the connection relationship of the branch line, the longitudinal range of each hierarchical channel is obtained, and it is compared with the longitudinal range of the bus in the hierarchical channel to determine the longitudinal path of the branch line, and the lateral path of the bus and the branch line path from the bus to each component pin are integrated to determine the overall path of the branch line.

[0011] Furthermore, the step S1 further includes:

[0012] When there are upper and lower pins in the circuit to be analyzed, a virtual pin is introduced for the circuit to be analyzed. The virtual pin is located at the left boundary of the component where the upper and lower pins are located, and the vertical coordinate value of the virtual pin is the vertical coordinate value of the real upper and lower pins of the component after being translated up or down by one unit cell.

[0013] Furthermore, the step S2 comprises:

[0014] Step S21: sorting the connection relationships of all components and the corresponding coordinate sets to find the two coordinate points with the farthest distance, and determining a preset vertical coordinate according to a linear search algorithm, so that a horizontal line segment that does not cross any component can be obtained through the preset vertical coordinate, and the horizontal coordinates of the two endpoints of the horizontal line segment are respectively the horizontal coordinates of the two coordinate points with the farthest distance;

[0015] Step S22: obtaining the maximum and minimum values ​​of the ordinates of the pins of the components in each of the hierarchical channels, and comparing them with the preset ordinates to determine the longitudinal range of the hierarchical channels;

[0016] Step S23: sorting the longitudinal range sets in each of the hierarchical channels, and assigning non-conflicting tracks in the hierarchical channels as longitudinal paths of the bus in a preset order, and obtaining the horizontal coordinates of the longitudinal paths;

[0017] Step S24: connecting the horizontal line segment with the vertical path, and using the path obtained after the connection as the bus path.

[0018] Furthermore, the step S23 further includes:

[0019] The set of vertical ranges preset in the hierarchical channel is sorted in order according to the vertex value of each vertical range, and each vertical range is preset as a track. Starting from the sorting order, the vertical range in the current track is compared with other tracks in a front-to-back order to determine whether the vertical range in the current track conflicts with the vertical range of the previous track;

[0020] When the judgment is no, the longitudinal range in the current track is allocated to the previous track, the current track is deleted, the current track is set as the next track, and the tracks are traversed one by one;

[0021] When the judgment is yes, the current track is compared with the next previous track.

[0022] Furthermore, the step S3 includes:

[0023] Step S31: obtaining a set of longitudinal paths connected to the pins of each component in the hierarchical channel;

[0024] Step S32: Compare the horizontal coordinate values ​​in the longitudinal path set to obtain the longitudinal path farthest from the current pin, and from the longitudinal path, obtain a transverse path connected to the current pin and not crossing any components, and connect the transverse path to the longitudinal path in step S23;

[0025] Step S33: Obtain the lateral path of each pin and use it as the branch path from the bus to each pin.

[0026] Furthermore, the step S32 includes:

[0027] After obtaining the longitudinal path farthest from the current pin in the longitudinal path set, determining whether a horizontal line between the current pin and the longitudinal path farthest from the current pin can be free from overlap with other horizontal lines;

[0028] When the judgment is no, a linear search is performed from the current pin position to the farthest longitudinal path to find a vertical line that does not overlap with any longitudinal path;

[0029] Connect the current pin to the vertical line horizontally to determine one end of the vertical line;

[0030] Connect the other end of the vertical line with the longitudinal path to obtain a horizontal line segment, and when the vertical line coincides with other horizontal line segments, translate the horizontal line segment upward by a unit length;

[0031] The vertical line, the horizontal line connecting the vertical line and the current pin, and the horizontal line segment connected to the longitudinal path are connected as the transverse path from the longitudinal path of the bus to the current pin.

[0032] Further, the step S4 includes:

[0033] Step S41: sorting the coordinate sets corresponding to the connection relationships of the branch lines to determine the two points farthest apart, integrating the lateral paths of the main line, and determining the lateral paths of the branch lines;

[0034] Step S42: according to the ordinate of the pin of the hierarchical channel and the ordinate value of the horizontal path of the branch line, the longitudinal range of the branch line in the hierarchical channel is obtained, and according to the horizontal coordinate of the longitudinal path of the bus in the hierarchical channel, the longitudinal path of the branch line in the hierarchical channel is obtained;

[0035] Step S43: determining the overall path of the branch line according to the transverse path of the branch line and the longitudinal path of the branch line in the hierarchical channel.

[0036] Compared with the prior art, the present invention has at least the following beneficial effects:

[0037] The present invention introduces a vertical sorting algorithm for hierarchical channels, optimizes the utilization space of channels, reduces crossovers, and standardizes the order of wiring, making the overall wiring more compact and beautiful;

[0038] At the same time, when designing the branching path, the present invention will only perform wiring when a line segment that does not overlap with the longitudinal path is found, so the present invention also avoids line overlap to a greater extent;

[0039] The present invention can efficiently display the circuit schematic diagram. Compared with the heuristic wiring algorithm, the present invention reduces a large number of search operations and inflection point setting operations, thus significantly improving the speed of determining the connection path.

[0040] In addition, the present invention can handle complex circuits and complex components well, not only completely displaying the connection path of the bus, but also distinguishing the bus path from the branch path. The present invention is also applicable to non-bus connection relationships. Therefore, compared with the prior art, the present invention can more completely display the connection information of the circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0042] Figure 1 It is a flow chart of an automatic wiring method for EDA circuit schematic display provided by the present invention;

[0043] Figure 2 is a flow chart of determining a bus path provided by the present invention;

[0044] Figure 3 It is a flow chart of determining a branching path from a bus path to a pin provided by the present invention;

[0045] Figure 4 is a flow chart for determining the overall path of a circuit provided by the present invention;

[0046] Figure 5 This is a schematic diagram of the connection relationship provided by the present invention.

[0047] Figure 6 It is a schematic diagram of the hierarchical channel provided by the present invention;

[0048] Figure 7 It is a schematic diagram of obtaining a horizontal line segment of a bus path provided by the present invention;

[0049] Figure 8is a schematic diagram of a longitudinal line segment sorting algorithm provided by the present invention;

[0050] Fig. 9 is a schematic diagram of a bus path provided by the present invention;

[0051] Fig.10 It is a schematic diagram of determining a branching path from a bus path to a pin provided by the present invention;

[0052] Fig.11 It is a schematic diagram of the overall path of the circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0054] Thus, a feature indicated in this specification will be used to illustrate one of the features of an embodiment of the present invention, rather than implying that each embodiment of the present invention must have the described feature. In addition, it should be noted that this specification describes many features. Although some features can be combined together to illustrate possible system designs, these features can also be used in other combinations that are not explicitly described. Thus, unless otherwise stated, the described combinations are not intended to be limiting.

[0055] The principle and structure of the present invention are described in detail below with reference to the accompanying drawings and embodiments.

[0056] The algorithm in the prior art only considers the connection path, and does not consider the relationship between the bus and the branch line. It is just a simple connection from one port to another, and then the entire path is represented by the bus. However, in actual circuits, some pins are often connected to branch lines. For example, there is a bus called addr[3:0], and pins are p1 and p2. p1 is connected to branch line addr[0], and p2 is connected to branch line addr[1]. That is, p1 is connected to the 0th bit of bus addr, and p2 is connected to the 1st bit of bus addr. The above algorithm does not consider how to distinguish between the bus path and the branch line path, but will represent the entire path with bus addr[3:0]. This is not clear for circuit representation and is not conducive to circuit designers analyzing circuits.

[0057] Based on the above problems, the present invention relates to an automatic wiring method for EDA circuit schematic display, which comprises:

[0058] Step S1: Read the design file of the circuit to be analyzed, obtain the connection relationship of all components and the corresponding coordinate set, and lay out the components in layers and divide the hierarchical channels;

[0059] Step S2: sorting the connection relationships of all components and the corresponding coordinate sets, finding the two coordinate points with the farthest distance to determine the horizontal path of the bus, and then classifying the coordinate points according to the hierarchical channels to determine the vertical range of the bus, and at the same time sorting the vertical range to determine the non-conflicting tracks as the vertical path of the bus, and combining the horizontal path and the vertical path of the bus to determine the bus path;

[0060] Step S3: determining a branching path from the bus to each pin according to the horizontal coordinate of the vertical path of the bus path in the hierarchical channel and the coordinates of the pins of each component;

[0061] Step S4: According to the coordinate set corresponding to the connection relationship of the branch line, the longitudinal range of each hierarchical channel is obtained, and it is compared with the longitudinal range of the bus in the hierarchical channel to determine the longitudinal path of the branch line, and the lateral path of the bus and the branch line path from the bus to each component pin are integrated to determine the overall path of the branch line.

[0062] See also Figure 1 , which is a flow chart of the present invention as a whole, from which Figure 1 It can be seen that the present invention is mainly divided into four processes, among which "obtaining a coordinate set of a connection relationship" is step S1 in the above process;

[0063] “Determine the bus path” is also step S2 in the above process;

[0064] “Determine the branching path from the bus path to the pin in a divergent manner” is step S3 in the above process;

[0065] “Determining the overall path of the branch line” is also step S4 in the above process.

[0066] Wherein, in the above step S1, it also includes:

[0067] When there are upper and lower pins in the circuit to be analyzed, a virtual pin is introduced for the circuit to be analyzed. The virtual pin is located at the left boundary of the component where the upper and lower pins are located, and the vertical coordinate value of the virtual pin is the vertical coordinate value of the real upper and lower pins of the component after being translated up or down by one unit cell.

[0068] That is, for special pins, such as the upper and lower pins of components, a virtual pin is introduced. The virtual pin is located at the left boundary of the component, and its y value in the Cartesian coordinate system is the y value of the upper and lower pins of the component translated up or down by one cell.

[0069] The virtual pin is added to the coordinate set of the connection relationship for calculation. When calculating the branch line path, the horizontal and vertical paths from the upper virtual pin to the actual upper and lower pins need to be supplemented.

[0070] Furthermore, the above step S2 includes:

[0071] Step S21: sorting the connection relationships of all components and the corresponding coordinate sets to find the two coordinate points with the farthest distance, and determining a preset vertical coordinate according to a linear search algorithm, so that a horizontal line segment that does not cross any component can be obtained through the preset vertical coordinate, and the horizontal coordinates of the two endpoints of the horizontal line segment are respectively the horizontal coordinates of the two coordinate points with the farthest distance;

[0072] Step S22: obtaining the maximum and minimum values ​​of the ordinates of the pins of the components in each of the hierarchical channels, and comparing them with the preset ordinates to determine the longitudinal range of the hierarchical channels;

[0073] Step S23: sorting the longitudinal range sets in each of the hierarchical channels, and assigning non-conflicting tracks in the hierarchical channels as longitudinal paths of the bus in a preset order, and obtaining the horizontal coordinates of the longitudinal paths;

[0074] Step S24: connecting the horizontal line segment with the vertical path, and using the path obtained after the connection as the bus path.

[0075] See also Figure 2 , which is a flowchart for determining the bus path in the present invention, from which Figure 2 It can be seen that the process of determining the bus path of the present invention is mainly divided into four steps, among which "the two points P1 (x1, y1) and p2 (x2, y2) that are farthest apart, determine the horizontal path through a linear search algorithm within the range [x1, x2]" is also the process of determining the horizontal line segment in the above step S21;

[0076] “Determining the longitudinal range of the hierarchical channel” is also the above-mentioned step S22;

[0077] “Sort the vertical range set of the hierarchical channels and determine the vertical path” is the above-mentioned step S23;

[0078] “Obtaining the bus path” is the above-mentioned step S24.

[0079] See also Figure 5 , which is a schematic diagram of the connection relationship of the circuit to be analyzed in the present invention, in which there are five components A, B, C, D, and E, and there are Figure 5 The connection relationship between the addr[4:0] bus and the new_addr[10:0] bus, where the ellipse represents the pin, the rounded rectangle and the thick arrow represent the bus, and the thin arrow represents the branch line;

[0080] Figure 6Schematic diagram of the hierarchical channel in the present invention, wherein the hierarchical channel is the range from the right edge of the component with the largest width to the left edge of the component of the next level after the components are layered;

[0081] See also Figure 7 , which is a flowchart of obtaining horizontal line segments in the above step S21, which first Figure 5 The coordinate set corresponding to the given connection relationship, in step S21, taking the addr[4:0] bus as an example, can find the two points a2(x1, y1) and d5(x2, y2) that are farthest apart, and then use the linear search algorithm to find a y value to obtain a line segment AB that does not cross components and does not overlap with other line segments;

[0082] The line segment AB is also the horizontal line segment obtained in the step S21.

[0083] Furthermore, in the present invention, the above step S23 also includes:

[0084] The set of vertical ranges preset in the hierarchical channel is sorted in order according to the vertex value of each vertical range, and each vertical range is preset as a track. Starting from the sorting order, the vertical range in the current track is compared with other tracks in a front-to-back order to determine whether the vertical range in the current track conflicts with the vertical range of the previous track;

[0085] When the judgment is no, the longitudinal range in the current track is allocated to the previous track, the current track is deleted, the current track is set as the next track, and the tracks are traversed one by one;

[0086] When the judgment is yes, the current track is compared with the next previous track.

[0087] See also Figure 8 , which is a flowchart of obtaining the horizontal coordinate of the longitudinal path in the above step S23. In step S22, the longitudinal range of each connection relationship in the hierarchical channel can be obtained, and the longitudinal range set S{R1, R2, R3, ...} in the hierarchical channel can be obtained;

[0088] Then the vertex values ​​of the longitudinal range are sorted from small to large. Starting from the sorted order, it is tested whether the line segment with a large vertex value can be filled into the same track occupied by the line segment with a small vertex value without any range conflict. If so, it is assigned to the track; otherwise, it will try to traverse the next track in the same way, determine the order of the longitudinal path of the line segment, and then determine the physical position of the line segment.

[0089] Here, "test whether the line segment with a larger vertex value can be filled into the same track occupied by the line segment with a smaller vertex value without any range conflict" is the same as "determine whether the longitudinal range in the current track does not conflict with the longitudinal range of the previous track" in the previous text;

[0090] "If so, it is assigned to the track" means "When it is determined to be yes, the vertical range in the current track is assigned to the previous track, and the current track is deleted, and the current track is set as the next track, traversing one by one."

[0091] The present invention can make the circuit diagram more beautiful as a whole and improve space utilization through the above-mentioned sorting method.

[0092] See also Fig. 9 , which is a schematic diagram of obtaining a bus path in the present invention. After the above steps S22 and S23, the paths of the buses such as addr[4:0] and new_addr[10:0] in the present invention can be obtained. Fig. 9 Indicated by thick solid line.

[0093] Furthermore, the above step S3 includes:

[0094] Step S31: obtaining a set of longitudinal paths connected to the pins of each component in the hierarchical channel;

[0095] Step S32: Compare the horizontal coordinate values ​​in the longitudinal path set to obtain the longitudinal path farthest from the current pin, and from the longitudinal path, obtain a transverse path connected to the current pin and not crossing any components, and connect the transverse path to the longitudinal path in step S23;

[0096] Step S33: Obtain the lateral path of each pin and use it as the branch path from the bus to each pin.

[0097] See also Figure 3 , which is a flow chart for determining the branching path in the present invention, from which Figure 2 It can be seen that the process of determining the branching path of the present invention is mainly divided into three steps, among which "obtaining the horizontal coordinate set of the longitudinal path of the pin in the hierarchical channel" is the above-mentioned step S31;

[0098] “Determine the longest path from the bus path to the pin in the multiple connection relationships” is also the above step S32 “compare the horizontal coordinate values ​​in the longitudinal path set, obtain the longitudinal path farthest from the current pin, and obtain the transverse path connected to the current pin and not crossing any components from the longitudinal path”, which is expressed as obtaining the transverse path connected to the pin from the longitudinal path farthest from the pin in step S32, which also corresponds to the longest path;

[0099] "According to the x value of the bus path of each connection relationship in the hierarchical channel, the path of the bus path of each connection relationship connected to the pin can be obtained, and the branch line information is attached", which is the above-mentioned step S33. After the branch line information is attached in this process, it is used as the branch line path in the above-mentioned step S33.

[0100] Among them, the above step S32 in the present invention further specifically includes the following steps:

[0101] After obtaining the longitudinal path farthest from the current pin in the longitudinal path set, determining whether a horizontal line between the current pin and the longitudinal path farthest from the current pin can be free from overlap with other horizontal lines;

[0102] When the judgment is no, a linear search is performed from the current pin position to the farthest longitudinal path to find a vertical line that does not overlap with any longitudinal path;

[0103] Connect the current pin to the vertical line horizontally to determine one end of the vertical line;

[0104] Connect the other end of the vertical line with the longitudinal path to obtain a horizontal line segment, and when the vertical line coincides with other horizontal line segments, translate the horizontal line segment upward by a unit length;

[0105] The vertical line, the horizontal line connecting the vertical line and the current pin, and the horizontal line segment connected to the longitudinal path are connected as the transverse path from the longitudinal path of the bus to the current pin.

[0106] See also Fig.10 , which is a schematic diagram of obtaining a branch line path from a bus path to a pin in the present invention, Fig.10 In the example, pin b1[2:0] is connected to bus e[1:0] and bus d[1:0].

[0107] According to step S31 and step S32, the pin farthest away is e[1:0], and its horizontal coordinate value is known to be x max .Depend on Fig.10 It can be seen that if a straight line is drawn directly from e[1:0] to b1[2:0], there will be line overlap. Therefore, starting from d1[2:0], at (x, x max ) range, find the line segment B'(x mid ,y-UNIT_GAP)C'(x mid , y+UNIT_GAP).

[0108] Determine x mid After the value of mid , x max ]Search for line segment A(xmid ,y mid )B(x max ,y mid ), line segment AB does not overlap with other line segments and does not cross components. Determine y mid After that, the branch common path A->B->C->D can be obtained. According to step S33, the branch paths from bus e[1:0] and bus d[1:0] to pin b1[2:0] can be determined. If a single pin has multiple connection relationships, we use oblique lines to distinguish the paths in the diagram.

[0109] according to Figure 3 According to the process shown in , the branching paths from the bus paths to the pins of each connection relationship in the embodiment are obtained one by one.

[0110] After the branch line path is obtained through the above process, the overall path of the circuit to be analyzed can be obtained by combining the bus path and the branch line path. Specifically, the above step S4 includes:

[0111] Step S41: sorting the coordinate sets corresponding to the connection relationships of the branch lines to determine the two points farthest apart, integrating the lateral paths of the main line, and determining the lateral paths of the branch lines;

[0112] Step S42: according to the ordinate of the pin of the hierarchical channel and the ordinate value of the horizontal path of the branch line, the longitudinal range of the branch line in the hierarchical channel is obtained, and according to the horizontal coordinate of the longitudinal path of the bus in the hierarchical channel, the longitudinal path of the branch line in the hierarchical channel is obtained;

[0113] Step S43: determining the overall path of the branch line according to the transverse path of the branch line and the longitudinal path of the branch line in the hierarchical channel.

[0114] See also Figure 4 , which is a flow chart of determining the overall path of the branch line in the present invention, from which Figure 4 It can be seen that the process of determining the overall path of the branch line in the present invention is mainly divided into four steps, among which, "according to the coordinate set of the connection relationship of the branch line, the longitudinal range of the hierarchical channel can be obtained, the longitudinal range of the hierarchical channel is compared with the y value obtained by the bus in step S21, the y value of the overall path of the branch line is determined, and the x value of the hierarchical channel is assigned to the path of the branch line", which is equivalent to the process of obtaining the longitudinal range of the branch line in the hierarchical channel in the above step S41, and the y value here is the preset longitudinal coordinate in step S21;

[0115] “Using the hierarchical channel x value obtained by the bus path in step S22 as the hierarchical channel x value of the overall path of the branch line” is equivalent to the process of obtaining the horizontal coordinate value of the branch line in the above step S42;

[0116] "Add the branch path from the bus path to the pin obtained in step S3 to the branch path to obtain the final overall branch path" is equivalent to the process of obtaining the overall branch path in the above step S43. Fig.11 , which is a schematic diagram of the overall circuit to be analyzed in the present invention. Fig.11 As can be seen in the figure, it distinguishes between the bus path and the branch line path, indicating the information of the connection between the branch line and the pin. In actual application, according to step S4, the overall path of the branch line can be obtained, and then some mouse click operations can be added to the view so that the branch line path can be displayed above the bus path. Fig.11 The medium-gray path is the overall path of branch addr[1].

[0117] The process of the present invention is generally described below, which includes the following steps:

[0118] Step S1, obtaining a coordinate set of a connection relationship: reading a circuit design file, obtaining information about components and their connection relationships, performing a hierarchical layout of the components, dividing hierarchical channels, and finding a coordinate set of corresponding pins according to the connection relationship;

[0119] For special pins, such as the upper and lower pins of components, a virtual pin position is introduced. The virtual pin position is located at the left edge of the component, and its y value in the Cartesian coordinate system is the y value of the upper and lower pins of the component translated up or down by one unit cell;

[0120] The virtual pin is added to the coordinate set of the connection relationship for calculation. When finding the branch path, the horizontal and vertical paths from the virtual pin to the actual upper and lower pins are finally added.

[0121] Step S2, determining the bus path, is divided into the following steps:

[0122] Step S21: sort the coordinate sets of the connection relationship to obtain the two points p1(x1, y1) and p2(x2, y2) that are the farthest apart, and then use a linear search algorithm to find a y value to obtain a line segment that does not cross components and does not overlap with other line segments. Let the endpoints be A(x1, y) and B(x2, y) respectively. The line segment passes through all hierarchical channels corresponding to the coordinate set.

[0123] Step S22: classify the coordinates in the coordinate set according to the hierarchical channel, and obtain the pins with the smallest and largest vertical coordinates in the hierarchical channel, and compare the obtained pin vertical coordinates with the y value obtained in step S21, so as to obtain the vertical range R[y', y"] of the coordinate set in the hierarchical channel;

[0124] Step S23: sort the vertical range set S{R1, R2, R3, ...} of the hierarchical channel from small to large according to the vertex value of the vertical range, and test whether the line segment with a large vertex value can be filled into the same track occupied by the line segment with a small vertex value based on the sorting order, and there is no range conflict. If so, it is assigned to the track;

[0125] Otherwise, it attempts to traverse the next track in the same way;

[0126] According to this method, the x-coordinate value of the coordinate set in the longitudinal path of the hierarchical channel is determined.

[0127] In step S24, the bus path can be obtained according to the y value obtained in step S21, the longitudinal range of each level channel obtained in step S22, and the x value of the level channel obtained in step S23.

[0128] Step S3, determining the branching path from the bus path to the pin, is divided into the following steps:

[0129] Step S31: because there are multiple pins, there may be multiple connection relationship coordinate sets that all contain the coordinates of this multiple pin;

[0130] According to step S2, the bus path of each connection relationship is obtained, indicating that the pin may correspond to the horizontal coordinate x values ​​of multiple vertical paths in the hierarchical channel. Let the obtained set be X{x1, x2, x3, ...}.

[0131] Step S32: Sort the set X to obtain the x that is farthest from the pin max , let the pin coordinates be P(x, y), and determine the line segment A(x max , y)B(x, y) can not overlap with other line segments. Otherwise, starting from pin P(x, y), through linear search, in (x, x max ) range, find a line segment that does not overlap with other vertical line segments, set it as C(x mid ,y-UNIT_GAP)D(x mid , y+UNIT_GAP), UNIT_GAP is the minimum spacing between lines.

[0132] Determine x mid After the value of mid , x max ]Search for the horizontal line segment E(x mid ,y mid )F(x max ,y mid ), line segment EF does not overlap with other line segments and does not cross components.

[0133] Step S33: According to step S31 and step S32, the longest path from the bus path in multiple connection relationships to the pin is obtained. According to the x value of the bus path in each connection relationship in the hierarchical channel, the path from the bus path in each connection relationship to the pin can be obtained, and the branch line information is attached.

[0134] Step S4, determining the overall path of the branch line, is divided into the following steps:

[0135] Step S41: According to the coordinate set of the connection relationship of the branch line, the longitudinal range of the hierarchical channel can be obtained, and the longitudinal range of the hierarchical channel is compared with the y value of the bus obtained in step S21 to determine the y value of the lateral path of the branch line.

[0136] Step S42: Using the x value of the longitudinal path of the bus path in the hierarchical channel obtained in step S22 as the x value of the longitudinal path of the branch line in the hierarchical channel.

[0137] Step S43: Add the path from the bus path to the pin obtained in step S3 to the path of the branch line, and finally obtain the overall path of the branch line.

[0138] Based on the automatic wiring method for EDA circuit schematic display proposed by the present invention, the present invention has the following beneficial effects:

[0139] The present invention introduces a vertical sorting algorithm for hierarchical channels, optimizes the utilization space of channels, reduces crossovers, and standardizes the order of wiring, making the overall wiring more compact and beautiful;

[0140] At the same time, when designing the branching path, the present invention will only perform wiring when a line segment that does not overlap with the longitudinal path is found, so the present invention also avoids line overlap to a greater extent;

[0141] The present invention can efficiently display the circuit schematic diagram. Compared with the heuristic wiring algorithm, the present invention reduces a large number of search operations and inflection point setting operations, thus significantly improving the speed of determining the connection path.

[0142] In addition, the present invention can handle complex circuits and complex components well, not only completely displaying the connection path of the bus, but also distinguishing the bus path from the branch path. The present invention is also applicable to non-bus connection relationships. Therefore, compared with the prior art, the present invention can more completely display the connection information of the circuit design.

[0143] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An automatic wiring method for EDA circuit schematic display, characterized in that: include: Step S1: Read the design file of the circuit to be analyzed, obtain the connection relationship of all components and the corresponding coordinate set, and lay out the components in layers and divide the hierarchical channels; Step S2: sorting the connection relationships of all components and the corresponding coordinate sets, finding the two coordinate points with the farthest distance to determine the horizontal path of the bus, and then classifying the coordinate points according to the hierarchical channels to determine the vertical range of the bus, and at the same time sorting the vertical range to determine the non-conflicting tracks as the vertical path of the bus, and combining the horizontal path and the vertical path of the bus to determine the bus path; Step S3: determining a branching path from the bus to each pin according to the horizontal coordinate of the vertical path of the bus path in the hierarchical channel and the coordinates of the pins of each component; Step S4: According to the coordinate set corresponding to the connection relationship of the branch line, the longitudinal range of each hierarchical channel is obtained, and it is compared with the longitudinal range of the bus in the hierarchical channel to determine the longitudinal path of the branch line, and the lateral path of the bus and the branch line path from the bus to each component pin are integrated to determine the overall path of the branch line.

2. The automatic wiring method for EDA circuit schematic display according to claim 1, characterized in that: The step S1 further comprises: When there are upper and lower pins in the circuit to be analyzed, a virtual pin is introduced for the circuit to be analyzed. The virtual pin is located at the left boundary of the component where the upper and lower pins are located, and the vertical coordinate value of the virtual pin is the vertical coordinate value of the real upper and lower pins of the component after being translated up or down by one unit cell.

3. The automatic wiring method for EDA circuit schematic display according to claim 1, characterized in that: The step S2 comprises: Step S21: sorting the connection relationships of all components and the corresponding coordinate sets to find the two coordinate points with the farthest distance, and determining a preset vertical coordinate according to a linear search algorithm, so that a horizontal line segment that does not cross any component can be obtained through the preset vertical coordinate, and the horizontal coordinates of the two endpoints of the horizontal line segment are respectively the horizontal coordinates of the two coordinate points with the farthest distance; Step S22: obtaining the maximum and minimum values ​​of the ordinates of the pins of the components in each of the hierarchical channels, and comparing them with the preset ordinates to determine the longitudinal range of the hierarchical channels; Step S23: sorting the longitudinal range sets in each of the hierarchical channels, and assigning non-conflicting tracks in the hierarchical channels as longitudinal paths of the bus in a preset order, and obtaining the horizontal coordinates of the longitudinal paths; Step S24: connecting the horizontal line segment with the vertical path, and using the path obtained after the connection as the bus path.

4. The automatic wiring method for EDA circuit schematic display according to claim 3, characterized in that: The step S23 further comprises: The set of vertical ranges preset in the hierarchical channel is sorted in order according to the vertex value of each vertical range, and each vertical range is preset as a track. Starting from the sorting order, the vertical range in the current track is compared with other tracks in a front-to-back order to determine whether the vertical range in the current track conflicts with the vertical range of the previous track; When the judgment is no, the longitudinal range in the current track is allocated to the previous track, the current track is deleted, the current track is set as the next track, and the tracks are traversed one by one; When the judgment is yes, the current track is compared with the next previous track.

5. The automatic wiring method for EDA circuit schematic display according to claim 4, characterized in that: The step S3 comprises: Step S31: obtaining a set of longitudinal paths connected to the pins of each component in the hierarchical channel; Step S32: Compare the horizontal coordinate values ​​in the longitudinal path set to obtain the longitudinal path farthest from the current pin, and from the longitudinal path, obtain a transverse path connected to the current pin and not crossing any components, and connect the transverse path to the longitudinal path in step S23; Step S33: Obtain the lateral path of each pin and use it as the branch path from the bus to each pin.

6. The automatic wiring method for EDA circuit schematic display according to claim 5, characterized in that: The step S32 comprises: After obtaining the longitudinal path farthest from the current pin in the longitudinal path set, determining whether a horizontal line between the current pin and the longitudinal path farthest from the current pin can be free from overlap with other horizontal lines; When the judgment is no, a linear search is performed from the current pin position to the farthest longitudinal path to find a vertical line that does not overlap with any longitudinal path; Connect the current pin to the vertical line horizontally to determine one end of the vertical line; Connect the other end of the vertical line with the longitudinal path to obtain a horizontal line segment, and when the vertical line coincides with other horizontal line segments, translate the horizontal line segment upward by a unit length; The vertical line, the horizontal line connecting the vertical line and the current pin, and the horizontal line segment connected to the longitudinal path are connected as the transverse path from the longitudinal path of the bus to the current pin.

7. The automatic wiring method for EDA circuit schematic display according to claim 6, characterized in that: The step S4 comprises: Step S41: sorting the coordinate sets corresponding to the connection relationships of the branch lines to determine the two points farthest apart, integrating the lateral paths of the main line, and determining the lateral paths of the branch lines; Step S42: according to the ordinate of the pin of the hierarchical channel and the ordinate value of the horizontal path of the branch line, the longitudinal range of the branch line in the hierarchical channel is obtained, and according to the horizontal coordinate of the longitudinal path of the bus in the hierarchical channel, the longitudinal path of the branch line in the hierarchical channel is obtained; Step S43: determining the overall path of the branch line according to the transverse path of the branch line and the longitudinal path of the branch line in the hierarchical channel.

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