Integrated circuit, method for generating circuit design and chip

Abstract

The invention relates to the field of integrated circuits, and provides an integrated circuit, a method for generating circuit design and a chip. The integrated circuit comprises M functional clock gating groups, M control registers and a functional logic circuit, each clock gating group comprises at least one clock gating circuit, and the M control registers are connected with the at least one clock gating circuit in the M clock gating groups and used for providing a first test control signal for the at least one clock gating circuit, the first test control signal is used for controlling the on-off state of the clock gating circuit when the working mode of the clock gating circuit is a capture mode. A control test input end is additionally arranged in the clock gating circuit and is used for forcibly controlling the clock gating circuit to be closed, so that the integrated circuit comprising the clock gating circuit can realize group control on a plurality of clock gating circuits, and the control precision of the clock gating circuit is improved; and the flip rate of the tested circuit is conveniently and effectively controlled in the capture stage.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and more specifically, to an integrated circuit, a method for generating a circuit design, and a chip. Background Art

[0002] During chip testing, the high flip rate of the circuit under test during the register capture phase will produce a large voltage drop, causing the minimum operating voltage of the chip under test to be abnormally high, affecting the chip yield. By setting the environment variables of the test vector generation tool and controlling the flip rate of the test vector, the flip rate of the circuit under test can be constrained.

[0003] However, adjusting the environment variables to generate new test vectors for retesting prolongs the test lead-in cycle on the one hand; on the other hand, since the switch state of the existing clock gating circuit in the register capture phase is completely controlled by the functional input signal, the flip rate of the test vector is constrained, which may make it difficult to generate vectors for test coverage on some paths, and it is difficult to effectively reduce the flip rate of the circuit under test while ensuring the completeness of the test path coverage. Therefore, how to conveniently and effectively control the flip rate of the circuit under test in the capture phase has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The embodiments of the present application provide an integrated circuit, a method for generating a circuit design, and a chip. By adding an additional control test input terminal on the basis of the original test control terminal of the clock gating circuit, the test control signal can force the clock gating circuit to be closed during the capture phase without relying on the functional input signal, thereby enabling group control of multiple clock gating circuits during the integrated circuit test process, thereby conveniently and effectively controlling the flip rate of the tested circuit during the capture phase.

[0005] In a first aspect, an integrated circuit is provided, comprising M clock gating groups, M control registers, and a functional logic circuit, wherein each of the M clock gating groups comprises at least one clock gating circuit, and M is a positive integer greater than 1; the clock gating circuit is connected to the functional logic circuit, and is used to output a clock output signal to the functional logic circuit in response to a functional input signal, a first test control signal, a second test control signal, and a clock input signal, wherein the second test control signal is used to indicate an operating mode of the clock gating circuit, and the first test control signal is used to control the switching state of the clock gating circuit when the operating mode of the clock gating circuit is a capture mode; the M control registers are respectively connected to at least one clock gating circuit in the M clock gating groups, and are used to provide a first test control signal to at least one clock gating circuit.

[0006] According to the technical solution provided by the present application, by adding an additional control test input terminal on the basis of the original test control terminal of the clock gating circuit, the additional test control terminal enables the test control signal to control the switch state of the clock gating circuit in the capture phase, and can force the clock gating circuit to close without relying on the functional input signal, so that the generated test vector can control the number of flips of the functional logic circuit under test according to the requirements without affecting the functional input signal, thereby conveniently and effectively controlling the flip rate of the circuit under test in the capture phase. Based on the above-mentioned improvement of the clock gating circuit, group control of multiple clock gating circuits in the integrated circuit is realized, and the test control signals of different clock gating groups are generated by different control registers, so that the test control of each group of clock gating circuits can be independent of each other, and forcing a group of clock gating circuits to close by the test control signal can not affect other groups of clock gating circuits, thereby improving the precision of the control of the clock gating circuit, and further conveniently and effectively controlling the flip rate of the circuit under test.

[0007] In combination with the first aspect, in certain implementations of the first aspect, when the second test control signal indicates that the operating mode of the clock gating circuit is the capture mode and the first test control signal indicates that the clock gating circuit is in the off state, the clock output signal is constantly at a low level.

[0008] According to the above technical solution, during the capture phase, when the test control signal indicates that the clock gating circuit is turned off, the clock gating circuit can remain in the closed state without being affected by the functional input signal, so that the test signal can force the tested circuit not to flip during the capture phase, thereby effectively controlling the flip rate of the test circuit without affecting the functional input signal.

[0009] In combination with the first aspect, in certain implementations of the first aspect, the functional logic circuit includes multiple regions, each clock gating group is connected to one region of the multiple regions, and the number of clock gating circuits in each clock gating group is negatively correlated with the voltage drop of one region.

[0010] According to the above technical solution, the number of clock gating circuits in each clock gating group is determined based on the voltage drop in each area in the test circuit. Since the voltage drop is positively correlated with the flip rate of the circuit, it can be used as a basis for determining the control accuracy required for the clock gating circuit, thereby improving the rationality and effectiveness of the clock gating circuit grouping method.

[0011] In combination with the first aspect, in certain implementations of the first aspect, the multiple regions include at least one first region and at least one second region, the voltage drop of at least one first region is greater than a first threshold, the voltage drop of at least one second region is less than or equal to the first threshold, the M clock gating groups include at least one first clock gating group and at least one second clock gating group, the first clock gating group is connected to the first region, the second clock gating is connected to the second region, the first clock gating group includes P clock gating circuits, and the second clock gating group includes Q clock gating circuits, wherein P and Q are positive integers and P is less than Q.

[0012] According to the above technical solution, the clock gating circuits are non-uniformly grouped based on the voltage drop of the region. The number of clock gating circuits in each group in the group responsible for the low voltage drop region is larger, while the number of clock gating circuits in each group responsible for the high voltage drop region is smaller. This allows a limited number of control registers to be allocated as many as possible to the regions that require more precise control, thereby improving the rationality and effectiveness of the clock gating circuit grouping method.

[0013] In combination with the first aspect, in some implementations of the first aspect, the voltage drop is obtained through simulation.

[0014] According to the above technical solution, the data of regional voltage drop is obtained through simulation in the circuit design stage, so that the grouping method of the clock gating circuit can be adjusted before the integrated circuit is produced, thereby optimizing the grouping method of the clock gating circuit.

[0015] In combination with the first aspect, in some implementations of the first aspect, the M control registers include registers in a functional logic circuit.

[0016] According to the above technical solution, the control register can use the existing register in the functional logic circuit as the control register, thereby saving the area of ​​the integrated circuit.

[0017] In combination with the first aspect, in some implementations of the first aspect, it includes a register on a test point chain of an integrated circuit and / or a register on an on-chip clock control chain of an integrated circuit.

[0018] According to the above technical solution, the control register may also be a register specially inserted into the test circuit in order to control the clock gating circuit, thereby providing a better control effect.

[0019] In a second aspect, a method for generating a circuit design is provided, comprising: obtaining a circuit design of a first circuit, the first circuit comprising a functional logic circuit, a plurality of clock gating circuits connected to a clock gating circuit, the clock gating circuit being used to output a clock output signal to the functional logic circuit in response to a functional input signal, a first test control signal, a second test control signal and a clock input signal, wherein the second test control signal is used to indicate an operating mode of the clock gating circuit, and the first test control signal is used to control a switching state of the clock gating circuit when the operating mode of the clock gating circuit is a capture mode; outputting a circuit design of a second circuit, the second circuit comprising a functional logic circuit, M clock gating groups and M control registers, M being a positive integer greater than 1, wherein each clock gating group comprises at least one clock gating circuit among a plurality of clock gating circuits, and the M control registers are respectively connected to the clock gating circuits in the M clock gating groups, and are used to provide a first test control signal for the clock gating circuits in the connected clock gating groups.

[0020] Optionally, the above method may be executed by electronic design automation (EDA) software or a computing device including EDA software.

[0021] In combination with the second aspect, in certain implementations of the second aspect, when the second test control signal indicates that the operating mode of the clock gating circuit is the capture mode and the first test control signal indicates that the clock gating circuit is in the off state, the clock output signal is constantly at a low level.

[0022] In combination with the second aspect, in certain implementations of the second aspect, the functional logic circuit includes multiple regions, and before outputting the circuit design of the second circuit, the method also includes: obtaining voltage drop data, the voltage drop data is used to indicate the voltage drop of each region of the multiple regions; each clock gating group in the second circuit is connected to one region of the multiple regions, and the number of clock gating circuits in each clock gating group is negatively correlated with the voltage drop of one region.

[0023] In combination with the second aspect, in certain implementations of the second aspect, the multiple regions include at least one first region and at least one second region, the voltage drop of at least one first region is greater than a first threshold, the voltage drop of at least one second region is less than or equal to the first threshold, the M clock gating groups include at least one first clock gating group and at least one second clock gating group, the first clock gating group is connected to the first region, the second clock gating is connected to the second region, the first clock gating group includes P clock gating circuits, and the second clock gating group includes Q clock gating circuits, wherein P and Q are positive integers and P is less than Q.

[0024] In combination with the second aspect, in some implementations of the second aspect, obtaining voltage drop data includes: obtaining the voltage drop data through simulation.

[0025] In combination with the second aspect, in some implementations of the second aspect, the M control registers include registers in a functional logic circuit.

[0026] In combination with the second aspect, in some implementations of the second aspect, the M control registers include registers on a test point chain of the second circuit and / or registers on an on-chip clock control chain of the second circuit.

[0027] In a third aspect, a device for generating a circuit design is provided, comprising: an acquisition module, used to acquire a circuit design of a first circuit, the first circuit comprising a functional logic circuit, and a plurality of clock gating circuits connected to a clock gating circuit, the clock gating circuit being used to output a clock output signal to the functional logic circuit in response to a functional input signal, a first test control signal, a second test control signal and a clock input signal, wherein the second test control signal is used to indicate an operating mode of the clock gating circuit, and the first test control signal is used to control a switching state of the clock gating circuit when the operating mode of the clock gating circuit is a capture mode; an output module, used to output a circuit design of a second circuit, the second circuit comprising a functional logic circuit, M clock gating groups and M control registers, M being a positive integer greater than 1, wherein each clock gating group comprises at least one clock gating circuit among a plurality of clock gating circuits, and the M control registers are respectively connected to the clock gating circuits in the M clock gating groups, and are used to provide a first test control signal for the clock gating circuits in the connected clock gating groups.

[0028] In combination with the third aspect, in certain implementations of the third aspect, when the second test control signal indicates that the operating mode of the clock gating circuit is the capture mode and the first test control signal indicates that the clock gating circuit is in the off state, the clock output signal is constantly at a low level.

[0029] In combination with the third aspect, in certain implementations of the third aspect, the functional logic circuit includes multiple regions, and before outputting the circuit design of the second circuit, the acquisition module is also used to: obtain voltage drop data, the voltage drop data is used to indicate the voltage drop of each region of the multiple regions; each clock gating group in the second circuit is connected to one region of the multiple regions, and the number of clock gating circuits in each clock gating group is negatively correlated with the voltage drop of one region.

[0030] In combination with the third aspect, in certain implementations of the third aspect, the multiple regions include at least one first region and at least one second region, the voltage drop of at least one first region is greater than a first threshold, the voltage drop of at least one second region is less than or equal to the first threshold, the M clock gating groups include at least one first clock gating group and at least one second clock gating group, the first clock gating group is connected to the first region, the second clock gating is connected to the second region, the first clock gating group includes P clock gating circuits, and the second clock gating group includes Q clock gating circuits, wherein P and Q are positive integers and P is less than Q.

[0031] In combination with the third aspect, in some implementations of the third aspect, the acquisition module is used to: acquire voltage drop data through simulation.

[0032] In combination with the third aspect, in certain implementations of the third aspect, the M control registers include registers in a functional logic circuit.

[0033] In combination with the third aspect, in certain implementations of the third aspect, the M control registers include registers on a test point chain of the second circuit and / or registers on an on-chip clock control chain of the second circuit.

[0034] In a fourth aspect, a computer-readable storage medium is provided, comprising computer program instructions. When the computer program instructions are executed by a computing device, the computing device executes the method in the above-mentioned second aspect or any possible implementation manner of the second aspect.

[0035] By way of example, these computer-readable storage media include, but are not limited to, one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), Flash memory, electrically EPROM (EEPROM), and hard drive.

[0036] Optionally, as an implementation manner, the above-mentioned storage medium may specifically be a non-volatile storage medium.

[0037] In a fifth aspect, a computer program product comprising instructions is provided. When the instructions are executed by a computing device, the computing device executes the method in the above-mentioned second aspect or any possible implementation manner of the second aspect.

[0038] In a sixth aspect, a computing device is provided, comprising a processor and a memory, wherein the memory is used to store instructions, and the processor is used to call and execute the instructions from the memory, so that the computing device executes the method in the second aspect or any possible implementation of the second aspect.

[0039] In a seventh aspect, a chip is provided, comprising an integrated circuit as in the first aspect or any possible implementation of the first aspect.

[0040] In an eighth aspect, an electronic device is provided, comprising the chip in the sixth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic diagram of clock gating.

[0042] Figure 2 is a schematic diagram of a conventional clock gating circuit 200 .

[0043] Figure 3 is a schematic diagram of a clock gating circuit 300 provided in an embodiment of the present application.

[0044] Figure 4 It is a schematic diagram of a register in a test circuit used as a control register in an embodiment of the present application.

[0045] Figure 5 It is a schematic diagram of a functional register in a functional logic circuit used as a control register in an embodiment of the present application.

[0046] Figure 6 It is a schematic diagram of a non-uniform grouping scheme of clock gating circuits provided in an embodiment of the present application.

[0047] Figure 7 It is a schematic flowchart of a method for generating a circuit design provided in an embodiment of the present application.

[0048] Figure 8 It is a schematic flowchart of a method for generating a circuit design provided in an embodiment of the present application.

[0049] Fig. 9 It is a schematic structural block diagram of a device for generating a circuit design provided in an embodiment of the present application.

[0050] Fig.10 It is a schematic structural block diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0052] The present application will present various aspects, embodiments or features around a system including multiple devices, components, modules, etc. It should be understood and appreciated that each system may include additional devices, components, modules, etc., and / or may not include all devices, components, modules, etc. discussed in conjunction with the figures. In addition, combinations of these schemes may also be used.

[0053] In addition, in the embodiments of the present application, words such as "exemplary" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0054] In the embodiments of the present application, "corresponding (corresponding, relevant)" and "corresponding (corresponding)" can sometimes be used interchangeably. It should be pointed out that when the distinction between them is not emphasized, the meanings they intend to express are consistent.

[0055] The architecture or application scenario described in the embodiments of the present application is intended to more clearly illustrate the technical solutions of the embodiments of the present application, and does not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0056] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0057] In the present application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: including the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0058] To facilitate understanding, relevant terms and concepts that may be involved in the embodiments of the present application are first introduced below.

[0059] 1. Automatic test pattern generation (ATPG): ATPG is a technology that automatically generates test patterns and provides them to manufactured integrated circuits for testing during chip testing. It is an implementation of design for testability (DFT). The test patterns generated by ATPG include the timing of input signals to the input end of the circuit and the timing of the expected output signals at the output end of the circuit. During testing, the input signals in the test pattern are loaded into the input end of the circuit under test, and the signals output from the output end of the circuit under test are collected and compared with the expected output signals in the test pattern to determine the test results.

[0060] 2. Flip rate: The number of changes in signal logic per unit time is called flip rate. The flip rate of the test vector refers to the flip rate of the output signal of the circuit or device under test expected in the test vector. The flip rate of the circuit under test refers to the flip rate of the actual output signal of the circuit or device under test after the test vector is loaded.

[0061] It should be understood that the output signal for which the flip rate is targeted is determined according to the test object. For example, when testing the implementation of a certain function by a functional logic circuit, the functional logic circuit as a whole can be regarded as the test object, in which case the output signal can refer to the signal output from the output end of the functional logic circuit. For another example, when it is necessary to test the working state of a part of the circuit in the functional logic circuit, the part of the circuit can be combined, in which case the output signal can refer to the signal output from the output end of the combination circuit. For another example, when it is necessary to test the working state of a certain device (such as a register) inside the functional logic circuit, the device can be regarded as the test object, in which case the output signal can refer to the signal output from the output end of the device.

[0062] 3. Clock gating: Clock gating is a technology that reduces power consumption by controlling the on / off of the circuit clock. Due to the high flip rate of the clock signal, the signal output by the register will flip as the clock signal of the input register flips, which makes the dynamic power consumption of the register in the functional logic circuit high due to the flip. By setting a clock gating circuit on the clock input path of the register of the functional logic circuit, the switching state of the clock gating circuit determines whether the clock signal of the input register flips, thereby controlling the flip rate of the register to reduce power consumption.

[0063] Figure 1 The schematic diagram of clock gating is shown. As shown in the figure, the clock gating circuit controls the clock signal input to the functional logic circuit, wherein the functional logic circuit includes at least one register and other combinational circuit parts directly controlled by the clock gating circuit. The clock gating circuit includes a clock input terminal, a functional input terminal, a test control terminal and a clock output terminal. The signal input to the functional input terminal is a functional input signal, which is generally controlled by the functional logic and is related to the signal when the functional logic circuit is working. For example, it can be an input signal and / or output signal of a certain part of the combinational circuit in the functional logic circuit. The signal input to the test control terminal is a test control signal, which is generally controlled by DFT logic. The signals of the functional input terminal and the test control terminal jointly determine the switching state of the clock gating circuit: when the clock gating circuit is in the open state, the circuit is turned on, and the signal output by the clock output terminal is the same as the signal input by the clock input terminal, that is, the clock signal of the input register flips normally; when the clock gating circuit is in the closed state, the circuit is not turned on, and the signal output by the clock output terminal is not affected by the clock input terminal and is constant at a low level, that is, the clock signal of the input register does not flip.

[0064] 4. Voltage drop: The voltage drop of a circuit refers to the difference between the external power supply voltage and the actual voltage input to the circuit. The voltage drop is positively correlated with the power consumption of the circuit. The greater the power consumption of the circuit, the greater the current generated, and thus the greater the voltage drop caused by the resistance in the power supply path. It should be understood that, like the flip rate mentioned above, the circuit targeted by the voltage drop is also related to the granularity of the test object. For example, the circuit can be the entire functional logic circuit, or a partial combinational circuit in the functional logic circuit, or a single register, etc.

[0065] At-speed testing is a technology that tests whether a chip can work properly at the actual operating frequency. In ATPG high-speed testing, the test vector is generated by an automatic test vector generator and can be run under a high-speed flip clock to test possible faults that may occur when the chip is running at high speed, such as timing problems, voltage noise, etc. In other implementations, high-speed testing may also be called full-speed testing or working speed testing.

[0066] Due to the high flip rate of the clock signal in high-speed testing, the input of the high flip rate clock signal to the register will cause the high flip rate of the register, resulting in high power consumption, causing a large voltage drop in the circuit under test. The large voltage drop will cause the minimum operating voltage of the chip under test to be abnormally high, thereby affecting the yield of the chip under test.

[0067] Through Figure 1 The clock gating technology can control the clock gating circuit of the register of part of the circuit under test to be in a closed state when the controlled register does not need to work, thereby controlling the flip rate of the circuit under test. Therefore, by setting the environment variables of the test vector generation tool, by limiting the functional input signal and test control signal of the clock gating circuit indicated by the generated test vector, the flip rate of the test vector can be controlled, thereby constraining the flip rate of the circuit under test.

[0068] However, adjusting the environment variables to generate new test vectors for retesting prolongs the test introduction cycle. On the other hand, due to the characteristics of traditional clock gating circuits, the switching state of the clock gating circuit in the register capture phase needs to be controlled by the functional input signal. As mentioned above, the functional input end is related to the signal when the functional logic circuit is working, which makes the control logic of the functional input signal complex, resulting in a large number of clock gating that is difficult to turn off in the generated test vector without affecting the functional test, making it difficult to effectively reduce the flip rate of the circuit under test. If the flip rate of the test vector is forcibly constrained, it will affect the signals related to the functional logic circuit, making it difficult to generate vectors for test coverage on some paths. Therefore, how to conveniently and effectively control the flip rate of the circuit under test in the capture phase has become a technical problem that needs to be solved urgently.

[0069] In view of this, the embodiments of the present application provide a clock gating circuit, an integrated circuit and a chip. By adding an additional control test input terminal on the basis of the original test control terminal, the test control signal can control the switching state of the clock gating circuit independently of the functional input signal during the capture stage, thereby conveniently and effectively controlling the flip rate of the circuit under test during the capture stage.

[0070] Figure 2 FIG. 2 shows a schematic diagram of a conventional clock gating circuit 200. Figure 2 As shown, the traditional clock gating circuit can be composed of an OR gate, a latch and a logic gate (such as an AND gate). The two input ends of the AND gate are the functional input end and the test control end of the clock gating circuit, and the output end provides the input signal of the latch. Among them, when the level value of the signal output by the output end of the AND gate is 1, the latch and the logic gate can control the conduction; correspondingly, when the level value of the signal output by the output end of the AND gate is 0, the latch and the logic gate can control the clock gating to be closed. Table 1 is Figure 2 The truth table corresponding to the clock gating circuit shown.

[0071] Table 1

[0072]

[0073] As shown in Table 1, the test control signal is used to indicate the working mode of the clock gating circuit. When the level value of the test control signal is 1 (high level), it indicates that the working mode of the gating circuit is the shift mode, that is, the register controlled by it is in the shift stage. At this time, the clock gating circuit is in the open state without being affected by the functional input signal, and the clock output signal is the same as the clock input signal. When the level value of the test control signal is 0 (low level), it indicates that the working mode of the gating circuit is the capture mode, that is, the register controlled by it is in the capture stage. At this time, the opening and closing of the clock gating circuit are completely controlled by the functional input signal. In the capture mode, when the level value of the functional input signal is 1, the clock gating circuit is in the open state, and the clock output signal is the same as the clock input signal; when the level value of the functional input signal is 0, the clock gating circuit is in the closed state, and the clock output signal remains constant at 0.

[0074] Among them, the above-mentioned shift phase and capture phase are two processes unique to the registers in the functional logic circuit during the test process. In order to facilitate the testing of the working state of the registers embedded in the complex circuit logic inside the functional logic circuit, DFT usually combines specific structures (such as scannable triggers) in the registers to be tested to form a scan chain. During the test process, the input data and output data of the registers to be tested are loaded and obtained through the scan chain respectively. The shift phase refers to the process of loading the test value in the test vector into the register through the scan chain; the capture phase refers to the process in which the register provides the test value to a specific combinational circuit in the functional logic circuit, and after obtaining the output value corresponding to the test value, the output value corresponding to the test value is captured from the register through the scan chain. The shift mode and capture mode are two working modes of the clock gating circuit corresponding to the shift phase and capture phase of the above-mentioned register. Since a clock signal is required to load the test value in the shift stage, the clock gating circuit is completely controlled by the test control signal and is in a normally open state in the shift mode; the output value that needs to be captured in the register in the capture stage is related to the functional input signal of the circuit. Therefore, in the traditional solution, as long as there is a corresponding functional input signal in the combinational circuit, a clock signal is provided to the register for capture, so that the opening state of the clock gating circuit in the shift mode is completely controlled by the functional input signal.

[0075] It should be understood that Figure 2 Only one case of a traditional clock gating circuit is shown as an example, and there may be other implementations of the logic gate combination method inside the traditional clock gating circuit. However, no matter what kind of traditional clock gating circuit, it is impossible to control the clock gating circuit to be closed without relying on the value of the functional input signal during the register capture stage, that is, the clock output signal remains constantly 0.

[0076] Therefore, an embodiment of the present application provides a clock gating circuit, including a function input terminal, a first test control terminal, a second test control terminal, a clock input terminal and a clock output terminal. The function input terminal is used to receive a function input signal, the first test control terminal is used to receive a second test control signal, the second test control terminal is used to receive a second test control signal, the clock input terminal is used to receive a clock input signal, and the clock output terminal is used to output a clock output signal in response to the function input signal, the first test control signal, the second test control signal and the clock input signal. The second test control signal is used to indicate the working mode of the clock gating circuit, and the first test control signal is used to control the switch state of the clock gating circuit when the working mode of the clock gating circuit is the capture mode.

[0077] Figure 3 FIG. 3 is a schematic diagram of a clock gating circuit 300 provided in an embodiment of the present application. Figure 3As shown, the clock gating circuit provided in the embodiment of the present application can be composed of an AND gate, an OR gate, a latch and a logic gate (such as an AND gate). The two input ends of the AND gate can receive the functional input signal and the first test control signal respectively. One input end of the OR gate can be connected to the output end of the AND gate, and the other input end can receive the second test control signal. The output end of the OR gate provides the input signal of the latch.

[0078] One input of the latch can be connected to the output of the AND gate, and the other input can receive a clock input signal; one input of the logic gate can be connected to the output of the latch, and the other input can receive a clock input signal, and the output can output a clock output signal. Figure 3 The working logic of latches and logic gates can be Figure 2 The working logic of the latch and the logic gate is the same, you can refer to Figure 2 The relevant instructions are not repeated here.

[0079] Table 2 Figure 3 The truth table corresponding to the clock gating circuit shown. Specifically, the second test control signal is used to indicate the working mode of the clock gating circuit. When the level value of the second test control signal is 1, it indicates that the working mode of the gating circuit is the shift mode, that is, the register controlled by it is in the shift stage, at this time, the clock gating circuit is in the open state, and the clock output signal is the same as the clock input signal. When the level value of the second test control signal is 0, it indicates that the working mode of the gating circuit is the capture mode, that is, the register controlled by it is in the capture stage, at this time, the opening and closing of the clock gating circuit is controlled by the function input signal and the first test control signal.

[0080] Table 2

[0081]

[0082] Through the above scheme, the second test control signal in the embodiment of the present application can realize the role of the test control signal in the traditional clock gating circuit, normally indicate the working mode of the circuit and control the clock gating circuit to remain in the open state during the shift phase, thereby ensuring that the control ability of the clock control circuit that can be provided by the test control signal is not affected.

[0083] In the capture mode, the first test control signal has the ability to force the clock gating circuit to close. Specifically, when the level value of the first test control signal is 0, no matter what the value of the functional input signal is, the level value of the output of the AND gate is 0, so that the clock gating circuit is in the closed state in the capture mode, and the clock output signal remains constantly 0. When the level value of the first test control signal is 1, the switch state of the clock gating circuit will be affected by the functional input.

[0084] Through the above scheme, the first test control signal additionally introduced in the embodiment of the present application relative to the traditional clock gating circuit can enable the clock gating circuit to remain in a closed state during the capture phase without being affected by the functional input signal, forcing the tested circuit not to flip, thereby effectively controlling the flip rate of the test circuit without affecting the functional input signal.

[0085] Through the technical solution provided in the embodiment of the present application, the functional input terminal in the existing clock gating circuit is replaced by an additional AND gate, and the output result of the AND gate is determined by the functional input and the additional test control, so that when the first test control signal is at a low level, the output clock of the AND gate remains at a low level, thereby achieving the first test control signal forcing the clock gating circuit to be in a closed state during the capture phase without relying on the functional input signal.

[0086] It should be understood that Figure 3 The clock gating circuit shown is only Figure 2 The conventional clock gating circuit shown corresponds to an example, and the combination of logic gates in the clock gating circuit provided by the embodiment of the present application is not limited to this. For example, on the basis of any other conventional clock gating circuit including a functional input terminal, the functional input terminal is replaced with an AND gate, and the newly added input terminal is used to receive the newly added test control signal, which can achieve the effect of the clock gating circuit provided by the present application.

[0087] To summarize, the clock gating circuit provided in the embodiment of the present application adds an additional control test input terminal on the basis of the original test control terminal. The additional test control terminal enables the test control signal to control the switching state of the clock gating circuit during the capture phase, and can force the clock gating circuit to be closed without relying on the functional input signal, so that the generated test vector can control the number of flips of the functional logic circuit being tested as required without affecting the functional input signal, thereby conveniently and effectively controlling the flip rate of the circuit being tested during the capture phase.

[0088] The embodiment of the present application also provides an integrated circuit including the above-mentioned clock gating circuit. The integrated circuit includes a functional logic circuit to be tested and at least one clock gating circuit provided by the embodiment of the present application, and the output end of each clock gating circuit is respectively connected to the clock input end of at least one device (such as a register) in the functional logic circuit to be tested, and provides a clock signal for the at least one device or the at least one local circuit to which it belongs.

[0089] Specifically, the clock gating circuit included in the integrated circuit is used to receive the input functional input signal, the first test control signal, the second test control signal and the clock input signal, and determine the clock output signal according to the above input, and output the clock output signal from the output terminal. Among them, the second test control signal is used to indicate the working mode of the clock gating circuit, and the first test control signal is used to control the switch state of the clock gating circuit when the working mode of the clock gating circuit is the capture mode.

[0090] Optionally, the clock gating circuit included in the integrated circuit provided in the embodiment of the present application can be the same as the clock gating circuit in the aforementioned embodiment, for example Figure 3 The clock gating circuit shown has the same structure and / or function. For related descriptions, reference can be made to the previous description of the clock gating circuit provided in the embodiment of the present application, which will not be repeated here.

[0091] Since there is a first test control terminal in the clock gating circuit provided in the embodiment of the present application, the first test control signal received by the first test control terminal can force the clock gating circuit to close in the capture mode, and the first test control signal can be independently controlled, not affected by other signals in the circuit and unrelated to other controls or functions of the circuit. Therefore, when an integrated circuit including the clock gating circuit provided by the present application is tested after the integrated circuit is manufactured, the generated test vector can control the switching state of these clock gating circuits in the capture phase by constraining the first test control signal of these clock gating circuits in the integrated circuit, thereby affecting the flip rate of the device or local circuit connected to the output end of these clock gating circuits.

[0092] In some possible implementations, the first test control signal of the clock gating circuit in the integrated circuit is provided by a specific control register. Optionally, the integrated circuit may include multiple control registers, each of which controls the first test control signal of at least one clock gating circuit, wherein each control register controls a different clock gating circuit. Specifically, the output end of the control register may be connected to the first control signal input end of at least one clock gating circuit controlled by it, and during the test, the control register receives the corresponding input signal according to the instruction of the test vector, thereby outputting the first test control signal indicated by the test vector and providing it to the clock gating circuit controlled by it.

[0093] For example, an integrated circuit may include N clock gating circuits and M control registers, where N and M are positive integers greater than 1, and M is less than or equal to N. The N clock gating circuits are divided into M clock gating groups, the M control registers correspond to the M clock gating groups one by one, and the output end of each control register is connected to all the clock gating circuits in a corresponding clock gating group, so as to provide a first test control signal for the clock gating circuit in the clock gating group.

[0094] Through the above scheme, it is equivalent to dividing the N clock gating circuits in the integrated circuit into M groups, and each group is controlled by a control register to control at least one clock gating circuit. The clock gating circuits in the same group are controlled by the same control register, and the first test control signals input during the test of these clock gating circuits are the same. The test control signals of different groups of clock gating circuits are generated by different control registers, so that the test control of each group of clock gating circuits can be independent of each other. Forcibly closing a group of clock gating circuits through the test control signal can not affect other groups of clock gating circuits, thereby improving the precision of the control of the clock gating circuit and improving the effectiveness of the control circuit flip rate.

[0095] Optionally, the control register may be a register specifically inserted into the test circuit in order to control the clock gating circuit. Figure 4 Figure 1 shows a schematic diagram of a register in a test circuit being used as a control register. Figure 4 As shown, the control registers in the test circuit include but are not limited to registers on the test point chain and / or registers on the on-chip clock controller (OCC) chain. For example, the control register may be a register designed on the test point chain of the test circuit during the integrated circuit design stage, and its design function is to match the clock gating circuit provided in the embodiment of the present application and provide a first test control signal for the clock gating circuit. For another example, the control register may also be a register added to the OCC chain of the test circuit during the integrated circuit design stage, and is also a register specially designed to provide the first test control signal for the clock gating circuit. The difference is that the original register on the OCC chain is used for the control of the test clock, so the control register added to the OCC chain can generate a signal for controlling the clock of the functional logic circuit according to the signal controlling the test clock. Among them, the test point refers to the position in the integrated circuit where the internal signal can be obtained by the probe during the test, so the register on the test point chain can directly accept the test control signal input by the test vector and / or directly obtain the corresponding output signal therefrom during the test process. OCC is used to provide the clock signal required for the test to the scan chain during the test process, so the register on the OCC chain can also directly accept the external input signal during the test process.

[0096] Optionally, the control register may also be an existing functional register in the functional logic circuit. Figure 5 FIG. 1 shows a schematic diagram of a functional register in a functional logic circuit being used as a control register. Figure 5As shown, the function registers used as control registers can be existing registers on the local function register chain, which are registers designed to implement other functions when the integrated circuit is designed. However, since the above-mentioned function registers do not need to work in all test scenarios provided by the test vectors, and their circuit connection method can meet the requirements of connecting with the clock gating circuit that needs to be controlled when used as control registers, these function registers are used as control registers in test scenarios that do not need to implement the originally designed functions. In the test scenario where the function register needs to implement the originally designed function, the above-mentioned function registers are used normally as function registers, and the task of the control register is implemented by other idle function registers.

[0097] Through the above solution, the existing functional registers of the circuit to be tested are used as control registers, which can reduce the number of registers that need to be added to the test circuit, thereby saving the area of ​​the integrated circuit.

[0098] It should be understood that each of the above control registers can independently provide the first test control signal, so each control register can also be called a test point in the test process. The connection between the test point and the clock gating circuit it controls is called a control line, the connection between a test point and a clock gating circuit is called a control line, and all the control lines of a test point are called a group of control lines.

[0099] Whether inserting an additional control register into the test circuit or using the existing functional register as the control register, the number of test points that can be provided on the integrated circuit per unit area is limited, and is generally much smaller than the number of clock gating circuits in the integrated circuit. When the clock gating circuits are grouped, since a group of clock gating circuits controlled by a test point is controlled by the same first test control signal, the test point can only instruct the group of clock gating circuits to be forced to close if all the clock gating circuits in the group can be closed. On the contrary, if any clock gating circuit in the group cannot be closed, the test point will not instruct the group of clock gating circuits to be forced to close. Therefore, the grouping method of the clock gating circuits greatly affects the effectiveness of the clock gating, that is, how to make each clock gating circuit be forced to close in as much idle time as possible becomes a problem that needs to be considered when clock gating is grouped.

[0100] In view of this, the present application provides a solution for evenly grouping clock gating circuits based on the above-mentioned group clock gating embodiments, and the voltage drops in different areas of the circuit to be tested can be used as the basis for grouping the clock gating circuits.

[0101] Specifically, the functional logic circuit to be tested in the integrated circuit can be divided into a plurality of different regions, each region is connected to at least one clock gating circuit, and the at least one clock gating circuit is divided into at least one clock gating group. That is, the clock output signal of each clock gating group in the M clock gating groups included in the integrated circuit is input to one region in the plurality of regions, providing a clock signal for part or all of the combinational circuits or devices in the region. The clock gating circuits connected to each region are divided into at least one group, and the number of clock gating circuits in the group where the clock gating circuits responsible for different regions are located can be different, and the number of clock gating circuits in each group is determined according to the voltage drop of the plurality of regions. That is, the number of clock gating circuits connected to the output end of each of the M control registers included in the integrated circuit is determined according to the voltage drop of the plurality of regions.

[0102] It should be understood that the region mentioned in the above embodiment refers to a part of the devices (such as registers) included in the functional logic circuit to be tested or a local combinational circuit composed of the part of the devices. The voltage drop of the region can be a statistical data determined based on the voltage drop of each device in the region, such as a weighted average. The voltage drop of the region reflects the power consumption of the region as a whole, and the power consumption is positively correlated with the flip rate of the device or combinational circuit. Therefore, the average flip rate of the device or combinational circuit in the region can be reflected based on the voltage drop.

[0103] For example, the number of clock gating circuits in the group of clock gating circuits connected to each region of the integrated circuit may be negatively correlated with the voltage drop of the region, that is, the larger the voltage drop, the more groups of clock gating circuits connected to the region are divided into, and the fewer the number of clock gating circuits in each group.

[0104] For example, the multiple regions may include at least one first region and at least one second region, wherein the voltage drop in the first region is greater than a preset threshold, such as m%, and the voltage drop in the second region is less than or equal to the threshold. The at least one clock gating group connected to the first region is called the first clock gating group, and the at least one clock gating group connected to the second region is called the second clock gating group. Each first clock gating group includes P clock gating circuits, and each second clock gating group includes Q clock gating circuits, where P and Q are positive integers less than N and P is less than Q. That is, the region where the voltage drop exceeds m% is identified as a high voltage drop region, and the high voltage drop region is evenly grouped according to the gating of each group of P clock gating circuits; the region where the voltage drop does not exceed m% is identified as a low voltage drop region, and the low voltage drop region is evenly grouped according to each group of Q clock gating circuits, and P is less than Q.

[0105] Figure 6 FIG. 1 is a schematic diagram showing the non-uniform grouping of clock gating circuits. Figure 6Taking the case shown as an example, 3 test points are allocated to the 6 clock gating circuits in the high voltage drop area, and each test point controls 2 of the 6 clock gating circuits through a group of control lines; 2 test points are allocated to the 6 clock gating circuits in the low voltage drop area, and each test point controls 3 of the 6 clock gating circuits through a group of control lines. For the grouping method of 3 clock gating circuits in each group, the responsible control register can only force the clock gating circuit to be closed when the circuits responsible for the 3 clock gating circuits are all idle; and for the grouping method of 2 clock gating circuits in each group, the responsible control register can force the clock gating circuit to be closed when the circuits responsible for the 2 clock gating circuits coincide with the idle time. Therefore, the proportion of the time that the clock gating circuit is forced to be closed to the total idle time of the circuit responsible for the clock gating circuit in the grouping method of 2 groups may be higher than that in the grouping method of 3 groups. The average flip rate per unit time of the circuit responsible for the clock gating circuit in the high voltage drop area is higher than that of the circuit responsible for the clock gating circuit in the low voltage drop area. Therefore, when the number of control registers is limited, allocating more control registers to the high voltage drop area can more effectively control the total flip rate of the circuit to be tested.

[0106] Through the above scheme, the number of clock gating circuits in each group of clock gating circuits is determined according to the voltage drop in each area in the test circuit. Since the voltage drop is positively correlated with the flip rate of the circuit, it can be used as a basis for determining the control accuracy required for the clock gating circuit, thereby improving the rationality and effectiveness of the clock gating circuit grouping method.

[0107] In some possible implementations, the voltage drops of multiple regions in the above embodiments can be obtained by simulation. Specifically, by using the waveform in the vector capture phase as an excitation, the power supply voltage drop of the circuit design is simulated, and the grouping method of the clock gating circuit in the circuit design is adjusted according to the simulation results, and then the above process can be repeated until the voltage drop of the circuit design meets the expected requirements. Since the simulation is performed in the design stage before the actual production of the integrated circuit, the grouping method of the clock gating circuit is determined according to the simulation results, which can be adjusted more conveniently in the design stage, thereby optimizing the grouping method of the clock gating circuit.

[0108] In summary, by applying the clock gating circuit provided in the embodiment of the present application to control its forced shutdown, the flip rate of the module under DFT high-speed testing can be effectively reduced, and it is compatible with the existing ATPG test architecture. In addition, through the group control scheme of the clock gating circuit in the integrated circuit provided in the embodiment of the present application, the "voltage drop heat island effect" of the local module can be effectively reduced.

[0109] Table 3 is the evaluation result of the flip rate control effect of the clock gating circuit provided in the embodiment of the present application on three different evaluation modules (integrated circuits). It can be seen that as the proportion of forced closure of clock gating increases, the circuit flip rate decreases significantly, the number of generated vectors increases significantly, and no significant changes are caused in the vector generation time and test coverage. When 75% of the clock gating is forced to be closed, the peak flip rate of the three evaluation modules decreases by about 35.6%, and the average flip rate decreases by about 35.7%.

[0110] Table 3

[0111]

[0112]

[0113] Table 4 shows the results of voltage drop control for 7 different evaluation modules (integrated circuits) using the clock gating circuit grouping scheme provided in the embodiment of the present application relative to the traditional clock gating scheme. The proportion of clock gating that is forced to be turned off by each evaluation module using the scheme provided in the embodiment of the present application is 75%, and the capture phase waveforms of the 10 vectors with the highest flip rate weights in the test vectors generated in the traditional mode and the gated grouping mode are selected for power supply voltage drop simulation. It can be seen that by forcing 75% of the clock gating to be turned off for each vector, the average power consumption in the capture phase can be reduced by 13.62%, and the number of violation points with dynamic voltage drops exceeding 10% is reduced by about 24.66%.

[0114] Table 4

[0115]

[0116]

[0117] Combination of the above Figures 3 to 6 The integrated circuit provided by the present application is described, and the embodiment of the present application also provides a method for generating a circuit design of the above integrated circuit. Figures 7 and 8 , the method for generating circuit design provided in this application is described.

[0118] Figure 7 A schematic flow chart of a method for generating a circuit design provided in an embodiment of the present application is shown. Optionally, Figure 7 The method shown may be applied to electronic design automation (EDA) software or a computing device including EDA software.

[0119] like Figure 7 As shown, the method includes the following steps.

[0120] Step S710: Obtain a circuit design of a first circuit.

[0121] Specifically, the first circuit includes a functional logic circuit and a plurality of clock gating circuits connected to the clock gating circuit. The clock gating circuit is used to output a clock output signal to the functional logic circuit in response to a functional input signal, a first test control signal, a second test control signal and a clock input signal, wherein the second test control signal is used to indicate an operating mode of the clock gating circuit, and the first test control signal is used to control a switch state of the clock gating circuit when the operating mode of the clock gating circuit is a capture mode.

[0122] For example, the EDA software may provide a user interface (UI) for instructing the user to input a circuit design. For example, the user may draw a circuit design diagram of a functional logic circuit on the UI provided by the EDA software, or the user may load a design file of the circuit design by clicking a function button provided by the UI, so that the EDA software obtains the input circuit design from the UI. The user may also input the circuit design into the EDA software in other ways, such as a hardware description language, or the EDA software may obtain the circuit design in other ways, such as the software or tool for designing functional logic circuits directly outputting the design results to the EDA software, and this application does not specifically limit this.

[0123] It should be understood that the first circuit may only include functional logic circuits and clock gating circuits. For example, the first circuit may be a circuit after the user completes the design of the integrated circuit functional logic in the process of designing the integrated circuit of the chip. The user takes the design of the circuit after the functional logic design is completed as input, and the EDA software can insert and / or specify multiple control registers in the circuit design to provide a test control signal for the clock gating circuit during the test process, that is, to provide the integrated circuit with a DFT for clock gating grouping, so that the user can control the clock signal of the input functional logic circuit during the test process. The first circuit may also only include functional logic circuits and clock gating circuits. For example, the first circuit may be an integrated circuit in which multiple control registers have been inserted and / or specified. After the design of the above integrated circuit is simulated (e.g., dynamic voltage drop simulation) and other verifications are performed, the EDA software can adjust the number, position, connection mode, etc. of the control registers in the circuit design according to the verification results, that is, optimize the existing DFT for clock gating grouping in the integrated circuit, thereby optimizing the control effect of clock gating on the circuit flip rate during the test process.

[0124] Optionally, the clock gating circuit in the first circuit may be a clock gating circuit provided in an embodiment of the present application, such as the clock gating circuit 300, so that it can be forcibly turned off in response to the first test control signal during the register capture phase. For example, when the second test control signal indicates that the working mode of the clock gating circuit is the capture mode, and the first test control signal indicates that the clock gating circuit is in the off state, the clock output signal is constantly at a low level.

[0125] It should be understood that the clock gating circuit in the first circuit may also be other clock gating circuits that can be forcibly turned off by a test control signal during the register capture phase, and this application does not make any specific limitation on this.

[0126] Step S720: Output the circuit design of the second circuit.

[0127] Specifically, the second circuit includes a functional logic circuit, M clock gating groups and M control registers, where M is a positive integer greater than 1. Each clock gating group includes at least one clock gating circuit among a plurality of clock gating circuits, and the M control registers are respectively connected to the clock gating circuits in the M clock gating groups, and are used to provide a first test control signal for the clock gating circuits in the connected clock gating groups.

[0128] For example, the EDA software may output a circuit design of an integrated circuit to which a DFT for clock gating group control is added and / or optimized. The output circuit design may be a circuit design diagram, a hardware description language, a design file, etc., which is not specifically limited in this application.

[0129] In some possible implementations, before outputting the circuit design of the second circuit, the method further includes acquiring voltage drop data. The voltage drop data is used to indicate the voltage drop of each of the multiple regions included in the functional logic circuit. In this case, the grouping method of the clock gating circuits in the second circuit can be determined according to the voltage drop data. Specifically, each clock gating group in the second circuit is connected to one of the multiple regions, and the number of clock gating circuits in each clock gating group is negatively correlated with the voltage drop of one region.

[0130] For example, the multiple regions may include at least one first region and at least one second region, the voltage drop of at least one first region is greater than the first threshold, and the voltage drop of at least one second region is less than or equal to the first threshold. The M clock gating groups may include at least one first clock gating group and at least one second clock gating group, the first clock gating group is connected to the first region, and the second clock gating group is connected to the second region. The first clock gating group may include P clock gating circuits, and the second clock gating group may include Q clock gating circuits, where P and Q are positive integers and P is less than Q.

[0131] Optionally, the voltage drop data may be obtained through simulation. For example, before executing the above method, the user may obtain the voltage drop data of the functional logic circuit in the first circuit through simulation through other software or equipment, so that the user uses the voltage drop data as input data when executing the above method. For another example, the voltage drop data may also be obtained through simulation by the software or equipment executing the above method, that is, the software or equipment executing the above method obtains the voltage drop data of the functional logic circuit in the first circuit according to the input circuit design of the first circuit.

[0132] Optionally, the above-mentioned division method of multiple areas in the functional logic circuit can be specified by the user through input data, or it can be determined autonomously by the software or device executing the above-mentioned method according to the input circuit design. For example, the user's input data can also include the first circuit layout position data, which is used to specify the division method of multiple areas in the functional logic circuit. For another example, the software or device executing the above-mentioned method can also divide the area of ​​the functional logic circuit according to the circuit design of the first circuit input by the user, combined with the voltage drop data of the functional logic circuit in the first circuit.

[0133] Optionally, the output second circuit may be an integrated circuit provided in an embodiment of the present application. The second circuit may have the same structure or features as the integrated circuit described above. For example, the M control registers of the second circuit may include registers in a functional logic circuit, and / or, the M control registers of the second circuit may include registers on a test point chain of the second circuit and / or registers on an on-chip clock control chain of the second circuit. The specific description of the second circuit structure or features may refer to the description of the integrated circuit provided in the present application in the previous embodiment, and will not be repeated here.

[0134] Figure 8 The following is a flowchart of generating a circuit design based on the above method. The following description is based on EDA software as the execution subject, and other methods that can be implemented can also be used. Figure 7 The software or equipment of the method shown is not specifically limited in this application. Figure 8As shown, the input data may include the circuit design of the first circuit including the functional logic circuit, the layout position data of the functional logic circuit, and the dynamic simulation voltage drop data of the functional logic circuit. The EDA software can divide the layout area of ​​the functional logic circuit in the lower point according to the voltage drop, and determine the granularity of the clock gating grouping in the area according to the voltage drop of each area. After determining the clock gating grouping, the EDA software designs a corresponding number of control registers in the circuit, and connects the second test control end of the clock gating circuit belonging to the same group in the circuit design to the same control register, and the first test control end of the clock gating circuit belonging to different groups is connected to different control registers. Thereby generating and outputting the circuit design of the second circuit, the second circuit can realize the function of a low-power test gate-level circuit.

[0135] An embodiment of the present application also provides a device for generating a circuit design, which includes a functional module for executing the above-mentioned method for generating a circuit design. Fig. 9 A schematic structural diagram of a device 900 for generating a circuit design provided in an embodiment of the present application is shown. Optionally, the device 900 can be used to provide or optimize DFT for the circuit design of an integrated circuit, for example, to provide a DFT for clock gating grouping for the integrated circuit or to optimize the existing DFT for clock gating grouping in the integrated circuit.

[0136] like Fig. 9 As shown, the device 900 includes: an acquisition module 910 and an output module 920.

[0137] Specifically, the acquisition module 910 is used to acquire the circuit design of the first circuit, which includes a functional logic circuit and multiple clock gating circuits connected to the clock gating circuit, and the clock gating circuit is used to output a clock output signal to the functional logic circuit in response to a functional input signal, a first test control signal, a second test control signal and a clock input signal, wherein the second test control signal is used to indicate the working mode of the clock gating circuit, and the first test control signal is used to control the switching state of the clock gating circuit when the working mode of the clock gating circuit is a capture mode.

[0138] Optionally, the acquisition module 910 is further used to acquire voltage drop data.

[0139] Optionally, the acquisition module 910 is specifically configured to acquire voltage drop data through simulation.

[0140] Specifically, the output module 920 is used to output the circuit design of the second circuit, which includes a functional logic circuit, M clock gating groups and M control registers, where M is a positive integer greater than 1, wherein each clock gating group includes at least one clock gating circuit among multiple clock gating circuits, and the M control registers are respectively connected to the clock gating circuits in the M clock gating groups, for providing a first test control signal for the clock gating circuits in the connected clock gating groups.

[0141] For the specific description of the circuit design of the first circuit input and / or the circuit design of the second circuit output by the device 900, reference can be made to the method for generating the circuit design in the previous text, which will not be repeated here. The device included as an EDA tool, its internal acquisition module 910 and output module 920 can be implemented by software, or by combining software and hardware, which is not limited in this embodiment.

[0142] The above functional modules can be implemented by software, such as code running on a computing device, or can be implemented by hardware, such as a computing device.

[0143] The present application also provides a computing device 100 for generating a circuit design, such as a computing device including EDA software, used as an EDA device tool. Fig.10 As shown, computing device 100 includes: bus 102, processor 104, memory 106 and communication interface 108. Processor 104, memory 106 and communication interface 108 communicate with each other via bus 102. It should be understood that the present application does not limit the number of processors and memories in computing device 100.

[0144] The bus 102 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.10 The bus 102 is represented by only one line, but it does not mean that there is only one bus or one type of bus. The bus 102 may include a path for transmitting information between various components of the computing device 100 (eg, the memory 106, the processor 104, and the communication interface 108).

[0145] The processor 104 may include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0146] The memory 106 may include a volatile memory, such as a random access memory (RAM). The memory 106 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

[0147] The memory 106 stores executable program codes, and the processor 104 executes the executable program codes to respectively implement the functions of the acquisition module and the output module, thereby implementing the above-mentioned method for generating a circuit design. That is, the memory 106 stores instructions for executing the above-mentioned method for generating a circuit design.

[0148] The communication interface 108 uses a command distribution module such as, but not limited to, a network interface card, a transceiver, etc. to implement communication between the computing device 100 and other devices or a communication network.

[0149] The embodiment of the present application also provides a computer program product including instructions. The computer program product may be software or a program product including instructions that can be run on a computing device or stored in any available medium. When the computer program product is run on at least one computing device, the at least one computing device executes the above-mentioned method for generating a circuit design.

[0150] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by a computing device or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk). The computer-readable storage medium includes instructions that instruct the computing device to execute the above-mentioned method for generating a circuit design.

[0151] The present application also provides a chip. The chip includes: Figure 3 The clock gating circuit shown, or an integrated circuit including the clock gating circuit.

[0152] The embodiment of the present application also provides an electronic device, which includes the above chip.

[0153] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0154] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the protection scope of the technical solutions of the embodiments of the present application.

Claims

1. An integrated circuit, characterized in that: It includes M clock gating groups, M control registers, and functional logic circuits. Each of the M clock gating groups includes at least one clock gating circuit, and M is a positive integer greater than 1; The M control registers are respectively connected to at least one clock gating circuit in the M clock gating groups, and are used to provide a first test control signal for the at least one clock gating circuit; Each clock gating circuit is connected to the functional logic circuit, and is used to output a clock output signal to the functional logic circuit in response to a functional input signal, the first test control signal, the second test control signal and the clock input signal, wherein the second test control signal is used to indicate the working mode of the clock gating circuit, and the first test control signal is used to control the switching state of the clock gating circuit when the working mode of the clock gating circuit is the capture mode.

2. The integrated circuit according to claim 1, characterized in that When the second test control signal indicates that the working mode of the clock gating circuit is the capture mode, and the first test control signal indicates that the clock gating circuit is in the closed state, the clock output signal is constantly at a low level.

3. The integrated circuit according to claim 1 or 2, characterized in that: The functional logic circuit includes a plurality of regions, each of the clock gating groups is connected to one of the plurality of regions, and the number of clock gating circuits in each clock gating group is negatively correlated to a voltage drop of the one region.

4. The integrated circuit according to claim 3, characterized in that The multiple regions include at least one first region and at least one second region, the voltage drop of the at least one first region is greater than a first threshold, and the voltage drop of the at least one second region is less than or equal to the first threshold, The M clock gating groups include at least one first clock gating group and at least one second clock gating group, the first clock gating group is connected to the first region, and the second clock gating group is connected to the second region, The first clock gating group includes P clock gating circuits, and the second clock gating group includes Q clock gating circuits, where P and Q are positive integers and P is less than Q.

5. The integrated circuit according to claim 3 or 4, characterized in that: The voltage drop is obtained through simulation.

6. The integrated circuit according to any one of claims 1 to 5, characterized in that: The M control registers include registers in the functional logic circuit.

7. The integrated circuit according to any one of claims 1 to 6, characterized in that: The M control registers include registers on a test point chain of the integrated circuit and / or registers on an on-chip clock control chain of the integrated circuit.

8. A method for generating a circuit design, characterized in that include: Acquire a circuit design of a first circuit, wherein the first circuit includes a functional logic circuit, and a plurality of clock gating circuits connected to the clock gating circuit, wherein the clock gating circuit is used to output a clock output signal to the functional logic circuit in response to a functional input signal, a first test control signal, a second test control signal, and a clock input signal, wherein the second test control signal is used to indicate an operating mode of the clock gating circuit, and the first test control signal is used to control a switch state of the clock gating circuit when the operating mode of the clock gating circuit is a capture mode; Output a circuit design of a second circuit, wherein the second circuit includes the functional logic circuit, M clock gating groups and M control registers, where M is a positive integer greater than 1, wherein each clock gating group includes at least one clock gating circuit among the multiple clock gating circuits, and the M control registers are respectively connected to the clock gating circuits in the M clock gating groups, for providing the first test control signal to the clock gating circuits in the connected clock gating groups.

9. The method according to claim 8, characterized in that When the second test control signal indicates that the working mode of the clock gating circuit is the capture mode, and the first test control signal indicates that the clock gating circuit is in the closed state, the clock output signal is constantly at a low level.

10. The method according to claim 8 or 9, characterized in that: The functional logic circuit includes a plurality of regions. Before outputting the circuit design of the second circuit, the method further includes: acquiring voltage drop data, the voltage drop data being used to indicate a voltage drop in each of the plurality of regions; Each clock gating group in the second circuit is connected to one of the multiple regions, and the number of clock gating circuits in each clock gating group is negatively correlated to the voltage drop of the one region.

11. The method according to claim 10, characterized in that The multiple regions include at least one first region and at least one second region, the voltage drop of the at least one first region is greater than a first threshold, and the voltage drop of the at least one second region is less than or equal to the first threshold, The M clock gating groups include at least one first clock gating group and at least one second clock gating group, the first clock gating group is connected to the first region, and the second clock gating group is connected to the second region, The first clock gating group includes P clock gating circuits, and the second clock gating group includes Q clock gating circuits, where P and Q are positive integers and P is less than Q.

12. The method according to claim 10 or 11, characterized in that: The obtaining of voltage drop data comprises: The voltage drop data is obtained through simulation.

13. The method according to any one of claims 8 to 12, characterized in that The M control registers include registers in the functional logic circuit.

14. The method according to any one of claims 8 to 13, characterized in that The M control registers include registers on a test point chain of the second circuit and / or registers on an on-chip clock control chain of the second circuit.

15. A chip, characterized in that: Comprising an integrated circuit as claimed in any one of claims 1 to 7.

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