Neural parameter optimization method for digital in-memory calculation and terminal
By establishing the energy consumption model of the neural network and iteratively optimizing its parameters, the problem of high power consumption in digital in-memory computing is solved, and the effect of reducing power consumption is achieved while maintaining the accuracy of the neural network.
Patent Information
- Application Number
- CN202411791710.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-06
- Publication Date
- 2025-03-28
AI Technical Summary
In the prior art, the power consumption of digital in-memory computing is high, resulting in increased resource consumption and high requirements for power supply capacity. Especially in the scenarios of neural network installation, how to reduce power consumption has become an important issue.
By establishing an energy consumption model for in-memory computing of neural networks, iteratively optimizes the parameters of the neural network according to the energy consumption model, and obtains and outputs optimization parameters to reduce the power consumption of digital in-memory computing.
It realizes the power consumption of digital in-memory computing without losing the accuracy of the neural network, and solves the problem of high power consumption of digital in-memory computing in the prior art.
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Figure CN119721159A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of machine learning technology, and in particular to a neural parameter optimization method and terminal for digital in-memory computing. Background Art
[0002] When CPUs and GPUs of traditional architectures perform computationally intensive tasks, they need to read massive parameters from memory and then perform calculations. In this architecture, data transmission between computing units and storage units greatly limits the computing speed, and frequent read and write operations consume a lot of energy, often exceeding the energy consumption of the computing units themselves. In order to solve this problem, in-memory computing came into being. Computing In Memory (CIM) is an emerging computer architecture technology that integrates storage functions with computing functions, avoiding data transmission between storage units and computing units, thereby improving computing efficiency and reducing energy consumption.
[0003] In-memory computing is divided into digital in-memory computing and analog in-memory computing. Analog in-memory computing is mainly based on the laws of physics (Ohm's law and Kirchhoff's law) to implement multiplication and accumulation operations on the memory array, and its area and power consumption are small. However, since analog signals are sensitive to factors such as process, temperature, voltage, and noise, calculations based on analog signals are also very susceptible to these factors, which in turn affect the accuracy of the calculation results. Therefore, analog in-memory computing is suitable for scenarios with low computing power and low power consumption. In some high-precision application scenarios, digital in-memory computing has been widely used in scenarios such as large computing power, cloud computing, and edge computing due to its high precision, strong noise resistance, and high flexibility.
[0004] However, digital in-memory computing requires the integration of logical computing circuits inside the storage array, which increases power consumption overhead. High-precision computing often requires more computing resources and higher operating voltages, resulting in higher power consumption. This not only leads to more resource consumption, but also places higher demands on the power supply capacity in application scenarios. In the neural network deployment scenario, since the output power of the power management circuit has a design upper limit, how to reduce the power consumption of digital in-memory computing becomes particularly important. Summary of the invention
[0005] The purpose of the present invention is to provide a neural parameter optimization method for digital in-memory computing, aiming to solve the problem of high power consumption of digital in-memory computing in the prior art.
[0006] The technical solution adopted by the present invention to solve the technical problem is as follows:
[0007] The present invention provides a neural parameter optimization method for digital in-memory computing, and the neural parameter optimization method for digital in-memory computing comprises:
[0008] Acquire a neural network, and train the neural network to obtain parameters of the neural network that meet target requirements;
[0009] Establishing an energy consumption model for the operation of the neural network;
[0010] Iteratively optimize the parameters of the neural network according to the energy consumption model, and obtain and output the optimized parameters.
[0011] Furthermore, the energy consumption model of the neural network operation is established, specifically including:
[0012] Establish a dynamic energy model of storage basic unit array;
[0013] Establishing the dynamic energy model of the additive tree;
[0014] The storage basic unit array dynamic energy model and the addition tree dynamic energy model are used as the energy consumption model.
[0015] Furthermore, the establishment of a dynamic energy model of a storage basic unit array specifically includes:
[0016] Obtaining the energy consumption when the storage basic unit array is flipped, and establishing a storage basic unit energy lookup table;
[0017] An input mode of a storage basic unit is acquired, and a dynamic energy model of the storage basic unit array is established according to the input mode and the storage basic unit energy lookup table.
[0018] Furthermore, the establishment of the addition tree dynamic energy model specifically includes:
[0019] Obtain the energy consumption of the storage basic unit array when performing addition operations, and establish a full adder energy lookup table;
[0020] The addition tree structure of the neural network is obtained, and the addition tree dynamic energy model is established according to the addition tree structure and the full adder energy lookup table.
[0021] Furthermore, the calculating the average model energy consumption of the neural network on the validation set according to the energy consumption model and the validation set specifically includes:
[0022] Furthermore, the energy consumption model of the neural network operation is established, and then further includes:
[0023] Obtain a validation set, and calculate the average model energy consumption of the neural network on the validation set according to the energy consumption model;
[0024] The iterative optimization of the parameters of the neural network according to the energy consumption model, each iteration, includes:
[0025] Optimizing the parameters of the neural network to obtain intermediate parameters;
[0026] Calculate the intermediate average energy consumption of the intermediate parameter on the verification set according to the energy consumption model;
[0027] It is determined whether the intermediate average energy consumption is lower than the model average energy consumption; if the intermediate average energy consumption is lower than the model average energy consumption, the intermediate parameters and the intermediate average energy consumption are recorded.
[0028] Furthermore, the calculating the average energy consumption of the model of the neural network on the validation set according to the energy consumption model specifically includes:
[0029] Running the neural network on the validation set, and recording the number of activation value flips of each layer;
[0030] Calculating the average energy consumption of the model according to the activation value flipping times and the energy consumption model;
[0031] The calculating the intermediate average energy consumption of the intermediate parameter on the verification set according to the energy consumption model specifically includes:
[0032] Setting the parameters of the neural network to the intermediate parameters, running the neural network on the validation set, and recording the number of intermediate flips of the activation value of each layer;
[0033] The intermediate average energy consumption is calculated according to the intermediate flipping times of the activation value and the energy consumption model.
[0034] Further, the optimizing the parameters of the neural network to obtain the intermediate parameters specifically includes:
[0035] Performing a perturbation on the parameter and training the neural network multiple times to obtain the parameter to be verified;
[0036] Calculate the average accuracy of the parameter to be verified on the verification set according to the verification set;
[0037] If the average accuracy of the parameter to be verified on the verification set meets the verification condition, the parameter to be verified is used as the intermediate parameter;
[0038] If the average accuracy of the parameter to be verified on the verification set does not meet the verification condition, the parameter to be verified is obtained again.
[0039] Furthermore, the obtaining and outputting of optimization parameters specifically includes:
[0040] Retrieve all recorded intermediate average energy consumptions and obtain the lowest intermediate average energy consumption;
[0041] The intermediate parameter corresponding to the lowest intermediate average energy consumption is used as the optimization parameter and output.
[0042] In addition, to achieve the above-mentioned purpose, the present invention also provides a terminal, which includes: a memory, a processor, and a neural parameter optimization program for digital in-memory calculation stored in the memory and run on the processor, and when the neural parameter optimization program for digital in-memory calculation is executed by the processor, the terminal is controlled to implement the steps of the neural parameter optimization method for digital in-memory calculation as described above.
[0043] In addition, to achieve the above-mentioned purpose, the present invention also provides a readable storage medium, which stores a neural parameter optimization program for digital in-memory calculations, and when the neural parameter optimization program for digital in-memory calculations is executed by a processor, the steps of the neural parameter optimization method for digital in-memory calculations as described above are implemented.
[0044] The present invention adopts the above technical solution to achieve the following effects:
[0045] The present invention establishes an energy consumption model for in-memory computing of a neural network, and then optimizes the energy consumption of the neural network operation according to the energy consumption model, thereby obtaining the neural network parameters with the lowest energy consumption, thereby reducing the power consumption of digital in-memory computing in the prior art and solving the problem of high power consumption of digital in-memory computing in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] Figure 1 It is a flowchart of the steps of a neural parameter optimization method for digital in-memory calculation in a preferred embodiment of the present invention;
[0047] Figure 2 It is a flow chart of a neural parameter optimization method for digital in-memory computing in a preferred embodiment of the present invention;
[0048] Figure 3 Schematic diagram of input and output of a single convolutional layer in a preferred embodiment of the present invention;
[0049] Figure 4 It is a schematic diagram of the operating environment of a preferred embodiment of the terminal of the present invention. DETAILED DESCRIPTION
[0050] In order to make the purpose, technical solution and advantages of the present invention clearer and more specific, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0051] Embodiment 1
[0052] See also Figure 1 and Figure 2 , Embodiment 1 of the present application is a neural parameter optimization method for digital in-memory computing, which comprises the steps of:
[0053] S1. Obtain a neural network, and train the neural network to obtain parameters of the neural network that meet target requirements.
[0054] In this embodiment, the target requirement is specifically that the classification accuracy of the neural network is greater than the set accuracy threshold, and the purpose of the overall neural parameter search method is to search for the weight parameters with the lowest or approximately the lowest flipping energy consumption while meeting the accuracy requirement.
[0055] To this end, in this embodiment, the neural network is first trained according to the gradient descent method or other training methods to obtain the neural network parameters that meet the accuracy requirements. Since the target requirement of this embodiment is the accuracy, the loss function in the training in this embodiment is mainly based on the loss value of the accuracy, and on this basis, the L1 regularization parameter is introduced:
[0056] L(θ)=L accuracy (θ)+α∑|θ j |;
[0057] Among them, θ represents the neural network parameters, L accuracy (θ) represents the accuracy loss value under the neural network parameter θ, α∑|θ j | is a regularization term, where α is the regularization strength. The larger α is, the sparser the model parameters are. j represents the jth parameter of the neural network, and L(θ) represents the total loss value under the neural network parameter θ.
[0058] L1 regularization, also known as Lasso regularization, is a regularization technique commonly used in machine learning, especially when dealing with data sets with a large number of features. It encourages the model to produce sparse weights by adding the L1 norm of the weights (i.e. the sum of the absolute values of the weight vector) as a penalty term in the loss function of the model. This means that L1 regularization will push some weight coefficients to shrink exactly to zero, thereby achieving automatic feature selection.
[0059] This sparsity helps with feature selection, making the model more concise and easier to understand, so that the model not only performs well on the training data, but also improves its generalization ability on unseen data.
[0060] In this embodiment, since the energy consumption of the neural network needs to be optimized subsequently, the accuracy may decrease during the optimization process. Therefore, it is necessary to leave a certain margin for the accuracy. Specifically, the accuracy threshold can be set to the sum of the true accuracy threshold and the accuracy margin.
[0061] The final model parameter obtained from the initial training is θ0, which is used to obtain the final neural network parameters in subsequent optimization.
[0062] S2. Establishing an energy consumption model for the operation of the neural network.
[0063] Specifically, the energy consumption model is composed of multiple energy consumption lookup tables, which record the energy consumption of the neural network during operation. The power consumption of digital memory computing is mainly composed of dynamic power and static power. Static power consumption is related to the leakage current of the storage unit. It also exists when the digital computing circuit keeps the data state unchanged. In digital memory computing, although the static power consumption is relatively small, it still needs to be considered in low-power application scenarios.
[0064] Dynamic power consumption is caused by the flipping of the storage cell state (i.e., the reading and writing operations of data), which is directly related to the flipping rate. Each flipping requires charging or discharging the nodes of the digital circuit, which involves the charging and discharging process of the capacitor, thereby consuming energy. Therefore, the higher the flipping rate, the more times the nodes of the digital circuit are charged and discharged, and the greater the dynamic power consumption.
[0065] Among them, in digital in-memory computing, "toggle" refers to the change of the data state in the digital computing circuit, that is, from 0 to 1 or from 1 to 0. The toggle rate refers to the number of times the data state changes in unit time, which is a key indicator to measure data activity.
[0066] In this embodiment, when establishing the energy consumption lookup table of the energy consumption model, on the one hand, the mapping of the convolutional layer in the neural network on the in-memory computing macro (CIM macro) is taken into account. Please refer to Figure 3 If the number of convolution output channels is Cout, the number of convolution input channels is Cin, and the convolution kernel size is K, then there are Cout convolution kernels of size K×K×Cin (number of convolution input channels), input weights and feature maps of size Hin×Win×Cin, where Hin and Win are the width and height of the input feature map, respectively, and the output is a feature map of size Hout×Wout×Cout, where Hout and Wout are the width and height of the output feature map, respectively.
[0067] During mapping, in this embodiment, an in-memory computing macro is divided into Cout banks with the same size and function. In order to simulate the sliding and multiplication and accumulation operations of the convolution kernel on the feature map, each bank stores a convolution kernel of size K×K×Cin and implements the input of the feature map. The in-memory computing is used to accelerate the multiplication and accumulation operations of the feature map and the convolution kernel.
[0068] On the other hand, it is necessary to calculate the energy consumed by the convolution on the digital memory computing macro hardware, and it is also necessary to consider the input model. In this embodiment, it is assumed that the digital memory computing macro input mode is the "most significant bit first, serial input" input mode. If the number of weight quantization bits of each input channel is N, then a library on the hardware mainly consists of a storage array composed of K×K×Cin×N basic storage units (bitcells) for multiplication and a multi-level adder tree (adder tree) composed of full adders that add K×K×Cin multiplication results, so as to realize the convolution operation (multiplication-accumulation operation) of a convolution kernel and a partial feature map of the same size (selected by the convolution kernel when the feature map slides).
[0069] Based on this, we start from the dynamic energy of the storage basic unit. The function of a storage basic unit is the multiplication of one bit of a weight and one bit of an activation value. Since all weights are stored in the storage basic unit array and will not change, the dynamic energy of the storage basic unit for multiplication is directly related to the flipping of the input activation value. The flipping of the activation value in the in-memory calculation comes from two aspects.
[0070] The first is the flipping of the activation value when it is input serially. Since the storage basic unit can only realize the multiplication of single-bit weight and activation value, and the in-memory calculation macro in this embodiment is "most significant bit first, serial input", for a neural network quantized into N bits, to realize the multiplication of an N-bit weight and an N-bit activation value, N storage basic units and N cycle inputs are required. Therefore, the flipping at this time comes from the flipping between each bit within a single activation value. For example, an activation value has 8 bits, which is "01010101", which requires 8 cycle inputs, and the flipping between "0" and "1" is 8 times; the second is the flipping generated when the convolution kernel moves on the feature map. For example, the lowest bit (LSB) of the number at a certain position in the feature map selected before the convolution kernel moves is "0", and the highest bit (MSB) of the corresponding number in the feature map selected after the movement is "1", then for the storage basic unit, the activation value is flipped once.
[0071] From the above two flipping situations, we can get the flipping situation of the storage basic unit array. Adding the energy look-up table of a single storage basic unit in Table 1, we can get the dynamic energy model of the storage basic unit array. The energy look-up table of a single storage basic unit mainly has four columns, namely: the activation value IN(t-1) at time t-1, the activation value IN(t) at time t, the weight W and the energy consumption of the storage basic unit bitcell_energy.
[0072] Table 1: Storage basic unit energy lookup table
[0073] IN(t-1) IN(t) W bitcell_energy 0 0 0 0 0 0 1 0 0 1 0 3.60E-15 0 1 1 3.00E-15 1 0 0 2.49E-15 1 0 1 4.15E-15 1 1 0 0 1 1 1 0
[0074] It should be noted that if the input mode changes, the corresponding dynamic energy model of the storage basic unit array must also be changed accordingly. For example, for an 8-bit input data "10010010", if the high-order bit is input first, it will flip from 1→0 3 times and 0→1 2 times. If the low-order bit is input first, it will flip from 0→1 3 times and 1→0 2 times. The energy consumption can be calculated using the same method.
[0075] After obtaining the dynamic energy model of the storage basic unit array, we can consider the dynamic energy of the addition tree, which is composed of full adders. Similarly, we can extract the energy lookup table of the full adder in Table 2, which includes the input ABCi(t-1) at time t-1, the input ABCi(t) at time t, and the full adder energy consumption FA energy. Then, according to the function of the full adder and the structure of the addition tree, we can get the dynamic energy model of the addition tree.
[0076] Table 2: Full adder energy lookup table
[0077]
[0078]
[0079] The storage basic unit array dynamic energy model and the addition tree dynamic energy model together constitute the energy consumption model.
[0080] S3. Iteratively optimize the parameters of the neural network according to the energy consumption model, and obtain and output the optimized parameters.
[0081] In order to reduce the power consumption of digital in-memory computing, various strategies can be adopted, such as optimizing the design of the storage array to reduce the energy consumption of each flip, using low-power storage technology, or reducing unnecessary data flips through algorithm optimization. In addition, power consumption can also be reduced by controlling the flip rate, such as by reducing the operating frequency or optimizing the data access pattern.
[0082] If it is possible to avoid combinations with high power consumption as much as possible by finding appropriate neural network weight parameters and mapping the weight parameters in memory without losing too much neural network accuracy, so that the overall power consumption tends to be the minimum, the neural network can work well and the overall power consumption can be reduced. How to find the neural network parameters with the lowest power consumption while meeting the accuracy requirements is the main technical problem to be solved by the present invention.
[0083] To this end, in this embodiment, the neural network parameters are searched by adding random perturbations and L1 regularization, so as to find out the neural network parameters with the lowest power consumption while meeting the accuracy requirements.
[0084] Specifically, first use the neural network with parameters θ0 to verify the accuracy in the validation set, and calculate the energy consumption of the validation set to obtain the initial average accuracy η0 and average energy consumption E0. Specifically, input the validation set into the neural network with parameters θ0, count the number of activation value flips of each layer, and then calculate the total energy consumption based on the corresponding weight parameters and the lookup table.
[0085] Then the initial parameters are iteratively optimized. In each iteration, a perturbation is made on the parameters of the current neural network. For example, in the first iteration, a perturbation is made on the basis of the initial weight value θ0 to generate a new set of values θ1. θ1 is used as the initialization value for training, and several gradient descent iterative trainings are performed to obtain the optimized weights and the corresponding accuracy.
[0086] In the validation set, check whether the network with the current weight parameters meets the accuracy requirements, that is, whether the average accuracy drops within T% compared with the original average accuracy, where T% is the accuracy drop threshold set by the user (or directly check whether the average accuracy is not lower than the true accuracy threshold). If the accuracy does not meet the requirements, adjust the regularization strength α, and re-perform several gradient descent iterations to obtain new weights and accuracy. If the accuracy requirements are still not met, repeat the above steps until the weight θ1 that meets the requirements is obtained.
[0087] After obtaining the weight θ1 that meets the accuracy requirement, calculate the average energy consumption E1 of this group of weights on the validation set and compare it with the initial energy consumption E0. If the energy consumption is reduced, record the group of weights θ1 and the corresponding accuracy and energy consumption values, and continue to generate random perturbations for the next search. If the energy consumption does not decrease, proceed directly to the next perturbation. After several perturbations and gradient descent optimization, the weight parameters that meet the accuracy requirements and have the lowest energy consumption are obtained. This group of data is used as the final result and written into the storage array of the computing chip in the digital memory.
[0088] Embodiment 2
[0089] See also Figure 4 Based on the above method, the present invention also provides a terminal, which includes a processor 10, a memory 20 and a display 30. Figure 4 Only some components of the terminal are shown, but it should be understood that it is not required to implement all of the components shown, and more or fewer components may be implemented instead.
[0090] In some embodiments, the memory 20 may be an internal storage unit of the terminal, such as a hard disk or memory of the terminal. In other embodiments, the memory 20 may also be an external storage device of the terminal, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), etc. equipped on the terminal. Further, the memory 20 may also include both an internal storage unit of the terminal and an external storage device. The memory 20 is used to store application software and various types of data installed on the terminal, such as the program code of the installation terminal. The memory 20 may also be used to temporarily store data that has been output or is to be output. In one embodiment, a neural parameter optimization program 40 for digital in-memory calculation is stored on the memory 20, and the neural parameter optimization program 40 for digital in-memory calculation can be executed by the processor 10, thereby realizing the terminal in the present application.
[0091] In some embodiments, the processor 10 may be a central processing unit (CPU), a microprocessor or other data processing chip, used to run the program code or process data stored in the memory 20, such as executing related programs of the neural parameter optimization method for digital in-memory calculations.
[0092] In some embodiments, the display 30 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch device, etc. The display 30 is used to display information on the terminal and to display a visual user interface. The terminals communicate with each other via a system bus.
[0093] In one embodiment, when the processor 10 executes a neural parameter optimization program 40 for digital in-memory computing in the memory 20, the steps of the neural parameter optimization method for digital in-memory computing as described above are implemented.
[0094] Embodiment 3
[0095] This embodiment provides a storage medium, wherein the readable storage medium stores a neural parameter optimization program for digital in-memory calculations, and when the neural parameter optimization program for digital in-memory calculations is executed by a processor, the steps of the neural parameter optimization method for digital in-memory calculations described above are implemented.
[0096] In summary, the present invention establishes an energy consumption model for in-memory computing of a neural network, then verifies the energy consumption of the neural network calculated on a verification set based on the energy consumption model, and optimizes the energy consumption of the neural network calculated on the verification set, thereby obtaining the neural network parameters with the lowest energy consumption, thereby reducing the power consumption of in-memory computing in digital technology and solving the problem of high power consumption of in-memory computing in digital technology.
[0097] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or terminal including the element.
[0098] Of course, those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing related hardware (such as a processor, a controller, etc.) through a computer program, and the program can be stored in a computer-readable storage medium, and the program can include the processes of the above-mentioned method embodiments when executed. The storage medium can be a memory, a disk, an optical disk, etc.
[0099] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.
Claims
1. A neural parameter optimization method for digital in-memory computing, characterized in that: The neural parameter optimization method for digital in-memory computing includes: Acquire a neural network, and train the neural network to obtain parameters of the neural network that meet target requirements; Establishing an energy consumption model for the operation of the neural network; Iteratively optimize the parameters of the neural network according to the energy consumption model, and obtain and output the optimized parameters.
2. A neural parameter optimization method for digital in-memory computing according to claim 1, characterized in that: The energy consumption model for the operation of the neural network is established, specifically comprising: Establish a dynamic energy model of storage basic unit array; Establishing the dynamic energy model of the additive tree; The storage basic unit array dynamic energy model and the addition tree dynamic energy model are used as the energy consumption model.
3. A neural parameter optimization method for digital in-memory computing according to claim 2, characterized in that: The step of establishing a dynamic energy model of a storage basic unit array specifically includes: Obtaining the energy consumption when the storage basic unit array is flipped, and establishing a storage basic unit energy lookup table; An input mode of a storage basic unit is acquired, and a dynamic energy model of the storage basic unit array is established according to the input mode and the storage basic unit energy lookup table.
4. The neural parameter optimization method for digital in-memory computing according to claim 2, characterized in that: The establishment of the addition tree dynamic energy model specifically includes: Obtain the energy consumption of the storage basic unit array when performing addition operations, and establish a full adder energy lookup table; The addition tree structure of the neural network is obtained, and the addition tree dynamic energy model is established according to the addition tree structure and the full adder energy lookup table.
5. The neural parameter optimization method for digital in-memory computing according to claim 1, characterized in that: The step of establishing an energy consumption model for the operation of the neural network further includes: Obtain a validation set, and calculate the average model energy consumption of the neural network on the validation set according to the energy consumption model; The iterative optimization of the parameters of the neural network according to the energy consumption model, each iteration, includes: Optimizing the parameters of the neural network to obtain intermediate parameters; Calculate the intermediate average energy consumption of the intermediate parameter on the verification set according to the energy consumption model; It is determined whether the intermediate average energy consumption is lower than the model average energy consumption; if the intermediate average energy consumption is lower than the model average energy consumption, the intermediate parameters and the intermediate average energy consumption are recorded.
6. The neural parameter optimization method for digital in-memory computing according to claim 5, characterized in that: The calculating the average energy consumption of the model of the neural network on the validation set according to the energy consumption model specifically includes: Running the neural network on the validation set, and recording the number of activation value flips of each layer; Calculating the average energy consumption of the model according to the activation value flipping times and the energy consumption model; The calculating the intermediate average energy consumption of the intermediate parameter on the verification set according to the energy consumption model specifically includes: Setting the parameters of the neural network to the intermediate parameters, running the neural network on the validation set, and recording the number of intermediate flips of the activation value of each layer; The intermediate average energy consumption is calculated according to the intermediate flipping times of the activation value and the energy consumption model.
7. The neural parameter optimization method for digital in-memory computing according to claim 5, characterized in that: The step of optimizing the parameters of the neural network to obtain intermediate parameters specifically includes: Performing a perturbation on the parameter and training the neural network multiple times to obtain the parameter to be verified; Calculate the average accuracy of the parameter to be verified on the verification set according to the verification set; If the average accuracy of the parameter to be verified on the verification set meets the verification condition, the parameter to be verified is used as the intermediate parameter; If the average accuracy of the parameter to be verified on the verification set does not meet the verification condition, the parameter to be verified is obtained again.
8. The neural parameter optimization method for digital in-memory computing according to claim 5, characterized in that: The obtaining and outputting of optimization parameters specifically includes: Retrieve all recorded intermediate average energy consumptions and obtain the lowest intermediate average energy consumption; The intermediate parameter corresponding to the lowest intermediate average energy consumption is used as the optimization parameter and outputted.
9. A terminal, characterized in that: The terminal includes: a memory, a processor, and a neural parameter optimization program for digital in-memory calculations stored in the memory and executable on the processor. When the neural parameter optimization program for digital in-memory calculations is executed by the processor, the terminal is controlled to implement the steps of a neural parameter optimization method for digital in-memory calculations as described in any one of claims 1 to 8.
10. A readable storage medium, characterized in that: The readable storage medium stores a neural parameter optimization program for digital in-memory calculations, and when the neural parameter optimization program for digital in-memory calculations is executed by a processor, the steps of a neural parameter optimization method for digital in-memory calculations as described in any one of claims 1-8 are implemented.