Data processing method and device

Abstract

The invention discloses a data processing method and device, and the method comprises the steps: obtaining a first data object and a second data object corresponding to each data processing channel, and enabling the data in the first data object and the second data object corresponding to the same data processing channel to be a corresponding to-be-processed data pair; determining valid data pairs respectively corresponding to each data processing channel from the to-be-processed data pairs; based on the total number of the effective data pairs of all the data processing channels, the effective data pairs are distributed among the available hardware processing channels in a balanced mode; and carrying out data processing on the obtained effective data pairs on each available hardware processing channel according to a parallel mode.

Description

Technical Field

[0001] The present application belongs to the field of artificial intelligence technology, and in particular, relates to a data processing method and device. Background Art

[0002] Neural Networks (NN) are complex network systems formed by a large number of simple processing units (called neurons) that are widely interconnected. At present, in data processing based on neural network models, there are problems such as low computing performance and data processing easily reaching system bottlenecks, thus restricting system performance. How to solve this problem has become a technical difficulty in this field. Summary of the invention

[0003] To this end, this application discloses the following technical solutions:

[0004] A data processing method, the method comprising:

[0005] Acquire the first data object and the second data object corresponding to each data processing channel respectively, and the data in the first data object and the second data object corresponding to the same data processing channel correspond to the corresponding data pair to be processed;

[0006] Determine the valid data pairs corresponding to the respective data processing channels from the data pairs to be processed;

[0007] Based on the total number of valid data pairs of all data processing channels, the valid data pairs are evenly distributed among the available hardware processing channels;

[0008] The resulting valid data pairs are data processed in parallel on each available hardware processing channel.

[0009] Optionally, determining valid data pairs corresponding to respective data processing channels from the to-be-processed data pairs includes:

[0010] Determine a pair of data to be processed consisting of data with consistent positions between a first data object and a second data object corresponding to each data processing channel;

[0011] A data pair that does not contain invalid data among the data pairs to be processed is determined as a valid data pair corresponding to the data processing channel.

[0012] Optionally, the step of evenly distributing the valid data pairs among the available hardware processing channels based on the total number of valid data pairs of all data processing channels includes:

[0013] According to the total number of valid data pairs of all data processing channels, the valid data pairs corresponding to each data processing channel are distributed among each available hardware processing channel across the data processing channels, so that the number of valid data pairs processed between each available hardware processing channel meets the balance condition.

[0014] Optionally, the step of evenly distributing the valid data pairs among the available hardware processing channels based on the total number of valid data pairs of all data processing channels includes:

[0015] Constructing a valid data pair set including valid data pairs corresponding to each data processing channel, and determining the total number of valid data pairs in the valid data pair set according to the number of valid data pairs corresponding to each data processing channel, to obtain the total number of valid data pairs;

[0016] Splitting the valid data pair set into a first number of multiple subsets according to the total number, so that the number of valid data pairs respectively contained in each subset meets a proximity condition; the first number is the number of channels of each available hardware processing channel;

[0017] The valid data pairs contained in different subsets are respectively allocated to different available hardware processing channels.

[0018] Optionally, the construction includes a valid data pair set of valid data pairs corresponding to each data processing channel, including:

[0019] A valid data pair sequence including valid data pairs corresponding to each data processing channel is constructed; wherein each valid data pair in the valid data pair sequence is stored sequentially and continuously.

[0020] Optionally, splitting the valid data pair set into a first number of multiple subsets according to the total number, and respectively allocating the valid data pairs included in different subsets to different available hardware processing channels includes:

[0021] Dividing the valid data pair sequence into the first number of multiple subsequences according to the total number of valid data pairs included; each subsequence includes a corresponding number of valid data pairs continuously stored in the valid data pair sequence;

[0022] The valid data pairs contained in different subsequences are respectively allocated to different available hardware processing channels.

[0023] Optionally, dividing the valid data pair sequence into the first number of subsequences according to the total number of valid data pairs included in the sequence, comprises:

[0024] Determine a second number and a first address of a storage location of a valid data pair in the valid data pair sequence; the second number is an upward rounded value of an average value obtained by averaging the total number according to the first number;

[0025] Starting from the target address, determine valid data pairs stored continuously, the number of which is not greater than the second number, as a subsequence of the valid data pair sequence, until all valid data pairs in the valid data pair sequence are divided into corresponding subsequences;

[0026] Among them, among the obtained subsequences, the number of valid data pairs contained in a subsequence is equal to or less than the second number, and the number of valid data pairs contained in each subsequence other than the one subsequence is equal to the second number; the target address is the first address or the starting address determined based on the first address for the subsequence to be divided.

[0027] Optionally, determining a starting address for a subsequence to be divided based on the first address includes:

[0028] The starting address of the subsequence to be divided is determined according to the first address, the second number and the corresponding order of the subsequence to be divided in each subsequence of the valid data pair sequence.

[0029] A data processing device, comprising:

[0030] An acquisition unit, used to acquire first data objects and second data objects corresponding to respective data processing channels, wherein the data in the first data object and the second data object corresponding to the same data processing channel correspond to corresponding data pairs to be processed;

[0031] A determination unit, used to determine valid data pairs corresponding to each data processing channel from the to-be-processed data pairs;

[0032] an allocating unit, configured to evenly allocate the valid data pairs among the available hardware processing channels based on the total number of valid data pairs of all data processing channels;

[0033] The data processing unit is used to perform data processing on the obtained valid data pairs on each available hardware processing channel in a parallel manner.

[0034] Optionally, the device further comprises:

[0035] a compression unit, configured to remove data other than valid data pairs from the to-be-processed data pairs formed by the first data object and the second data object respectively corresponding to each data processing channel according to the determination result of the determination unit, so as to obtain valid data pairs respectively corresponding to each data processing channel;

[0036] The storage unit is used to store the valid data pairs and the number of valid data pairs corresponding to each data processing channel, so that the allocation unit can acquire and allocate data.

[0037] Optionally, valid data pairs of all data processing channels in the storage unit are stored continuously.

[0038] It can be seen from the above scheme that the present application discloses a data processing method and device, wherein the data processing method includes: obtaining the first data object and the second data object corresponding to each data processing channel respectively, and the data in the first data object and the second data object corresponding to the same data processing channel correspond to the corresponding data pairs to be processed; determining the valid data pairs corresponding to each data processing channel respectively from the data pairs to be processed; based on the total number of valid data pairs of all data processing channels, evenly distributing the valid data pairs among each available hardware processing channel; and performing data processing on the obtained valid data pairs on each available hardware processing channel in a parallel manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0040] Figure 1 This is an example of the comparison of data processing volume before and after the input channel jump 0 processing provided by this application;

[0041] Figure 2 It is a flow chart of the data processing method provided by this application;

[0042] Figure 3 It is a schematic diagram of the convolution kernel weight matrix corresponding to the four input channels provided in this application;

[0043] Figure 4 It is a flowchart for realizing balanced distribution of valid data pairs corresponding to each data processing channel among each available hardware processing channel provided by the present application;

[0044] Figure 5 It is a schematic diagram of the sequence of valid data pairs provided by this application;

[0045] Figure 6 is a hardware system structure diagram in an application example provided by this application;

[0046] Figure 7 It is a schematic diagram of two aspects of data information obtained after data compression provided by this application;

[0047] Figure 8 It is a schematic diagram of the number of valid data pairs corresponding to the six input channels provided in this application;

[0048] Fig. 9 This application provides a traditional method for Figure 8 Schematic diagram of performing two rounds of allocation and processing on valid data pairs corresponding to the six input channels;

[0049] Fig.10 This application provides Figure 8 Schematic diagram of balanced distribution of valid data pairs corresponding to the six input channels;

[0050] Fig.11 It is a structural diagram of the data processing device provided by the present application;

[0051] Fig.12 It is a structural diagram of the electronic device provided in this application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] Mainstream commercial hardware architectures, such as mainstream NPU (neural-netWork process units, neural network processor) hardware architectures, have multiple hardware processing channels that can be used to perform parallel calculations on multiple network channels (such as multiple input channels) of the network layer of a neural network model.

[0054] In the model training of neural networks, the convolution kernel weights are often quantized and pruned, resulting in a large number of zero values ​​in the weights. This phenomenon of a large number of zero values ​​in the network is called sparsification. The applicant has found that the main operations in neural networks include multiplication and addition operations, and zero values ​​(such as zero-valued weights and / or zero-valued feature values ​​in the input feature map) do not contribute to the final calculation result. Accordingly, zero values ​​can be used as invalid data and non-zero values ​​can be used as valid data. In traditional calculation methods, zero values ​​are also involved in the calculation, but because zero values ​​do not contribute to the calculation results, the operation on zero values ​​is an invalid operation. If the operation on zero values ​​can be skipped so that the data processing volume of each hardware processing channel is the corresponding valid data volume, the data processing volume of the hardware processing channel can be reduced, the efficiency can be improved, and the transmission and storage bandwidth can be reduced. Figure 1In the example, if only valid data pairs formed by non-zero weights of the convolution kernel and non-zero eigenvalues ​​in the input feature map are processed, the amount of data processed will be reduced from the original 9 to 2.

[0055] However, the applicant further discovered that when each hardware processing channel in the hardware architecture performs parallel calculations on multiple network channels of the neural network model, the next batch of data can only be processed after the current batch of data processing of all the hardware processing channels participating in the parallel calculations is completed. In an unstructured weight sparse network, the sparse random distribution of each network channel, such as the input channel, may result in different amounts of valid data (such as non-zero weights) in different network channels, which can easily lead to different data loading and calculation amounts of each parallel hardware processing channel when multiple hardware processing channels are used to parallelly process the data calculation tasks of the network layer network channels of the model. The data loading and calculation amounts of some hardware processing channels are higher or much higher than other channels, becoming the critical path of the hardware system, which will correspondingly restrict system performance and reduce system parallel efficiency.

[0056] Based on this, the present application provides a data processing method and device for solving the above technical problems, which can be applied to but not limited to electronic devices such as personal computers or servers. And the data processing method provided in this application can be applied to but not limited to natural language processing, image processing, video processing, speech recognition, industrial detection (such as equipment defect detection) and other fields. The embodiment of this application mainly takes the data processing of a neural network model (such as a deep neural network model) as an example to illustrate the solution.

[0057] See also Figure 2 , shows a flow chart of the data processing method of the present application, the method at least comprising:

[0058] Step 201: Acquire first data objects and second data objects corresponding to respective data processing channels, and the data in the first data object and the second data object corresponding to the same data processing channel correspond to corresponding data pairs to be processed.

[0059] Each data processing channel can be, but is not limited to, each network channel of the network layer in the neural network model, such as each input channel. Taking the input channel as an example, for image processing based on the neural network model, each data processing channel can specifically be, but is not limited to, the R, G, B three primary color input channels of each convolutional layer of the model, as well as the texture input channel, the semantic input channel, etc.

[0060] Optionally, the first data object and the second data object corresponding to the data processing channel may be the convolution kernel weight matrix (referred to as "weight matrix") and the input feature map corresponding to the input channel of the network layer in the neural network model, respectively. When applying this application, the types of the first data object and the second data object corresponding to the data processing channel may be determined according to the actual application scenario.

[0061] Among them, the input feature map can be but is not limited to the data to be processed corresponding to various types of information such as images and voices. Specifically, the input feature map can be subjected to one-dimensional convolution, two-dimensional convolution or three-dimensional convolution without limitation, depending on actual needs. For example, for a one-dimensional convolution kernel of size 1*3, a one-dimensional convolution can be performed on the input feature map based on a 1*3 convolution kernel weight matrix. For a two-dimensional convolution kernel of size 3*3, a two-dimensional convolution can be performed on the input feature map based on a 3*3 convolution kernel weight matrix.

[0062] The network layer in the neural network model can be, but is not limited to, a convolutional layer or a fully connected layer in the model network.

[0063] For data processing of neural network models, we can first obtain the weight matrix and input feature map corresponding to each input channel in the current network layer of the model. The data in the weight matrix and input feature map on the same input channel correspond to the corresponding data pairs to be processed according to their positions to participate in subsequent data operations on each input channel.

[0064] Step 202: Determine valid data pairs corresponding to respective data processing channels from the to-be-processed data pairs.

[0065] Typically, each data object contains multiple data to be processed, including valid data, and may also contain non-valid data (invalid data). Valid data in a data object refers to data contained in the data object that contributes to the data processing of the data object, while data contained in the data object that does not contribute to the data processing can be regarded as non-valid data or invalid data of the data object.

[0066] The valid data pair corresponding to the data processing channel specifically refers to a valid data pair in the to-be-processed data pair formed by the first data object and the second data object corresponding to the data processing channel.

[0067] For the case where the data processing channel is the input channel of the network layer of the neural network model, the first data object and the second data object of the data processing channel are the weight matrix and the input feature map of the input channel respectively. Since the value of 0 has no contribution value to the model operation, the non-zero weights / non-zero eigenvalues ​​in the weight matrix / input feature map can be regarded as valid data, while the zero weights and / or the zero eigenvalues ​​can be regarded as invalid data.

[0068] Correspondingly, the non-zero value data in the weight matrix / input feature map corresponding to each input channel can be determined, and based on the non-zero value data, the valid data pair in the data pair to be processed formed by the weight matrix corresponding to each input channel and the input feature map is determined as the valid data pair corresponding to each input channel.

[0069] Step 203: Based on the total number of valid data pairs of all data processing channels, the valid data pairs are evenly distributed among the available hardware processing channels.

[0070] The available hardware processing channel is a hardware computing channel that is not currently occupied and can be scheduled to perform the required operations on valid data pairs, such as a computing channel based on an operator and a register. Each channel can include the required number of operators and registers, and can also include other required hardware. Furthermore, for data processing of a neural network model, the available hardware processing channel can be the core hardware unit Tensor core corresponding to the NPU.

[0071] In the known technology, when the data processing channel is processed by each available hardware processing channel of the hardware architecture, there is a mapping relationship between the data processing channel and each available hardware processing channel. Taking the data processing of the neural network model as an example, the input channels of the model network layer are mapped to the available hardware processing channels in a fixed order in sequence, so that there is a certain mapping relationship between the input channel and the available hardware processing channels. The data pairs on the overall input channel are used as the minimum allocation unit, and the data pairs on different input channels are respectively allocated to different available hardware processing channels, wherein the data pairs on the same input channel are allocated to the same available hardware processing channel.

[0072] In this implementation, when invalid data (such as 0 values) are skipped, the random sparse characteristics of the data on the network layer input channel can easily lead to large differences in the amount of data processed by different available hardware processing channels. For example, assuming there are four input channels, the corresponding convolution kernel weight matrices are as follows: Figure 3 As shown, and assuming that the numbers of valid data pairs corresponding to the four input channels are 4, 7, 2, and 3 respectively, and there are four available hardware processing channels, then when the known technology is used to allocate valid data pairs to each available hardware processing channel, the four available hardware processing channels obtain 4, 7, 2, and 3 valid data pairs respectively. During parallel processing, the critical path length of the four available hardware processing channels is 7, and the amount of data processed by each available hardware processing channel varies greatly.

[0073] To overcome the above problems, the embodiment of the present application proposes a distribution method that evenly distributes the valid data pairs among the available hardware processing channels based on the total number of valid data pairs of all data processing channels. This distribution method supports the distribution of valid data pairs across data processing channels, thereby breaking the concept of data processing channels and decoupling the mapping relationship between data processing channels and available hardware processing channels, so as to minimize the critical path length in the parallel processing of each available hardware processing channel.

[0074] For neural network models, the concept of network channels (such as input channels) is broken accordingly, and the mapping relationship between network channels and available hardware processing channels is decoupled. All valid data pairs on all network channels are equally divided and allocated as a whole. There is no need to move data between different network channels separately, and there is no need to map the relationship between network channels and available hardware processing channels.

[0075] Under the allocation method of the present application, this step can specifically first determine the number of valid data pairs corresponding to each data processing channel, and determine the total number of valid data pairs of all data processing channels based on the number of valid data pairs corresponding to each data processing channel. On this basis, based on the total number of valid data pairs of all data processing channels, the valid data pairs corresponding to each data processing channel are allocated across data processing channels among the available hardware processing channels. Taking the data processing channel as the input channel of the network layer of the neural network model as an example, the valid data pairs corresponding to each input channel can be allocated across input channels among the available hardware processing channels based on the total number of valid data pairs corresponding to each input channel. After the allocation is completed, the number of valid data pairs processed between the available hardware processing channels meets the equilibrium condition.

[0076] The applicant found that when using the hardware architecture to process the data on each input channel of the neural network model (the data pairs to be processed formed by the convolution kernel weight matrix and the input feature map), the operation performed by each hardware processing channel is a multiplication-accumulation operation (multiplying the two data contained in the same data pair, and accumulating the multiplication results corresponding to different data pairs). At the same time, the operation results between the parallel available hardware processing channels are also accumulated, and the result of the addition operation is independent of the calculation order. After decoupling the mapping relationship between the input channel and other network channels and the available hardware processing channels, and based on the balanced allocation rule of the present application, the valid data pairs corresponding to each input channel are respectively allocated between each available hardware processing channel across the input channels, it does not affect the correctness of the hardware architecture for the operation results of the neural network model.

[0077] It is precisely based on the characteristic that the addition result is independent of the calculation order that the valid data pair distribution method across input channels (data processing channels) of the present application is proposed, so that there is no need to distinguish between input channels and other data processing channels to distribute the valid data pairs on each channel to the available hardware processing channels. That is, all valid data pairs corresponding to each input channel and other data processing channels are directly regarded as a unified whole, and all valid data pairs are evenly distributed across data processing channels to each available hardware processing channel according to the total number of valid data pairs of all data processing channels.

[0078] After the allocation is completed, the number of valid data pairs processed between the available hardware processing channels meets the balance condition, which can be but is not limited to any of the following situations:

[0079] a) The number of valid data pairs processed by each available hardware processing channel is the same;

[0080] b) The number of valid data pairs processed by each available hardware processing channel is different, but the absolute value of the difference in the number of valid data pairs processed by different available hardware processing channels is less than a set threshold;

[0081] c) After data allocation is completed, the critical path length corresponding to each available hardware processing channel is reduced compared to the traditional allocation method (i.e., valid data pairs on the same input channel are allocated to the same available hardware processing channel).

[0082] Step 204: Process the obtained valid data pairs on each available hardware processing channel in parallel.

[0083] After the valid data pairs corresponding to each data processing channel are evenly distributed among each available hardware processing channel based on the total number of valid data pairs of all data processing channels, the valid data pairs obtained are processed in parallel on each available hardware processing channel to improve the overall processing performance of the system. Furthermore, the available hardware processing channel can also perform on-demand processing on the data processing results corresponding to each valid data pair.

[0084] To summarize, the method of the embodiment of the present application, after obtaining the first data object and the second data object corresponding to each data processing channel respectively (the data in the first data object and the second data object corresponding to the same data processing channel correspond to the corresponding data pairs to be processed), determines the valid data pairs corresponding to each data processing channel respectively from the data pairs to be processed, and based on the total number of valid data pairs of all data processing channels, evenly distributes the valid data pairs among the available hardware processing channels, and then processes the obtained valid data pairs on each available hardware processing channel in parallel, which can effectively avoid the processing of invalid data pairs on each data processing channel, thereby reducing the data processing amount of the available hardware processing channels, improving the processing efficiency, and reducing the transmission and storage bandwidth.

[0085] At the same time, by distributing valid data pairs across data processing channels based on the total number of valid data pairs of all data processing channels, the number of valid data pairs processed by each available hardware processing channel is balanced, which can reduce the critical path length in the parallel processing of each available hardware processing channel, thereby reducing the constraints on system performance and further improving the system processing performance.

[0086] The first data object and the second data object corresponding to the data processing channel can be regarded as a data object pair corresponding to the data processing channel, and different data processing channels correspond to different data object pairs, and the to-be-processed data of different data objects in the same data object pair correspond to corresponding to the to-be-processed data pairs by position. For example, in the "weight matrix-input feature map" object pair corresponding to the input channel of the network layer of the neural network model, the weight and the feature value correspond to the corresponding to-be-processed data pair by position.

[0087] In an optional embodiment, when determining the valid data pairs corresponding to each data processing channel, the valid data in the first data object contained in the data object pair corresponding to each data processing channel can be determined, and the to-be-processed data corresponding to the valid data in the second data object contained in the data object pair to which it belongs can be determined, and the data pair formed by the determined to-be-processed data and the valid data in the first data object is used as the valid data pair of the data processing channel.

[0088] Optionally, it is also possible to determine the valid data in the second data object contained in the data object pair corresponding to each data processing channel, and determine the data to be processed corresponding to the valid data in the first data object contained in the corresponding data object pair, and use the data pair formed by the determined data to be processed and the valid data in the second data object as the valid data pair of the data processing channel.

[0089] However, it is not limited to the above-mentioned situation. In other implementations, the data pairs to be processed, which are composed of data with consistent positions between different data objects included in the data object pair corresponding to each data processing channel, can be first determined, and then the data pairs that do not contain invalid data in the data pairs to be processed corresponding to each data object pair are determined as the valid data pairs corresponding to each data processing channel. That is, the data pairs to be processed that do not have any invalid data in the data pairs to be processed included in the data object pair corresponding to each data processing channel are directly screened out as the valid data pairs for each data processing channel.

[0090] Alternatively, it is also possible to first use a data object in the data object pair corresponding to each data processing channel as a screening dimension to determine the valid data in the data object, and determine the data to be processed that is consistent with the position of the valid data from the other data object in the data object pair to which the data object belongs, to form a data pair with the valid data, and then further use the other data object as a screening dimension to screen out the data pair corresponding to the valid data in the other data object from the formed data pair as the valid data pair of the data object pair, that is, the valid data pair corresponding to the data processing channel to which the data object pair belongs.

[0091] For the application scenarios of deep learning networks, zero-valued weights and zero-valued eigenvalues ​​have no contribution to model operations. Accordingly, the third implementation method mentioned above can be preferably adopted to directly select the data pairs formed by non-zero weights and non-zero eigenvalues ​​with consistent positions from the various data pairs contained in the "convolution kernel weight matrix-input feature map" data object pair corresponding to the model network channel (such as the input channel) as the valid data pairs of the network channel.

[0092] Alternatively, first use a data object in the "convolution kernel weight matrix-input feature map" as the screening dimension, such as using weight as the screening dimension, first determine the non-zero weight from the convolution kernel weight matrix corresponding to the model network channel, and determine the eigenvalue consistent with the non-zero weight position from the input feature map of the network channel to form a data pair with the non-zero weight. For the formed data pairs, there may be a situation where the weight is valid but the eigenvalue is invalid (0 eigenvalue). Therefore, after obtaining the data pairs corresponding to each non-zero weight, the eigenvalue can be further used as the screening dimension to screen out the data pairs corresponding to the non-zero eigenvalues ​​from each data pair as the valid data pairs of the model network channel, so as to further compress the number of valid data pairs.

[0093] When applying the present application, software can be used to perform the above-mentioned processing to determine the valid data pairs in the data pairs to be processed formed by the first data object and the second data object corresponding to each data processing channel, so as to compress and trim at least part of the invalid data pairs corresponding to each data processing channel that do not contribute to the data processing results, thereby improving the system processing performance.

[0094] In an alternative embodiment, see Figure 4 , step 203 in the data processing method of the present application can be further implemented as follows:

[0095] Step 401, construct a valid data pair set including valid data pairs corresponding to each data processing channel, determine the total number of valid data pairs in the valid data pair set according to the number of valid data pairs corresponding to each data processing channel, and obtain the total number of valid data pairs of all data processing channels.

[0096] Optionally, the constructed valid data pair set may be a valid data pair sequence, and accordingly a valid data pair sequence including valid data pairs corresponding to each data processing channel may be constructed.

[0097] by Figure 3 As an example, the convolution kernel weight matrices corresponding to the four input channels in the figure are assumed to have 4, 7, 2, and 3 valid data pairs, respectively. Then, the following can be constructed: Figure 5 The valid data pair sequence shown is:

[0098] {p00, p02, p04, p07, p11, p12, p13, p14, p15, p17, p18, p21, p23, p30, p34, p38}.

[0099] Each element in the sequence represents a valid data pair. For simplicity, directly in the sequence, Figure 3 The valid data pair corresponding to each valid weight in the convolution kernel weight matrix shown is represented by the character corresponding to the weight, such as the element p00 in the sequence Figure 3 The valid data pairs corresponding to the weight p00 in the first convolution kernel weight matrix in . The sequence contains a total of (4+7+2+3)=16 valid data pairs. The valid data pairs corresponding to the four convolution kernel weight matrices are organized in sequence. Among them, the 4 elements corresponding to positions 1-4 in the sequence are Figure 3 The valid data pairs corresponding to the first convolution kernel weight matrix in , the 7 elements corresponding to positions 5-11, the 2 elements corresponding to positions 12-13, and the 3 elements corresponding to positions 14-16 are the valid data pairs corresponding to the second, third, and fourth convolution kernel weight matrices, respectively.

[0100] Optionally, each valid data pair in the valid data pair sequence is stored sequentially and continuously, so as to facilitate the subsequent subsequence splitting of the valid data pair sequence and the reading of the valid data pairs, thereby improving the efficiency of the subsequence splitting and the reading of the valid data pairs.

[0101] After constructing the valid data pair set, the total number of valid data pairs in the valid data pair set is further determined, such as the total number of valid data pairs contained in the valid data pair sequence. This total number is the total number of valid data pairs in all data processing channels, so that the total number of valid data pairs can be used as the basis for subsequent allocation of valid data pairs across data processing channels to each available hardware processing channel.

[0102] Step 402: split the valid data pair set into a first number of multiple subsets according to the total number, so that the number of valid data pairs contained in each subset satisfies a proximity condition.

[0103] The proximity condition may be, but is not limited to, that each subset contains the same number of valid data pairs, or each subset contains a different number of valid data pairs but the absolute value of the difference in the number of valid data pairs is less than a set threshold.

[0104] The first number is the channel number of each available hardware processing channel.

[0105] Preferably, the embodiment of the present application uses the total number of valid data pairs in the valid data pair set and the first number as the basis, and adopts an even division method to split the valid data pair set into a first number of multiple subsets. In the case where the valid data pair set is a valid data pair sequence, the valid data pair sequence is evenly divided into a first number of multiple subsequences according to the total number of valid data pairs included; and preferably, each subsequence includes a corresponding number of valid data pairs stored continuously in the valid data pair sequence.

[0106] The valid data pair sequence is divided into a first number of subsequences according to the total number of valid data pairs included, which can be further implemented as follows:

[0107] 11) Determine the first address of the storage location of the valid data pair in the second quantity and valid data pair sequence.

[0108] Optionally, the second number is: an upward rounded value of an average value obtained by averaging the total number of valid data pairs in the valid data pair sequence according to the first number. However, the present invention is not limited thereto. For example, the second number may also be: a downward rounded value of an average value obtained by averaging the total number of valid data pairs in the valid data pair sequence according to the first number.

[0109] 12) Starting from the target address, determine the valid data pairs stored continuously, whose number is not greater than the second number, as a subsequence of the valid data pair sequence, until all the valid data pairs in the valid data pair sequence are divided into corresponding subsequences.

[0110] Among them, among the obtained subsequences, the number of valid data pairs contained in a subsequence is equal to or less than the second number, and the number of valid data pairs contained in each subsequence other than the one subsequence is equal to the second number; the target address is the first address or the starting address determined based on the first address for the subsequence to be divided.

[0111] Optionally, the one subsequence is the last subsequence of the valid data pair sequence, that is, any other subsequences except the last subsequence respectively contain the second number of valid data pairs, and the number of valid data pairs contained in the last subsequence depends on actual conditions and is equal to or less than the second number. However, it is not limited to this. In actual applications, the one subsequence may also be any other subsequence except the last subsequence.

[0112] When determining the starting address for the subsequence to be divided based on the first address, the starting address of the subsequence to be divided can be determined specifically according to the first address, the second number and the corresponding order of the subsequence to be divided in each subsequence of the valid data pair sequence.

[0113] The following provides an optional implementation method for dividing the valid data pair sequence into subsequences for the case where the one subsequence is the last subsequence of the valid data pair sequence:

[0114] First, the starting address of the i-th subsequence in the valid data pair sequence is calculated using the following formula:

[0115] The first address of the sequence storage location of the valid data pair + (the second number * (i-1));

[0116] Wherein, 1≤i≤n, i is an integer, and n represents the number of subsequences, that is, the first number.

[0117] Afterwards, starting from the starting address of the ith subsequence, a second number of consecutively stored valid data pairs is determined and divided into the ith subsequence of the valid data pair sequence, until the number of valid data pairs remaining undivided in the valid data pair sequence is equal to or less than the second number, and the remaining consecutively stored valid data pairs are used as the last subsequence of the valid data pair sequence.

[0118] In one embodiment, a serial method may be used, starting from the head of the valid data pair sequence (it may also be from the tail, without limitation), and the starting address of each subsequence of the valid data pair sequence is calculated in sequence, so that each subsequence of the valid data pair sequence is divided in sequence.

[0119] In other implementations, a parallel approach may be used to calculate the starting addresses of each subsequence of the valid data pair sequence in parallel based on a corresponding calculation formula, such as the above calculation formula, so that each subsequence of the valid data pair sequence is obtained by parallel division.

[0120] Step 403: distribute the valid data pairs contained in different subsets to different available hardware processing channels respectively.

[0121] Specifically, valid data pairs contained in different subsequences can be allocated one-to-one to different available hardware processing channels, with a single subsequence as the minimum allocation unit.

[0122] The valid data pairs contained in different subsequences are allocated one-to-one to different available hardware processing channels with a single subsequence as the minimum allocation unit, so that each available hardware processing channel can evenly share and process all valid data pairs corresponding to each data processing channel across the data processing channels, thereby reducing the critical path length in the parallel processing of each available hardware processing channel, reducing the constraints on system performance, and improving the overall processing performance of the system.

[0123] It should be noted that when allocating valid data pairs, it is not inevitable that they cross data processing channels, but it can occur. By treating all valid data pairs on the data processing channels as a whole, dividing them equally, and evenly allocating them among the available hardware processing channels based on the division results, the effect of reducing the critical path length in the parallel processing of the available hardware processing channels is achieved. The allocation process is not limited by the data processing channels, and whether the valid data pairs actually cross the data processing channels after allocation depends on the actual situation.

[0124] In an optional embodiment, the processing method of the valid data pairs allocated to the available hardware processing channels and / or the processing method of the data processing results corresponding to each valid data pair can be determined according to business requirements.

[0125] Optionally, the determined processing method may include at least one of multiplication processing and addition processing.

[0126] Taking the data processing of the neural network model as an example, the corresponding valid data pairs formed and allocated based on the convolution kernel weight matrix and the input feature map can be multiplied and accumulated on the available hardware processing channel. Specifically, the weights and eigenvalues ​​in each valid data pair are first multiplied, and then the multiplication results corresponding to each valid data pair are accumulated. For example, for two valid "weight-eigenvalue" data pairs Aa and Ff, after performing multiplication and accumulation operations on them, A*a+F*f can be obtained.

[0127] For the application scenarios of deep learning networks, after obtaining the calculation results corresponding to each available hardware processing channel, that is, the multiplication and accumulation operation results, the calculation results of each available hardware processing channel can be further accumulated to generate an output data.

[0128] An application example of the present application method is provided below.

[0129] This example provides a process for processing the data to be processed on the input channel of the network layer of the neural network model. The hardware system of the main device (such as a personal computer or server) executing the method of the present application consists of five modules, see Figure 6 The hardware system structure diagram shown in the figure includes valid data pair generation module, data compression module, storage module, channel data balance control module, and hardware channel calculation module. The detailed description of each module is as follows:

[0130] (I) Valid data pair generation module

[0131] It is used to screen the "weight-eigenvalue" data pairs formed by the convolution kernel weight matrix on the input channel and the input feature map, and determine the valid data pairs whose weights and eigenvalues ​​are both non-zero values.

[0132] (II) Data Compression Module

[0133] It is used to compress the convolution kernel weight matrix and input feature map corresponding to the input channel based on the determination result of the valid data pair generation module, and store the compressed valid data pairs into the storage module.

[0134] The data compression specifically refers to eliminating invalid data from the convolution kernel weight matrix corresponding to the input channel and the data provided by the input feature map, retaining only valid data to form valid data pairs of "non-0 weight-non-0 eigenvalue", and storing the valid data pairs corresponding to each input channel in sequence to form a valid data pair sequence, which is convenient for subsequent splitting and reading of the valid data pair sequence.

[0135] The compressed data consists of two information sequences: a valid data pair sequence and a channel data volume sequence of the input channel. The channel data volume sequence contains the number of valid data pairs on the corresponding input channel.

[0136] For example, for Figure 5 For examples, see Figure 7 , the information obtained after compression includes:

[0137] Valid data pair sequence: {p00, p02, p04, p07, p11, p12, p13, p14, p15, p17, p18, p21, p23, p30, p34, p38}

[0138] Channel data volume sequence: {4, 7, 2, 3}.

[0139] (III) Storage Module

[0140] It is used to store the compressed data information, such as storing the valid data pair sequence and the channel data quantity sequence. Among them, each valid data pair contained in the valid data pair sequence is stored in sequence in the storage module.

[0141] That is to say, for the valid data pairs obtained after compression of each input channel, there is no need to record and store the corresponding position information of each valid data pair within the corresponding input channel. It is only necessary to record and store the channel data volume of each input channel (the number of valid data pairs corresponding to the input channel). At the same time, by organizing the valid data pairs corresponding to each input channel in sequence to form a corresponding valid data pair sequence, not only can the valid data pairs corresponding to each input channel be directly determined from the valid data pair sequence based on the recorded channel data volume, but the recorded channel data volume can also be used as an information basis for dividing the valid data pair sequence into subsequences when the channel data volume is balanced by the subsequent available hardware processing, thereby reducing the data storage volume and the calculation amount of the subsequent process.

[0142] (IV) Channel data balance control module

[0143] It is used to obtain the valid data pair sequence and the channel data volume sequence stored in the storage module, and divide the valid data pair sequence into subsequences according to the channel data volume sequence.

[0144] In the mainstream NPU hardware architecture, data allocation of available hardware processing channels is to allocate data pairs on network channels such as multiple input channels to multiple parallel available hardware processing channels based on the mapping relationship between network channels and available hardware processing channels. After the data processing of all available hardware processing channels participating in the parallel processing is completed, the next batch of data will be processed. Due to unstructured sparsity, the number of valid data pairs on different network channels is easily different, which correspondingly leads to different numbers of valid data pairs allocated on different available hardware processing channels, making the hardware processing channel with the largest number of valid data pairs become the system bottleneck.

[0145] like Figure 8 As shown, assuming that the model network layer has 6 input channels, the number of valid data pairs corresponding to each input channel are: 4, 7, 2, 3, 2, 1, and there are 4 available hardware processing channels. The mainstream hardware needs to perform two rounds of processing. See Fig. 9 , the first round processes the first 4 input channels, and the second round processes the last 2 input channels. In the case of jump 0, the longest path of the first round is 7, and the longest path of the second round is 2. When the 7 data (7 valid data pairs) of the longest path of the first round are processed, the second round is processed. The sum of the longest paths of the two rounds, that is, the total critical path length of the two rounds, is: 7+2=9.

[0146] This example treats the valid data pair sequence formed after compression as a unified whole, does not distinguish between input channels, decouples the mapping relationship between input channels and available hardware processing channels, directly splits the valid data pair sequence in an equal manner according to the number of available hardware processing channels, and allocates different subsequences obtained by the split to different available hardware processing channels, thereby reducing the critical path length of the system.

[0147] The specific steps are as follows:

[0148] 21) Read the number of valid data pairs of each input channel from the storage module, and add them up to obtain the total number of valid data pairs of each input channel;

[0149] 22) Calculate the total number of valid data pairs (sum) relative to the average number of available hardware processing channels according to the following formula:

[0150] Average = [sum / number of available hardware processing channels];

[0151] 23) Divide the valid data pair sequence according to the average to obtain subsequences, and assign different subsequences to different available hardware processing channels.

[0152] Each valid data in the valid data pair sequence is stored continuously. Based on this, this example first determines the starting address of each subsequence according to the first address of the valid data pair sequence and the above average. The starting address of the i-th subsequence in the valid data pair sequence is:

[0153] The first address of the sequence storage location of the valid data pair + (average number * (i-1));

[0154] Where 1≤i≤n, i is an integer, and n represents the number of available hardware processing channels.

[0155] Afterwards, starting from the determined starting address, the average number of continuously stored valid data pairs is obtained from the valid data pair sequence as a subsequence until the valid data pair sequence is divided, wherein the number of valid data pairs in the last subsequence may be less than the average, depending on the total number of valid data pairs actually contained in the valid data pair sequence.

[0156] like Fig.10 As shown, for Figure 8 For example, the total number of valid data pairs of the 6 input channels is: 4+7+2+3+2+1=19. The valid data pairs of the 6 input channels are divided into 4 continuous data and respectively allocated to the 4 available hardware processing channels. After the allocation is completed, the number of valid data pairs of the first three available hardware processing channels is 5, and the number of valid data pairs of the last available hardware processing channel is 4. Each available hardware processing channel corresponds to a maximum of 5 consecutive valid data pairs, and each available hardware processing channel only needs to process one round of operations. The critical path of the system is reduced from 9 in the mainstream architecture to 5. After obtaining the calculation results corresponding to each available hardware processing channel, such as the results of multiplication and accumulation operations, the calculation results of each available hardware processing channel can be further accumulated to generate an output data to form a corresponding output feature map based on the data output (i.e. Fig.10 OFM in ).

[0157] Among them, after the allocation is completed, the allocation result may be across input channels, such as Fig.10 The allocation result corresponding to the first available hardware processing channel in ; there may also be no cross-input channels, such as Fig.10 The allocation result corresponding to the second available hardware processing channel in .

[0158] (V) Hardware channel calculation module

[0159] Used to provide hardware computing resources for data operations of the model network.

[0160] The hardware channel calculation module includes multiple hardware processing channels. During the data operation of the model network, the multiple hardware processing channels participating in the parallel calculation respectively load their assigned valid data pairs and perform the required processing on the loaded valid data pairs.

[0161] Based on the present application, it is only necessary to perform a simple division of the valid data pair sequence of each input channel to achieve the global overall optimal allocation of the valid data pairs of each input channel in the hardware architecture, which can significantly improve the system performance without adjusting the hardware architecture and the hardware operation is simple.

[0162] Corresponding to the above data processing method, the present application also provides a data processing device, see Fig.11 The data processing device at least comprises:

[0163] An acquiring unit 1101 is used to acquire first data objects and second data objects corresponding to respective data processing channels, wherein the data in the first data object and the second data object corresponding to the same data processing channel correspond to corresponding data pairs to be processed;

[0164] A determining unit 1102 is used to determine valid data pairs corresponding to each data processing channel from the to-be-processed data pairs;

[0165] An allocating unit 1103 is used to determine valid data pairs corresponding to each data processing channel from the to-be-processed data pairs;

[0166] The data processing unit 1104 is used to perform data processing on the obtained valid data pairs on each available hardware processing channel in a parallel manner.

[0167] Optional, for the above provided Figure 6 The hardware system structure example shown in the figure can specifically integrate the functions of the acquisition unit 1101 and the determination unit 1102 into the effective data pair generation module. The effective data pair generation module obtains the convolution kernel weight matrix and the input feature map corresponding to each input channel of the model network through the integrated acquisition unit 1101 function, and screens the "weight-eigenvalue" data pairs formed by the convolution kernel weight matrix and the input feature map on each input channel through the integrated determination unit 1102 function, determines the effective data pairs whose weights and eigenvalues ​​are non-zero values, and stores the generated effective data pairs in Figure 6 The allocation unit 1103 can be implemented as Figure 6 The channel data balance control module in the embodiment is used to evenly distribute the valid data pairs corresponding to each input channel, which can be implemented in software form. The data processing unit 1104 can be implemented as Figure 6The hardware channel computing module in is mainly a hardware structure, including multiple available hardware processing passes, and can correspond to the relevant soft processing required for hardware collaboration, and is used to load the valid data pairs allocated by the allocation unit 1103 and perform the required processing on the loaded data.

[0168] In one embodiment, the data processing device further includes:

[0169] a compression unit, configured to remove data other than valid data pairs from the to-be-processed data pairs formed by the first data object and the second data object respectively corresponding to each data processing channel according to the determination result of the determination unit, so as to obtain valid data pairs respectively corresponding to each data processing channel;

[0170] The storage unit is used to store the valid data pairs and the number of valid data pairs corresponding to each data processing channel, so that the allocation unit can acquire and allocate data.

[0171] In one embodiment, valid data pairs of all data processing channels in the storage unit are stored continuously.

[0172] In one implementation, the determining unit 1102 is specifically configured to:

[0173] Determine a data pair to be processed consisting of data with consistent position correspondence between a first data object and a second data object corresponding to each data processing channel; determine a data pair in the data pair to be processed that does not contain invalid data as a valid data pair in the data pair to be processed formed by the first data object and the second data object corresponding to the data processing channel.

[0174] In one embodiment, the allocation unit 1103 is specifically used to: allocate the valid data pairs corresponding to each data processing channel across the data processing channels among each available hardware processing channel according to the total number of valid data pairs of all data processing channels, so that the number of valid data pairs processed between each available hardware processing channel meets the balance condition.

[0175] In one implementation, the allocation unit 1103 is specifically configured to:

[0176] Constructing a valid data pair set including valid data pairs corresponding to each data processing channel, and determining the total number of valid data pairs in the valid data pair set according to the number of valid data pairs corresponding to each data processing channel, to obtain the total number of valid data pairs;

[0177] Splitting the valid data pair set into a first number of multiple subsets according to the total number, so that the number of valid data pairs respectively contained in each subset meets a proximity condition; the first number is the number of channels of each available hardware processing channel;

[0178] The valid data pairs contained in different subsets are respectively allocated to different available hardware processing channels.

[0179] In one embodiment, when constructing a valid data pair set including valid data pairs corresponding to each data processing channel, the allocation unit 1103 is specifically used to: construct a valid data pair sequence including valid data pairs corresponding to each data processing channel; wherein each valid data pair in the valid data pair sequence is stored sequentially and continuously.

[0180] In one embodiment, when the allocation unit 1103 splits the valid data pair set into a first number of multiple subsets according to the total number, and allocates the valid data pairs contained in different subsets to different available hardware processing channels, it is specifically used to:

[0181] Dividing the valid data pair sequence into the first number of multiple subsequences according to the total number of valid data pairs included; each subsequence includes a corresponding number of valid data pairs continuously stored in the valid data pair sequence;

[0182] The valid data pairs contained in different subsequences are respectively allocated to different available hardware processing channels.

[0183] In one implementation, when the allocation unit 1103 divides the valid data pair sequence into the first number of subsequences according to the total number of valid data pairs included, the allocation unit 1103 is specifically configured to:

[0184] Determine a second number and a first address of a storage location of a valid data pair in the valid data pair sequence; the second number is an upward rounded value of an average value obtained by averaging the total number according to the first number;

[0185] Starting from the target address, determine valid data pairs stored continuously, the number of which is not greater than the second number, as a subsequence of the valid data pair sequence, until all valid data pairs in the valid data pair sequence are divided into corresponding subsequences;

[0186] Among them, among the obtained subsequences, the number of valid data pairs contained in a subsequence is equal to or less than the second number, and the number of valid data pairs contained in each subsequence other than the one subsequence is equal to the second number; the target address is the first address or the starting address determined based on the first address for the subsequence to be divided.

[0187] In one embodiment, when the allocation unit 1103 determines the starting address for the subsequence to be divided based on the first address, it is specifically used to: determine the starting address of the subsequence to be divided according to the first address, the second number and the corresponding order of the subsequence to be divided in each subsequence of the valid data pair sequence.

[0188] For the data processing device disclosed in the embodiment of the present application, since it corresponds to the data processing method disclosed in the above method embodiment, the description is relatively simple. For relevant similarities, please refer to the description of the above method embodiment, which will not be described in detail here.

[0189] The present application also discloses an electronic device, the composition structure of the electronic device, such as Fig.12 As shown, including at least:

[0190] A memory 10, for storing a computer instruction set;

[0191] A set of computer instructions can be implemented in the form of a computer program.

[0192] The processor 20 is used to implement the data processing method disclosed in any of the above method embodiments by executing a computer instruction set.

[0193] The processor 20 can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a neural network processor (NPU), a deep learning processor (DPU) or other programmable logic devices, etc.

[0194] The electronic device includes a display device and / or includes a display interface and can be connected to an external display device.

[0195] Optionally, the electronic device also includes a camera assembly, and / or is connected to an external camera assembly.

[0196] In addition, the electronic device may also include components such as a communication interface and a communication bus. The memory, the processor and the communication interface communicate with each other through the communication bus.

[0197] The communication interface is used for communication between electronic devices and other devices. The communication bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc.

[0198] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0199] For the convenience of description, the above system or device is described by dividing it into various modules or units according to its functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0200] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly contributed to the prior art in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.

[0201] Finally, it should be noted that, in this article, relational terms such as first, second, third and fourth are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0202] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A data processing method, the method comprising: Acquire the first data object and the second data object corresponding to each data processing channel respectively, and the data in the first data object and the second data object corresponding to the same data processing channel correspond to the corresponding data pair to be processed; Determine the valid data pairs corresponding to the respective data processing channels from the data pairs to be processed; Based on the total number of valid data pairs of all data processing channels, the valid data pairs are evenly distributed among the available hardware processing channels; The resulting valid data pairs are data processed in parallel on each available hardware processing channel.

2. The method according to claim 1, wherein determining the valid data pairs corresponding to the respective data processing channels from the to-be-processed data pairs comprises: Determine a pair of data to be processed consisting of data with consistent positions between a first data object and a second data object corresponding to each data processing channel; A data pair that does not contain invalid data among the data pairs to be processed is determined as a valid data pair corresponding to the data processing channel.

3. The method according to claim 1, wherein the step of evenly distributing the valid data pairs among the available hardware processing channels based on the total number of valid data pairs of all data processing channels comprises: According to the total number of valid data pairs of all data processing channels, the valid data pairs corresponding to each data processing channel are distributed among each available hardware processing channel across the data processing channels, so that the number of valid data pairs processed between each available hardware processing channel meets the balance condition.

4. The method according to claim 1, wherein the step of evenly distributing the valid data pairs among the available hardware processing channels based on the total number of valid data pairs of all data processing channels comprises: Constructing a valid data pair set including valid data pairs corresponding to each data processing channel, and determining the total number of valid data pairs in the valid data pair set according to the number of valid data pairs corresponding to each data processing channel, to obtain the total number of valid data pairs; Splitting the valid data pair set into a first number of multiple subsets according to the total number, so that the number of valid data pairs respectively contained in each subset meets a proximity condition; the first number is the number of channels of each available hardware processing channel; The valid data pairs contained in different subsets are respectively allocated to different available hardware processing channels.

5. The method according to claim 4, wherein constructing a valid data pair set including valid data pairs corresponding to each data processing channel comprises: A valid data pair sequence including valid data pairs corresponding to each data processing channel is constructed; wherein each valid data pair in the valid data pair sequence is stored sequentially and continuously.

6. The method according to claim 5, wherein the step of dividing the valid data pair set into a first number of multiple subsets according to the total number, and respectively allocating the valid data pairs contained in different subsets to different available hardware processing channels comprises: Divide the valid data pair sequence into the first number of subsequences according to the total number of valid data pairs included; Each subsequence includes a corresponding number of valid data pairs stored consecutively in the valid data pair sequence; The valid data pairs contained in different subsequences are respectively allocated to different available hardware processing channels.

7. The method according to claim 6, wherein the step of dividing the valid data pair sequence into the first number of subsequences according to the total number of valid data pairs included in the sequence comprises: Determining a second quantity and a first address of a storage location of valid data pairs in the sequence of valid data pairs; The second number is an upward rounded value of an average value obtained by averaging the total number according to the first number; Starting from the target address, determine valid data pairs stored continuously, the number of which is not greater than the second number, as a subsequence of the valid data pair sequence, until all valid data pairs in the valid data pair sequence are divided into corresponding subsequences; Among them, among the obtained subsequences, the number of valid data pairs contained in a subsequence is equal to or less than the second number, and the number of valid data pairs contained in each subsequence other than the one subsequence is equal to the second number; the target address is the first address or the starting address determined based on the first address for the subsequence to be divided.

8. The method according to claim 7, determining the starting address for the subsequence to be divided based on the first address, comprises: The starting address of the subsequence to be divided is determined according to the first address, the second number and the corresponding order of the subsequence to be divided in each subsequence of the valid data pair sequence.

9. A data processing device, comprising: An acquisition unit, used to acquire first data objects and second data objects corresponding to respective data processing channels, wherein the data in the first data object and the second data object corresponding to the same data processing channel correspond to corresponding data pairs to be processed; A determination unit, used to determine valid data pairs corresponding to each data processing channel from the to-be-processed data pairs; an allocating unit, configured to evenly allocate the valid data pairs among the available hardware processing channels based on the total number of valid data pairs of all data processing channels; The data processing unit is used to perform data processing on the obtained valid data pairs on each available hardware processing channel in a parallel manner.

10. The apparatus according to claim 9, further comprising: a compression unit, configured to remove data other than valid data pairs from the to-be-processed data pairs formed by the first data object and the second data object respectively corresponding to each data processing channel according to the determination result of the determination unit, so as to obtain valid data pairs respectively corresponding to each data processing channel; The storage unit is used to store the valid data pairs and the number of valid data pairs corresponding to each data processing channel, so that the allocation unit can acquire and allocate data.

11. The device according to claim 10, wherein the valid data pairs of all data processing channels in the storage unit are stored continuously.

Images