A time delay determination method and apparatus, electronic device, and storage medium

Abstract

Embodiments of the present application provide a time delay determination method and device, electronic equipment and storage medium. The scheme is as follows: determining a to-be-processed line channel group in a quantum computing measurement and control system, the to-be-processed line channel group including a first line channel, a second line channel and a third line channel; obtaining a first relative time delay and a second relative time delay; respectively searching for a first time delay, a second time delay and a third time delay corresponding to the first line channel, the second line channel and the third line channel at a current time; and updating at least one of the first time delay, the second time delay and the third time delay based on the first relative time delay and the second relative time delay. Through the technical scheme provided by the embodiments of the present application, the time delay of signal transmission between each magnetic flux modulation line channel in the quantum computing measurement and control system is determined, so that the quantum bit frequency regulation signal can be transmitted to the quantum bit and the adjustable coupler at the same time when the multi-qubit gate operation is performed, and the accuracy of quantum computing is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computing, and in particular to a time delay determination method and device, electronic equipment and a storage medium. BACKGROUND

[0002] Quantum computing is a computing mode for solving problems by using the basic characteristics of quantum mechanics. By constructing a quantum physics hardware system that can be precisely operated, running quantum computing software to implement quantum algorithms, and solving computing problems, quantum computing can be applied to specific problems or fields.

[0003] In the quantum computing process, especially when multiple qubits are used for multi-qubit gate operations, such as two-qubit gate operations, two qubits and an adjustable coupler coupled to the two qubits need to be called each time for quantum computing. In this process, the quantum computing measurement and control system (such as a measurement and control all-in-one machine) transmits quantum bit frequency control signals to the interfaces of the magnetic flux modulation lines (i.e., Z lines) corresponding to the two qubits and the adjustable coupler through the magnetic flux modulation line channels, thereby implementing two-qubit gate operations. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a time delay determination method and device, electronic equipment and a storage medium to determine the time delay of signal transmission between each magnetic flux modulation line channel in a quantum computing measurement and control system, thereby ensuring that the quantum bit frequency control signals can be transmitted to the qubits and the adjustable coupler at the same time when performing multi-qubit gate operations, and improving the accuracy of quantum computing. The specific technical solutions are as follows:

[0005] The embodiments of the present application provide a time delay determination method, which comprises:

[0006] determining a to-be-processed line channel group in a quantum computing measurement and control system, the to-be-processed line channel group comprising a first line channel, a second line channel and a third line channel for transmitting quantum bit frequency control signals;

[0007] In the case where the first line channel, the second line channel and the third line channel are linked through a first qubit, a second qubit and a first adjustable coupler, a first relative time delay and a second relative time delay are obtained, the first relative time delay and the second relative time delay being the signal transmission time delays between any two of the first line channel, the second line channel and the third line channel;

[0008] The first time delay, the second time delay and the third time delay corresponding to the first line channel, the second line channel and the third line channel at the current time are respectively found; the first time delay, the second time delay and the third time delay are preset time delays or time delays obtained by updating before the current time.

[0009] update at least one of the first latency, the second latency and the third latency based on the first relative latency and the second relative latency.

[0010] The embodiment of the present application further provides a latency determination device, the device comprises:

[0011] The first determining module is used to determine a to-be-processed line channel group in a quantum computing measurement and control system, and the to-be-processed line channel group comprises a first line channel, a second line channel and a third line channel used for transmitting a quantum bit frequency regulation signal.

[0012] The acquisition module is used to acquire a first relative latency and a second relative latency in the case that the first line channel, the second line channel and the third line channel establish a link through a first quantum bit, a second quantum bit and a first adjustable coupler, and the first relative latency and the second relative latency are signal transmission latencies between any two of the first line channel, the second line channel and the third line channel.

[0013] The searching module is used to search a first latency, a second latency and a third latency corresponding to the first line channel, the second line channel and the third line channel at a current time respectively, and the first latency, the second latency and the third latency are preset latencies or latencies obtained by updating before the current time.

[0014] The first updating module is used to update at least one of the first latency, the second latency and the third latency based on the first relative latency and the second relative latency.

[0015] The embodiment of the present application further provides an electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus.

[0016] The memory is used to store a computer program.

[0017] The processor is used to execute the program stored on the memory, and implement the latency determination method steps of any of the above.

[0018] The embodiment of the present application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the latency determination method steps of any of the above.

[0019] The embodiment of the present application further provides a computer program product comprising instructions which, when executed on a computer, cause the computer to perform the latency determination method of any of the above.

[0020] The embodiment of the application further provides a quantum computing measurement and control system.

[0021] The embodiment of the application has the following beneficial effects:

[0022] The technical scheme provided by the embodiment of the application, in the case that the determined first line channel, second line channel and third line channel in the quantum computing measurement and control system are linked through the first qubit, second qubit and first adjustable coupler, the first relative time delay and second relative time delay between any two line channels are obtained, and at least one of the first time delay corresponding to the first line channel, second time delay corresponding to the second line channel and third time delay corresponding to the third line channel at the current time is updated based on the first relative time delay and second relative time delay, which can realize the time delay determination of signal transmission between the magnetic flux modulation line channels in the quantum computing measurement and control system.

[0023] Since the update of at least one of the first time delay, second time delay and third time delay is based on the first relative time delay and second relative time delay, the updated time delay is matched with the first relative time delay and second relative time delay, which effectively guarantees the accuracy of the updated time delay, so that the quantum bit frequency control signal transmitted based on the updated time delay can reach the quantum bit and adjustable coupler at the same time when the multi-qubit gate operation is performed, and the accuracy of quantum computing is effectively improved.

[0024] In addition, when the first time delay, second time delay or third time delay is the time delay obtained before the current time, the time delay update according to the first relative time delay and second relative time delay between any two line channels of the first line channel, second line channel and third line channel can effectively establish the relevance of each line channel in time delay, so that the time delay corresponding to each line channel determined finally is associated with each other, effectively improving the accuracy and relevance of the determined time delay. And once the line channel is replaced, since the determined time delay is bound to each line channel, the signal transmission can be directly performed according to the determined time delay, without the need to re-determine the time delay, and the applicability of the determined time delay is improved.

[0025] Of course, implementing any product or method of the application does not necessarily need to achieve all the advantages described above at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 A schematic diagram of the structure of a 9-qubit quantum chip in related technology;

[0028] Figure 2 A schematic diagram of a first flow chart of a method for determining a time delay provided in an embodiment of the present application;

[0029] Figure 3 A second flow chart of the delay determination method provided in an embodiment of the present application;

[0030] Figure 4 A third flow chart of the delay determination method provided in an embodiment of the present application;

[0031] Figure 5 A fourth flow chart of the delay determination method provided in an embodiment of the present application;

[0032] Figure 6 A fifth flow chart of the delay determination method provided in an embodiment of the present application;

[0033] Figure 7 A sixth flow chart of the delay determination method provided in an embodiment of the present application;

[0034] Figure 8 A schematic diagram of a flow chart of a method for determining associated line channels provided in an embodiment of the present application;

[0035] Figure 9 A seventh flow chart of the delay determination method provided in an embodiment of the present application;

[0036] Figure 10 This is a schematic diagram of an eighth flow chart of the delay determination method provided in an embodiment of the present application;

[0037] Figure 11 A ninth flow chart of the method for determining the time delay provided in an embodiment of the present application;

[0038] Figure 12 A schematic diagram of the structure of a delay determination device provided in an embodiment of the present application;

[0039] Figure 13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0041] Currently, a quantum chip can include multiple quantum bits, and adjacent quantum bits are coupled and connected through adjustable couplers. For ease of understanding, the following will be described in combination with Figure 1 Figure 1 is a structural diagram of a 9-quantum-bit quantum chip in the related art. Among them, Q1-Q9 are 9 quantum bits on the quantum chip, and C1-C12 are adjustable couplers for coupling and connecting adjacent quantum bits.

[0042] The adjustable coupler is similar in structure to the quantum bit, and the difference lies in that the adjustable coupler does not have an interface for receiving a quantum state control signal and a resonant cavity for directly reading information. For the structure of the quantum bit and the adjustable coupler, reference can be made to the quantum bit and the adjustable coupler in the related art, and no specific description will be made here.

[0043] When performing a multi-quantum-bit gate operation, since multiple quantum bits need to be called at the same time, the time delay of each quantum bit and the adjustable coupler on the corresponding magnetic flux modulation line channel needs to be determined, so that the quantum bit frequency control signal can be transmitted to the quantum bit and the adjustable coupler at the same time.

[0044] In the related art, when the magnetic flux modulation line channel on the quantum computing measurement and control system is connected to the Z line interface corresponding to the quantum bit and the adjustable coupler, the user can determine the time delay between the pulse modulation line (i.e., the XY line) corresponding to each quantum bit and the Z line through experiments. Moreover, considering that the adjustable coupler and at least two quantum bits are used in the multi-quantum logic gate operation, the time delay between the adjustable coupler and the Z line corresponding to each two quantum bits needs to be determined manually.

[0045] With the increasing number of quantum bits on the quantum chip, the manual time delay determination method requires a large amount of manual cost, and the error rate caused by manual errors will also be greatly increased. In addition, since the time delay is set for each quantum bit and adjustable coupler, but the line delay is caused by the devices, line length, etc. on each line channel on the quantum computing measurement and control system, once the line channel is replaced, the time delay between each quantum bit and the adjustable coupler needs to be determined again.

[0046] To solve the problems in the related art, the present application provides a time delay determination method. As shown in​ Figure 2 As shown, Figure 2 This is a schematic diagram of the first flow chart of the delay determination method provided in the embodiment of the present application. This method can be applied to any electronic device, which can be a quantum computing measurement and control system or other device, and the electronic device is not specifically limited here. Figure 2 The method shown includes the following steps.

[0047] Step S201: determining a line channel group to be processed in a quantum computing measurement and control system, where the line channel group to be processed includes a first line channel, a second line channel, and a third line channel for transmitting a quantum bit frequency control signal.

[0048] In step S202, when the first line channel, the second line channel, and the third line channel are linked through the first quantum bit, the second quantum bit, and the first adjustable coupler, a first relative delay and a second relative delay are obtained. The first relative delay and the second relative delay are signal transmission delays between any two line channels among the first line channel, the second line channel, and the third line channel.

[0049] Step S203 , respectively searching for the first delay, second delay, and third delay corresponding to the first line channel, the second line channel, and the third line channel at the current moment; the first delay, the second delay, and the third delay are preset delays, or delays updated before the current moment.

[0050] Step S204: Update at least one of the first delay, the second delay, and the third delay based on the first relative delay and the second relative delay.

[0051] pass Figure 1 The method shown, when the first, second, and third line channels in the determined quantum computing measurement and control system are linked via the first qubit, the second qubit, and the first adjustable coupler, obtains two sets of signal transmission delays between any two line channels, namely, a first relative delay and a second relative delay. Based on the first relative delay and the second relative delay, at least one of the first delay corresponding to the first line channel, the second delay corresponding to the second line channel, and the third delay corresponding to the third line channel at the current moment is updated. This can achieve the determination of the signal transmission delay between each flux modulation line channel in the quantum computing measurement and control system.

[0052] Since at least one of the first delay, the second delay and the third delay is updated based on the first relative delay and the second relative delay, the updated delay matches the first relative delay and the second relative delay, which effectively ensures the accuracy of the updated delay. Therefore, when performing multi-qubit gate operations, the qubit frequency control signal transmitted based on the updated delay can reach the qubit and the adjustable coupler at the same time, effectively improving the accuracy of quantum computing.

[0053] Furthermore, when the first, second, or third delay is a delay updated prior to the current moment, updating the delay based on the first and second relative delays between any two of the first, second, and third line channels effectively establishes a correlation between the delays of the individual line channels, ensuring that the delays ultimately determined for each line channel are correlated with each other, effectively improving the accuracy and relevance of the determined delays. Furthermore, if a line channel is replaced, since the determined delay is bound to each line channel, signal transmission can be performed directly based on the determined delay without requiring a new delay determination, thereby improving the applicability of the determined delay.

[0054] The embodiments of the present application are described below through specific examples.

[0055] With respect to the above step S201, that is, determining the line channel group to be processed in the quantum computing measurement and control system, the line channel group to be processed includes a first line channel, a second line channel and a third line channel for transmitting the quantum bit frequency control signal.

[0056] In an embodiment of the present application, the quantum computing measurement and control system may include multiple pulse modulation circuit channels (i.e., the fourth circuit channel below) and multiple flux modulation circuit channels (i.e., the fifth circuit channel below).

[0057] The fourth circuit channel is used to transmit quantum state control signals to the qubits, and the fifth circuit channel is used to transmit qubit frequency control signals to the qubits or tunable couplers. The number of fourth and fifth circuit channels in the quantum computing measurement and control system can be set based on the number of qubits and tunable couplers included on the quantum chip. The number of fifth circuit channels is greater than the number of fourth circuit channels. The number of fourth and fifth circuit channels in the quantum computing measurement and control system is not specifically limited.

[0058] The electronic device may store link relationships (or association relationships) between each fifth line channel. Based on the link relationships between each fifth line channel, the electronic device may select three fifth line channels as a line channel group to be processed. These three fifth line channels are respectively designated as the first line channel, the second line channel, and the third line channel. The method for determining the line channel group to be processed is described below and is not further detailed here.

[0059] In an optional embodiment, the link relationship between the fifth line channels may be represented in the form of a table, a character string, or the like.

[0060] For ease of understanding, the link relationship between the fifth line channels is described below using a first table. The first table may be shown in Table 1.

[0061] Table 1

[0062] XY / Z Z1 Z2 Z3 … XY1 0 / 1 0 / 1 0 / 1 … XY2 0 / 1 0 / 1 0 / 1 … XY3 0 / 1 0 / 1 0 / 1 … … … … … …

[0063] In Table 1, each row corresponds to a fourth circuit channel in the quantum computing measurement and control system, i.e., XY1, XY2, XY3, etc. in Table 1, and each column corresponds to a fifth circuit channel in the quantum computing measurement and control system, i.e., Z1, Z2, Z3, etc. in Table 1. Each cell in Table 1 contains the corresponding fourth circuit channel, fifth circuit channel, and value.

[0064] The value of each cell in Table 1 can be a first value or a second value. A first value indicates that the fourth and fifth line channels corresponding to the cell are not linked, such as 0 in Table 1; a second value indicates that the fourth and fifth line channels corresponding to the cell are linked, such as 1 in Table 1. For ease of understanding, the following description uses the first value of 0 and the second value of 1 as an example, which is not intended to be limiting.

[0065] For each row in the first list, if the values ​​corresponding to any two cells in the row are both the second value, the electronic device can determine that there is an association relationship between the fifth line channels corresponding to the two cells.

[0066] For ease of understanding, cell 1 corresponding to XY1 and Z1, and cell 2 corresponding to XY1 and Z2 in Table 1 are taken as examples for description.

[0067] When the values ​​corresponding to the above-mentioned cell 1 and cell 2 are both 1, that is, the values ​​corresponding to cell 1 and cell 2 are 11, the electronic device can determine that there is an association relationship between Z1 and Z2; when at least one of the values ​​corresponding to the above-mentioned cell 1 and cell 2 is 0, that is, the values ​​corresponding to cell 1 and cell 2 are 00, 01 or 10, the electronic device can determine that there is no association relationship between Z1 and Z2.

[0068] For the above step S202, that is, when the first line channel, the second line channel and the third line channel are linked through the first quantum bit, the second quantum bit and the first adjustable coupler, the first relative delay and the second relative delay are obtained. The first relative delay and the second relative delay are the signal transmission delays between any two line channels among the first line channel, the second line channel and the third line channel.

[0069] In this step, when the first, second, and third line channels are linked through two qubits (denoted as the first qubit and the second qubit) and an adjustable coupler (denoted as the first adjustable coupler) coupling the two qubits, the electronic device can respectively obtain the signal transmission duration (denoted as the first transmission duration) of the first line channel transmitting the qubit frequency signal, the signal transmission duration (denoted as the second transmission duration) of the second line channel transmitting the qubit frequency signal, and the signal transmission duration (denoted as the third transmission duration) of the third line channel transmitting the qubit frequency signal. The electronic device can obtain the time delay between the signal transmission durations of any two lines of the other channels based on the first transmission duration, the second transmission duration, and the third transmission duration, to obtain a first relative delay and a second relative delay.

[0070] When the above-mentioned first line channel, second line channel and third line channel establish a link through the first quantum bit, the second quantum bit and the first adjustable coupler, the first line channel, the second line channel and the third line channel will be connected to the Z-line interface corresponding to the first quantum bit, the second quantum bit and the first adjustable coupler respectively.

[0071] In the embodiments of this application, the connection relationships between the first, second, and third line channels and the first and second qubits, as well as the first tunable coupler, are not specifically limited. For ease of understanding, the following description uses the example of the first line channel connected to the Z-line interface of the first qubit, the second line channel connected to the Z-line interface of the second qubit, and the third line channel connected to the Z-line interface of the first tunable coupler. This does not serve to limit the connection in any way.

[0072] Regarding the first relative delay and the second relative delay, the first relative delay is different from the second relative delay. For example, the first relative delay may be the difference between the first transmission duration and the second transmission duration, and the second relative delay may be the difference between the first transmission duration and the third transmission duration. No specific limitations are imposed on the first relative delay and the second relative delay. For ease of understanding, the following description uses the example of the first relative delay being the difference between the first transmission duration and the second transmission duration, and the second relative delay being the difference between the third transmission duration and the second transmission duration, without limiting the scope of this description.

[0073] In the embodiments of the present application, since the first relative delay and the second relative delay are the difference between the transmission times of the two signals, they can be either positive or negative. For ease of understanding, the following description will only take the case where both the first relative delay and the second relative delay are positive as an example, which is not intended to be limiting.

[0074] With respect to the above step S203, the first delay, second delay and third delay corresponding to the first line channel, the second line channel and the third line channel at the current moment are respectively searched; the first delay, the second delay and the third delay are preset delays, or delays updated before the current moment.

[0075] In an embodiment of the present application, the electronic device stores a correspondence between all fifth line channels and delays (referred to as a first correspondence). The first correspondence can be represented in a table, a string, or the like. For ease of understanding, the following description will only use the second table as an example to illustrate the first correspondence. The second table can be shown in Table 2.

[0076] Table 2

[0077] Line Channel Z1 Z2 Z3 … Latency 0 0 0 …

[0078] In Table 2 above, the fifth line channel may include Z1, Z2, Z3, etc. in Table 2 above. Each fifth line channel has a corresponding delay, that is, 0 in Table 2 above.

[0079] For each fifth line channel in the second list, the delay corresponding to the fifth line channel may be a preset delay, such as 0 in Table 2, or a delay updated before the current moment.

[0080] In an optional embodiment, for each fifth line channel in the above-mentioned second list, if the delay corresponding to the fifth line channel is the delay updated before the current moment, then the delay corresponding to the fifth line channel can be the delay updated before the current moment based on the relative delay between any two line channels, where the any two line channels can be any fourth line channel and any fifth line channel, or any two fifth line channels.

[0081] In another optional embodiment, for each fifth channel in the second list, if the delay corresponding to the fifth channel is a delay updated before the current moment, the delay corresponding to the fifth channel may be a delay updated before the current moment based on the delay update amount corresponding to the associated channel associated with the fifth channel. The method for determining the associated channel is described below and is not detailed here.

[0082] For the above-mentioned first line channel, second line channel and third line channel, the electronic device can respectively search the delay corresponding to the first line channel (recorded as the first delay), the delay corresponding to the second line channel (recorded as the second delay), and the delay corresponding to the third line channel (recorded as the third delay) in the above-mentioned second list.

[0083] The first delay, the second delay, and the third delay may be the preset delays or the delays updated before the current moment.

[0084] In the above Figure 1 In the method shown, step S203 is performed after step S202. Alternatively, step S203 may be performed before step S202 or simultaneously with step S202. The order of performing steps S202 and S203 is not specifically limited.

[0085] In the embodiment of the present application, in addition to storing the first correspondence relationship, the electronic device may also store the correspondence relationship between all fourth line channels and delays (recorded as the second correspondence relationship). For ease of understanding, the second correspondence relationship is described using the third table as an example. The third table may be as shown in Table 3.

[0086] Table 3

[0087] Line Channel XY1 XY2 XY3 … Latency 0 0 0 …

[0088] In Table 3, the fourth line channels may include XY1, XY2, XY3, etc. in Table 3. Each fourth line channel has a corresponding delay, that is, 0 in Table 3.

[0089] The description of the second correspondence relationship may refer to the description of the first correspondence relationship, and will not be described in detail here.

[0090] In this embodiment of the present application, the latency corresponding to each channel in the second and third lists can be expressed as the corresponding waiting time when the channel transmits the corresponding quantum state control signal or qubit frequency control signal. The difference between the latency corresponding to any two channels is the time difference between the signals sent by the two channels when transmitting the corresponding quantum state control signal or qubit frequency control signal.

[0091] With respect to the above step S204, that is, based on the first relative delay and the second relative delay, at least one of the first delay, the second delay and the third delay is updated.

[0092] In this step, the two fifth line channels corresponding to the first relative delay or the second relative delay are, respectively, two line channels among the first line channel, the second line channel, and the third line channel. The electronic device can update the delay of one or both of the two line channels corresponding to the first relative delay based on the first relative delay, and update the delay of one or both of the two line channels corresponding to the second relative delay based on the second relative delay. In other words, one or more of the first, second, and third delays are updated based on the first and second relative delays. The method for updating at least one of the first, second, and third delays is described below and is not detailed here.

[0093] In this embodiment of the present application, when one or more of the first, second, and third delays are updated, the delays of all other line channels except the updated line channel remain unchanged. For example, when only the first delay is updated, the second and third delays remain unchanged. In this case, the second delay, the third delay, and the updated first delay match the first relative delay and the second relative delay.

[0094] Through the above Figure 1 With the method shown, the electronic device can accurately determine the time delays between the first line channel, the second line channel, and the third line channel, so that the updated time delays match the first relative time delay and the second relative time delay. As a result, based on the updated time delays, the quantum bit frequency control signal transmitted using the first line channel, the second line channel, and the third line channel can reach the quantum bit and the adjustable coupler at the same time. This eliminates the manual delay determination method used in related arts, improves the accuracy of the determined time delay, and reduces labor costs.

[0095] In addition, compared with the method of binding delay to quantum bits or adjustable couplers in related technologies, in the embodiments of the present application, the delay is directly bound to each fifth line channel. Therefore, in actual application, after the delay between any three fifth line channels is determined, the updated delay can be matched with the relative delay between any two line channels regardless of whether the line channels are replaced. This avoids the waste of resources caused by the need to re-determine the delay when the line channels are changed, and improves the applicability of the determined delay to the line channel change scenario.

[0096] In an optional embodiment, according to the above Figure 2 The method shown in the embodiment of the present application also provides a method for determining the time delay. Figure 3 As shown, Figure 3 This is a second flow chart of the delay determination method provided in the embodiment of the present application. Figure 3 In the method shown, the above step S202 is refined into the following steps, namely step S2021 - step S2022.

[0097] Step S2021: When the first line channel, the second line channel, and the third line channel are linked through the first quantum bit, the second quantum bit, and the adjustable coupler, a first transmission duration corresponding to the first line channel, a second transmission duration corresponding to the second line channel, and a third transmission duration corresponding to the third line channel are obtained.

[0098] In an optional embodiment, when obtaining the above-mentioned first transmission duration, second transmission duration and third transmission duration, the electronic device can respectively measure the transmission duration of the quantum bit frequency control signal on the first line channel, the second line channel and the third line channel.

[0099] In another optional embodiment, when obtaining the above-mentioned first transmission duration, second transmission duration and third transmission duration, the electronic device can use the ZZTiming experiment to obtain the first transmission duration, second transmission duration and third transmission duration corresponding to the first line channel, the second line channel and the third line channel.

[0100] In related technologies, transmitting a π pulse through a pulse modulation channel can excite a qubit to the |1> state if the frequency of the qubit is the same as the qubit's operating frequency. Therefore, by transmitting a square wave of a certain amplitude through a flux modulation channel, the qubit's frequency can be changed, thereby affecting the effect of the π pulse on the qubit's excitation to the |1> state. Based on this, during a ZZTiming experiment, by performing a SWAP gate operation on two qubits, the transmission timing of the square wave relative to the π pulse on the two qubits and the tunable coupler can be varied. This allows the transmission duration of the two qubits through the flux modulation channel on the tunable coupler to be determined. The ZZTiming experiment will not be described in detail here.

[0101] In the embodiment of the present application, there is no specific limitation on the method for obtaining the signal transmission duration corresponding to the first line channel, the second line channel, and the third line channel.

[0102] Step S2022: If the second transmission duration is less than the first transmission duration and the third transmission duration, the difference between the first transmission duration and the second transmission duration is calculated as the first relative delay between the first line channel and the second line channel, and the difference between the third transmission duration and the first transmission duration is calculated as the second relative delay between the third line channel and the second line channel.

[0103] In an optional embodiment, if the relationship between the first transmission duration, the second transmission duration and the third transmission duration is: t1 <t2<t3,则第一相对时延可以为t 21 =t2-t1, the second relative delay can be: t 31 =t3-t1.

[0104] In an optional embodiment, in order to facilitate the subsequent updating of the corresponding delays of each fifth line channel, for the above-mentioned first transmission duration, second transmission duration and third transmission duration, when the minimum transmission duration among the first transmission duration, the second transmission duration and the third transmission duration is not 0, the electronic device can reset the first transmission duration, the second transmission duration and the third transmission duration to zero, that is, each transmission duration is subtracted from the minimum transmission duration.

[0105] For ease of understanding, we still use the above t1 <t2<t3为例进行说明。最小传输时长为t1,此时,归零化后的t′1=t1-t1=0,归零化后的t′2=t2-t1,归零化后的t′3=t3-t1。

[0106] Through the above-mentioned zeroing processing, the sizes of the first transmission duration, the second transmission duration and the third transmission duration can be effectively reduced, thereby facilitating the calculation of the first relative delay and the second relative delay, effectively reducing the computing resources required for delay update, and reducing the delay update cost.

[0107] Through the above steps S2021-S2022, the electronic device can accurately determine the first relative delay and the second relative delay based on the above first transmission duration, the second transmission duration and the third transmission duration, and ensure that the determined first relative delay and the second delay are both positive numbers, effectively reducing the computational complexity of the subsequent delay update and reducing the computational cost of the delay update.

[0108] In the above Figure 3 In the illustrated embodiment, only the example of the second transmission duration being shorter than the first and third transmission durations is used for illustration. Depending on the differences in the first, second, and third transmission durations, the calculation methods for the first and second relative delays will also vary. For details, refer to the method in step S2022 above and are not further described here.

[0109] In an optional embodiment, according to the above Figure 3 The method shown in the embodiment of the present application also provides a method for determining the time delay. Figure 4 As shown, Figure 4 This is a third flow chart of the delay determination method provided in the embodiment of the present application. Figure 4 In the method shown, the above step S204 is refined into the following steps, namely step S2041 - step S2042.

[0110] Step S2041: Update the first delay and / or the second delay based on the first relative delay.

[0111] For ease of understanding, the following describes the update of the first delay and / or the second delay by the electronic device based on the first relative delay, taking the first relative delay as the time difference between the first transmission duration corresponding to the first line channel and the second transmission duration corresponding to the second line channel as an example.

[0112] In an optional embodiment, if the first delay is greater than the second delay, the above step S2041 can be refined into the following steps, namely, step 1 to step 2.

[0113] Step 1: When the first difference is less than the first relative delay, the first delay is updated to a first sum value.

[0114] The first difference is the difference between the first delay and the second delay, and the first sum is the sum of the second delay and the first relative delay.

[0115] Step 2: When the first difference is greater than the first relative delay, the second delay is updated to the second difference.

[0116] The second difference is the difference between the first time delay and the first relative time delay.

[0117] For ease of understanding, the first delay is t z1 , the second delay is t z2 , the first relative delay t Δ1 This is explained as an example.

[0118] Due to t z1 Greater than t z2 , therefore, the first difference must be greater than 0, that is, t z1 -t z2 >0.

[0119] When the electronic device compares the first difference with the first relative delay, if t z1 -t z2 <t Δ1 , then according to the first delay t′ updated in step 1 above z1 =t z2 +t Δ1 Due to t z1 -t z2 <t Δ1 , therefore, t z1 <t Δ1 +t z2 , that is, t z1 <t′ z1 , which is the first updated delay t′ z1 The first delay before relative update t z1 Correspondingly, the delay update amount corresponding to the first delay is Δ=t′ z1 -t z1 =t z2 +t Δ1 -t z1 .

[0120] If t z1 -t z2 >t Δ1 , then the second delay t′ is updated according to the above step 2 z2 =t z1 -t Δ1 Due to t z1 -t z2 >t Δ1 , therefore, t z1 -t Δ1 >t z2 , that is, t′ z2 >t z2 , which is the updated second delay t′z2 the second time delay t z2 is increased. Accordingly, the second time delay corresponds to a time delay update amount Δ = t' z2 -t z2 = t z1 -t Δ1 -t z2 .

[0121] The step one and the step two are respectively executed when the first difference value is different from the first relative time delay. In this case, the execution of the step one and the step two is not specifically limited.

[0122] Through the step one and the step two, when the electronic device updates the first time delay or the second time delay based on the first relative time delay, each time of the update only updates one of the first time delay and the second time delay, that is, only updates the time delay corresponding to one of the first line channel and the second line channel, effectively reduces the number of times of the time delay update, thereby reducing the number of times of the global update caused by the line channel time delay adjustment.

[0123] In addition, when the electronic device updates the first time delay or the second time delay based on the first relative time delay, the updated time delay is increased relative to the time delay before the update, which makes the time delay update process a cumulative process of the time delay, avoids the situation that the time delay update process appears to be reduced, thereby avoiding the situation that the updated time delay is negative and the abnormal situation caused by the negative updated time delay.

[0124] In an optional embodiment, when the first difference value is the same as the first relative time delay, the electronic device can determine that the time difference between the first time delay and the second time delay corresponding to the first line channel and the second line channel at the current time matches the first relative time delay. At this time, the electronic device can not perform any processing, that is, does not perform the time delay update operation.

[0125] In an optional embodiment, if the first time delay is less than the second time delay, the step S2041 can be further refined into the following steps, that is, the step three to the step four.

[0126] The step three updates the second time delay as a second sum value when a third difference value is less than the first relative time delay.

[0127] The third difference value is a difference value between the second time delay and the first time delay, and the second sum value is a sum value between the first time delay and the first relative time delay.

[0128] The step four updates the first time delay as a fourth difference value when the third difference value is greater than the first relative time delay.

[0129] The fourth difference value is a difference value between the second time delay and the first relative time delay.

[0130] For the convenience of understanding, still take the first time delay as t z1 , the second time delay as t z2 , and the first relative time delay as t Δ1 for example to make an illustration.

[0131] Since the first time delay is less than the second time delay, the third difference value is certainly greater than 0, that is, t z2 -t z1 >0 When the electronic device compares the third difference value with the first relative time delay, if t z2 -t z1 <t Δ1 , then the first time delay t′ z2 =t z1 +t Δ1 is updated according to the above step three. Since t z2 -t z1 <t Δ1 , t z2 <t Δ1 +t z1 , that is, t z2 <t′ z2 , that is, the updated first time delay t′ z2 is increased relative to the updated second time delay t z2 . Correspondingly, the time delay updating amount Δ corresponding to the second time delay is Δ=t′ z2 -t z2 =t z1 +t Δ1 -t z2 .

[0132] If t z2 -t z1 >t Δ1 , then the first time delay t′ z1 =t z2 -t Δ1 is updated according to the above step four. Since t z2 -t z1 >t Δ1 , t z2 -t Δ1 >t z1 , that is, t′ z1 >t z1 , that is, the updated first time delay t′ z1 is increased relative to the updated first time delay t z1 . Correspondingly, the time delay updating amount Δ corresponding to the first time delay is Δ=t′ z1 -t z1 =t z2 -t Δ1 -t z1 .

[0133] The third difference and the first relative time delay are compared in step three and step four, respectively, when the third difference and the first relative time delay are different. In this case, the execution of step three and step four is not specifically limited.

[0134] In step three and step four, the electronic device updates only one of the first time delay and the second time delay, i.e., only the time delay corresponding to one of the first line channel and the second line channel, when the first time delay or the second time delay is updated based on the first relative time delay. The number of time delay updates is effectively reduced, thereby reducing the number of global updates caused by line channel time delay adjustment.

[0135] In addition, when the first time delay or the second time delay is updated based on the first relative time delay, the updated time delay is greater than the time delay before the update. This makes the time delay update process a cumulative process, avoiding the situation where the time delay decreases during the time delay update process, thereby avoiding the situation where the updated time delay is negative and the abnormal situation caused by the negative updated time delay.

[0136] In an optional embodiment, when the third difference and the first relative time delay are the same, the electronic device can determine that the time difference between the first time delay and the second time delay corresponding to the first line channel and the second line channel at the current time matches the first relative time delay. At this time, the electronic device can not perform any processing, i.e., not perform a time delay update operation.

[0137] In an optional embodiment, when the first time delay and the second time delay are equal, the electronic device can update the first time delay or the second time delay based on the first relative time delay. For example, when the first relative time delay is the difference between the first transmission time and the second transmission time, the electronic device can update the first time delay, such as updating the first time delay to the sum of the first time delay and the first relative time delay. Alternatively, the electronic device can update the second time delay, such as updating the second time delay to the difference between the second time delay and the first relative time delay. In this case, the time delay update method when the first time delay and the second time delay are equal is not specifically limited.

[0138] In step S2042, the second time delay and / or the third time delay is updated based on the second relative time delay.

[0139] For ease of understanding, the second relative time delay is taken as an example of the time difference between the third transmission time corresponding to the third line channel and the second transmission time corresponding to the second line channel, and the update of the second time delay and / or the third time delay based on the second relative time delay is described below.

[0140] In an optional embodiment, if the second time delay is greater than the third time delay, step S2042 can be refined into the following steps, i.e., step five to step six.

[0141] Step 5: When the fifth difference is smaller than the second relative delay, the second delay is updated to the third sum value.

[0142] The fifth difference is the difference between the second delay and the third delay, and the third sum is the sum of the third delay and the second relative delay.

[0143] Step six: when the fifth difference is greater than the second relative delay, update the third delay to the sixth difference.

[0144] The sixth difference is the difference between the second time delay and the second relative time delay.

[0145] For ease of understanding, the second delay is t z2 , the third delay is t z3 , the second relative delay t Δ2 This is explained as an example.

[0146] Due to t z2 Greater than t z3 , therefore, the fifth difference must be greater than 0, that is, t z2 -t z3 >0.

[0147] When the electronic device compares the fifth difference with the second relative delay, if t z2 -t z3 <t Δ2 , then according to the second delay t′ updated in step 5 above z2 =t z3 +t Δ2 Due to t z2 -t z3 <t Δ2 , therefore, t z2 <t z3 +t Δ2 , that is, t z2 <t′ z2 , which is the updated second delay t′ z2 The second delay before relative update t z2 Correspondingly, the delay update amount corresponding to the second delay is Δ=t′ z2 -t z2 =t z3 +t Δ2 -t z2 .

[0148] If t z2 -t z3 >t Δ2 , then according to the third delay t′ updated in step 6 above z3 =t z2 -t Δ2 Due to tz2 -t z3 >t Δ2 , therefore, t z2 -t Δ2 >t z3 , that is, t′ z3 >t z3 , which is the updated third delay t′ z3 The third delay before relative update t z3 Correspondingly, the delay update amount corresponding to the third delay is Δ=t′ z3 -t z3 =t z2 -t Δ2 -t z3 .

[0149] The above steps 5 and 6 are respectively executed when the comparison results of the fifth difference and the second relative delay are different. Here, the execution of steps 5 and 6 is not specifically limited.

[0150] Through the above steps 5 and 6, when the electronic device updates the second delay or the third delay based on the second relative delay, only one of the second delay and the third delay is updated each time, that is, only the delay corresponding to one of the second line channel and the third line channel is updated, which effectively reduces the number of delay updates, thereby reducing the number of global updates caused by the line channel delay adjustment.

[0151] In addition, when the electronic device updates the second delay or the third delay based on the second relative delay, the updated delay increases relative to the delay before the update, which makes the delay update process a delay accumulation process, avoiding the occurrence of delay reduction in the delay update process, thereby avoiding the updated delay being a negative value and the abnormal situation caused by the updated delay being a negative number.

[0152] In an optional embodiment, when the fifth difference is the same as the second relative delay, the electronic device may determine that the time difference between the second delay and the third delay corresponding to the second and third line channels at the current moment matches the second relative delay. In this case, the electronic device may perform no processing, that is, no delay update operation is performed.

[0153] In an optional embodiment, if the second delay is less than the third delay, the above step S2042 can be refined into the following steps, namely, step seven to step eight.

[0154] Step seven: when the seventh difference is smaller than the second relative delay, update the third delay to the fourth sum value.

[0155] The seventh difference is the difference between the third delay and the second delay, and the fourth sum is the sum of the second delay and the second relative delay.

[0156] Step eight: when the seventh difference is greater than the second relative delay, update the second delay to the eighth difference.

[0157] The eighth difference is the difference between the third time delay and the second relative time delay.

[0158] For ease of understanding, the second delay is t z2 , the third delay is t z3 , the second relative delay t Δ2 This is explained as an example.

[0159] Due to t z2 Less than t z3 , therefore, the seventh difference must be greater than 0, that is, t z3 -t z2 >0.

[0160] When the electronic device compares the seventh difference with the second relative time delay, if t z3 -t z2 <t Δ2 , then the third delay t′ after updating according to the above step 7 z3 =t z2 +t Δ2 . Due to t z3 -t z2 <t Δ2 , therefore, t z3 <t z2 +t Δ2 , that is, t z3 <t′ z3 , which is the updated third delay t′ z3 The third delay before relative update t z3 Correspondingly, the delay update amount corresponding to the third delay is Δ=t′ z3 -t z3 =t z2 +t Δ2 -t z3 .

[0161] If t z3 -t z2 >t Δ2 , then the second delay t′ after updating according to the above step eight z2 =t z3 -t Δ2 . Due to t z3 -t z2 >t Δ2 , therefore, t z3 -t Δ2>t z2 , that is, t′ z2 >t z2 , which is the updated second delay t′ z2 The second delay before relative update t z2 Correspondingly, the delay update amount corresponding to the second delay is Δ=t′ z2 -t z2 =t z3 -t Δ2 -t z2 .

[0162] The above steps 7 and 8 are respectively executed when the comparison result of the seventh difference value and the second relative delay is different. Here, the execution of steps 7 and 8 is not specifically limited.

[0163] Through the above steps 7 and 8, when the electronic device updates the second delay or the third delay based on the second relative delay, only one of the second delay and the third delay is updated each time, that is, only the delay corresponding to one of the second line channel and the third line channel is updated, which effectively reduces the number of delay updates, thereby reducing the number of global updates caused by the line channel delay adjustment.

[0164] In addition, when the electronic device updates the second delay or the third delay based on the second relative delay, the updated delay increases relative to the delay before the update, which makes the delay update process a delay accumulation process, avoiding the occurrence of delay reduction in the delay update process, thereby avoiding the updated delay being a negative value and the abnormal situation caused by the updated delay being a negative number.

[0165] In an optional embodiment, when the fifth difference is the same as the second relative delay, the electronic device may determine that the time difference between the second delay and the third delay corresponding to the second and third line channels at the current moment matches the second relative delay. In this case, the electronic device may perform no processing, that is, no delay update operation is performed.

[0166] In an optional embodiment, when the second delay and the third delay are equal, the electronic device may select to update the second delay or the third delay based on the second relative delay. For details, refer to the description above when the first delay and the second delay are equal, and are not further described here.

[0167] In the above Figure 4 In the embodiment shown, step S2041 is performed before step S2042. Alternatively, step S2042 may be performed before step S2041 or simultaneously with step S2041. The execution of steps S2041 and S2042 is not specifically limited.

[0168] In an optional embodiment, when updating at least one of the first delay, the second delay, or the third delay based on the first relative delay and the second relative delay, in addition to the methods shown in steps 1 to 8 above, other methods may also be used.

[0169] For ease of understanding, description is given by taking as an example that the electronic device updates the first delay and / or the second delay based on the first relative delay.

[0170] For example, when the first transmission duration is greater than the second transmission duration, that is, the speed at which the first channel transmits the qubit frequency signal is slower than the speed at which the second channel transmits the qubit frequency signal. In this case, the electronic device can update the delay of the channel with the faster transmission speed. Specifically, the electronic device can update the second delay corresponding to the second channel, where the difference between the first delay and the updated second delay is the first relative delay.

[0171] When the first transmission duration is shorter than the second transmission duration, that is, the first channel transmits the qubit frequency signal faster than the second channel. In this case, the electronic device can update the delay of the channel with the faster transmission speed. The electronic device can update the first delay corresponding to the first channel, where the difference between the second delay and the updated first delay is the first relative delay.

[0172] In addition, the electronic device may also update the delay of the line channel with a slower transmission speed. Alternatively, the electronic device may also update the first delay and the second delay at the same time so that the time difference between the updated first delay and the second delay matches the first relative delay.

[0173] The above-mentioned method of updating the second delay and / or the third delay based on the second relative delay can refer to the above-mentioned method of updating the first delay and / or the second delay based on the first relative delay, and will not be described in detail here.

[0174] In the embodiment of the present application, when the electronic device updates at least one of the first delay, the second delay, and the third delay based on the first relative delay and the second relative delay, different updating methods may be used. The delay updating method is not specifically limited herein.

[0175] In an optional embodiment, according to the above Figure 2 The method shown in the embodiment of the present application also provides a method for determining the time delay. Figure 5 As shown, Figure 5This is a fourth flow chart of the delay determination method provided in an embodiment of the present application. The method includes the following steps.

[0176] Step S501: Select a cell group to be processed based on the value and line channel corresponding to each cell in the first list. The cell group to be processed includes a first cell, a second cell, and a third cell. The fourth line channel corresponding to the first cell, the second cell, and the third cell is the same, and the value of at least two cells is the first value. The first value indicates that the fourth line channel and the fifth line channel corresponding to the cell are not linked. The fourth line channel is used to transmit quantum state control signals, and the fifth line channel is used to transmit quantum bit frequency control signals.

[0177] For ease of understanding, the determination of the above-mentioned cell group to be processed is explained in conjunction with Table 4.

[0178] Table 4

[0179] XY / Z Z1 Z2 Z3 Z4 Z5 Z6 Z7 Z8 XY1 1 0 0 0 0 0 0 0 XY2 0 1 0 0 0 0 0 0 XY3 0 0 1 0 0 0 0 0 XY4 0 0 0 1 0 0 0 0

[0180] In the first table shown in Table 4 above, each row corresponds to a fourth line channel, namely XY1-XY4, and each column corresponds to a fifth line channel, namely Z1-Z8. The fourth line channel is used to transmit quantum state control signals, and the fifth line channel is used to transmit quantum bit frequency control signals.

[0181] When selecting the above-mentioned cell group to be processed, the electronic device can traverse each row in the first list, determine the value corresponding to each cell in the row, and thus select the cells where the three line channels with no associated relationship are located as the cell group to be processed.

[0182] For example, when the electronic device traverses the first row of the first list, that is, the row corresponding to XY1, only the cells corresponding to XY1 and Z1 have a value of 1, while the values ​​of the remaining cells are all 0. At this time, because the values ​​of the cells corresponding to any two fifth-line channels and XY1 are not 1 at the same time, the electronic device can determine that no link is established between any two fifth-line channels. At this time, the electronic device can obtain any three cells corresponding to the fifth-line channels and XY1 as the group of cells to be processed. For example, the electronic device can select the cells Z1, Z2, and Z3 corresponding to XY1 as the first cell, second cell, and third cell, respectively, to obtain the group of cells to be processed.

[0183] In the embodiments of the present application, the values corresponding to the first cell, the second cell and the third cell at least include two first values. For example, the values corresponding to the first cell, the second cell and the third cell can be any one of 000, 100, 010 and 001. Here, the values corresponding to the first cell, the second cell and the third cell are not specifically limited.

[0184] In the embodiments of the present application, only taking an example that each row in the first list corresponds to a fourth line channel and each column corresponds to a fifth line channel, the determination of the group of cells to be processed is described. When each column in the first list corresponds to a fourth line channel and each row corresponds to a fifth line channel, the group of cells to be processed can be determined by referring to a similar method, which is not specifically described here. Only taking an example that each row in the first list corresponds to a fourth line channel and each column corresponds to a fifth line channel, which does not have any limiting effect.

[0185] In step S502, the fifth line channels corresponding to the first cell, the second cell and the third cell are determined as the first line channel, the second line channel and the third line channel, and a group of line channels to be processed is obtained.

[0186] In this step, after determining the first cell, the second cell and the third cell, the electronic device can determine the fifth line channel corresponding to each cell. That is, the fifth line channel corresponding to the first cell is determined as the first line channel in the group of line channels to be processed; the fifth line channel corresponding to the second cell is determined as the second line channel in the group of line channels to be processed; and the fifth line channel corresponding to the third cell is determined as the third line channel in the group of line channels to be processed.

[0187] Through the above steps S501-S502, the electronic device can determine three fifth line channels in the first list that do not have an association relationship as the line channels in the group of line channels to be processed, so as to update the time delay of the three fifth line channels in the later stage, establish the association relationship between the three fifth line channels, ensure the accuracy of the determined time delay, avoid repeated update of the time delay of the line channels that already have an association relationship, and improve the association between the time delays corresponding to all fifth line channels.

[0188] The above steps S501-S502 are a refinement of the above step S201.

[0189] In step S503, the first relative time delay and the second relative time delay are obtained in the case that the first quantum bit, the second quantum bit and the first adjustable coupler establish links among the first line channel, the second line channel and the third line channel. The first relative time delay and the second relative time delay are the signal transmission time delays between any two of the first line channel, the second line channel and the third line channel.

[0190] In step S504, the first time delay, the second time delay and the third time delay corresponding to the current time of the first line channel, the second line channel and the third line channel are respectively searched. The first time delay, the second time delay and the third time delay are preset time delays or time delays obtained by updating before the current time.

[0191] In step S505, at least one of the first time delay, the second time delay and the third time delay is updated based on the first relative time delay and the second relative time delay.

[0192] The steps S503-S505 are the same as the steps S202-S204.

[0193] In an optional embodiment, according to the method shown in the above Figure 5 The embodiment of the present application also provides a time delay determination method. As shown in the above Figure 6 Figure 6 The fifth flowchart of the time delay determination method provided by the embodiment of the present application. The method adds the following steps, i.e., steps S506-S507.

[0194] In step S506, the value of the cell corresponding to the update line channel in the to-be-processed line channel group is updated to a second value. The second value indicates that the fourth line channel and the fifth line channel corresponding to the cell establish links. The update line channel is the line channel whose time delay is updated.

[0195] In this step, after the electronic device updates the time delay of at least one fifth line channel in the first line channel, the second line channel and the third line channel through the step S505, the electronic device can determine the line channel whose time delay is updated as the update line channel. When the value of the cell corresponding to the update line channel in the to-be-processed line channel group is the first value, the electronic device updates the first data to the second value.

[0196] The update line channel can be one or more of the first line channel, the second line channel and the third line channel. Herein, the update line channel is not specifically limited.

[0197] ​For ease of understanding, the example in which the updated delay in step S505 is the first delay is used. Because the updated delay is the first delay, the electronic device can determine that the updated line channel is the first line channel. In this case, the cell in the pending line channel group corresponding to the updated line channel is the first cell, and the electronic device can update the value of the first cell to a second value, such as 1.

[0198] In an embodiment of the present application, with respect to the above-mentioned updated line channels, the electronic device can, through the above-mentioned step S506, promptly update the values ​​of the first cell, the second cell, or the third cell in the first list after the delay update, thereby promptly completing the establishment of the association relationship between the above-mentioned first line channel, the second line channel, and the third line channel, thereby avoiding the three fifth line channels from being reselected as line channels in the line channel group to be processed in the later stage, thereby avoiding waste of computing resources.

[0199] Step S507 , when the first list includes the cell group to be processed, returns to the step of selecting the cell group to be processed according to the value and line channel corresponding to each cell in the first list, until the first list does not include the cell group to be processed.

[0200] In this step, the electronic device completes one round of delay updates for the corresponding line channels after updating the values ​​of the cells corresponding to the updated line channels in the pending line channel group to the second values. At this point, if the first list still contains three fifth line channels with no associated relationship, i.e., if a cell group to be processed exists, the electronic device can return to step S501, i.e., select a cell group to be processed based on the values ​​and line channels corresponding to each cell in the first list, until the first list contains no cell groups to be processed, thereby starting a new round of delay updates for the line channels, until the first list contains no cell groups to be processed.

[0201] Through the above-mentioned step S507, the electronic device can cyclically execute the above-mentioned steps S501-S506, so that there is a correlation between the delays of each fifth line channel in the determined quantum computing measurement and control system, thereby improving the correlation between the determined delays, and improving the accuracy of the quantum bit frequency control signal transmitted based on the updated delay, thereby improving the accuracy of quantum computing.

[0202] In an optional embodiment, according to the above Figure 6 The method shown in the embodiment of the present application also provides a method for determining the time delay. Figure 7 As shown, Figure 7 This is a sixth flow chart of the delay determination method provided in the embodiment of the present application. Figure 7The following steps are added to the method shown, namely step S508 to step S509.

[0203] Step S508 : determining a sixth line channel associated with the updated line channel based on the value and line channel corresponding to each cell in the first list.

[0204] In this step, through step S506, the electronic device can promptly update the value of the cell corresponding to the updated line channel in the pending line channel group to the second value, thereby establishing an association between the updated line channel and the other fifth line channel. At this point, the electronic device can determine the line channel associated with the updated line channel based on the value and line channel corresponding to each cell in the first list, and record this as the sixth line channel.

[0205] The number of the sixth line channels corresponding to the above-mentioned update line channel can be one or more. When the number of the sixth line channels is multiple, the sixth line channels can include the above-mentioned fourth line channel and fifth line channel. Here, the number and type of the above-mentioned sixth line channels are not specifically limited.

[0206] In an optional embodiment, when each row of the first list corresponds to a fourth line channel and each column corresponds to a fifth line channel, the embodiment of the present application provides a method for determining associated line channels. Figure 8 As shown, Figure 8 A flowchart of a method for determining associated line channels provided in an embodiment of the present application is provided. The method includes the following steps.

[0207] Step S801: Determine a column in the first list corresponding to the updated line channel as a first target column.

[0208] In this step, after updating the delay corresponding to the update line channel, the electronic device may traverse each column in the first list to determine the column corresponding to the update line channel, and determine the column as the first target column.

[0209] For ease of understanding, the following description is provided in conjunction with Table 5. Assuming that the delay updated in step S505 is the delay corresponding to Z5, the electronic device updates the cell value corresponding to Z5 and XY1 to 1 through step S506.

[0210] Table 5

[0211] XY / Z Z1 Z2 Z3 Z4 Z5 Z6 Z7 Z8 XY1 1 0 1 0 1 0 0 0 XY2 0 1 0 0 0 0 0 0 XY3 0 0 1 0 1 0 0 0 XY4 0 0 0 1 0 0 0 0

[0212] For all fifth line channels in Table 5, namely Z1-Z8, since the line channel with time delay update is Z5, the electronic device traverses each column in Table 5. When traversing the column where Z5 is located, this column can be determined as the first target column.

[0213] Step S802, a fourth line channel corresponding to the second value and not selected as the first associated line channel on the first target column is selected as the first associated line channel associated with the update line channel.

[0214] In this step, for the first target column, the electronic device can select all cells with the second value on the first target column, and select a fourth line channel not selected as the first associated line channel as the associated line channel (denoted as the first associated line channel) associated with the update line channel according to the fourth line channel corresponding to each cell.

[0215] For ease of understanding, the above table 5 is still taken as an example for description. After the column where Z5 is located is determined as the first target column, the electronic device can determine that the values corresponding to the cells 3 corresponding to XY1 and Z5 and the cells 4 corresponding to XY3 and Z5 are the second value, i.e., the value 1, according to the values corresponding to each cell. Since the fourth line channel associated with Z5 is determined as empty at this time, the electronic device can determine that XY1 and XY3 are both the fourth line channel associated with the update line channel. That is, the determined first associated line channel is XY1 and XY3.

[0216] In the embodiments of the present application, the number of the first associated line channels determined above can be empty, one or more, which is not limited here.

[0217] Step S803, if the first associated line channel is not empty, for each first target row, a fifth line channel corresponding to the second value and not selected as the second associated line channel on the first target row is selected as the second associated line channel associated with the update line channel, and the first target row is the row corresponding to the first associated line channel in the first list.

[0218] In this step, when the first associated line channel determined above is not empty, for each first associated line channel determined, the electronic device can determine the row corresponding to the first associated line channel in the first list as the first target row. For each first target row, the electronic device can determine all cells with the second value in the first target row, and select a fifth line channel not selected as the second associated line channel as the associated line channel (denoted as the second associated line channel) associated with the update line channel according to the fifth line channel corresponding to each cell.

[0219] For ease of understanding, the above table 5 is still taken as an example for description. Through the above step S802, the electronic device determines that the first associated line channel is XY1 and XY3. The electronic device can determine the row where XY1 and XY3 are located as the first target row.

[0220] For the row where XY1 is located, the electronic device can determine through traversal that the values ​​corresponding to cell 5 corresponding to XY1 and Z1, cell 6 corresponding to XY1 and Z3, and cell 7 corresponding to XY1 and Z5 are all 1. Since the number of second-associated line channels determined at this time is empty, and Z5 itself is an update line channel, the electronic device can determine that Z1 and Z3 are both the fifth line channels associated with the update line channel. In other words, the second-associated line channels determined are: Z1 and Z3.

[0221] For the row where XY3 is located, since Z3 has been determined as the second associated line channel and Z5 itself is the updated line channel, the second associated line channel determined based on XY3 is empty.

[0222] In an optional embodiment, when the number of the first associated line channels determined above is empty, the electronic device may determine that there is no line channel associated with the updated line channel at the current moment.

[0223] Step S804: for each second-associated line channel, determine the column corresponding to the second-associated line channel in the first list as the first target column, and return to the step of selecting the fourth line channel on the first target column that has not been selected as the first-associated line channel and whose corresponding value is the second value as the first-associated line channel associated with the updated line channel, until the first-associated line channel determined based on all second-associated channels is empty, or until the second-associated line channel determined based on all first-associated line channels is empty.

[0224] In this step, for each second associated line channel, the electronic device can determine the column corresponding to the second associated line channel as the above-mentioned first target column, and return to execute the above-mentioned step S802, that is, return to execute the step of selecting the fourth line channel on the first target column that has not been selected as the first associated line channel and whose corresponding value is the second value as the first associated line channel associated with the updated line channel.

[0225] In this embodiment of the present application, during each round of determining the first associated line channel and each round of determining the second associated line channel, if the second associated line channel determined based on each first associated line channel is empty, or if the first associated line channel determined based on each second associated line channel is empty, the electronic device may have determined all associated line channels associated with the updated line channel. In this case, the electronic device may stop the process of determining the associated line channel.

[0226] For ease of understanding, Table 5 is used as an example. The second associated line channels determined in step S803 are: Z1 and Z3. The electronic device can determine the columns containing Z1 and Z3 in the first list as the first target columns. Since XY1, corresponding to the cell with a value of 1 in the column containing Z1, has already been determined as the first associated line channel, and XY1 and XY3, corresponding to the cell with a value of 1 in the column containing Z3, have also been determined as the first associated line channel, the electronic device can therefore determine that all associated line channels associated with Z5 have been found, namely, XY1, XY3, Z1, and Z3.

[0227] Step S805: Determine the union of the first associated line channel and the second associated line channel as the sixth line channel associated with the updated line channel.

[0228] In this step, for each round of determined first associated line channels and second associated line channels, the electronic device may obtain the union of all first associated line channels and all second associated line channels to obtain a sixth line channel associated with the updated line channel.

[0229] In the embodiment of the present application, after the electronic device completes the search process for the first associated line channel and the second associated line channel, all the first associated line channels and all the second associated line channels found are the sixth line channel. Figure 8 In the embodiment shown, step S805 is added. In actual application, the electronic device may not perform the above step S805.

[0230] Through the above steps S801 to S805, the electronic device can determine all sixth line channels associated with the updated line channel by looping through the first list, effectively improving the accuracy and completeness of the determined sixth line channels, laying the foundation for the subsequent synchronous update of the corresponding delays of the associated line channels, improving the correlation between the corresponding delays of each fifth line channel, and improving the accuracy of the determined delays.

[0231] The above steps S801 to S805 are refinements of the above step S508.

[0232] Step S509: Update the fourth delay of the sixth line channel at the current moment according to the delay update amount corresponding to the updated line channel.

[0233] In this step, after determining all the sixth line channels corresponding to the update line channel, the electronic device may update the delay corresponding to each sixth line channel according to the delay update amount corresponding to the update line channel.

[0234] The delay update method for the sixth line channel is the same as the delay update method for the updated line channel. For example, if the delay update method for the updated line channel is to increase a certain time, the delay corresponding to each sixth line channel will also be increased by the same time. For another example, if the delay update method for the updated line channel is to decrease a certain time, the delay corresponding to each sixth line channel will also be decreased by the same time.

[0235] For ease of understanding, the description is still made using the above Table 5 as an example. Through the above steps S801 to S805, the electronic device can determine that the associated line channels associated with Z5 are XY1, XY3, Z1 and Z3.

[0236] If the electronic device increases the delay of Z5 by Δ when updating the delay of Z5, the electronic device may increase the delays corresponding to XY1, XY3, Z1 and Z3 in the second list and the third list by Δ respectively.

[0237] The delay update amount of the above-mentioned updated delay line channel may be the difference between the delay after the update and the delay before the update.

[0238] Through the above steps S508 and S509, the electronic device can synchronously update the delay of all sixth line channels associated with the updated line channel according to the delay update amount of the updated line channel, effectively ensuring the association relationship between the updated line channel and its associated line channels, and improving the association between each line channel.

[0239] In an optional embodiment, according to the above Figure 6 The method shown in the embodiment of the present application also provides a method for determining the time delay. Figure 9 As shown, Figure 9 This is a seventh flow chart of the delay determination method provided in the embodiment of the present application. Figure 9 The following steps are added to the method shown, namely step S510 - step S511.

[0240] Step S510 : In the second target column of the first list, the fourth line channel corresponding to the cell with the second value is selected as the seventh line channel. The second target column corresponds to a line channel corresponding to the first relative delay or the second relative delay.

[0241] In an optional embodiment, after the electronic device updates the value of the cell corresponding to the updated line channel in the pending line channel group to a second value, if the delay of the updated line channel is updated based on the first relative delay, the electronic device may determine the column corresponding to one of the two line channels corresponding to the first relative delay in the first list as the second target column. The electronic device may traverse each cell in the second target column and select the fourth line channel corresponding to the cell with the second value as the seventh line channel.

[0242] In another optional embodiment, after the electronic device updates the value of the cell corresponding to the updated line channel in the pending line channel group to a second value, if the delay of the updated line channel is updated based on the second relative delay, the electronic device may determine the column corresponding to one of the two line channels corresponding to the second relative delay in the first list as the second target column. The electronic device may traverse each cell in the second target column and select the fourth line channel corresponding to the cell with the second value as the seventh line channel.

[0243] The number of the seventh line channel can be empty, one or more. Here, the number of the seventh line channel determined above is not specifically limited.

[0244] In an optional embodiment, when the number of the seventh line channels determined in the above step S510 is empty, the electronic device may not perform any processing, that is, the electronic device may not execute step S511.

[0245] Step S511: for each seventh line channel, update the value of the cell corresponding to the seventh line channel and the eighth line channel in the first list to the second value; the eighth line channel is another line channel corresponding to the first relative delay or the second relative delay.

[0246] In an optional embodiment, if the delay update of the updated line channel is based on the first relative delay, then after determining the seventh line channel, the electronic device may determine, for each seventh line channel, whether the value of the cell corresponding to the seventh line channel and another line channel corresponding to the first relative delay (referred to as the eighth line channel) is the second value. If the value of the cell corresponding to the seventh line channel and the eighth line channel is not the second value, the value of the cell is updated to the second value.

[0247] In another optional embodiment, if the time delay of the updating line channel is updated according to the second relative time delay, after determining the seventh line channel, the electronic device can determine, for each seventh line channel, whether the value of the cell corresponding to the seventh line channel and the other line channel (denoted as the eighth line channel) corresponding to the second relative time delay is the second value. If the value of the cell corresponding to the seventh line channel and the eighth line channel is not the second value, the value of the cell is updated to the second value.

[0248] In an optional embodiment, when the value of the cell corresponding to the seventh line channel and the eighth line channel is the second value, the electronic device can not perform any processing, that is, the electronic device will not update the value corresponding to the cell.

[0249] For ease of understanding, still taking Table 5 as an example for illustration. It is assumed that after updating the time delay of Z5 according to the relative time delay between Z1 and Z5, the value of the cell corresponding to Z5 and XY1 is updated to 1.

[0250] In the execution of the above step S510, the electronic device can determine any one of the columns of Z1 and Z5 as the second target column, for example, the column where Z5 is located is determined as the second target column. At this time, the electronic device can traverse each row in the first list to determine the fourth line channel corresponding to the cell with a value of 1 in the second target column. For example, in Table 5, the cells with a value of 1 are the cells corresponding to Z5, XY1 and XY3. The electronic device can determine that the above seventh line channel is XY1 and XY3.

[0251] In the execution of the above step S510, for the seventh line channel XY1, since the value of the cell corresponding to Z1 and XY1 in Table 5 is 1, the electronic device can not perform updating operation. For the seventh line channel XY3, since the value of the cell corresponding to Z1 and XY3 in Table 5 is 0, at this time, the electronic device can update the value of the cell to 1.

[0252] Through the above steps S510-S511, after the value of the cell corresponding to the updating line channel in the group of line channels to be processed is updated to the second value, by updating the values of the above seventh line channel and eighth line channel to the second value, the electronic device can make the two line channels corresponding to the first relative time delay and / or the second relative time delay in the first list establish a link, so that in the subsequent time delay updating process, the two line channels corresponding to the first relative time delay and / or the second relative time delay will not be determined as the line channels in the above group of line channels to be processed again, and in the subsequent time delay updating process, the time delays corresponding to the two line channels can be updated synchronously with the updating amount of the time delays corresponding to the associated line channels, thereby improving the accuracy of the time delay updating.

[0253] In an optional embodiment, according to the method shown in the above Figure 6 The embodiment of the present application also provides a time delay determination method. As shown in the above Figure 10 Figure 10 The eighth flowchart of the time delay determination method provided by the embodiment of the present application is shown in the above Figure 10 The method shown in the above is increased by the following steps, i.e., step S512-step S513.

[0254] In step S512, the minimum fifth time delay is selected according to the fifth time delay corresponding to each ninth line channel at the current time. The ninth line channel is all the fifth line channels whose time delays are updated before the current time.

[0255] In this step, after updating the time delay corresponding to the above-mentioned updated line channel, the electronic device can determine all the fifth line channels whose time delays are updated before the current time in the above-mentioned second list as the ninth line channel. The electronic device can select the minimum fifth time delay according to the time delay (denoted as the fifth time delay) corresponding to each ninth line channel in the second list.

[0256] In step S513, if the minimum fifth time delay is not equal to the third value, the fifth time delay of each ninth line channel is updated to the difference between the fifth time delay of the ninth line channel and the minimum fifth time delay.

[0257] In this step, the electronic device can compare the minimum fifth time delay with the third value. If the minimum fifth time delay is not equal to the third value, the electronic device can update the time delay of each ninth line channel. That is, for each ninth line channel, the electronic device can subtract the minimum fifth time delay from the time delay of the ninth line channel. The third value can be 0.

[0258] In an optional embodiment, when the minimum fifth time delay is equal to the third value, the electronic device can not make any processing, that is, the electronic device will not update the time delay of each ninth line channel.

[0259] Through the above steps S512-step S513, when the minimum fifth time delay is not equal to the third value, the electronic device can update the time delay of each ninth line channel, so that the minimum value of the updated time delay of all the ninth line channels is 0, and in the case of ensuring that the time difference between the time delays corresponding to each ninth line channel is unchanged, the size of the time delay corresponding to each ninth line channel is effectively reduced, thereby reducing the calculation amount of the subsequent time delay update and improving the efficiency of the later time delay update.

[0260] ​In an optional embodiment, in addition to updating the delay of each of the ninth line channels mentioned above, the electronic device can also use a similar method to synchronously update the delay corresponding to the line channels whose delays are updated before the current moment in the third list above, which is not described in detail here.

[0261] In an optional embodiment, according to the above Figure 2 The method shown in the embodiment of the present application also provides a method for determining the time delay. Figure 11 As shown, Figure 11 This is a ninth flow chart of the delay determination method provided in the embodiment of the present application. Figure 11 The following steps are added to the method shown, namely, step S205 to step S206.

[0262] In step S205, when the first line channel, the second line channel, and the third line channel are linked through the third quantum bit, the fourth quantum bit, and the second adjustable coupler, if an enable signal for the third quantum bit, the fourth quantum bit, and the second adjustable coupler is received, the sixth delay of the first line channel, the seventh delay of the second line channel, and the eighth delay of the third line channel at the current moment are found.

[0263] In this step, the first, second, and third line channels can establish links via the third qubit, fourth qubit, and second tunable coupler. For example, the first line channel establishes a connection with the Z-line interface of the third qubit, the second line channel establishes a connection with the Z-line interface of the fourth qubit, and the third line channel establishes a connection with the Z-line interface of the second tunable coupler. At this point, if the electronic device receives an enable signal for the third qubit, the fourth qubit, and the second tunable coupler, the electronic device can determine the sixth delay corresponding to the first line channel, the seventh delay corresponding to the second line channel, and the eighth delay corresponding to the third line channel based on the second list at the current moment.

[0264] The third qubit, the fourth qubit and the second adjustable coupler may be the same as or different from the first qubit, the second qubit and the first adjustable coupler, and are not specifically limited here.

[0265] Step S206: Based on the time difference between the sixth delay, the seventh delay, and the eighth delay, the quantum bit frequency control signal is transmitted to the third quantum bit, the fourth quantum bit, and the second adjustable coupler using the first line channel, the second line channel, and the third line channel, respectively.

[0266] In this step, the electronic device can determine the time difference between the sixth, seventh, and eighth time delays based on the aforementioned delays. Based on the time difference, the electronic device can transmit a qubit frequency control signal to the third qubit, the fourth qubit, and the second tunable coupler via the first, second, and third line channels, respectively.

[0267] For ease of understanding, the sixth delay is greater than the seventh delay and greater than the eighth delay. Now assume that the time difference between the sixth delay and the seventh delay is t1, and the time difference between the seventh delay and the eighth delay is t2.

[0268] At time t, the electronic device uses the third line channel to transmit the quantum bit frequency control signal to the second adjustable coupler. At t+t2, the electronic device can use the second line channel to transmit the quantum bit frequency control signal to the fourth quantum bit. At t+t2+t1, the electronic device can use the first line channel to transmit the quantum bit frequency control signal to the third quantum bit.

[0269] In the above embodiment, the transmission of the qubit frequency control signal using the first, second, and third circuit channels is described as an example. Alternatively, the electronic device can transmit the qubit frequency control signal based on the time delays corresponding to any three fifth circuit channels in the second list at the current moment. The specific process can be found in the above description and is not detailed here.

[0270] Through the above steps S205-S206, the electronic device can transmit the quantum bit frequency control signal according to the time delay corresponding to any three fifth line channels in the second list at the current moment, so that the three-way quantum bit frequency control signal can reach two quantum bits and one adjustable coupler at the same time, ensuring the accuracy of quantum computing.

[0271] In the above embodiment, only the delay update corresponding to three fifth-line channels is used as an example for description. Furthermore, signal transmission delays may exist between the fourth and fifth-line channels due to differences in line length, components on the lines, and so on. Therefore, for each group of fourth and fifth-line channels, the electronic device can update the current delay of the group of fourth and fifth-line channels based on the relative delay between the group of fourth and fifth-line channels. The specific update method can refer to the update method described in step S2041 or step S2042 above and is not described in detail here. Accordingly, after the current delay of the group of fourth and fifth-line channels is updated, the delay of the associated channel corresponding to the updated fourth or fifth-line channel is synchronously updated. For details, refer to the description of steps S508 and S509 above and are not described in detail here.

[0272] Based on the same inventive concept, according to the time delay determination method provided by the embodiment of the application, the embodiment of the application further provides a time delay determination device. As shown in Figure 12 Figure 12 A structural schematic diagram of the time delay determination device provided by the embodiment of the application. The device comprises the following modules.

[0273] The first determination module 1201 is configured to determine a to-be-processed line channel group in the quantum computing measurement and control system, the to-be-processed line channel group comprising a first line channel, a second line channel and a third line channel for transmitting a quantum bit frequency regulation signal.

[0274] The acquisition module 1202 is configured to, in a case where the first line channel, the second line channel and the third line channel establish a link through a first quantum bit, a second quantum bit and a first adjustable coupler, acquire a first relative time delay and a second relative time delay, the first relative time delay and the second relative time delay being a signal transmission time delay between any two of the first line channel, the second line channel and the third line channel.

[0275] The searching module 1203 is configured to search for a first time delay, a second time delay and a third time delay corresponding to the current time of the first line channel, the second line channel and the third line channel respectively; the first time delay, the second time delay and the third time delay being a preset time delay or a time delay obtained by updating before the current time.

[0276] The first updating module 1204 is configured to update at least one of the first time delay, the second time delay and the third time delay based on the first relative time delay and the second relative time delay.

[0277] Optionally, the first determination module 1201 can be specifically configured to select a to-be-processed cell group according to a value corresponding to each cell in the first list and a line channel, the to-be-processed cell group comprising a first cell, a second cell and a third cell, the first cell, the second cell and the third cell corresponding to a fourth line channel, and the values of at least two cells being a first value, the first value indicating that the fourth line channel and a fifth line channel corresponding to the cells have not established a link, the fourth line channel being used for transmitting a quantum state regulation signal, and the fifth line channel being used for transmitting a quantum bit frequency regulation signal.

[0278] The fifth line channel corresponding to the first cell, the second cell and the third cell is determined as the first line channel, the second line channel and the third line channel, and a to-be-processed line channel group is obtained.

[0279] Optionally, the time delay determination device can further comprise:

[0280] ​The second updating module is configured to update the value of the cell corresponding to the updating link path in the to-be-processed link path group to a second value after updating at least one of the first time delay, the second time delay and the third time delay based on the first relative time delay and the second relative time delay, where the second value indicates that the fourth link path and the fifth link path corresponding to the cell are linked, and the updating link path is the time delay updating link path.

[0281] The time delay determination apparatus can further include:

[0282] The calling module is configured to call the first determination module 1201 to return to execute the step of selecting the to-be-processed cell group according to the value and the link path corresponding to each cell in the first list until the to-be-processed cell group is not included in the first list when the to-be-processed cell group is included in the first list.

[0283] Optionally, the time delay determination apparatus can further include:

[0284] The second determination module is configured to determine the sixth link path associated with the updating link path based on the value and the link path corresponding to each cell in the first list after updating the value of the cell corresponding to the updating link path to the second value according to the value and the link path corresponding to each cell in the first list.

[0285] The third updating module is configured to update the fourth time delay of the sixth link path at the current time according to the time delay updating amount corresponding to the updating link path.

[0286] Optionally, the second determination module can be specifically configured to determine a first target column as the column corresponding to the updating link path in the first list if each row of the first list corresponds to a fourth link path and each column corresponds to a fifth link path.

[0287] The fourth link path on the first target column that is not selected as the first associated link path and corresponds to the second value is selected as the first associated link path associated with the updating link path.

[0288] If the first associated link path is not empty, for each first target row, the fifth link path on the first target row that is not selected as the second associated link path and corresponds to the second value is selected as the second associated link path associated with the updating link path, and the first target row is the row corresponding to the first associated link path in the first list.

[0289] For each second associated line channel, determine the column corresponding to the second associated line channel in the first list as the first target column, and return to the step of selecting a fourth line channel in the first target column that has not been selected as the first associated line channel and whose corresponding value is the second value as the first associated line channel associated with the updated line channel, until the first associated line channel determined based on all the second associated lines is empty, or until the second associated line channel determined based on all the first associated lines is empty;

[0290] A union of the first associated line channel and the second associated line channel is determined as a sixth line channel associated with the update line channel.

[0291] Optionally, the delay determination device may further include:

[0292] a selection module, configured to select, in the second target column of the first list, the fourth line channel corresponding to the cell having the second value as the seventh line channel, the second target column corresponding to a line channel corresponding to the first relative delay or the second relative delay;

[0293] The fourth updating module is configured to update the values ​​of the cells corresponding to the seventh line channel and the eighth line channel in the first list to the second values ​​for each seventh line channel; the eighth line channel is another line channel corresponding to the first relative delay or the second relative delay.

[0294] Optionally, the acquisition module 1202 may be specifically configured to acquire, when the first line channel, the second line channel, and the third line channel are linked through the first qubit, the second qubit, and the adjustable coupler, a first transmission duration corresponding to the first line channel, a second transmission duration corresponding to the second line channel, and a third transmission duration corresponding to the third line channel;

[0295] If the second transmission duration is less than the first transmission duration and the third transmission duration, the difference between the first transmission duration and the second transmission duration is calculated as the first relative delay between the first line channel and the second line channel, and the difference between the third transmission duration and the first transmission duration is calculated as the second relative delay between the third line channel and the second line channel.

[0296] Optionally, the first updating module 1204 may be configured to update the first delay and / or the second delay based on the first relative delay;

[0297] Based on the second relative delay, the second delay and / or the third delay is updated.

[0298] Optionally, the first updating module 1204 may be configured to update the first delay to a first sum value if the first delay is greater than the second delay and when the first difference is less than the first relative delay;

[0299] When the first difference is greater than the first relative delay, updating the second delay to the second difference;

[0300] or,

[0301] If the first delay is less than the second delay, then when the third difference is less than the first relative delay, the second delay is updated to the second sum value;

[0302] When the third difference is greater than the first relative delay, updating the first delay to a fourth difference;

[0303] Among them, the first difference is the difference between the first delay and the second delay, the first sum is the sum of the second delay and the first relative delay, and the second difference is the difference between the first delay and the first relative delay; the third difference is the difference between the second delay and the first delay, the second sum is the sum of the first delay and the first relative delay, and the fourth difference is the difference between the second delay and the first relative delay.

[0304] Optionally, the first updating module 1204 may be configured to update the second delay to a third sum value if the second delay is greater than the third delay and when the fifth difference is less than the second relative delay;

[0305] When the fifth difference is greater than the second relative delay, updating the third delay to the sixth difference;

[0306] or;

[0307] If the second delay is less than the third delay, then when the seventh difference is less than the second relative delay, the third delay is updated to the fourth sum value;

[0308] When the seventh difference is greater than the second relative delay, updating the second delay to the eighth difference;

[0309] Among them, the fifth difference is the difference between the second delay and the third delay, the third sum is the sum of the third delay and the second relative delay, the sixth difference is the difference between the second delay and the second relative delay, the seventh difference is the difference between the third delay and the second delay, the fourth sum is the sum of the second delay and the second relative delay, and the eighth difference is the difference between the third delay and the second relative delay.

[0310] Optionally, the delay determination device may further include:

[0311] After the value of the cell corresponding to the number value and the line channel in the first list is updated to the second value, the minimum fifth time delay is selected according to the fifth time delay corresponding to each ninth line channel at the current time; the ninth line channel is all the fifth line channel whose time delay is updated before the current time;

[0312] If the minimum fifth time delay is not equal to the third value, the fifth time delay of each ninth line channel is updated to the difference between the fifth time delay of the ninth line channel and the minimum fifth time delay.

[0313] Optionally, the time delay determination device can further include:

[0314] In the case that the first line channel, the second line channel and the third line channel establish a link through the third quantum bit, the fourth quantum bit and the second adjustable coupler, if an enable signal for the third quantum bit, the fourth quantum bit and the second adjustable coupler is received, the sixth time delay of the first line channel, the seventh time delay of the second line channel and the eighth time delay of the third line channel at the current time are found.

[0315] According to the time difference between the sixth time delay, the seventh time delay and the eighth time delay, the first line channel, the second line channel and the third line channel are respectively used to transmit quantum bit frequency control signals to the third quantum bit, the fourth quantum bit and the second adjustable coupler.

[0316] Through the device provided by the embodiment of the application, in the case that the determined first line channel, second line channel and third line channel in the quantum computing measurement and control system establish a link through the first quantum bit, the second quantum bit and the first adjustable coupler, two groups of signal transmission time delays between any two line channels, i.e., the first relative time delay and the second relative time delay, are obtained, and at least one of the first time delay corresponding to the first line channel, the second time delay corresponding to the second line channel and the third time delay corresponding to the third line channel at the current time is updated based on the first relative time delay and the second relative time delay, which can realize the determination of the signal transmission time delay between the magnetic flux modulation line channels in the quantum computing measurement and control system.

[0317] Since the update of at least one of the first time delay, the second time delay and the third time delay is based on the first relative time delay and the second relative time delay, the updated time delay is matched with the first relative time delay and the second relative time delay, which effectively guarantees the accuracy of the updated time delay, so that the quantum bit frequency control signals transmitted based on the updated time delay can reach the quantum bit and the adjustable coupler at the same time when the multi-quantum bit gate operation is performed, and the accuracy of quantum computing is effectively improved.

[0318] In addition, when the first delay, the second delay or the third delay is a delay obtained before the current time, the correlation of the delays of the respective line channels can be effectively established when the first relative delay and the second relative delay between any two of the first line channel, the second line channel and the third line channel are updated, so that the determined delays of each line channel are associated with each other, and the accuracy and correlation of the determined delays are effectively improved. Moreover, once the line channel is replaced, since the determined delay is bound to each line channel, the signal transmission can be directly performed according to the determined delay, without the need to re-determine the delay, thereby improving the applicability of the determined delay.

[0319] Based on the same inventive concept, according to the delay determination method provided in the above embodiments of the present application, the present application further provides an electronic device, as shown in the accompanying drawings, comprising a processor 1301, a communication interface 1302, a memory 1303 and a communication bus 1304, wherein the processor 1301, the communication interface 1302 and the memory 1303 are in communication with each other through the communication bus 1304, Figure 13

[0320] The memory 1303 is used to store a computer program.

[0321] The processor 1301 is used to execute the program stored in the memory 1303, and the following steps are implemented:

[0322] Determining a to-be-processed line channel group in a quantum computing measurement and control system, the to-be-processed line channel group comprising a first line channel, a second line channel and a third line channel for transmitting a quantum bit frequency regulation signal;

[0323] In a case where the first line channel, the second line channel and the third line channel are linked through a first quantum bit, a second quantum bit and a first adjustable coupler, obtaining a first relative delay and a second relative delay, the first relative delay and the second relative delay being signal transmission delays between any two of the first line channel, the second line channel and the third line channel;

[0324] Respectively finding a first delay, a second delay and a third delay corresponding to the first line channel, the second line channel and the third line channel at the current time; the first delay, the second delay and the third delay being preset delays or delays obtained before the current time;

[0325] Based on the first relative delay and the second relative delay, updating at least one of the first delay, the second delay and the third delay.

[0326] ​Through the electronic device provided in the embodiments of the present application, when the first line channel, the second line channel, and the third line channel in the determined quantum computing measurement and control system are linked through the first quantum bit, the second quantum bit, and the first adjustable coupler, by obtaining two sets of signal transmission delays between any two line channels, namely, the first relative delay and the second relative delay, at least one of the first delay corresponding to the first line channel, the second delay corresponding to the second line channel, and the third delay corresponding to the third line channel at the current moment is updated based on the first relative delay and the second relative delay. This can achieve the determination of the signal transmission delay between each flux modulation line channel in the quantum computing measurement and control system.

[0327] Since at least one of the first delay, the second delay and the third delay is updated based on the first relative delay and the second relative delay, the updated delay matches the first relative delay and the second relative delay, which effectively ensures the accuracy of the updated delay. Therefore, when performing multi-qubit gate operations, the qubit frequency control signal transmitted based on the updated delay can reach the qubit and the adjustable coupler at the same time, effectively improving the accuracy of quantum computing.

[0328] Furthermore, when the first, second, or third delay is a delay updated prior to the current moment, updating the delay based on the first and second relative delays between any two of the first, second, and third line channels effectively establishes a correlation between the delays of the individual line channels, ensuring that the delays ultimately determined for each line channel are correlated with each other, effectively improving the accuracy and relevance of the determined delays. Furthermore, if a line channel is replaced, since the determined delay is bound to each line channel, signal transmission can be performed directly based on the determined delay without requiring a new delay determination, thereby improving the applicability of the determined delay.

[0329] The communication bus mentioned in the electronic device mentioned above may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used in the figure, but this does not mean that there is only one bus or only one type of bus.

[0330] The communication interface is used for communication between the above electronic device and other devices.

[0331] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk memory. Alternatively, the memory may be at least one storage device located away from the processor.

[0332] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0333] Based on the same inventive concept, according to the delay determination method provided in the above-mentioned embodiments of the present application, the embodiments of the present application also provide a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps of any of the above-mentioned delay determination methods.

[0334] Based on the same inventive concept, according to the delay determination method provided in the above-mentioned embodiments of the present application, the embodiments of the present application also provide a computer program product containing instructions, which, when executed on a computer, enables the computer to execute any of the delay determination methods in the above-mentioned embodiments.

[0335] Based on the same inventive concept, according to the delay determination method provided in the above-mentioned embodiments of the present application, the embodiments of the present application also provide a quantum computing measurement and control system to implement any of the above-mentioned delay determination methods.

[0336] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0337] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0338] Each embodiment in this specification is described in a related manner. Similar portions between embodiments can be referenced to each other. Each embodiment focuses on the differences between other embodiments. In particular, for embodiments such as apparatus, electronic equipment, computer-readable storage medium, computer program product, and quantum computing and measurement and control system, since they are generally similar to method embodiments, their descriptions are relatively simplified. For relevant portions, reference can be made to the descriptions of the method embodiments.

[0339] The above merely provides the preferred embodiments of the application, and not intended to limit the protection scope of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall fall within the protection scope of the application.

Claims

1. A method for determining a time delay, characterized in that: The method comprises: Determine a line channel group to be processed in a quantum computing measurement and control system, where the line channel group to be processed includes a first line channel, a second line channel, and a third line channel for transmitting a quantum bit frequency control signal; When the first line channel, the second line channel, and the third line channel are linked through the first qubit, the second qubit, and the first tunable coupler, obtaining a first relative delay and a second relative delay, where the first relative delay and the second relative delay are differences between signal transmission times of any two line channels among the first line channel, the second line channel, and the third line channel; respectively searching for a first delay, a second delay, and a third delay corresponding to the first line channel, the second line channel, and the third line channel at a current moment; the first delay, the second delay, and the third delay are preset delays, or delays updated before the current moment; At least one of the first delay, the second delay, and the third delay is updated based on the first relative delay and the second relative delay.

2. The method according to claim 1, characterized in that The step of determining the line channel group to be processed in the quantum computing measurement and control system includes: Selecting a cell group to be processed based on the value and circuit channel corresponding to each cell in the first list, the cell group to be processed including a first cell, a second cell, and a third cell, the fourth circuit channel corresponding to the first cell, the second cell, and the third cell is the same, and the value of at least two cells is a first value, the first value indicates that the fourth circuit channel and the fifth circuit channel corresponding to the cell are not linked, the fourth circuit channel is used to transmit a quantum state control signal, and the fifth circuit channel is used to transmit a quantum bit frequency control signal; The fifth line channels corresponding to the first cell, the second cell, and the third cell are determined as the first line channel, the second line channel, and the third line channel to obtain a line channel group to be processed.

3. The method according to claim 2, characterized in that After updating at least one of the first delay, the second delay, and the third delay based on the first relative delay and the second relative delay, the method further includes: Updating the value of the cell corresponding to the updated line channel in the to-be-processed line channel group to a second value, wherein the second value indicates that a link is established between the fourth line channel and the fifth line channel corresponding to the cell, and the updated line channel is a line channel with a time delay update; The method further comprises: When the first list includes the cell group to be processed, the step of selecting the cell group to be processed according to the value and line channel corresponding to each cell in the first list is returned to execution until the first list does not include the cell group to be processed.

4. The method according to claim 3, characterized in that After updating the value of the cell corresponding to the updated line channel to a second value based on the value and line channel corresponding to each cell in the first list, the method further includes: determining a sixth line channel associated with the updated line channel based on a value and a line channel corresponding to each cell in the first list; The fourth delay of the sixth line channel at the current moment is updated according to the delay update amount corresponding to the updated line channel.

5. The method according to claim 4, characterized in that If each row of the first list corresponds to a fourth line channel and each column corresponds to a fifth line channel, then the step of determining the sixth line channel associated with the updated line channel based on the value and line channel corresponding to each cell in the first list includes: Determine the column in the first list corresponding to the update line channel as a first target column; selecting a fourth line channel on the first target column that is not selected as the first associated line channel and whose corresponding value is the second value as the first associated line channel associated with the updated line channel; If the first associated line channel is not empty, then for each first target row, selecting a fifth line channel on the first target row that has not been selected as the second associated line channel and whose corresponding value is the second value as the second associated line channel associated with the updated line channel, where the first target row is the row in the first list corresponding to the first associated line channel; For each second associated line channel, determining the column corresponding to the second associated line channel in the first list as the first target column, and returning to the step of selecting a fourth line channel that has not been selected as the first associated line channel in the first target column and has a corresponding value of the second value as the first associated line channel associated with the updated line channel, until the first associated line channel determined based on all the second associated channels is empty, or until the second associated line channel determined based on all the first associated line channels is empty; A union of the first associated line channel and the second associated line channel is determined as a sixth line channel associated with the update line channel.

6. The method according to claim 3, characterized in that After updating the value of the cell corresponding to the updated line channel to a second value based on the value and line channel corresponding to each cell in the first list, the method further includes: In the second target column of the first list, the fourth line channel corresponding to the cell having the second value is selected as the seventh line channel, and the second target column corresponds to a line channel corresponding to the first relative delay or the second relative delay; For each seventh line channel, the values ​​of the cells corresponding to the seventh line channel and the eighth line channel in the first list are updated to the second value; the eighth line channel is another line channel corresponding to the first relative delay or the second relative delay.

7. The method according to claim 1, characterized in that The step of obtaining the first relative delay and the second relative delay when the first line channel, the second line channel, and the third line channel are linked via the first qubit, the second qubit, and the first adjustable coupler includes: When the first line channel, the second line channel, and the third line channel are linked through the first qubit, the second qubit, and the adjustable coupler, obtaining a first transmission duration corresponding to the first line channel, a second transmission duration corresponding to the second line channel, and a third transmission duration corresponding to the third line channel; If the second transmission duration is less than the first transmission duration and the third transmission duration, the difference between the first transmission duration and the second transmission duration is calculated as the first relative delay between the first line channel and the second line channel, and the difference between the third transmission duration and the first transmission duration is calculated as the second relative delay between the third line channel and the second line channel.

8. The method according to claim 7, characterized in that The step of updating at least one of the first delay, the second delay, and the third delay based on the first relative delay and the second relative delay comprises: updating the first delay and / or the second delay based on the first relative delay; Based on the second relative delay, the second delay and / or the third delay are updated.

9. The method according to claim 8, characterized in that The step of updating the first delay and / or the second delay based on the first relative delay includes: If the first delay is greater than the second delay, when the first difference is less than the first relative delay, updating the first delay to a first sum value; When the first difference is greater than the first relative delay, updating the second delay to a second difference; or, If the first delay is less than the second delay, then when the third difference is less than the first relative delay, updating the second delay to a second sum value; When the third difference is greater than the first relative delay, updating the first delay to a fourth difference; Among them, the first difference is the difference between the first delay and the second delay, the first sum is the sum of the second delay and the first relative delay, and the second difference is the difference between the first delay and the first relative delay; the third difference is the difference between the second delay and the first delay, the second sum is the sum of the first delay and the first relative delay, and the fourth difference is the difference between the second delay and the first relative delay.

10. The method according to claim 8, characterized in that The step of updating the second delay and / or the third delay based on the second relative delay includes: If the second delay is greater than the third delay, when the fifth difference is less than the second relative delay, updating the second delay to a third sum value; When the fifth difference is greater than the second relative delay, updating the third delay to a sixth difference; or; If the second delay is less than the third delay, when the seventh difference is less than the second relative delay, updating the third delay to a fourth sum value; When the seventh difference is greater than the second relative delay, updating the second delay to an eighth difference; Among them, the fifth difference value is the difference between the second delay and the third delay, the third sum value is the sum value between the third delay and the second relative delay, the sixth difference value is the difference between the second delay and the second relative delay, the seventh difference value is the difference between the third delay and the second delay, the fourth sum value is the sum value between the second delay and the second relative delay, and the eighth difference value is the difference between the third delay and the second relative delay.

11. The method according to claim 3, characterized in that After updating the value of the cell corresponding to the updated line channel to a second value based on the value and line channel corresponding to each cell in the first list, the method further includes: Selecting the minimum fifth delay based on the fifth delay corresponding to each ninth line channel at the current moment; the ninth line channel is all fifth line channels with updated delays before the current moment; If the minimum fifth delay is not equal to the third value, then for each ninth line channel, the fifth delay of the ninth line channel is updated to the difference between the fifth delay of the ninth line channel and the minimum fifth delay.

12. The method according to claim 1, characterized in that The method further comprises: In a case where the first line channel, the second line channel, and the third line channel are linked through the third qubit, the fourth qubit, and the second tunable coupler, if an enable signal for the third qubit, the fourth qubit, and the second tunable coupler is received, finding the sixth delay of the first line channel, the seventh delay of the second line channel, and the eighth delay of the third line channel at a current moment; According to the time difference between the sixth delay, the seventh delay and the eighth delay, the first line channel, the second line channel and the third line channel are used to transmit the quantum bit frequency control signal to the third quantum bit, the fourth quantum bit and the second adjustable coupler respectively.

13. A delay determination device, characterized in that: The device comprises: A first determining module is used to determine a line channel group to be processed in a quantum computing measurement and control system, where the line channel group to be processed includes a first line channel, a second line channel, and a third line channel for transmitting a quantum bit frequency control signal; an acquisition module, configured to acquire a first relative delay and a second relative delay when the first line channel, the second line channel, and the third line channel are linked via the first qubit, the second qubit, and the first tunable coupler, where the first relative delay and the second relative delay are differences between signal transmission times of any two line channels among the first line channel, the second line channel, and the third line channel; a search module, configured to search for a first delay, a second delay, and a third delay corresponding to the first line channel, the second line channel, and the third line channel at a current moment, respectively; the first delay, the second delay, and the third delay are preset delays, or delays updated before the current moment; A first updating module is configured to update at least one of the first delay, the second delay, and the third delay based on the first relative delay and the second relative delay.

14. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory for storing computer programs; A processor, configured to implement the method steps described in any one of claims 1 to 12 when executing a program stored in a memory.

15. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps of any one of claims 1 to 12 are implemented.

Images