Wafer edge area determination method and device, equipment, medium and product
By acquiring and analyzing the combination of wafer design images and actual wafer images and determining the wafer edge region, the problem of low accuracy in the determination of wafer edge region in the prior art is solved, and higher accuracy is achieved.
Patent Information
- Application Number
- CN202411813857.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-10
- Publication Date
- 2025-03-28
AI Technical Summary
Existing methods lead to lower accuracy due to differences between different wafer design images when determining wafer edge regions.
By acquiring the wafer design image of the target product and at least one actual wafer image, the target boundary in the wafer design image near the center side of the wafer in the actual wafer image is determined according to the wafer abnormal position, and the area between it and the wafer edge of the wafer design image is determined as the wafer edge region.
The accuracy of determining the wafer edge region is improved, and the target boundary corresponding to the design characteristics of the wafer design image corresponding to the target product is accurately obtained by accurately analyzing the abnormal positions in the actual wafer image.
Smart Images
Figure CN119722718A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of semiconductor integrated circuit technology, and in particular, relates to a method, device, equipment, medium and product for determining a wafer edge area. Background Art
[0002] In integrated circuit manufacturing, due to the manufacturing equipment and the wafer itself, such as the flatness and warpage of the wafer itself, the manufacturing effect of the edge area is more unstable than other areas. Therefore, marking the edge area of the wafer to analyze and monitor the edge area of the wafer becomes a crucial link.
[0003] In the existing method, the wafer layout diagram is marked into multiple annular areas according to the same preset radius, and then other annular areas in non-edge areas are merged to achieve marking of the wafer edge area.
[0004] However, due to the differences between different wafer design images, the accuracy of the wafer edge area obtained by simply dividing the wafer design image into annular areas is low. Summary of the invention
[0005] The embodiments of the present application provide a method, device, equipment, medium and product for determining a wafer edge area, which can improve the accuracy of determining a wafer edge area.
[0006] In one aspect of an embodiment of the present application, a method for determining a wafer edge region is provided, comprising:
[0007] Acquire a wafer design image of a target product and at least one actual wafer image of the target product, wherein the wafer design image is used to characterize the arrangement of the die units of the wafer corresponding to the target product during the manufacturing process;
[0008] According to the wafer abnormal position in the actual wafer image, a target boundary of the wafer edge region close to the wafer center side in the wafer design image is determined, wherein the wafer abnormal position is any one of a defect contour point position of the wafer defect region and an abnormal grain unit position;
[0009] An area between the target boundary and the wafer edge of the wafer design image is determined as a wafer edge area of the wafer design image.
[0010] In one aspect of an embodiment of the present application, a device for determining a wafer edge area is provided, comprising:
[0011] An image acquisition module, used to acquire a wafer design image of a target product and at least one actual wafer image of the target product, wherein the wafer design image is used to characterize the arrangement of the grain units of the wafer corresponding to the target product during the manufacturing process;
[0012] A boundary determination module is used to determine a target boundary of a wafer edge region close to a wafer center side in a wafer design image according to a wafer abnormality position in an actual wafer image, wherein the wafer abnormality position is any one of a defect contour point position of a wafer defect region and an abnormal grain unit position;
[0013] The region determination module is used to determine the region between the target boundary and the wafer edge of the wafer design image as the wafer edge region of the wafer design image.
[0014] According to one aspect of an embodiment of the present application, an electronic device is provided, which includes: a memory and a program or instruction stored in the memory and executable on a processor, wherein when the program or instruction is executed by the processor, a method for determining a wafer edge area as provided in any aspect of the above-mentioned embodiment of the present application is implemented.
[0015] In one aspect of an embodiment of the present application, a readable storage medium is provided, on which a program or instruction is stored. When the program or instruction is executed by a processor, a method for determining a wafer edge area as provided in any aspect of the above-mentioned embodiment of the present application is implemented.
[0016] According to one aspect of an embodiment of the present application, a computer program product is provided. When instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes a method for determining a wafer edge area as provided in any aspect of the above-mentioned embodiment of the present application.
[0017] In the method for determining the wafer edge area provided in the embodiment of the present application, the differences between the wafer design images corresponding to different products are taken into account. Therefore, at least one actual wafer image generated according to the wafer design image is first obtained. Then, according to the abnormal position of the wafer in the actual wafer image, the target boundary of the wafer edge area close to the center side of the wafer in the wafer design image is determined. Finally, the area between the target boundary and the wafer edge of the wafer design image is determined as the wafer edge area of the wafer design image. In this way, the embodiment of the present application accurately analyzes the actual wafer image generated according to the wafer design image, and according to the abnormal position of the wafer in the actual wafer image, the target boundary corresponding to the wafer design characteristics of the wafer design image corresponding to the target product can be accurately obtained, thereby improving the accuracy of determining the wafer edge area. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0019] Figure 1It is a flowchart of a method for determining a wafer edge area provided by an embodiment of the present application;
[0020] Figure 2 It is a schematic diagram of determining a wafer edge area of a wafer design image based on an extension length provided by an embodiment of the present application;
[0021] Figure 3 It is a schematic diagram of determining a wafer edge area of a wafer design image based on the number of extended grain units provided by an embodiment of the present application;
[0022] Figure 4 is a schematic structural diagram of a device for determining a wafer edge region provided by an embodiment of the present application;
[0023] Figure 5 It is a schematic diagram of the structure of a device for determining a wafer edge area provided by an embodiment of the present application. DETAILED DESCRIPTION
[0024] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.
[0025] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0026] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of this application are in compliance with the relevant provisions of national laws and regulations.
[0027] It should be noted that in the embodiments of the present application, certain software, components, models and other existing solutions in the industry may be mentioned, and they should be regarded as exemplary. Their purpose is only to illustrate the feasibility of implementing the technical solution of the present application, but it does not mean that the applicant has or will necessarily use the solution.
[0028] In the existing method, the wafer layout image is marked into multiple annular areas according to the preset same radius, and then the other annular areas in the non-edge area are merged to achieve the marking of the wafer edge area. However, due to the differences between different wafer design images, the accuracy of the wafer edge area obtained by simply dividing the wafer design image into annular areas is low.
[0029] The purpose of the present application is to provide a method, device, equipment, medium and product for determining the edge area of a wafer. In the method for determining the edge area of a wafer provided in the embodiment of the present application, the differences between the wafer design images corresponding to different products are taken into account. Therefore, at least one actual wafer image generated according to the wafer design image is first obtained. Then, according to the abnormal position of the wafer in the actual wafer image, the target boundary of the wafer edge area close to the center side of the wafer in the wafer design image is determined. Finally, the area between the target boundary and the wafer edge of the wafer design image is determined as the wafer edge area of the wafer design image. In this way, the embodiment of the present application accurately analyzes the actual wafer image generated according to the wafer design image, and according to the abnormal position of the wafer in the actual wafer image, the target boundary corresponding to the wafer design characteristics of the wafer design image corresponding to the target product can be accurately obtained, thereby improving the accuracy of determining the edge area of the wafer.
[0030] The following describes specific embodiments of the method, device, equipment, medium and product for determining the wafer edge region provided by the embodiments of the present application. First, the method for determining the wafer edge region is described below.
[0031] Figure 1 A flow chart of a method for determining a wafer edge region is provided. The method for determining a wafer edge region can be applied to a service end. The method for determining a wafer edge region can include the following S101 to S103.
[0032] S101, obtaining a wafer design image of a target product and at least one actual wafer image of the target product, wherein the wafer design image is used to represent an arrangement of die units of a wafer corresponding to the target product during a manufacturing process.
[0033] In this embodiment, during the chip manufacturing process, different products have different design rules and performance requirements. Each product has a corresponding wafer design image according to its corresponding product design rules and performance requirements. According to the wafer design image, multiple wafers of the same type that meet the design rules and performance requirements of the product can be produced.
[0034] The target product is the product selected by the user from among the candidate products, and the wafer edge area of which needs to be determined in the corresponding wafer design image.
[0035] The wafer design image is used to characterize the arrangement of the die units of the wafer corresponding to the target product during the manufacturing process. For example, the wafer design image is generated by computer-aided design software and contains the precise position and size information of all the die units on the wafer.
[0036] The actual wafer image is a physical image of the wafer obtained by an optical microscope, an electron microscope or other imaging technology. For example, the actual wafer image shows the state of the wafer during the actual manufacturing process, including the actual arrangement of the grain units, defects on the wafer surface, etc.
[0037] As an example, the server first displays a user interaction interface, wherein the user interaction interface includes multiple candidate product identifiers. In response to the user selecting a target product identifier from each candidate product identifier, the corresponding target product is determined, and a wafer design image and at least one actual wafer image corresponding to the target product are obtained from a database.
[0038] S102, determining a target boundary of a wafer edge region close to a wafer center side in a wafer design image according to a wafer abnormal position in an actual wafer image, wherein the wafer abnormal position is any one of a defect contour point position in a wafer defect region and an abnormal grain unit position.
[0039] In this embodiment, the wafer abnormal position is used to characterize the position that deviates from the ideal state in the wafer design image. For example, the wafer abnormal position can be the position of each defect contour point corresponding to the wafer defect area, or can be the position of an abnormal grain unit.
[0040] Among them, the wafer defect area is used to characterize the defective wafer area determined only from the overall actual wafer image, that is, the defective local area composed of multiple grain units in the actual wafer image. The abnormal grain unit position is used to characterize the position of a single grain unit with abnormal electrical performance parameters or wafer edge problems in the actual wafer image.
[0041] Specifically, the abnormal position of the wafer is manually marked in the actual wafer image. When the abnormal content marked in the actual wafer image is a local area composed of multiple grain units, that is, when the specific single abnormal grain unit position cannot be accurately determined at this time, the abnormal position of the wafer is determined as the defect contour point position of the wafer defect area; when the abnormal content marked in the actual wafer image is a grain unit, that is, when the specific single abnormal grain unit position can be accurately determined at this time, the abnormal position of the wafer is determined as the abnormal grain unit position. As an example, the service end determines the target boundary of the wafer edge area close to the center side of the wafer in the wafer design image based on the defect contour point position or abnormal grain unit position of the wafer defect area marked in the actual wafer image.
[0042] Specifically, when only a defect contour point position or an abnormal grain unit position of a wafer defect area is marked in the actual wafer image, a circular boundary can be determined along the defect contour point position or the abnormal grain unit position, and the circular boundary is determined as the target boundary.
[0043] When multiple defect contour point positions or abnormal grain unit positions of the wafer defect area are marked in the actual wafer image, a circular boundary can be determined along the average length between the multiple defect contour point positions and the wafer edge, or the average number of grain units between the abnormal grain unit positions and the wafer edge, and the circular boundary can be determined as the target boundary.
[0044] S103 , determining an area between the target boundary and the wafer edge of the wafer design image as a wafer edge area of the wafer design image.
[0045] In this embodiment, the server divides the area between the target boundary and the wafer edge in the wafer design image into a wafer edge area, which is an area prone to defects in the wafer manufacturing process and therefore requires special attention.
[0046] In the method for determining the wafer edge area provided in the embodiment of the present application, the differences between the wafer design images corresponding to different products are taken into account. Therefore, at least one actual wafer image generated according to the wafer design image is first obtained. Then, according to the abnormal position of the wafer in the actual wafer image, the target boundary of the wafer edge area close to the center side of the wafer in the wafer design image is determined. Finally, the area between the target boundary and the wafer edge of the wafer design image is determined as the wafer edge area of the wafer design image. In this way, the embodiment of the present application accurately analyzes the actual wafer image generated according to the wafer design image, and according to the abnormal position of the wafer in the actual wafer image, the target boundary corresponding to the wafer design characteristics of the wafer design image corresponding to the target product can be accurately obtained, thereby improving the accuracy of determining the wafer edge area.
[0047] As an optional embodiment, S101 may specifically include:
[0048] Acquire at least one actual wafer image of the target product;
[0049] Based on the actual wafer image, a wafer design image corresponding to the target product is constructed.
[0050] In this embodiment, the server can use a high-resolution optical microscope, electron microscope or other imaging equipment to photograph the wafer of the target product and obtain at least one actual wafer image. The actual wafer image obtained is preprocessed, including denoising, contrast enhancement, color correction, etc., to improve the clarity and accuracy of the image.
[0051] Then, the actual wafer image is analyzed using image processing technology (such as edge detection, image segmentation, feature extraction, etc.) to identify key features such as die units and connection lines on the wafer. Based on the key features obtained from the analysis, computer-aided design software is used to construct the wafer design image corresponding to the target product.
[0052] Through this embodiment, the actual wafer image corresponding to the target product is obtained, and the corresponding wafer design image is constructed accordingly, which helps to accurately mark the wafer edge area in the wafer design image according to the actual wafer image and the wafer design image.
[0053] As an optional embodiment, at least one actual wafer image of the target product is obtained by any of the following methods:
[0054] In response to a user inputting an actual wafer image of a target product, acquiring the actual wafer image;
[0055] In response to a user's operation of selecting an actual wafer image from among candidate wafer images corresponding to a target product, the actual wafer image is acquired.
[0056] In this embodiment, as an example, the server may display a user interaction interface including an option for uploading or inputting an actual wafer image. When the user triggers the option and chooses to upload or input an actual wafer image, the server can receive and process the corresponding actual wafer image.
[0057] As another example, the server may pre-build a database containing multiple candidate wafer images, wherein each candidate wafer image may come from a previous wafer manufacturing batch, a quality inspection sample, or a test image during the research and development process.
[0058] Then, the server provides a user interaction interface, which includes an image selection area for displaying thumbnails or lists of candidate wafer images. The user can find and select the actual wafer image from the candidate wafer images by browsing, searching, or filtering. After the user confirms the selection, the server stores the selected candidate wafer image as the actual wafer image.
[0059] Through this embodiment, two flexible and user-friendly methods are provided to obtain the actual wafer image of the target product, thereby helping to improve the efficiency and accuracy of obtaining the actual wafer image and improving the user experience.
[0060] As an optional embodiment, S102 may specifically include:
[0061] According to the abnormal position of the wafer in the actual wafer image, an extension parameter of the wafer edge in the wafer design image extending toward the wafer center along the wafer radial direction is determined, where the extension parameter is one of an extension length and a number of extended grain units;
[0062] The extension parameter is extended from the wafer edge toward the wafer center along the wafer radial direction to obtain a target boundary of the wafer edge region close to the wafer center side in the wafer design image.
[0063] In this embodiment, the extension parameter includes one of an extension length and an extension grain unit number, wherein the extension length is used to characterize the distance from the edge of the wafer to the center of the wafer along the radial direction, and the extension grain unit number is used to characterize the number of grain units included in the extension from the edge of the wafer to the center of the wafer along the radial direction.
[0064] As an example, the server selects the extension length or the number of extended grain units as the extension parameter according to the specific situation of the abnormal position of the wafer in the actual wafer image.
[0065] Specifically, when the wafer abnormal position is the defect contour point position of the wafer defect area, the extension length is selected as the extension parameter. The average length between the defect contour point position of each wafer defect area in the actual wafer image and the wafer edge is used as the specific parameter value corresponding to the extension parameter.
[0066] When the wafer abnormal position is an abnormal grain unit position, the number of extended grain units is selected as the extension parameter, and the average number of interval grain units between each abnormal grain unit position and the wafer edge in the actual wafer image is used as the specific parameter value corresponding to the extension parameter.
[0067] Finally, according to the determined extension parameters, the target boundary of the wafer edge area close to the wafer center side in the wafer design image is obtained by extending from the wafer edge toward the wafer center along the wafer radial direction.
[0068] Through this embodiment, according to the abnormal position of the wafer in the actual wafer image, the extension parameter of the wafer edge extending toward the wafer center along the radial direction of the wafer in the wafer design image corresponding to the actual wafer image can be accurately determined, thereby obtaining the target boundary of the wafer edge area close to the wafer center side in the wafer design image. In this way, according to the abnormal position of the wafer in the actual wafer image, the target boundary corresponding to the wafer design characteristics of the corresponding wafer design image can be accurately obtained, thereby improving the accuracy of determining the wafer edge area.
[0069] As an optional embodiment, the wafer abnormal position is a defect contour point position of a wafer defect area, and the extension parameter is an extension length;
[0070] According to the wafer abnormal position in the actual wafer image, the extension parameter of the wafer edge in the wafer design image extending toward the wafer center along the wafer radial direction is determined, which may specifically include:
[0071] Determine the radial distance between each defect contour point and the edge of the wafer in the actual wafer image according to the position of the defect contour point of the wafer defect area in the actual wafer image;
[0072] The maximum value among the radial distances is determined as the extension length of the wafer edge in the wafer design image extending toward the wafer center along the wafer radial direction.
[0073] In this embodiment, the radial distance is used to characterize the distance between the position of the defect contour point and the edge of the wafer in the actual wafer image along the radial direction.
[0074] As an example, the server extracts the defect contour points corresponding to the wafer defect areas in each wafer defect area marked in the actual wafer image. Then, for each defect contour point, the radial distance between the position of the defect contour point and the edge of the wafer in the actual wafer image is calculated. Finally, the maximum value is found among all the calculated radial distances, and the maximum value is determined as the extension length of the wafer edge in the wafer design image extending toward the center of the wafer along the radial direction of the wafer.
[0075] like Figure 2 As shown, a schematic diagram of determining the wafer edge area of a wafer design image based on an extension length is provided. Specifically, the method for determining the wafer edge area based on the extension length is applicable to determining the wafer edge area in a defect display type in which the actual wafer image is a display of defects existing on the wafer.
[0076] Through this embodiment, according to the radial distance between each defect contour point in the actual wafer image and the wafer edge in the actual wafer image, the extension length of the wafer edge in the wafer design image along the wafer radial direction toward the wafer center can be accurately determined. Thus, the corresponding target boundary in the wafer design image can be accurately obtained, and the accuracy of determining the wafer edge area can be improved.
[0077] As an optional embodiment, the abnormal position of the wafer is an abnormal grain unit position, and the extension parameter is the number of extended grain units;
[0078] According to the wafer abnormal position in the actual wafer image, the extension parameter of the wafer edge in the wafer design image extending toward the wafer center along the wafer radial direction is determined, which may specifically include:
[0079] According to the abnormal grain unit positions in the actual wafer image, the number of radial grain unit intervals between each abnormal grain unit position and the wafer edge in the actual wafer image is determined;
[0080] The maximum value among the numbers of the intervals between the various grain units is determined as the number of extended grain units extending from the edge of the wafer in the wafer design image along the radial direction of the wafer toward the center of the wafer.
[0081] In this embodiment, the number of grain unit intervals is used to represent the number of grain units spaced along the radial direction between the abnormal grain unit position and the wafer edge in the actual wafer image.
[0082] As an example, the server calculates the number of grain unit intervals between the abnormal grain unit position and the wafer edge in the actual wafer image along the radial direction for each abnormal grain unit position marked in the actual wafer image. Finally, the maximum value is found among all the calculated numbers of grain unit intervals, and the maximum value is determined as the number of extended grain units extending from the wafer edge in the wafer design image to the wafer center along the wafer radial direction.
[0083] like Figure 3 As shown, a schematic diagram of determining the wafer edge area of a wafer design image based on the number of extended grain units is provided. Specifically, the method for determining the wafer edge area based on the number of extended grain units is applicable to determining the wafer edge area in an electrical performance display type in which the actual wafer image is a display of the electrical performance distribution of each grain unit on the wafer.
[0084] Through this embodiment, according to the radial grain unit spacing between each abnormal grain unit position in the actual wafer image and the wafer edge in the actual wafer image, the number of extended grain units extending from the wafer edge in the wafer design image along the wafer radial direction to the wafer center can be accurately determined. Thus, the corresponding target boundary in the wafer design image can be accurately obtained, and the accuracy of determining the wafer edge area can be improved.
[0085] As an optional embodiment, the number of actual wafer images is multiple;
[0086] After determining the extension parameter of the wafer edge in the wafer design image extending toward the wafer center along the wafer radial direction according to the wafer abnormal position in the actual wafer image, the method for determining the wafer edge area may further specifically include:
[0087] Counting the extension parameters corresponding to each actual wafer image to obtain the occurrence frequency of various extension parameters;
[0088] The extension parameter with the highest frequency of occurrence is determined as the optimized extension parameter;
[0089] Extending the extension parameters from the wafer edge along the wafer radial direction toward the wafer center, obtaining the target boundary of the wafer edge area close to the wafer center side in the wafer design image, including:
[0090] The extension parameters are optimized by extending from the wafer edge toward the wafer center along the wafer radial direction to obtain a target boundary of the wafer edge area close to the wafer center side in the wafer design image.
[0091] In this embodiment, the optimized extension parameter is used to represent a more accurate extension parameter obtained after optimizing the extension parameter.
[0092] As an example, when the server obtains multiple actual wafer images, it calculates the extension parameter corresponding to each actual wafer image according to the wafer edge area determination method provided in the above embodiment of the present application, and performs statistics on the extension parameters corresponding to each actual wafer image to obtain the occurrence frequency of each extension parameter.
[0093] Finally, according to the statistical results, the extension parameter with the highest occurrence frequency is found, and the extension parameter with the highest occurrence frequency is determined as the optimized extension parameter.
[0094] Through this embodiment, according to the occurrence frequency of the extension parameter corresponding to each actual wafer image, the extension parameter with the highest occurrence frequency is determined as the optimized extension parameter. In this way, the final determination of the wafer edge area can meet the production conditions of most actual wafer images and improve the accuracy of the determination of the wafer edge area.
[0095] As an optional embodiment, after S103, the method for determining the wafer edge area may further include:
[0096] Counting the number of first normal grain units corresponding to the wafer edge region and the number of second normal grain units corresponding to the wafer center region in the actual wafer image, where the wafer center region is the region excluding the wafer edge region in the actual wafer image;
[0097] Determine a first chip qualified rate in a wafer edge region and a second chip qualified rate in a wafer center region respectively according to the first normal grain unit quantity and the second normal grain unit quantity;
[0098] When the difference between the first chip qualified rate and the second chip qualified rate is greater than a preset difference threshold, it is determined that an abnormality occurs in the corresponding wafer edge region in the actual wafer image.
[0099] In this embodiment, the first number of qualified grain units is used to characterize the number of grain units in the actual wafer image that belong to the edge area of the wafer and are marked as qualified grain units; the second number of qualified grain units is used to characterize the number of grain units in the actual wafer image that belong to the center area of the wafer and are marked as qualified grain units.
[0100] The first chip qualified rate is used to characterize the ratio of the number of qualified grain units to the number of unqualified grain units in the wafer edge area of the actual wafer image; the second chip qualified rate is used to characterize the ratio of the number of qualified grain units to the number of unqualified grain units in the wafer center area of the actual wafer image.
[0101] As an example, after determining the wafer edge area of the wafer design image, the server uses the wafer design image to generate a wafer of a target product and obtains an actual wafer image corresponding to the wafer of the target product.
[0102] Then, the user can mark the qualified die units and unqualified die units in the wafer of the target product. In response to the user's marking operation, the server counts the number of qualified die units in the wafer edge area and the wafer center area in the actual wafer image.
[0103] Then, according to the counted number of qualified die units, the first chip qualified rate in the wafer edge area and the second chip qualified rate in the wafer center area are calculated respectively, and the difference between the first chip qualified rate and the second chip qualified rate is calculated.
[0104] Finally, the calculated difference is compared with the preset difference threshold. If the difference is greater than the preset difference threshold, it is considered that an abnormality occurs in the wafer edge region of the target product wafer; if the difference is less than or equal to the preset difference threshold, it is considered that no abnormality occurs in the wafer edge region of the target product wafer.
[0105] Through this embodiment, the number of qualified die units in the wafer edge area and the wafer center area in the actual wafer image is counted, the chip qualification rate of the two areas is calculated, and the difference between the two is compared to determine whether there is an abnormality in the wafer edge area. In this way, the abnormality of the wafer edge area in the wafer of the target product generated by using the wafer design image can be discovered in time, which helps to improve the overall yield of the wafer, reduce production costs, and improve product quality and competitiveness.
[0106] As an optional embodiment, when the difference between the first chip qualified rate and the second chip qualified rate is greater than a preset difference threshold, after determining that an abnormality occurs in the corresponding wafer edge area in the actual wafer image, the method for determining the wafer edge area may further include:
[0107] Count the frequency of occurrence of actual wafer images with abnormalities in the wafer edge area;
[0108] When the occurrence frequency is greater than a preset frequency threshold, obtaining wafer layout difference information between a wafer edge region and a wafer center region in the wafer design image;
[0109] The wafer layout variation information is identified as the cause of the anomaly in the wafer edge area.
[0110] In this embodiment, the server collects statistics on actual wafer images with abnormalities in the wafer edge area detected, and calculates the frequency of occurrence of actual wafer images with abnormalities in the wafer edge area, which reflects the prevalence and severity of the abnormalities in the wafer edge area.
[0111] Then, the server sets a reasonable preset frequency threshold based on production experience and quality requirements. When the frequency of actual wafer images with abnormalities in the wafer edge area exceeds this threshold, it is considered that there is a significant abnormality problem in the wafer edge area.
[0112] At this time, the wafer design image is obtained from the database, and the wafer layout information of the wafer edge area in the wafer design image is compared with the wafer layout information of the wafer center area to obtain the wafer layout difference information between the wafer edge area and the wafer center area in the wafer design image. Specifically, the wafer layout difference information may include at least one of chip position offset, size change, and spacing inconsistency.
[0113] Finally, the extracted wafer layout difference information is comprehensively analyzed in combination with factors such as process parameters, equipment status, and material properties in the wafer manufacturing process. Through comprehensive analysis, the specific cause of the abnormality in the wafer edge area in the wafer design image is determined.
[0114] Through this embodiment, the wafer layout difference information between the wafer edge area and the wafer center area in the wafer design image is obtained, so as to accurately determine the specific cause of the abnormality of the wafer edge area in the wafer design image. In this way, the unreasonableness of the wafer design image design can be discovered in time, which helps to improve the overall yield of the wafer, reduce production costs, and improve product quality and competitiveness.
[0115] Based on the method for determining the wafer edge region, accordingly, the present application also provides a specific embodiment of a device for determining the wafer edge region.
[0116] like Figure 4 As shown, the wafer edge region determination device 400 provided in the embodiment of the present application includes an image acquisition module 410 , a boundary determination module 420 and a region determination module 430 .
[0117] The image acquisition module 410 is used to acquire a wafer design image of a target product and at least one actual wafer image of the target product. The wafer design image is used to characterize the arrangement of the die units of the wafer corresponding to the target product during the manufacturing process.
[0118] The boundary determination module 420 is used to determine the target boundary of the wafer edge area close to the wafer center side in the wafer design image according to the wafer abnormal position in the actual wafer image. The wafer abnormal position is any one of the defect contour point position of the wafer defect area and the abnormal grain unit position.
[0119] The region determination module 430 is configured to determine the region between the target boundary and the wafer edge of the wafer design image as the wafer edge region of the wafer design image.
[0120] As an optional embodiment, the image acquisition module 410 may specifically include the following units:
[0121] An image acquisition unit, used to acquire at least one actual wafer image of a target product;
[0122] The image construction unit is used to construct a wafer design image corresponding to the target product according to the actual wafer image.
[0123] As an optional embodiment, the image acquisition unit acquires at least one actual wafer image of the target product by any of the following methods:
[0124] In response to a user inputting an actual wafer image of a target product, acquiring the actual wafer image;
[0125] In response to a user's operation of selecting an actual wafer image from among candidate wafer images corresponding to a target product, the actual wafer image is acquired.
[0126] As an optional embodiment, the boundary determination module 420 specifically includes the following units:
[0127] A parameter determination unit, for determining an extension parameter of the wafer edge in the wafer design image extending toward the wafer center along the wafer radial direction according to the wafer abnormal position in the actual wafer image, wherein the extension parameter is one of an extension length and a number of extended grain units;
[0128] The boundary determination unit is used to extend the extension parameter from the wafer edge to the wafer center along the wafer radial direction to obtain the target boundary of the wafer edge area close to the wafer center side in the wafer design image.
[0129] As an optional embodiment, the wafer abnormal position is a defect contour point position of a wafer defect area, and the extension parameter is an extension length;
[0130] The parameter determination unit is specifically used for:
[0131] Determine the radial distance between each defect contour point and the edge of the wafer in the actual wafer image according to the position of the defect contour point of the wafer defect area in the actual wafer image;
[0132] The maximum value among the radial distances is determined as the extension length of the wafer edge in the wafer design image extending toward the wafer center along the wafer radial direction.
[0133] As an optional embodiment, the abnormal position of the wafer is an abnormal grain unit position, and the extension parameter is the number of extended grain units;
[0134] The parameter determination unit is specifically used for:
[0135] According to the abnormal grain unit positions in the actual wafer image, the number of radial grain unit intervals between each abnormal grain unit position and the wafer edge in the actual wafer image is determined;
[0136] The maximum value among the numbers of the intervals between the various grain units is determined as the number of extended grain units extending from the edge of the wafer in the wafer design image along the radial direction of the wafer toward the center of the wafer.
[0137] As an optional embodiment, the number of actual wafer images is multiple;
[0138] After determining the extension parameter of the wafer edge in the wafer design image extending toward the wafer center along the wafer radial direction according to the wafer abnormal position in the actual wafer image, the boundary determination module 420 specifically further includes the following units:
[0139] A frequency statistics unit is used to count the extension parameters corresponding to each actual wafer image to obtain the occurrence frequency of various extension parameters;
[0140] The parameter determination unit is further used to determine the extension parameter with the highest occurrence frequency as the optimized extension parameter;
[0141] The boundary determination unit is specifically used for:
[0142] The extension parameters are optimized by extending from the wafer edge toward the wafer center along the wafer radial direction to obtain a target boundary of the wafer edge area close to the wafer center side in the wafer design image.
[0143] As an optional embodiment, after determining the area between the target boundary and the wafer edge of the wafer design image as the wafer edge area of the wafer design image, the wafer edge area determination device 400 further includes the following modules:
[0144] A quantity counting module is used to count the number of first qualified grain units corresponding to the wafer edge area and the number of second qualified grain units corresponding to the wafer center area in the actual wafer image, where the wafer center area is the area excluding the wafer edge area in the actual wafer image;
[0145] A qualified rate determination module, used to determine the qualified rate of the first chip in the wafer edge area and the qualified rate of the second chip in the wafer center area respectively according to the first qualified grain unit quantity and the second qualified grain unit quantity;
[0146] The abnormality determination module is used to determine that an abnormality occurs in the corresponding wafer edge area in the actual wafer image when the difference between the first chip qualified rate and the second chip qualified rate is greater than a preset difference threshold.
[0147] As an optional embodiment, when the difference between the first chip qualified rate and the second chip qualified rate is greater than a preset difference threshold, after determining that the corresponding wafer edge region in the actual wafer image is abnormal, the wafer edge region determination device 400 further includes the following modules:
[0148] A frequency statistics module is used to count the frequency of occurrence of actual wafer images with abnormalities in the wafer edge area;
[0149] An information acquisition module, used for acquiring wafer layout difference information between a wafer edge region and a wafer center region in a wafer design image when the occurrence frequency is greater than a preset frequency threshold;
[0150] The cause determination module is used to determine the wafer layout difference information as the abnormal cause of the wafer edge area.
[0151] Based on the determination method of the wafer edge area. Accordingly, the present application also provides a method for determining the wafer edge area.
[0152] Figure 5A schematic diagram of the hardware structure of a device for determining a wafer edge area provided in an embodiment of the present application is shown.
[0153] The wafer edge region determination device may include a processor 501 and a memory 502 storing computer program instructions.
[0154] Specifically, the processor 501 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.
[0155] The memory 502 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 502 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 502 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 502 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 502 is a non-volatile solid-state memory.
[0156] The processor 501 reads and executes computer program instructions stored in the memory 502 to implement any one of the wafer edge region determination methods in the above embodiments.
[0157] In one example, the wafer edge region determination device may further include a communication interface 503 and a bus 510. Figure 5 As shown, the processor 501, the memory 502, and the communication interface 503 are connected via a bus 510 and communicate with each other.
[0158] The communication interface 503 is mainly used to implement communication between various modules, devices, layout units and / or equipment in the embodiments of the present application.
[0159] Bus 510 includes hardware, software or both, and the components of the determination equipment of wafer edge area are coupled to each other. For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front-end bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 510 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the present application considers any suitable bus or interconnection.
[0160] In addition, in combination with the wafer edge region determination method in the above embodiments, the present application embodiment may provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by a processor, any one of the wafer edge region determination methods in the above embodiments is implemented.
[0161] In addition, in combination with the method for determining the wafer edge area in the above-mentioned embodiments, the embodiments of the present application may provide a computer program product for implementation. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the method for determining the wafer edge area provided in any aspect of the above-mentioned embodiments of the present application.
[0162] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.
[0163] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.
[0164] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.
[0165] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.
[0166] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the system, module and layout unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.
Claims
1. A method for determining a wafer edge area, characterized in that: include: Acquire a wafer design image of a target product and at least one actual wafer image of the target product, wherein the wafer design image is used to characterize an arrangement of grain units of a wafer corresponding to the target product during a manufacturing process; Determine a target boundary of a wafer edge region close to a wafer center side in the wafer design image according to a wafer abnormal position in the actual wafer image, wherein the wafer abnormal position is any one of a defect contour point position of a wafer defect region and an abnormal grain unit position; An area between the target boundary and the wafer edge of the wafer design image is determined as a wafer edge area of the wafer design image.
2. The method according to claim 1, characterized in that The step of acquiring a wafer design image of a target product and at least one actual wafer image of the target product includes: Acquire at least one actual wafer image of the target product; A wafer design image corresponding to the target product is constructed based on the actual wafer image.
3. The method according to claim 2, characterized in that Acquire at least one actual wafer image of the target product by any of the following methods: In response to a user inputting an actual wafer image of the target product, acquiring the actual wafer image; In response to a user's operation of selecting an actual wafer image from among the candidate wafer images corresponding to the target product, the actual wafer image is acquired.
4. The method according to claim 1, characterized in that The step of determining a target boundary of a wafer edge region close to a wafer center side in the wafer design image according to the wafer abnormal position in the actual wafer image includes: Determine, according to the wafer abnormal position in the actual wafer image, an extension parameter of the wafer edge in the wafer design image extending toward the wafer center along the wafer radial direction, wherein the extension parameter is one of an extension length and a number of extended grain units; The extension parameter is extended from the wafer edge toward the wafer center along the wafer radial direction to obtain a target boundary of the wafer edge region close to the wafer center side in the wafer design image.
5. The method according to claim 4, characterized in that The wafer abnormal position is a defect contour point position of a wafer defect area, and the extension parameter is an extension length; The step of determining, according to the wafer abnormal position in the actual wafer image, an extension parameter of the wafer edge in the wafer design image extending toward the wafer center along the wafer radial direction, comprises: Determine the radial distance between each defect contour point and the edge of the wafer in the actual wafer image according to the position of the defect contour point of the wafer defect area in the actual wafer image; The maximum value among the radial distances is determined as the extension length of the wafer edge in the wafer design image extending toward the wafer center along the wafer radial direction.
6. The method according to claim 4, characterized in that The abnormal position of the wafer is an abnormal grain unit position, and the extension parameter is the number of extended grain units; The step of determining, according to the wafer abnormal position in the actual wafer image, an extension parameter of the wafer edge in the wafer design image extending toward the wafer center along the wafer radial direction, comprises: According to the abnormal grain unit positions in the actual wafer image, determining the number of radial grain unit intervals between each of the abnormal grain unit positions and the wafer edge in the actual wafer image; The maximum value among the numbers of the grain unit intervals is determined as the number of extended grain units extending from the edge of the wafer in the wafer design image along the radial direction of the wafer toward the center of the wafer.
7. The method according to claim 4, characterized in that The number of the actual wafer images is multiple; After determining the extension parameter of the wafer edge in the wafer design image extending toward the wafer center along the wafer radial direction according to the wafer abnormal position in the actual wafer image, the method further includes: Counting the extension parameters corresponding to each of the actual wafer images to obtain the occurrence frequencies of various extension parameters; Determine the extension parameter with the highest occurrence frequency as the optimized extension parameter; The step of extending the extension parameter from the wafer edge toward the wafer center along the wafer radial direction to obtain a target boundary of the wafer edge region close to the wafer center side in the wafer design image includes: The optimized extension parameter is extended from the wafer edge toward the wafer center along the wafer radial direction to obtain a target boundary of the wafer edge region close to the wafer center side in the wafer design image.
8. The method according to any one of claims 1 to 7, characterized in that: After determining the area between the target boundary and the wafer edge of the wafer design image as the wafer edge area of the wafer design image, the method further includes: Counting the number of first qualified grain units corresponding to the wafer edge region and the number of second qualified grain units corresponding to the wafer center region in the actual wafer image, wherein the wafer center region is the region in the actual wafer image excluding the wafer edge region; According to the first qualified grain unit quantity and the second qualified grain unit quantity, respectively determining a first chip qualified rate in the wafer edge region and a second chip qualified rate in the wafer center region; When the difference between the first chip qualified rate and the second chip qualified rate is greater than a preset difference threshold, it is determined that an abnormality occurs in the corresponding wafer edge region in the actual wafer image.
9. The method according to claim 8, characterized in that When the difference between the first chip qualified rate and the second chip qualified rate is greater than a preset difference threshold, after determining that an abnormality occurs in the corresponding wafer edge region in the actual wafer image, the method further includes: Counting the frequency of occurrence of actual wafer images in which abnormalities occur in the wafer edge region; When the occurrence frequency is greater than a preset frequency threshold, obtaining wafer layout difference information between the wafer edge area and the wafer center area in the wafer design image; The wafer layout difference information is determined as the cause of the abnormality in the wafer edge area.
10. An electronic device, characterized in that: The device comprises: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the method for determining the wafer edge area according to any one of claims 1 to 9 is implemented.
11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the method for determining the wafer edge area according to any one of claims 1 to 9 is implemented.
12. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the method for determining the wafer edge area as described in any one of claims 1-9.