Memory device, system and operation method thereof

Abstract

The present application discloses a memory device, system and operating method wherein the memory device includes: a memory array including a plurality of memory cells; the peripheral circuit is coupled with the memory array and comprises a plurality of page buffers; each page buffer comprises at least two groups of latch circuits; each group of latch circuits comprises a first sub latch circuit and a second sub latch circuit; the first sub-latch circuit is coupled with a sensing node and is configured to latch first information on the sensing node; the second sub-latch circuit is coupled with the sensing node and is configured to latch second information on the sensing node through the first sub-latch circuit; wherein the first information of the first sub latch circuit and the second information of the second sub latch circuit are exchanged through the sensing node.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to a memory device, system and device operation method. Background Art

[0002] As the storage density of 3D NAND flash memory devices increases, a large number of page buffers are used in the 3D NAND flash memory devices, and these page buffers occupy a large area in the peripheral circuits of the memory devices. Summary of the invention

[0003] In view of this, embodiments of the present application provide a memory device, system, and operating method.

[0004] In a first aspect, an embodiment of the present application provides a memory device, including:

[0005] A memory array including a plurality of memory cells;

[0006] The peripheral circuit is coupled to the memory array, and includes: a plurality of page buffers; each page buffer includes: at least two groups of latch circuits; each group of latch circuits includes: a first sub-latch circuit and a second sub-latch circuit, wherein;

[0007] The first sub-latch circuit is coupled to the sensing node and is configured to: latch the first information on the sensing node;

[0008] The second sub-latch circuit is coupled to the sensing node and is configured to: latch the second information on the sensing node through the first sub-latch circuit;

[0009] The first information of the first sub-latch circuit and the second information of the second sub-latch circuit are exchanged through the sensing node.

[0010] In the above scheme, each group of latch circuits also includes: a transmission control switch, which connects the first sub-latch circuit and the second sub-latch circuit, and is configured to: in response to a transmission control signal, be in an on state, and transmit the first information stored in the first sub-latch circuit to the second sub-latch circuit.

[0011] In the above solution, the second sub-latch circuit includes: a parasitic capacitor storing the second information; the parasitic capacitor is connected to a terminal of the transmission control switch away from the first sub-latch circuit.

[0012] In the above solution, the at least two groups of latch circuits are configured to store data to be written or read data.

[0013] In the above scheme, one group of latch circuits in the at least two groups of latch circuits is configured to: store intermediate data in a programming process or verification data in a verification process;

[0014] The other groups of latch circuits in the at least two groups of latch circuits are configured to store data to be written or read data.

[0015] In the above scheme, the first sub-latch circuit includes: a setting switch and a storage element, wherein:

[0016] The setting switch is coupled to the sensing node and connected to the storage element, and is configured to latch the first information on the sensing node to the storage element in response to a setting signal.

[0017] In the above solution, the first sub-latch circuit further includes: a reset switch connected to the storage element and configured to: reset the storage element in response to a reset signal.

[0018] In the above scheme, the first sub-latch circuit also includes: a sensing control switch, one end of which is connected to the set switch and the reset switch, and the other end is grounded; the sensing control switch is configured to: be turned on under the action of the level of the sensing node, and write the first information of the sensing node into the storage element through the set switch.

[0019] In the above scheme, the first sub-latch circuit further includes: a reset control switch, one end of which is connected to the set switch and the reset switch, and the other end of which is grounded; the reset control switch is further configured to: in response to a reset control signal, reset the first sub-latch circuit through the reset switch;

[0020] The reset control signal is generated by the control logic contained in the peripheral circuit.

[0021] In the above scheme, the storage element includes: a first inverter and a second inverter; wherein the input end of the first inverter is connected to the output end of the second inverter to form a first node; the output end of the first inverter is connected to the input end of the second inverter to form a second node; the second node is connected to the second sub-latch circuit and is configured to: store the first information.

[0022] In the above solution, the set switch includes a first transistor having one end connected to the first node; the reset switch includes a second transistor having one end connected to the second node;

[0023] The other end of the first transistor is connected to the other end of the second transistor.

[0024] In the above scheme, each group of latch circuits further includes: a first control switch and a second control switch connected in series between the sensing node and the ground, and the first control switch is controlled by the second information latched by the second sub-latch circuit; the second control switch is controlled by the read control signal, wherein,

[0025] When the second information controls the first control switch to be turned on and the read control signal controls the second control switch to be turned on, the second information is read to the sensing node.

[0026] In the above scheme, the transmission control switch includes: a transmission gate with a single MOS transistor structure or a transmission gate with a dual MOS transistor crystal structure; the dual MOS transistor crystal includes a CMOS transmission gate formed by connecting a PMOS transistor and an NMOS transistor in parallel.

[0027] In the above scheme, the page buffer further includes: a main latch circuit coupled to the sensing node, configured to: store intermediate data in a programming process or verification data in a verification process;

[0028] The structure of the main latch circuit is the same as that of the first sub-latch circuit; or, the main latch circuit and the first sub-latch circuit share the sensing control switch and the reset control switch, and the rest of the structures are the same.

[0029] In the above solution, the at least two groups of latch circuits include: two groups of latch circuits configured to store LP data, MP data, UP data and XP data of data to be written or read.

[0030] In the above scheme, the at least two groups of latch circuits include: three groups of latch circuits, wherein:

[0031] The two groups of latch circuits are configured to: store LP data, MP data, UP data and XP data for data to be written or read;

[0032] The remaining group of latch circuits is configured to store intermediate data in a programming process or verification data in a verification process.

[0033] In a second aspect, an embodiment of the present application further provides an operating method of a memory device, wherein the memory device includes a page buffer; the page buffer includes at least two groups of latch circuits; each group of latch circuits includes a first sub-latch circuit and a second sub-latch circuit that are mutually dependent and coupled to a sensing node; the operating method includes:

[0034] When selecting a data state to be operated in a programming operation or a verification operation of the memory device, reading the second information latched in the second sub-latch circuit to the sensing node;

[0035] storing the second information of the sensing node in a sensing latch circuit of the page buffer;

[0036] exchanging the second information of the second sub-latch circuit and the first information latched by the first sub-latch circuit;

[0037] The first information is read from the second sub-latch circuit to the sensing node, and the second information is read from the sensing latch circuit to the sensing node to obtain selected information indicating the data state to be operated.

[0038] In the above scheme, the sensing latch circuit includes a first sensing latch circuit and a second sensing latch circuit; the data state to be operated includes a data state to be programmed or a data state to be verified; the sensing latch circuit for storing the second information of the sensing node in the page buffer includes:

[0039] When selecting a data state to be programmed corresponding to a programming operation of the memory device, storing the second information of the sensing node in the second sensing latch circuit; wherein the first verification information stored in the second sensing latch circuit is invalid;

[0040] When selecting a data state to be verified corresponding to a verification operation of the memory device, storing the second information of the sensing node in the first sensing latch circuit, wherein the second verification information stored in the first sensing latch circuit is invalid;

[0041] The first verification information and the second verification information are generated when a verification operation is performed on the memory device last time.

[0042] In the above solution, the step of exchanging the second information of the second sub-latch circuit and the first information latched by the first sub-latch circuit includes:

[0043] charging the sensing node so that the level of the sensing node reaches a preset threshold value, so as to read the second information to the sensing node;

[0044] In response to a transmission control signal, closing a transmission path between the first sub-latch circuit and the second sub-latch circuit, and transmitting the first information to the second sub-latch circuit;

[0045] performing a clearing operation on the first sub-latch circuit so that the first sub-latch circuit is restored to an initial state;

[0046] The second information is written into the first sub-latch circuit.

[0047] In the above scheme, the operation method further includes:

[0048] When writing second information to the second sub-latch circuit in a programming operation or a verification operation of the memory device, the second information is written into the first sub-latch circuit; the first sub-latch circuit and the second sub-latch circuit are exchanged so that the second information is stored in the second sub-latch circuit.

[0049] In a third aspect, an embodiment of the present application further provides a memory system, comprising: one or more of the aforementioned memory devices and a memory controller coupled to the memory device and used to control the memory.

[0050] The embodiment of the present application provides a memory device, system and operation method. Here, the memory device includes: a memory array including a plurality of memory cells; a peripheral circuit coupled to the memory array, including: a plurality of page buffers; each page buffer includes: at least two groups of latch circuits; each group of latch circuits includes: a first sub-latch circuit and a second sub-latch circuit, wherein: the first sub-latch circuit is coupled to a sensing node and is configured to: latch the first information on the sensing node; the second sub-latch circuit is coupled to the sensing node and is configured to: latch the second information on the sensing node through the first sub-latch circuit; wherein the first information of the first sub-latch circuit and the second information of the second sub-latch circuit are exchanged through the sensing node. The page buffer included in the memory device provided in the embodiment of the present application reduces the number of elements constituting the page buffer to a certain extent by using at least two groups of two mutually dependent sub-latch circuits, thereby saving the area occupied by the page buffer in the memory chip (such as a NAND chip). BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In the drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar components in different views. The same numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0052] Figure 1 An exemplary system block diagram of an electronic device having a memory system according to an embodiment of the present application;

[0053] Figure 2 A schematic diagram of an exemplary memory card having a memory device according to an embodiment of the present application;

[0054] Figure 3 A schematic diagram of an exemplary SSD having a memory device according to an embodiment of the present application;

[0055] Figure 4A schematic diagram of an exemplary memory device including a peripheral circuit according to an embodiment of the present application;

[0056] Figure 5 A block diagram of an exemplary memory device including a memory array and a peripheral circuit according to an embodiment of the present application;

[0057] Figure 6 A schematic diagram of the relationship between a page buffer group and a memory array included in a memory device provided according to an embodiment of the present application;

[0058] Figure 7 A schematic diagram of the structure of a memory device provided according to an embodiment of the present application;

[0059] Figure 8 A schematic diagram of the structure of a first sub-latch circuit provided according to an embodiment of the present application;

[0060] Fig. 9 A schematic diagram of a connection relationship between a second sub-latch circuit provided in an embodiment of the present application and coupled to an SO;

[0061] Fig.10 A schematic diagram of the structure of a page buffer including two groups of latch circuits provided according to an embodiment of the present application;

[0062] Fig.11 A schematic diagram of the structure of a page buffer including three groups of latch circuits provided according to an embodiment of the present application;

[0063] Fig.12 A schematic diagram of a flow chart of an operating method of a memory device provided according to an embodiment of the present application;

[0064] Fig.13 A flowchart of a programming process provided according to an embodiment of the present application;

[0065] Fig.14 The present invention is a flowchart of a verification process provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0066] The following describes the various embodiments of the present application in more detail with reference to the accompanying drawings. Other embodiments that can be used as variations of any disclosed embodiment can be formed by configuring or arranging the elements and features in the embodiments of the present application in different ways. Therefore, the embodiments of the present application are not limited to the embodiments set forth herein. On the contrary, the described embodiments are provided so that the embodiments of the present application are thorough and complete, and the scope of the embodiments of the present application is fully conveyed to the technicians in the technical field to which the embodiments of the present application belong. It should be noted that references to "embodiment", "another embodiment" and the like do not necessarily represent only one embodiment, and different references to any such phrases are not necessarily for the same embodiment. It should be understood that, although the terms "first", "second", "third" and the like can be used in this article to identify various elements, these elements are not limited by these terms. These terms are used to distinguish an element from another element with the same or similar name. Therefore, without departing from the spirit and scope of the embodiments of the present application, the first element in one embodiment may also be referred to as the second or third element in another embodiment.

[0067] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly illustrate the features of the embodiments. When an element is referred to as being connected or coupled to another element, it should be understood that the former may be directly connected or coupled to the latter, or may be electrically connected or coupled to the latter via one or more intermediate elements therebetween. In addition, it should also be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may also be present.

[0068] The terms used in this article are only for the purpose of describing a specific embodiment, and are not intended to limit the present application. As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise. Unless otherwise specified or can be clearly understood from the context as a singular form, otherwise the articles "one" and / or "one" used in the present application embodiment and the appended claims should be collectively interpreted as indicating "one or more". It should be further understood that the terms "including", "including", "including" and "including" used in the present application embodiment specify the presence of the element and do not exclude the presence or addition of one or more other elements. The term "and / or" used in the present application embodiment includes any and all combinations of one or more associated listed items. Unless otherwise defined, all terms including technology and scientific technology used in the present application embodiment have the same meaning as those of ordinary skill in the field of the present application in view of the present application embodiment. It should be further understood that unless the present application embodiment is clearly defined, such as defined in a common dictionary, it should be interpreted as having a meaning consistent with its meaning in the environment of the present application embodiment and the related technology, and should not be interpreted in an idealized or overly formalized manner.

[0069] In the following description, many specific details are set forth to provide a thorough understanding of the present application, and the present application can be practiced without some or all of these specific details. In other cases, well-known processing structures and / or processing are not described in detail, so as not to unnecessarily obscure the present application. It should also be understood that, in some cases, unless otherwise special, it is obvious to those skilled in the relevant art that the features or elements described about one embodiment can be used alone or in combination with other features or elements of another embodiment. Hereinafter, various embodiments of the present application are described in detail with reference to the accompanying drawings. The following description focuses on details to facilitate understanding of the embodiments of the present application. Well-known technical details may be omitted, so as not to obscure the features and aspects of the embodiments of the present application.

[0070] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0071] Figure 1 A block diagram of an exemplary system with a memory provided according to some aspects of the present application is shown. Figure 1 In the embodiment, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1As shown, the system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memory devices 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), wherein the system on a chip may be, for example, an application processor (AP). The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104. Specifically, the memory device 104 may be any memory disclosed in the present application. For example, a phase change random access memory (PCRAM), a three-dimensional NAND flash memory, and the like.

[0072] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108. And is configured to control the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices with low duty cycle environments such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), wherein the SSD or eMMC is used as a data storage for mobile devices with high duty cycle environments such as smart phones, tablet computers, laptop computers, and enterprise storage arrays. The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnection (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0073] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2 In one example shown, the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a processor that connects the memory card to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 3 In another example shown, the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 302. The SSD may also include a processor that interfaces the SSD with a host (e.g., Figure 1 The memory controller 106 may be configured to control the erase, read, and write operations of the memory device 104.

[0074] Figure 4 A schematic diagram of an exemplary memory including peripheral circuits is shown. Figure 4As shown, the memory device 104 may include a memory array 401 and a peripheral circuit 402 coupled to the memory array 401, wherein the memory array 401 may be a NAND flash memory array, wherein memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the storage region of the memory cell 406. Each memory cell 406 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0075] In some embodiments, each memory cell 406 is a single level cell (SLC) having two possible data states and can therefore store one bit of data, for example, the first data state "0" can correspond to a first voltage range, and the second data state "1" can correspond to a second voltage range. In some embodiments, the first voltage range and the second voltage range can be referred to as the threshold voltage distribution of the memory cell. In some embodiments, each memory cell 406 can be a multi-level cell (MLC), for example, MLC can store two bits per cell, three bits per cell (also known as a tri-level cell (TLC), or four bits per cell (also known as a quadruple level cell (QLC). Wherein, regardless of the type of memory cell, the data state includes an erased state and (one or more) programmed states. When performing a programming operation on the memory cell, the memory cell in the erased state is programmed to a certain programmed state. Generally speaking, the voltage value in the voltage range corresponding to the programmed state of the memory cell is relatively large.

[0076] like Figure 4As shown, each NAND memory string 408 may include a source select gate (SSG) 410 at its source end and a drain select gate (DSG) 412 at its drain end. The SSG 410 and the DSG 412 may be configured to activate the selected NAND memory string 408 (column of the array) during read and program (or write) operations. In some embodiments, the sources of the NAND memory strings 408 in the same memory block 404 are coupled by the same source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same memory block 404 have an array common source (ACS). According to some embodiments, the DSG 412 of each NAND memory string 408 is coupled to a corresponding bit line 416, and data can be read and written from the bit line 416 via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having DSG412) or a deselect voltage (e.g., 0 volts (V)) to a corresponding DSG412 via one or more DSG lines 413 and / or applying a select voltage (e.g., higher than the threshold voltage of a transistor having SSG410) or a deselect voltage (e.g., 0 V) ​​to a corresponding SSG410 via one or more SSG lines 415.

[0077] like Figure 4 As shown, the NAND memory string 408 can be organized into a plurality of memory blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each memory block 404 is a basic data unit with an erase operation, that is, all memory cells 406 on the same memory block 404 are erased at the same time. In order to erase the memory cells 406 in the selected memory block 404, the source lines 414 coupled to the selected memory block 404 and the unselected memory blocks 404 in the same plane (Plane) as the selected memory block 404 can be biased with an erase voltage (Vers) (e.g., a high positive voltage of 20V or higher). It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. The memory cells 406 of adjacent NAND memory strings 408 can be coupled by word lines 418, which select which row of memory cells 406 receives read and program operations.

[0078] Return to reference Figure 4, the peripheral circuit 402 may be coupled to the memory array 401 via the bit line 416, the word line 418, the source line 414, the SSG line 415, and the DSG line 413. The peripheral circuit 402 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory array 401 by applying a voltage signal and / or a current signal to each target memory cell 406 via the bit line 416, the word line 418, the source line 414, the SSG line 415, and the DSG line 413 and sensing the voltage signal and / or the current signal from each target memory cell 406. The peripheral circuit 402 may include various types of circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 402 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional circuitry not shown.

[0079] The page buffer / sense amplifier 504 may be configured to read data from the memory array 401 and program (write) data to the memory array 401 according to a control signal from the control logic unit 512. In one example, the page buffer / sense amplifier 504 may store a page of programming data (write data) to be programmed into one page 420 of the memory array 401. In another example, the page buffer / sense amplifier 504 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 406 coupled to the selected word line 418. In yet another example, the page buffer / sense amplifier 504 may also sense a low-power signal from the bit line 416 representing a data bit stored in the memory cell 406, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 may be configured to be controlled by the control logic unit 512, and select one or more NAND memory strings 408 by applying a bit line voltage generated from the voltage generator 510.

[0080] The row decoder / word line driver 508 may be configured to be controlled by the control logic unit 512 and select / deselect the memory block 404 of the memory array 401 and select / deselect the word line 418 of the memory block 404. The row decoder / word line driver 508 may also be configured to drive the word line 418 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the SSG line 415 and the DSG line 413. As described in detail below, the row decoder / word line driver 508 is configured to perform an erase operation on the memory cell 406 coupled to the selected word line(s) 418. The voltage generator 510 may be configured to be controlled by the control logic unit 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 401.

[0081] The control logic unit 512 may be coupled to each peripheral circuit described above, and is configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic unit 512, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic unit 512, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 512, and to buffer status information received from the control logic unit 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via a data bus 518, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory array 401 or relay or buffer data from the memory array 401.

[0082] For the memory device or memory system described above, the page buffer included therein is as follows: Figure 6 As shown, it shows a schematic diagram of the structure of a page buffer group included in a memory device. Figure 6In the embodiment, the page buffer group also includes the page buffer / sense amplifier 504 as described above. In the memory device, each bit line 416 is coupled to a page buffer, that is, in some embodiments, the memory device may include a page buffer group 600, wherein the page buffer group 600 may include page buffer 1 (PB1) to page buffer k (PBK), and each page buffer 601 is coupled to the memory array 401 via a bit line, for example, page buffers PB1 to PBK may be coupled to the memory array 401 via corresponding bit lines BL1 to BLk, respectively. The page buffer referred to in the present application is any one of the aforementioned page buffer groups 60. As the storage density of the memory device increases, the number of page buffers used also increases significantly, thereby occupying a larger area, resulting in a higher cost for manufacturing the memory device.

[0083] In order to solve one or more of the above technical problems, the present application provides a memory device, such as Figure 7 As shown, the memory device 70 includes:

[0084] A memory array 71, comprising a plurality of memory cells;

[0085] The peripheral circuit 72 is coupled to the memory array and includes: a plurality of page buffers 721; each page buffer includes: at least two groups of latch circuits 7211; each group of latch circuits includes: a first sub-latch circuit 72111 and a second sub-latch circuit 72112, wherein;

[0086] The first sub-latch circuit is coupled to the sensing node and is configured to: latch the first information on the sensing node 7212;

[0087] The second sub-latch circuit is coupled to the sensing node and is configured to: latch the second information on the sensing node through the first sub-latch circuit;

[0088] The first information of the first sub-latch circuit and the second information of the second sub-latch circuit are exchanged through the sensing node.

[0089] Here, the structure of the memory array 71 described can be referred to in the previous Figure 4 The structure of the peripheral circuit 72 described can be mostly referred to in the previous Figure 5The structure drawn. In the present application, for each page buffer in the peripheral circuit, it includes at least two groups of latch circuits 7211, each group of latch circuits includes: a first sub-latch circuit 72111 and a second sub-latch circuit 72112, wherein the first sub-latch circuit 702111 is coupled to the sensing node and is configured to latch the first information of the sensing node (SO); the second sub-latch circuit is also coupled to the sensing node and is configured to: latch the second information on the sensing node through the first sub-latch circuit, and the first information in the first sub-latch circuit and the second information in the second sub-latch circuit are exchanged through the sensing node. According to the above description, it is explained that there is a certain dependency relationship between the first sub-latch circuit and the second sub-latch circuit, so that when the first sub-latch circuit and / or the second sub-latch circuit are used in the programming operation or verification operation of the memory device, the two need to cooperate with each other to complete the corresponding operation, and the dependency relationship between the two will be described in detail later.

[0090] Here, the SO may refer to a node in a page buffer coupled to a corresponding bit line (a bit line connected to the page buffer). The SO is a relatively important node in the programming process or verification process of the memory device, which can assist in implementing a variety of operations. For example, in some embodiments, the SO can be precharged to a higher potential, and then the SO performs at least one discharge operation, so that the voltage at the SO corresponding to the memory cell at different discharge stages is sensed by the sensing circuit in the page buffer, so as to determine whether the verification of the memory cell is completed based on this sensing result. For another example, in some other embodiments, the SO can also read the second information of the second sub-latch circuit so as to exchange the first information in the first sub-latch circuit with the second information in the second sub-latch circuit. For these two cases, examples will be given in detail later.

[0091] Here, each group of latch circuits may also include: a transmission control switch 72113, which connects the first sub-latch circuit and the second sub-latch circuit, and is configured to: respond to a transmission control signal, be in an on state, and transmit the first information stored in the first sub-latch circuit to the second sub-latch circuit.

[0092] That is to say, a transmission control switch is connected between the aforementioned first sub-latch circuit and the second sub-latch circuit, and the transmission control switch is in an on state under the control of a transmission control signal. At this time, the first information in the first sub-latch circuit can be stored in the second sub-latch circuit.

[0093] For the transmission control switch, the transmission control switch may include: a transmission gate of a single MOS transistor structure or a transmission gate of a dual MOS transistor crystal structure; the dual MOS transistor crystal includes a CMOS transmission gate formed by connecting a PMOS transistor and an NMOS transistor in parallel.

[0094] It should be noted that the transmission control switch can be implemented by various controllable switch elements, such as a transmission gate with a single MOS transistor structure or a transmission gate with a dual MOS transistor structure provided in the embodiments of the present application.

[0095] Here, the second sub-latch circuit may include: a parasitic capacitor storing the second information; and the parasitic capacitor is connected to a terminal of the transmission control switch away from the first sub-latch circuit.

[0096] That is, the second sub-latch circuit stores the second information via the parasitic capacitance included therein.

[0097] The memory device provided by the embodiment of the present application includes a page buffer including at least two groups of latch circuits, and each group of latch circuits includes a first sub-latch circuit and a second sub-latch circuit that are interdependent. The interdependence between the two is reflected in: on the one hand, when the second sub-latch circuit latches the second information, it can only be achieved with the assistance of the first sub-latch circuit. For example, when the second sub-latch circuit latches the second information, the second information can be latched to the first sub-latch circuit first, and then the transmission control switch is turned on to transmit the second information to the parasitic capacitance of the second sub-latch circuit to achieve the latching of the second information to the second sub-latch circuit. On the other hand, the first information latched by the first sub-latch circuit and the second information latched by the second sub-latch circuit can be exchanged with the assistance of the transmission control switch and the sensing node. For example, when the first information and the second information need to be exchanged, the second information can be read onto the SO first, and then the transmission control switch is turned on (i.e., the transmission control signal is connected to make it in the on state), the first information is transmitted to the second sub-latch circuit, and latched into its parasitic capacitance; then, the first information in the first sub-latch circuit is cleared (the first sub-latch circuit is reset); then, the transmission control switch is turned off (the transmission control signal is removed to make it in the off state), and the second information on the SO is latched into the first sub-latch circuit, thereby completing the exchange of the first information and the second information. With this design, the number of components used in the second sub-latch circuit will be reduced, thereby reducing the area of ​​the chip where the memory device is located, thereby saving the cost required for manufacturing the memory device.

[0098] In actual application, there are two types of latch circuits in the page buffer. One type of latch circuit can be used to temporarily store data to be programmed into the memory array or temporarily store data read from the memory array. This type of latch circuit can be called a data latch circuit. Another type of latch circuit can be used to temporarily store intermediate data in the programming operation (or programming process) of the memory cell or verification data in the verification operation (or verification process) after the programming operation. This type of latch circuit can be called a sensing circuit, wherein the sensing circuit includes at least a main latch circuit. The specific explanation of the intermediate data and verification data will be explained in detail when describing the programming process and the verification process.

[0099] Based on this, in some embodiments, the at least two groups of latch circuits are configured to store data to be written or read data.

[0100] That is to say, at least two groups of latch circuits provided in the embodiment of the present application are all used to temporarily store part or all of the data to be written and the data to be read.

[0101] In some embodiments, one set of latch circuits in the at least two sets of latch circuits is configured to: store intermediate data in a programming process or verification data in a verification process;

[0102] The other groups of latch circuits in the at least two groups of latch circuits are configured to store data to be written or read data.

[0103] That is to say, one of the at least two groups of latch circuits provided in the embodiment of the present application is used to temporarily store intermediate data in the programming process or verification data in the verification process; the other remaining groups of latch circuits are used to store part or all of the data to be written or read.

[0104] In some embodiments, the at least two groups of latch circuits include: two groups of latch circuits; wherein,

[0105] The two groups of latch circuits are configured to store LP data, MP data, UP data and XP data to be written or read.

[0106] It should be noted that when the memory cell is configured as a QLC type, the memory cell can store 4 bits of data, namely: low page (LP, Low Page) data, middle page (MP, Middle Page) data, upper page (UP, Up Page) data and extra page (XP, Extra Page) data. In this configuration, the memory cell corresponds to 16 data states (that is, it has 16 threshold voltage distributions, and the threshold voltage of each memory cell belongs to a certain threshold voltage distribution among the 16 threshold voltage distributions); it requires 4 latch circuits to store the LP data, MP data, UP data and XP data. These four latch circuits can use two groups of latch circuits provided in this application (including two first sub-latch circuits and two second sub-latch circuits, a total of 4 latch circuits) to store the LP data, MP data, UP data and XP data respectively.

[0107] That is, if the at least two groups of latch circuits include two groups of latch circuits, then both groups of latch circuits are used as data latch circuits. Then, when the storage unit is configured as an OLC type, it contains 16 data states, corresponding to 4 pages of data (LP data, MP data, UP data, and XP data). Then, each latch circuit in the two groups of latch circuits is used to store the corresponding LP data, MP data, UP data, and XP data.

[0108] In some embodiments, the at least two groups of latch circuits include: three groups of latch circuits; wherein,

[0109] The two groups of latch circuits are configured to: store LP data, MP data, UP data and XP data corresponding to the data to be written or read;

[0110] The remaining group of latch circuits is configured to store intermediate data in a programming process or verification data in a verification process.

[0111] It should be noted that the page buffer provided in the present application may include three groups of latch circuits, and the structure of each group of latch circuits is as described above. Figure 7 When the memory cell is also configured as a QLC type, two of the three groups of latch circuits can be used to store LP data, MP data, UP data, and XP data corresponding to the data to be written or read; the remaining group of latch circuits can be used to store intermediate data in the programming process or verification data in the verification process.

[0112] Here, the intermediate data in the programming process may include but is not limited to the data (or information) on the sensing node that may be damaged by certain operations during the programming process. Before the operation is performed, the data on the sensing node is temporarily stored in a latch circuit that is not used by the operation. At this time, the data on the sensing node is the intermediate data in the programming process. The verification data in the verification process may include but is not limited to the verification results in the verification process such as 4BL sensing information, 3BL sensing, pass sensing information, etc. in the programming verification operation using the 4BL (bit line) scheme.

[0113] It should be noted that when the at least two groups of latch circuits include two groups of latch circuits, it is also feasible to adopt the following design: for example, one group is used to store a part of the data to be written or read; the other group of latch circuits is used for intermediate data in the programming process or verification data in the verification process. In this design, the page buffer also includes other independent latch circuits used to store another part of the data to be written or read. The specific situation can be determined according to the specific circuit. Here, the storage unit can also be configured as a secondary unit (DLC, Double level cell) or TLC or SLC type. Different types of storage cells require different numbers of data latch circuits, but the working principle of each group of latch circuits provided in the embodiment of the present application is the same. Therefore, in the following description, unless otherwise specified, the storage unit is configured as a QLC type to illustrate how the page buffer provided in the embodiment of the present application works in the memory device.

[0114] In some embodiments, Figure 8 As shown, the first sub-latch circuit may include: a setting switch 801 and a storage element 802, wherein:

[0115] The setting switch is coupled to the sensing node and connected to the storage element, and is configured to latch the first information on the sensing node to the storage element in response to a setting signal.

[0116] In some embodiments, the first sub-latch circuit may further include: a reset switch 803 connected to the storage element and configured to: reset the storage element in response to a reset signal.

[0117] It should be noted that the first sub-latch circuit may also be referred to as a static latch, which may include a set switch and a storage element, wherein the set switch may be a control switch for writing data into the storage element, which is configured to latch the first information on the sensing node to the storage element in response to a set signal, that is, to write (or store) the first information on the sensing node into the storage element. The first sub-latch circuit may also include a reset switch coupled to the storage element, which may be a control switch for resetting the storage element included in the first sub-latch circuit, which is configured to reset the storage element in response to a reset signal.

[0118] Among them, Figure 8 As shown, the storage element 802 may include: a first inverter 8021 and a second inverter 8022; wherein, the input end of the first inverter is connected to the output end of the second inverter to form a first node 8023; the output end of the first inverter is connected to the input end of the second inverter to form a second node 8024; the second node is connected to the second sub-latch circuit and is configured to: store the first information.

[0119] The set switch 801 includes a first transistor connected to the first node at one end; the reset switch 803 includes a second transistor connected to the second node at one end;

[0120] The other end of the first transistor is connected to the other end of the second transistor.

[0121] Here, both the first transistor and the second transistor can be NMOS transistors. When the control end of the first transistor is connected to the set signal set, the first information on SO is transmitted to the second node 8024. When the control end of the second transistor is connected to the reset signal rst, the second node 8024 included in the storage element is reset.

[0122] In some embodiments, Figure 8 As shown, the first sub-latch circuit may also include: a sensing control switch 804, one end of which is connected to the set switch and the reset switch, and the other end is grounded; the sensing control switch is configured to: be turned on under the action of the level of the sensing node, and write the first information of the sensing node into the storage element through the set switch.

[0123] The type of the reset control switch may be the same as the type of the set switch and the reset switch. That is, the reset control switch may also include an NMOS transistor, which may be referred to as a sensing transistor.

[0124] In some embodiments, the first sub-latch circuit may further include: a reset control switch 805, one end of which is connected to the set switch and the reset switch, and the other end is grounded; the reset control switch is further configured to: in response to a reset control signal, reset the first sub-latch circuit through the reset switch;

[0125] The reset control signal is generated by the control logic contained in the peripheral circuit.

[0126] The type of the reset control switch may be the same as the type of the set switch and the reset switch. That is, the reset control switch may also include an NMOS transistor, which may be referred to as a reset transistor.

[0127] That is to say, based on the aforementioned reset switch, set switch and storage element, the first sub-latch circuit may further include a sensing control switch, which is turned on or off according to the level of SO, and when it is turned on, the first information on the sensing node is written into the storage element through the set switch. The first sub-latch circuit may further include a reset control switch, which is connected to a reset control signal to reset the first sub-latch circuit through the reset switch. The reset control signal may be generated by the peripheral circuit including the control logic according to the actual situation.

[0128] It should be noted that according to Figure 8 In the first sub-latch circuit shown, the on or off of the sensing transistor is affected by the level of the sensing node. In some embodiments, the sensing transistor can be an NMOS transistor, whose gate terminal is connected to the sensing node, the drain terminal is connected to the source terminal of the first transistor and the second transistor, and the source terminal is grounded. In this case, when the level of the sensing node is at a high level (for example, the voltage of the high level is greater than the turn-on voltage of the third transistor), the sensing transistor applies the ground voltage to the first transistor or the second transistor, and then the control terminal of the first transistor stores the ground voltage at the first node when the set signal is connected; or the control terminal of the second transistor stores the ground voltage at the second node when the reset signal is connected. In some embodiments, when the ground voltage is stored at the first node, it can represent the storage data "0".

[0129] Specifically, the first node can store the ground voltage in the following manner: when the sensing transistor is turned on, the ground voltage is allowed to be transmitted to the first transistor through the sensing transistor, and the first transistor is turned on under the action of the set control signal to transmit the ground voltage to the first node. The second transistor is turned on under the action of the reset control signal to transmit the ground voltage to the second node.

[0130] In some embodiments, when the voltage of the first node is at a high level (for example, a voltage higher than the ground voltage is a high level), it can be used to indicate storage data "1"; correspondingly, the voltage of the second node at this time is a low voltage (for example, the ground voltage), which can be used to indicate storage data "0". In other embodiments, when the voltage of the second node is at a high level, it can be used to indicate storage data "1"; correspondingly, the voltage of the first node at this time is a low voltage, which can be used to indicate storage data "0". In actual application, it can also be used that when the first node is at a low level, it indicates storage data "1"; conversely, when the first node is at a high level, it indicates storage data "0". The specific method used for representation depends on the specific encoding method.

[0131] In an optional implementation, it can be considered that when the ground voltage is transmitted to the first node, it means that the data on the SO is stored in the second node; when the ground voltage is transmitted to the second node, it means that the storage element is reset. Specifically, whether the data "0" or the data "1" is used to represent the data of the SO depends on the specific encoding method.

[0132] The control logic and implementation of the sensing control switch described above are as follows: Figure 8 As shown, for the first sub-latch circuit 702111 which can also include a reset control switch, the function of the reset transistor contained therein can be to reset the first sub-latch circuit when exchanging the first information in the first sub-latch circuit and the second information in the second sub-latch circuit, so as to clear the first information in the first sub-latch circuit. Among them, the exchange process of the first information in the first sub-latch circuit and the second information in the second sub-latch circuit can be as follows: first, read the second information in the second sub-latch circuit to SO; then turn on the control switch to transmit the first information to the second sub-latch circuit; then, reset the first sub-latch circuit to clear the first information contained therein, so that the first sub-latch circuit is restored to the initial state (for example, the first node or the second node of the first sub-latch circuit stores data "1" or data "0" to restore the initial state). The reset transistor here plays the role of resetting the first sub-latch circuit, and the reset control signal rst_latch connected to its control terminal can be directly generated by the control logic unit 512 in the aforementioned peripheral circuit, that is, the reset operation can be directly controlled by the control logic unit 512.

[0133] It should be noted that for Figure 8For the first sub-latch circuit shown, if the first information is stored at the second node. According to the working principle described above, the reset of the first sub-latch circuit can also be achieved through the reset transistor and the first transistor, that is, when the reset transistor and the first transistor are both in the on state, the ground voltage is latched at the first node. If the reset logic is represented by a high level, then at this time, the second node is at a high level, that is, the reset operation is achieved. In other words, whether the set switch and the reset switch in the first sub-latch circuit are used for setting or resetting depends on the specific control logic, as long as it can be implemented and logically reasonable. In other words, the specific operation steps of resetting and setting are not limited.

[0134] In some embodiments, Fig. 9 As shown, each group of latch circuits further includes: a first control switch 901 and a second control switch 902 connected in series between the sensing node and the ground, and the first control switch 901 is controlled by the second information latched by the second sub-latch circuit; the second control switch 902 is controlled by the read control signal, wherein,

[0135] When the second information controls the first control switch to be turned on and the read control signal controls the second control switch to be turned on, the second information is read to the sensing node.

[0136] It should be noted that the first control switch and the second control switch here may also include NMOS transistors, and the first control switch and the second control switch are connected in series between the sensing node and the ground, respectively controlled by the second information and the read control signal, and can be used to implement the circuit connection for exchanging the first information and the second information described above. Specifically, the implementation process of exchanging the first information and the second information described above can be as follows: under the action of the read control signal, the second control switch is in the on state, and the second information in the second sub-latch circuit is read to SO; then, under the action of the transmission control signal, the transmission control switch is turned on, and the first information is transmitted to the second sub-latch circuit; then, the first sub-latch circuit is reset; finally, under the action of the set signal, the first transistor is in the on state, and the second information is latched into the first sub-latch circuit, thereby realizing the exchange of the first information and the second information.

[0137] In some embodiments, the page buffer 721 may further include: a master latch circuit coupled to the sensing node, configured to: store intermediate data in a programming process or verification data in a verification process;

[0138] The structure of the main latch circuit is the same as that of the first sub-latch circuit; or, the main latch circuit and the first sub-latch circuit share the sensing control switch and the reset control switch, and the rest of the structures are the same.

[0139] That is to say, the structure of the main latch circuit is the same as that of the first sub-latch circuit, that is, the main latch circuit includes the first inverter, the second inverter, the first transistor, the second transistor, the sensing transistor, and the reset transistor included in the first sub-latch circuit, and the connection structure between the components is also the same as that of the first sub-latch circuit. In other implementations, the first inverter, the second inverter, the first transistor, and the second transistor included in the main latch circuit have the same structure as that of the first sub-latch circuit, and the sensing transistor and the reset transistor can be used together with the first sub-latch circuit.

[0140] It should be noted that the data in the programming process mentioned here has the same meaning as that described above, and will not be repeated here. The verification data in the verification process also has the same meaning as that described above, and will not be repeated here. The main latch circuit and the first sensing latch circuit described later may refer to the same latch circuit, such as ds. The main latch circuit is described in the memory device, and the first sensing latch circuit is described in the operating method described later, in order to form a corresponding relationship with the second sensing latch circuit (such as dl) and the third sensing latch circuit (such as dm). It is just a different name used in different descriptions, which is convenient for description and has no limiting effect.

[0141] In some embodiments, the page buffer may also include: a data transmission circuit, coupled to one group of latch circuits in the two groups of latch circuits, configured to: receive the data to be written and transfer the data to be written to each group of latch circuits in the two groups of latch circuits; or, output the read data.

[0142] It should be noted that the data transmission circuit can be used to receive the data to be written to the memory device through the data path to the latch circuit of the page buffer for temporary storage, so as to be used for subsequent programming. The data transmission circuit can be coupled to one of the two groups of latch circuits used for data latching, that is, the data transmission circuit can sequentially access the LP, MP, UP and XP of the data to be written, and sequentially store the corresponding data in the corresponding latch circuits of the two groups of latch circuits. The data transmission circuit can also output the read data to the datapath so that the memory device can feed back the read data to the memory controller or the host.

[0143] In some embodiments, the page buffer may further include: a pre-charging circuit and a discharging circuit, wherein;

[0144] The precharge circuit is configured to: precharge the sensing node corresponding to the selected storage unit in response to a precharge signal;

[0145] The discharge circuit is configured to discharge the sensing node corresponding to the selected storage unit in response to a discharge signal.

[0146] It should be noted that the pre-charge circuit and the discharge circuit are both coupled to the corresponding bit lines, and the two are used in conjunction with each other to realize pre-charging or discharging of the sensing node, thereby realizing a certain data latching operation. For example, in the verification process, the pre-charge circuit is first used to pre-charge the sensing node SO to a preset initial voltage, and then the sensing node SO is discharged at least once through the discharge circuit to complete at least one verification operation. In this at least one verification operation, the verification result can be latched into the aforementioned main latch circuit or other related latch circuits. There are multiple implementation methods for the structure of the pre-charge circuit and the discharge circuit. The following description can use a method to illustrate its working principle.

[0147] In order to clarify the structure of the page buffer included in the memory device provided in the embodiment of the present application, as shown in FIG. Fig.10 and Fig.11 As shown, Fig.10 A schematic diagram of a structure of a page buffer including two groups of latch circuits is provided for an embodiment of the present application; Fig.11 A schematic diagram of a structure in which a page buffer provided in an embodiment of the present application includes three groups of latch circuits.

[0148] Fig.10The provided page buffer includes two groups of latch circuits for storing data to be written or read: one group of latch circuits includes d2 (first sub-latch circuit) and d1 (second sub-latch circuit); the other group of latch circuits includes dc (first sub-latch circuit) and d3 (second sub-latch circuit), wherein d1 and d2 are connected through a transmission control switch, which is configured to connect d2 with d1 in response to a transmission control signal pass_2 (transmission control signal), and with the assistance of SO, complete the exchange of information between d2 and d1, wherein the second information in d1 is stored in the parasitic capacitance contained therein. Similarly, dc and d3 are not repeated. The page buffer also includes a main latch circuit (or a first sensing latch circuit) ds, a latch circuit dl (second sensing latch circuit) for storing 3BLsensing information, and a latch circuit dm (third sensing latch circuit) for storing 4BL sensing information. The page buffer also includes a precharge circuit and a discharge circuit, wherein the precharge circuit includes: three P-type transistors, wherein the connection structure of the three P-type transistors is as follows: two P-type transistors are connected in parallel to form a transmission gate, and then connected to another P-type transistor. One end of the precharge circuit under this structure is connected to the power supply voltage (such as VDD), and the other end is connected to SO, and in response to the precharge signal (Prech_all signal and Prech_sel signal), the sensing node is charged. The discharge circuit includes two N-type transistors connected in series between the sensing node and the ground (GND), and is configured to discharge SO in response to the discharge signal sodisch. Fig.10 As shown, the page buffer further includes a data transmission circuit configured to receive data to be written or output read data.

[0149] Fig.11 and Fig.10 The structure of the page buffer shown is basically the same, except that the latch circuit d1 for storing 3BL sensing information and the latch circuit dm for storing 4BL sensing information also adopt the structure of the first sub-latch circuit and the second sub-latch circuit. In this design, the page buffer also includes a control circuit, which includes two N-type transistors (a first control switch and a second control switch) connected in series between the power supply voltage and the sensing node, and is configured to read the information in dm to the sensing node in response to the control signal en_4bl_b, so as to subsequently transmit the information latched in d1 (such as 3BL sensing information) to dm, and then latch the relevant information (such as 4BL sensing information) in d1.

[0150] It should be noted that Fig.10 and Fig.11These are just two exemplary structures based on the inventive concept provided by the embodiments of the present application. Without violating the inventive concept of the present application, the page buffer may also have other structures, which will not be described one by one here.

[0151] based on Fig.10 and Fig.11 The basic working principle of each group of latch circuits of the page buffer is as follows:

[0152] (1) Switching the information of the first sub-latch circuit and the second sub-latch circuit. Taking d1 and d2 as an example, D1 represents the second information stored in d1, and D2 represents the first information stored in d2, that is, switching D1 / D2.

[0153] The specific steps may include: applying prech_all+prech_sel signals to pre-charge the sensing node first, and this operation can be represented by "prech_all+prech_sel(SO=1)"; then, applying rd_2 signal (read control signal) so that the second information in d1 is read onto SO, represented by rd_2(SO=~D1); thereafter, applying pass_2 (transmission control signal) to transfer the first information in d2 to d1, represented by pass_2(D1=D2); thereafter, applying rst_2_latch (reset control signal)+set_2 (set signal) to reset d2, represented by rst_2_latch+set_2(D2=1); finally, applying rst_2 (reset signal) to latch the second information into d2, represented by rst_2(D2=~SO=D1).

[0154] (2) Read the data of the latch circuit to SO (first sub-latch circuit or second sub-latch circuit)

[0155] For the second sub-latch circuit, take reading d1 as an example.

[0156] The process is as follows: prech_all+prech_sel(SO=1);rd_2(SO=~D1).

[0157] For the first sub-latch circuit, taking reading d2 as an example, the process can be: firstly exchanging information between the first sub-latch circuit and the second sub-latch circuit, and then reading information on the second sub-latch circuit, so as to complete reading the information of the first sub-latch circuit to SO.

[0158] (3) Write the data on SO into the latch circuit (first sub-latch circuit or second sub-latch circuit)

[0159] For writing into the first sub-latch circuit, d2 is taken as an example.

[0160] The process is: apply set_2 (set signal), write the data on SO into the first sub-latch circuit, and use set_2 (D2 = ~SO).

[0161] For writing into the second sub-latch circuit, taking d1 as an example, the process may be as follows: firstly, the data on SO is written into the first sub-latch circuit, and then the information of the first sub-latch circuit and the second sub-latch circuit are exchanged to complete writing the data on SO into the second sub-latch circuit.

[0162] (4) The second information in the second sub-latch circuit is transmitted to the first sub-latch circuit. Take the transmission of d3 to d2 as an example. The process can be as follows: rst_2_latch+set_2(D2=1); prech_all+prech_sel(SO=1); rd_c(SO=~D3); rst_2(D2=~so=D3).

[0163] It should be noted that the symbol “~” represents a negation logic operation; the symbol “=” represents an assignment operation.

[0164] In actual application, when page buffers with different structures are applied to memory devices, there will be some differences in the implementation of each step in the programming process and the verification process. Based on this, according to the memory device described above, it includes a page buffer; the page buffer includes at least two groups of latch circuits; each group of latch circuits includes a first sub-latch circuit and a second sub-latch circuit that are mutually dependent and coupled to the sensing node; see Fig.12 As shown, the embodiment of the present application also provides an operating method of a memory device, and the process may include:

[0165] Step 1201: when selecting a data state to be operated in a programming operation or a verification operation of the memory device, reading the second information latched in the second sub-latch circuit to the sensing node;

[0166] Step 1202: storing the second information of the sensing node in the sensing latch circuit of the page buffer;

[0167] Step 1203: exchanging the second information of the second sub-latch circuit and the first information latched by the first sub-latch circuit;

[0168] Step 1204: read the first information from the second sub-latch circuit to the sensing node, and read the second information from the sensing latch circuit to the sensing node to obtain selected information indicating the data state to be operated.

[0169] It should be noted that the operating method may include a method for programming a memory device, which may be a method for programming the memory device. Figures 7 to 11A programming and verification method for a memory device of the structure shown in FIG. In the programming and verification method, due to the existence of Figures 7 to 11 The page buffer shown in the figure, that is, the storage includes the first sub-latch circuit and the second sub-latch circuit which are interdependent. Therefore, when it comes to reading or writing the information stored in the first sub-latch circuit and the second sub-latch circuit, some operation steps have undergone some changes. For example, when the data state is selected during the programming process or the verification process, it is necessary to read the data from the first sub-latch circuit and the second sub-latch circuit storing the data to be written to the SO. Since the reading of the first sub-latch circuit requires the assistance of the second sub-latch circuit, it involves the exchange of information between the second sub-latch circuit and the first sub-latch circuit. When the information is exchanged between the second sub-latch circuit and the first sub-latch circuit, the data on the SO will be destroyed. Therefore, it is necessary to temporarily store the data read from the SO to the unused latch circuit.

[0170] Based on this, in the embodiments of the present application, based on Fig.10 and Fig.11 Under the page buffer shown, the specific operation of selecting the data state can be as follows: first read the second information in the second sub-latch circuit from the sensing node, then first store the second information on the sensing node in the sensing latch circuit included in the page buffer, then exchange the second information of the second sub-latch circuit with the first information latched by the first sub-latch circuit, and finally, read the first information from the second sub-latch circuit to the sensing node, and read the second information from the sensing latch circuit to the sensing node to obtain the selected information indicating the data state to be operated. Afterwards, the control logic determines the data state to be operated (the data state to be programmed or the data state to be verified) according to the selected information on SO. Here, the sensing latch circuit may include the aforementioned Fig.10 or Fig.11 ds or dl in.

[0171] Specifically, in some embodiments, the sensing latch circuit includes a first sensing latch circuit and a second sensing latch circuit; the data state to be operated includes a data state to be programmed or a data state to be verified; the storing the second information of the sensing node in the sensing latch circuit included in the page buffer includes:

[0172] When selecting a data state to be programmed corresponding to a programming operation of the memory device, storing the second information of the sensing node in the second sensing latch circuit; wherein the first verification information stored in the second sensing latch circuit is invalid;

[0173] When selecting a data state to be verified corresponding to a verification operation of the memory device, storing the second information of the sensing node in the first sensing latch circuit, wherein the second verification information stored in the first sensing latch circuit is invalid;

[0174] The first verification information and the second verification information are generated when a verification operation is performed on the memory device last time.

[0175] Here, the second sensing latch circuit may include the aforementioned d1. The first sensing latch circuit may include the aforementioned ds, or may be referred to as a master latch circuit. The second verification information may refer to 3BL sensing information. The first verification information may refer to pass sensing information.

[0176] In some embodiments, the step of exchanging the second information of the second sub-latch circuit and the first information latched by the first sub-latch circuit includes:

[0177] charging the sensing node so that the level of the sensing node reaches a preset threshold value, so as to read the second information to the sensing node;

[0178] In response to a transmission control signal, closing a transmission path between the first sub-latch circuit and the second sub-latch circuit, and transmitting the first information to the second sub-latch circuit;

[0179] performing a clearing operation on the first sub-latch circuit so that the first sub-latch circuit is restored to an initial state;

[0180] The second information is written into the first sub-latch circuit.

[0181] It should be noted that, for the specific operation steps, please refer to the first item (1) in the basic working principle of the first sub-latch circuit and the second sub-latch circuit mentioned above.

[0182] In some embodiments, the operation method may further include:

[0183] When writing second information to the second sub-latch circuit in a programming operation or a verification operation of the memory device, the second information is written into the first sub-latch circuit; the first sub-latch circuit and the second sub-latch circuit are exchanged so that the second information is stored in the second sub-latch circuit.

[0184] It should be noted that what is described here is the operational steps of writing the second information into the second sub-latch circuit in a programming operation or a verification operation. For specific implementation, please refer to the third item (3) of the basic working principle of the first sub-latch circuit and the second sub-latch circuit mentioned above.

[0185] In order to specifically understand the influence of the page buffer provided in the embodiment of the present application on programming and verification, the following is a diagram including the aforementioned Fig.11 The programming and verification of the memory device of the page buffer is shown as an example.

[0186] Specifically, Fig.13 As shown, it shows the programming process of the memory device. The process specifically includes:

[0187] Step 1: Cache the data to be written. For details, refer to the above steps for temporarily storing the data to be written.

[0188] Step 2: Preprocess the data to be written. For details, refer to the above preprocessing steps.

[0189] Step 3: Program prohibition setting, that is, applying a program prohibition bit line voltage to the program prohibition memory cell in the selected first memory cell.

[0190] Step 4: First forced programming setting, that is, using the first forced information to adjust the bit line voltages of some memory cells in the selected first memory cells to prevent over-programming.

[0191] Step 5: second forced programming setting, that is, using the second forced information to adjust the bit line voltages of some of the selected second memory cells to prevent over-programming.

[0192] Step 6: Selecting the data state to be programmed, that is, selecting the data state to which the selected first memory cell is to be programmed.

[0193] After step 6, a programming pulse corresponding to the data state to be programmed should be applied to the selected first memory cell to program the memory cell to be programmed.

[0194] Step 7: Fail Bit Count (FBC), that is, the number of programming failures after programming the selected first memory cell.

[0195] Step 8: Restore 4BL information.

[0196] Step 9: Programming passes the programming operation. That is, all latch circuits for storing data in the page buffer corresponding to the memory cells that have passed programming in the selected first memory cells are restored to their initial states, for example, all store the number "1".

[0197] Wherein, in step 1, the data to be written may be configured to include multiple pages of data, wherein the multiple pages of data may be related to the type into which the storage unit is to be configured. For example, if the storage unit is to be configured as a QLC type, the multiple pages of data may include: LP data, MP data, UP data, and XP data. For another example, if the storage unit is to be configured as a TLC type, the multiple pages of data may include: LP data, MP data, UP data. Regardless of the type into which the storage unit is to be configured, the programming method is similar.

[0198] Wherein, for step 1, the plurality of latch circuits include a first latch circuit and a second latch circuit; the data to be written is input from a data transmission circuit coupled to a first sub-latch circuit in the second latch circuit; the cache data to be written (step 1) may include:

[0199] receiving LP data of data to be written, and storing the LP data in a first sub-latch circuit in the second group of latch circuits;

[0200] Cutting off the path between the first sub-latch circuit and the second sub-latch circuit in the second group of latch circuits;

[0201] receiving MP data of data to be written, and storing the MP data in a second sub-latch circuit in a second group of latch circuits;

[0202] receiving UP data of data to be written, and storing the UP data in the second sub-latch circuit in the first group of latch circuits;

[0203] XP data of data to be written is received, and the XP data is stored in a first sub-latch circuit in a first group of latch circuits.

[0204] It should be noted that if Fig.11 and Fig.10 In the page buffer, d1 and d2 may be an example of the second group of latch circuits; dc and d3 may be an example of the first group of latch circuits. Fig.10 and Fig.11Under the page buffer structure shown, temporarily storing data to be written may include: pass_2+pass_c is opened to connect the path between the first sub-latch circuit and the second sub-latch circuit in the first group of latch circuits; and the path between the first sub-latch circuit and the second sub-latch circuit in the second group of latch circuits is connected, that is, d1 and d2 are connected; and dc and d3 are connected; dc receives LP data from the data transmission circuit, and stores the LP data in the first sub-latch circuit (d1) in the second group of latch circuits; then, pass_2 is closed, and dc receives MP data from the data transmission circuit and stores the MP data in the second sub-latch circuit (d2) in the second group of latch circuits; then, dc receives UP data from the data transmission circuit, and stores the UP data in the second sub-latch circuit (d3) in the first group of latch circuits; and dc receives XP data from the data transmission circuit and stores the XP data in the first sub-latch circuit (dc) in the first group of latch circuits.

[0205] The above process can be simplified as follows: the data to be written includes the input of the 4 pages of data as mentioned above. The data to be written input by the user is successively input into the DC latch through the datapath. The data to be written needs to realize D1=DC (dc receives data and transfers it to d1), D2=DC, and D3=DC in sequence. Among them, the operation of D1=DC can be as follows: pass_2+pass_c is turned on; connect D1 / D2, D3 / DC; transfer DC data to D2 and D1; close pass_2. The operation of D2=DC is as follows: pass_c is turned on, connect D3 / DC; transfer DC data to D2; the operation of D3=DC is as follows: pass_c is turned on; close pass_c.

[0206] Here, the operations of reading, writing and information exchange between the first sub-latch circuit (d2) and the second sub-latch circuit (d1) can be performed according to the steps described above, which will not be repeated here.

[0207] For step 2, preprocessing the data to be written may include: preprocessing the multiple pages of data so that the data to be written is stored in the corresponding latch circuit according to a preset code.

[0208] It should be noted that the purpose of this step is to re-transcode the data to be written that has been stored in the corresponding latch circuit according to the preset encoding, and store it in the corresponding internal data of the memory device for convenient operation, so as to facilitate the operation of the page buffer. The logic required to be implemented by the read latch circuit (latch) involved in the preprocessing process is: SO = ~DS&P*, where P* represents the selected data state, which is the same as the selection logic described above, and can refer to the previous description; DS stores the mark that has not been preprocessed in the selected data state. The logic required to be implemented by the write latch involved in the preprocessing process is to perform set / rst operations on the latch circuit that stores data corresponding to the page buffer corresponding to the selected storage unit, with the purpose of changing the corresponding number in the original code to the corresponding number in the internal encoding, for example, changing from the "0" corresponding to the original code to the corresponding "1" in the internal programming.

[0209] For example, a memory device includes Fig.11 The page buffer shown. For the case where the first sub-latch circuit needs to be written, the selected information on SO can be used to write to the latch directly. For example, writing 1 to D2: SO = ~DS&P*, set_2 (D2 = 1). For the case where the second sub-latch circuit needs to be written, a switch operation is required with the first sub-latch circuit. Since there is pre-processing mark information in DS, but DL is not used at this time, DL is used as a temporary storage of SO before the switch operation. For example, writing 0 to D1: SO is transferred to DL for temporary storage (DL = ~DS&P*); switch D1 / D2; prech_all + prech_sel (SO = 1); rd_l; rst_2 (D1 = 0).

[0210] For step 3, the programming prohibition setting may include sequentially storing the multiple pages of data in the first sensing latch circuit (i.e., ds) of the page buffer to generate programming inhibition information. Specifically, the following steps may be adopted to implement: first, the LP data stored in the second sub-latch circuit in the second group of latch circuits is transferred to the main latch circuit; then, the MP data in the first sub-latch circuit in the second group of latch circuits is transferred to the second sub-latch circuit in the second group of latch circuits; then, the MP data is read to the sensing node, and the MP data is stored in the main latch circuit; then, the UP data and the XP data are sequentially stored in the main latch circuit to generate programming inhibition information.

[0211] It should be noted that the above steps implement the logic DS=D1&D2&D3&DC, so that programming inhibition information is generated. The programming inhibition information can be used to select the storage cells that are prohibited from programming, and apply the bit line voltage that prohibits programming on the bit line corresponding to the storage cells that are prohibited from programming according to the programming inhibition information. That is, the operation as in step 3 is implemented. Here, for step 3, the selected first storage cell can be selected by the control logic unit according to the preset programming method. The storage cells that have been programmed in the previous programming operation in the selected first storage cells do not need to be programmed this time. Therefore, the corresponding bit line voltage is provided to the selected storage cells according to the programming inhibition information. The bit line voltage may include the bit line voltage (such as VDD) corresponding to the storage cells that have passed the programming in the selected storage cells and the bit line voltage (such as ground voltage) corresponding to the storage cells that have not passed the programming in the selected storage cells.

[0212] For the above process, it is still necessary to include Fig.11 The page buffer shown in FIG. 1 is used as an example for explanation. The process specifically includes the following steps:

[0213] 1. Transmit D1 to DS (DS = D1);

[0214] 2. switch D1 / D2;

[0215] 3.prech_all+prech_sel(so=1);

[0216] 4.rd_2 (so = ~D2);

[0217] 5.rst_s(DS=D1&D2);

[0218] 6. Repeat steps 3-5 for D3 (DS = D1&D2&D3);

[0219] 7. switch D3 / DC;

[0220] 8. Repeat step 6 (DS=D1&D2&D3&D4).

[0221] After the program inhibit information is obtained, a bit line voltage is provided to a selected first memory cell in the memory device according to the program inhibit information.

[0222] For steps 4 and 5, the first forced programming setting and the second forced programming setting may include: adjusting the bit line voltage according to first bit line forced information stored in a second sense latch circuit and second bit line forced information stored in a third sense latch circuit included in the page buffer.

[0223] It should be noted that the second sensing latch circuit can be as follows: Fig.10 or Fig.11 The third sensing latch circuit may be as follows: Fig.10 or Fig.11 The first bit line forced information may be the aforementioned 3BL sensing information, and the second bit line forced information may be the aforementioned 4BL sensing information. According to this programming method, the selected memory cell can be prevented from being over-programmed, thereby reducing the width of the threshold voltage distribution of multiple memory cells and improving the accuracy of the programming operation.

[0224] In actual application, the selected first storage cell may include multiple storage cells; these storage cells may be coupled to the same word line or several word lines. In other words, the word lines coupled to the selected first storage cell will be simultaneously applied with programming pulses to perform this programming operation. And if the selected first storage cell is configured as a multi-data state type for storing multi-bit data, the selected first storage cell needs to be programmed multiple times to complete the programming, and gradually complete the programming of each data state. Therefore, before applying a programming pulse to the word line coupled to the selected first storage cell, it is necessary to first select the corresponding state to be programmed, that is, select the data state to be programmed, in order to apply the corresponding programming pulse.

[0225] For step 6, the selection of the data state to be programmed may include: reading one or more pages of data selected from the multiple pages of data to a sensing node to generate selection operation information according to a preset logic, and the specific steps may include: selecting a first page of data to be used from the multiple pages of data according to the preset logic;

[0226] If the first page data is stored in the first sub-latch circuit, temporarily storing the data on the sensing node to the first sensing latch circuit or the second sensing latch circuit of the page buffer; transmitting the first page data to the second sub-latch circuit associated with the first sub-latch circuit; reading the first page data to the sensing node; the data in the first sensing latch circuit or the second sensing latch circuit is invalid data;

[0227] If the first page data is stored in the second sub-latch circuit, directly reading the first page data to the sensing node;

[0228] The first page data includes at least one of the following: LP data, MP data, UP data, and XP data.

[0229] Here, the preset logic can refer to a logic algorithm designed before programming for obtaining the data state to be programmed. For example, the type of the selected storage unit is QLC, which contains 16 data states (in order: P0, P1, P2, ..., P15), and the selection of a certain data state can be achieved by selecting all the "0"s of the coded data corresponding to the data to be written. Then, for example, the logic for selecting the P1 state is SO=~D1&~D2&~D3&~DC; the logic to be implemented for selecting P3 is SO=~D1&~D3&~DC; the logic to be implemented for selecting P7 is SO=~D1&~D2; the logic to be implemented for selecting P15 is SO=~D3.

[0230] Here, the second sensing latch circuit may be as follows: Fig.11 The page buffer shown includes d1. The first sensing latch circuit can be as follows Fig.11 The page buffer shown includes ds. According to the description of the information stored in the first sub-latch circuit described above, the description of SO is read, which needs to be converted into the information of the second sub-latch circuit. Since the data already read out in SO will be destroyed in this process, before exchanging the information in the first sub-latch circuit and the second latch circuit, the data on SO is temporarily stored in a latch circuit (latch) to prevent the loss of data on SO. For example, during the selection operation of the data state to be programmed in the programming process, the first sensing latch circuit stores 4BL sensing information, and the data in dl is useless (that is, invalid data), and dl can be used to temporarily store the data on SO. For another example, during the selection operation of the data state in the programming operation that prohibits programming in the programming process, the data in the first sensing latch circuit is useless (invalid data), and DS can be used to temporarily store SO data. For another example, during the selection of the data state to be verified in the verification process and the selection of the storage unit that has passed the programming, DS can also be used to temporarily store SO data. That is, in response to the latch circuit storing the first page data being the first sub-latch circuit, the data on the sensing node is temporarily stored in the first sensing latch circuit or the second sensing latch circuit of the page buffer; the first page data is transmitted to the second sub-latch circuit associated with the first sub-latch circuit; the first page data is read to the sensing node. When the first page data is stored in the second sub-latch circuit, the stored information can be directly read to the SO.

[0231] It should be noted that the first page data here may include one or more pages of the multiple pages of data. When the first page data includes one page, it is sufficient to execute the above method once. However, when the first page data includes several pages, it is executed multiple times in the above method, so that the several pages of data involved are read to the SO, and calculations are performed on the SO according to a certain logic to generate selection operation information or other selection operation information, so as to realize the selection of the data state to be programmed.

[0232] The implementation process of the specific circuit is as mentioned above Fig.11 The page buffer shown in the figure is used as an example. Taking the data state P1 to be programmed in the programming process as an example, the specific operation process can be as follows: rst_sa_latch+set_l(DL=1); prech_all+prech_sel(so=1); rd_2+rd_c(so=~D1&~D3); rst_l(DL=~(~D1&~D3)); switchD1 / D2; switch D3 / DC(D1=D2, D3=DC); rd_l, rd_2, rd_c(so=~D1&~D2&~D3&~DC).

[0233] For another example, taking the selection operation of data state P1 in the programming operation prohibited in the programming process as an example, the specific operation process can be as follows: rst_sa_latch+set_s(DS=1); prech_all+prech_sel(so=1); rd_2+rd_c(so=~D1&~D3); rst_s(DS=~(~D1&~D3)); switch D1 / D2, switch D3 / DC(D1=D2, D3=DC); rd_s, rd_2, rd_c(so=~D1&~D2&~D3&~DC).

[0234] For another example, the specific operation of selecting the storage unit that has passed programming during the verification process (in the P1 state) can be as follows: prech_all+prech_sel(SO=1); rd_s+rd_2+rd_c(so=~DS&~D1&~D3); rst_sa_latch+set_s(DS=1); rst_s(DS=~(~DS&~D1&~D3)); switch D1 / D2, switch D3 / DC(D1=D2, D3=DC); rd_s, rd_2, rd_c(SO=~DS&~D1&~D2&~D3&~DC).

[0235] The operations in step 7 and step 8 that do not involve the latch circuit in the page buffer in the embodiment of the present application will not be described in detail here.

[0236] See also Fig.14 , which shows a specific flow chart of the verification process.

[0237] exist Fig.14 The verification process may include:

[0238] Step 1, start verification, select Pn programming state. Assume that after Pn-1verify is completed, enter verify Pn state, select programming state operation DS=P*, where P* selects Pn programming state operation according to the data in D1 / D2 / D3 / DC.

[0239] Step 2, 3BL sensing; here, before 3BL sensing, the SO corresponding to the first storage unit and the second storage unit is precharged, and SO is precharged to a preset initial voltage. During 3BL sensing, the first verification information is latched into the first sensing latch circuit dl. SO is precharged using the data of DS (DS=P*), and then SO continues to developdischarge (gradually discharge). After the development time of t_sodev_3bl, soblk and sodisch are closed to stop development, and then rst_l is opened to store the 3BL sensing information in DL (DL=DL&~SO). Among them, the symbol & represents logical AND; the symbol ~ represents logical NOT.

[0240] Step 3: Exchange DL / DM. Transmit 3BL sensing information to DL / DM

[0241] Step 4, 4BL sensing; that is, DL=~SO. Here, based on 3BL sensing, SO continues to be discharged for a period of time (such as a second preset time length), and then the second verification information (that is, 4BL sensing information) is latched into the first sensing latch circuit DL.

[0242] Step 5, Pass sensing; here, based on 4BL sensing, continue to discharge SO for a period of time (such as the third preset time), and then latch the third verification information (i.e., pass sensing information) into the main latch circuit DS. The specific circuit operation is described as follows: turn on soblk and sodisch, and after the development time of t_sodev_Pass, turn off soblk and sodisch to stop development; clear DS data to prepare for Pass sensing (DS=1); turn on rst_s to sense Pass data into DS (DS=~SO); during the development process, because sodisch is turned on, the 4BL' data on SO will be cleared by DS.

[0243] Step 6, the Pass storage unit is prohibited from programming; here, the bit line voltages of the bit line coupled to the first storage unit are different according to the first verification information, the second verification information and the third verification information, wherein the storage unit that has passed the verification is prohibited from programming (the programming prohibition bit line voltage is applied to the third bit line connected to the third group of storage units). Use the Pass data in DS to inhibit the data of D1 / D2 / D3 / DC in the Pn state, that is, write it as 1. That is: D*= ～ DS&P*.

[0244] Step 7, determine whether it is the last programming state;

[0245] Step 8, if not, exchange DL / DM. This step describes the following exchange of data in DL / DM. After the exchange, DL contains 3BLsensing information and DM contains 4BLsensing information. After that, enter the Pn+1 state verify operation, which is similar to the above.

[0246] Step 9: If yes, end verification. Pn+1 is the last verify programming state, so after the end, directly enter the verify recovery and end the verify sequence.

[0247] It should be noted that the verification process also involves the selection operation of the data state, which is similar to the programming process, that is, the specific process may include: reading one or several pages of data selected from the multiple pages of data to the sensing node according to the preset logic, and generating selection operation information indicating the data state to be verified; the second selection operation information is used to select the second storage unit in the data state to be verified; thereafter, according to the three different potentials of the sensing node corresponding to the second storage unit, the first verification information, the second verification information and the third verification information are respectively stored in the first sensing latch circuit, the second sensing latch circuit and the third sensing latch circuit included in the memory device; wherein the first verification information, the second verification information and the third verification information are used to verify the programming result of the second storage unit.

[0248] It should be noted that the preset logic here has the same meaning as the preset logic in the previous programming, and will not be repeated here. This may be a verification operation after programming the storage unit. The first sensing latch circuit described here may be as follows Fig.10 or Fig.11 The second sensing latch circuit may be as shown in FIG. Fig.10 or Fig.11 The third sensing latch circuit may be as follows: Fig.10 or Fig.11The first verification information may be the pass sensing information as described above. The second verification information may be the 3BL sensing information as described above. The third verification information may refer to the verification result obtained by 4BL sensing in the verification operation of the 4BL BIAS programming mode.

[0249] It should be noted that when using Fig.11 When the page buffer shown in the figure performs programming or verification, since the latch circuit for storing the data to be written is composed of two groups including a first sub-latch circuit and a second sub-latch circuit that are mutually dependent, Fig.13 and Fig.14 Some operations of reading latch circuits and writing latch circuits in some steps of the programming process and verification process shown in the figure have been changed. For example, Fig.13 The programming process shown and Fig.14 The operations of reading the latch circuit (latch) in the verification process shown are: caching the data to be written (step 1 of the programming process), selecting the data state (steps 6 and 9 of the programming process, step 1 of the verification process), and prohibiting programming settings (step 3 of the programming process). The operations of writing the latch circuit (latch) are: caching the data to be written (step 1 of the programming process), data preprocessing (step 2 of the programming process), prohibiting settings of programming passing (step 9 of the programming process, step 6 of the verification process), etc. The operations involved in each step have been described in detail above and will not be repeated here.

[0250] The present application embodiment provides Fig.10 and Fig.11 The page buffer shown in the figure reduces the area of ​​the page buffer by arranging the latch circuits into several groups of latch circuits (first sub-latch circuits and second sub-latch circuits) that are interdependent, thereby saving the cost of manufacturing the memory device to a great extent.

[0251] An embodiment of the present application further provides a memory system, comprising: one or more of the aforementioned memory devices and a memory controller coupled to the memory device and used to control the memory.

[0252] An embodiment of the present application further provides an electronic system, comprising: the aforementioned memory system and a host coupled to the memory system.

[0253] It should be noted that the memory system and electronic system provided in the embodiments of the present application include the aforementioned memory, and the two have the same technical features. The aforementioned has already described in detail the structure of the memory and the nouns appearing in the technical solution of the present application. Therefore, the nouns appearing here can be understood according to the meaning of the aforementioned description and will not be repeated here.

[0254] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used, such as those available to those skilled in the art when reading the above description. It should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features can be combined together to simplify the application. This should not be interpreted as meaning that the disclosed features that are not claimed for protection are essential to any claim. On the contrary, the disclosed subject matter may be less than all the features of a specific disclosed embodiment. Therefore, the attached claims are thus incorporated into the detailed description, wherein each claim is independently used as a separate embodiment, and it is expected that these embodiments can be combined with each other in various combinations or permutations. The scope of the present application should be determined with reference to the attached claims and the full scope of the equivalents given by these claims.

Claims

1. A memory device, characterized in that: include: A memory array including a plurality of memory cells; The peripheral circuit is coupled to the memory array, and includes: a plurality of page buffers; each page buffer includes: at least two groups of latch circuits; each group of latch circuits includes: a first sub-latch circuit and a second sub-latch circuit, wherein; The first sub-latch circuit is coupled to the sensing node and is configured to: latch the first information on the sensing node; The second sub-latch circuit is coupled to the sensing node and is configured to: latch the second information on the sensing node through the first sub-latch circuit; The first information of the first sub-latch circuit and the second information of the second sub-latch circuit are exchanged through the sensing node.

2. The memory device according to claim 1, wherein: Each group of latch circuits also includes: a transmission control switch, which connects the first sub-latch circuit and the second sub-latch circuit and is configured to: in response to a transmission control signal, be in an on state, and transmit the first information stored in the first sub-latch circuit to the second sub-latch circuit.

3. The memory device according to claim 2, wherein: The second sub-latch circuit includes: a parasitic capacitor storing the second information; the parasitic capacitor is connected to a terminal of the transmission control switch away from the first sub-latch circuit.

4. The memory device according to claim 1, wherein: The at least two groups of latch circuits are configured to store data to be written or read data.

5. The memory device according to claim 1, wherein: One set of latch circuits in the at least two sets of latch circuits is configured to: store intermediate data in a programming process or verification data in a verification process; The other groups of latch circuits in the at least two groups of latch circuits are configured to store data to be written or read data.

6. The memory device according to any one of claims 1 to 5, characterized in that: The first sub-latch circuit includes: a setting switch and a storage element, wherein: The setting switch is coupled to the sensing node and connected to the storage element, and is configured to latch the first information on the sensing node to the storage element in response to a setting signal.

7. The memory device according to claim 6, wherein: The first sub-latch circuit further includes a reset switch connected to the storage element and configured to reset the storage element in response to a reset signal.

8. The memory device according to claim 7, wherein: The first sub-latch circuit also includes: a sensing control switch, one end of which is connected to the set switch and the reset switch, and the other end is grounded; the sensing control switch is configured to: be turned on under the action of the level of the sensing node, and write the first information of the sensing node into the storage element through the set switch.

9. The memory device according to claim 7, wherein: The first sub-latch circuit further includes: a reset control switch, one end of which is connected to the set switch and the reset switch, and the other end of which is grounded; the reset control switch is further configured to: in response to a reset control signal, reset the first sub-latch circuit through the reset switch; The reset control signal is generated by the control logic contained in the peripheral circuit.

10. The memory device according to claim 7, wherein: The storage element includes: a first inverter and a second inverter; wherein the input end of the first inverter is connected to the output end of the second inverter to form a first node; the output end of the first inverter is connected to the input end of the second inverter to form a second node; the second node is connected to the second sub-latch circuit and is configured to: store the first information.

11. The memory device according to claim 10, wherein: The set switch includes a first transistor connected to the first node at one end; the reset switch includes a second transistor connected to the second node at one end; The other end of the first transistor is connected to the other end of the second transistor.

12. The memory device according to any one of claims 1 to 5, characterized in that: Each group of latch circuits further includes: a first control switch and a second control switch connected in series between the sensing node and the ground, wherein the first control switch is controlled by the second information latched by the second sub-latch circuit; and the second control switch is controlled by a read control signal, wherein: When the second information controls the first control switch to be turned on and the read control signal controls the second control switch to be turned on, the second information is read to the sensing node.

13. The memory device according to claim 2, wherein: The transmission control switch comprises: a transmission gate of a single MOS transistor structure or a transmission gate of a dual MOS transistor crystal structure; the dual MOS transistor crystal comprises a CMOS transmission gate formed by connecting a PMOS transistor and an NMOS transistor in parallel.

14. The memory device according to claim 9, wherein: The page buffer further includes: a master latch circuit coupled to the sensing node, configured to: store intermediate data in a programming process or verification data in a verification process; The structure of the main latch circuit is the same as that of the first sub-latch circuit; or, the main latch circuit and the first sub-latch circuit share the sensing control switch and the reset control switch, and the rest of the structures are the same.

15. The memory device according to claim 4, wherein: The at least two groups of latch circuits include: two groups of latch circuits configured to store LP data, MP data, UP data and XP data of data to be written or read.

16. The memory device according to claim 5, wherein: The at least two groups of latch circuits include: three groups of latch circuits, wherein: The two groups of latch circuits are configured to: store LP data, MP data, UP data and XP data for data to be written or read; The remaining group of latch circuits is configured to store intermediate data in a programming process or verification data in a verification process.

17. A method for operating a memory device, characterized in that: The memory device includes a page buffer; the page buffer includes at least two groups of latch circuits; each group of latch circuits includes a first sub-latch circuit and a second sub-latch circuit that are mutually dependent and coupled to a sensing node; the operation method includes: When selecting a data state to be operated in a programming operation or a verification operation of the memory device, reading the second information latched in the second sub-latch circuit to the sensing node; storing the second information of the sensing node in a sensing latch circuit of the page buffer; exchanging the second information of the second sub-latch circuit and the first information latched by the first sub-latch circuit; The first information is read from the second sub-latch circuit to the sensing node, and the second information is read from the sensing latch circuit to the sensing node to obtain selected information indicating the data state to be operated.

18. The operating method according to claim 17, characterized in that: The sensing latch circuit includes a first sensing latch circuit and a second sensing latch circuit; the data state to be operated includes a data state to be programmed or a data state to be verified; the sensing latch circuit storing the second information of the sensing node in the page buffer includes: When selecting a data state to be programmed corresponding to a programming operation of the memory device, storing the second information of the sensing node in the second sensing latch circuit; wherein the first verification information stored in the second sensing latch circuit is invalid; When selecting a data state to be verified corresponding to a verification operation of the memory device, storing the second information of the sensing node in the first sensing latch circuit, wherein the second verification information stored in the first sensing latch circuit is invalid; The first verification information and the second verification information are generated when a verification operation is performed on the memory device last time.

19. The operating method according to claim 17, characterized in that: The exchanging the second information of the second sub-latch circuit and the first information latched by the first sub-latch circuit comprises: charging the sensing node so that the level of the sensing node reaches a preset threshold value, so as to read the second information to the sensing node; In response to a transmission control signal, closing a transmission path between the first sub-latch circuit and the second sub-latch circuit, and transmitting the first information to the second sub-latch circuit; performing a clearing operation on the first sub-latch circuit so that the first sub-latch circuit is restored to an initial state; The second information is written into the first sub-latch circuit.

20. The operating method according to claim 17, characterized in that: The operation method also includes: When writing second information to the second sub-latch circuit in a programming operation or a verification operation of the memory device, the second information is written into the first sub-latch circuit; the first sub-latch circuit and the second sub-latch circuit are exchanged so that the second information is stored in the second sub-latch circuit.

21. A memory system, characterized in that: include: A memory device as claimed in any one of claims 1 to 16 and a memory controller coupled to the memory device and configured to control the memory.

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