Storage device, storage device operation method and storage system

Abstract

The invention provides a storage device, a storage device operation method and a storage system, and relates to the technical field of semiconductor chips. The storage device comprises a storage unit array and a peripheral circuit coupled to the storage unit array, wherein the storage unit array comprises a first storage unit and a second storage unit which are coupled to the same bit line and are adjacent to each other; the peripheral circuit includes a page buffer circuit including: a sensing node coupled to a bit line; a first latch circuit coupled to the sensing node and configured to latch a program state of the first memory cell; the charging and discharging circuit is coupled to the sensing node and is configured to charge the sensing node and discharge the sensing node, and the discharging duration of the sensing node is related to the programming state; and the second latch circuit is coupled to the sensing node and is configured to latch information about whether the second storage unit passes programming verification or not according to the voltage value of the sensing node after the discharge duration. The programming time of the storage device is shortened.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor chip technology, and in particular, relates to a storage device, a storage device operating method, and a storage system. Background Art

[0002] As a non-volatile storage device, NAND flash memory has the advantages of low cost, high capacity, fast rewrite speed, etc. In NAND flash memory, peripheral circuits usually supply power to the storage unit to implement various logic operations, such as read operation, program operation and erase operation. Summary of the invention

[0003] The embodiments disclosed in the present application provide a storage device, a storage device operating method and a storage system, which are used to shorten the programming time of the storage device.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a storage device is provided, the storage device comprising a storage cell array and a peripheral circuit coupled to the storage cell array. The storage cell array comprises a first storage cell and a second storage cell coupled to the same bit line, the first storage cell and the second storage cell being adjacent; the peripheral circuit comprises a page buffer circuit, the page buffer circuit comprises: a sensing node coupled to the bit line; a first latch circuit coupled to the sensing node and configured to latch the programming state of the first storage cell; a charge-discharge circuit coupled to the sensing node and configured to charge the sensing node and discharge the sensing node; the discharge time of the sensing node is related to the programming state of the first storage cell; a second latch circuit coupled to the sensing node and configured to latch information on whether the second storage cell passes programming verification according to the voltage value of the sensing node after the discharge time.

[0006] The present application sets a first latch circuit in the page buffer, and the first latch circuit is coupled to the sensing node and is configured to latch the programming state of the first storage unit. Thus, when verifying the second storage unit (the second storage unit is adjacent to the first storage unit), the present application controls the discharge time of the charging and discharging circuit to the sensing node according to the programming state of the first storage unit latched by the first latch circuit. Under the same verification voltage, the longer the discharge time, the more charge released by the sensing node, the greater the voltage reduction value of the sensing node, the more difficult it is for the second storage unit to pass the verification, and then continue to program the second storage unit, so that the second storage unit stores more charge. In other words, under the same verification voltage, different discharge times can make the amount of charge stored in the second storage unit different. For the same programming level, the traditional solution uses multiple (not less than two) different verification voltages to repeat the verification in sequence when verifying the second storage unit, so that the amount of charge stored in the second storage unit is different. Therefore, for the same programming level, compared with the traditional solution, the present application only uses one verification voltage to verify the second storage unit, which greatly shortens the programming time.

[0007] In some embodiments, the charge and discharge circuit includes a charging circuit and a discharging circuit. The first end of the charging circuit is configured to input a supply voltage, and the second end of the charging circuit is coupled to the sensing node and configured to charge the sensing node. The first end of the discharging circuit is coupled to the bit line, and the second end of the discharging circuit is coupled to the sensing node and configured to discharge the sensing node. The sensing node is first charged by the charging circuit, and then discharged by the discharging circuit, so as to apply various bit line voltages to the bit line; for example, a programming voltage is selected, a programming voltage is prohibited, etc.

[0008] In some embodiments, the programming state of the first storage unit includes a first state and a second state, and the threshold voltage of the first storage unit in the first state is greater than the threshold voltage in the second state. When the programming state of the first storage unit is the first state, the discharge duration of the sensing node is the first duration; when the programming state of the first storage unit is the second state, the discharge duration is the second duration; the first duration is less than the second duration. Among them, the discharge duration of the sensing node is equal to the difference between the time when the discharge circuit stops discharging the sensing node and the time when the charging circuit stops charging the sensing node. Because the programming state of the first storage unit affects the parallel channel charge loss of the second storage unit. After the second storage unit is programmed, if the first storage unit is in the first state, the parallel channel charge loss of the second storage unit is small; if the first storage unit is in the second state, the parallel channel charge loss of the second storage unit is large. Therefore, in the stage of verifying the second storage unit, the lower the programming state of the first storage unit, the longer the discharge duration of the sensing node, so that the second storage unit stores more charge to compensate for the influence of the larger parallel channel charge loss on data retention, thereby improving the data retention performance of the storage device.

[0009] In some embodiments, the first latch circuit is coupled to a charging circuit, and the charging circuit includes a first charging subcircuit and a second charging subcircuit. The first end of the first charging subcircuit is coupled to the first end of the charging circuit, and the second end of the first charging subcircuit is coupled to the second end of the charging circuit. The first end of the second charging subcircuit is coupled to the first end of the charging circuit, and the second end of the second charging subcircuit is coupled to the second end of the charging circuit. When the programming state of the first storage unit is the first state, the first charging subcircuit charges the sensing node; when the programming state of the first storage unit is the second state, the second charging subcircuit charges the sensing node. When the charging circuit stops charging the sensing node, the sensing node starts to discharge. The first charging subcircuit and the second charging subcircuit stop charging the sensing node at different times, so that the sensing node starts to discharge at different times, and finally the discharge duration of the sensing node is different. Among them, since the time when the first charging subcircuit stops charging the sensing node is after the time when the second charging subcircuit stops charging the sensing node; that is, the second charging subcircuit stops charging the sensing node before the first charging subcircuit. Therefore, the discharge duration (first duration) of the sensing node in the first state is less than the discharge duration (second duration) of the sensing node in the second state.

[0010] In some embodiments, the first charging subcircuit includes a first transistor and a second transistor; the first end of the first transistor is coupled to the first end of the first charging subcircuit, the second end of the first transistor is coupled to the first end of the second transistor, the second end of the second transistor is coupled to the second end of the first charging subcircuit, and the control end of the second transistor is coupled to the output end of the first latch circuit; the peripheral circuit also includes a control logic circuit, the control end of the first transistor is coupled to the first output end of the control logic circuit; when the programming state of the first storage unit is the first state, the second transistor is turned on; the control logic circuit is configured to: control the first transistor to be turned on, and the first charging subcircuit charges the sensing node; or, control the first transistor to be turned off, and the first charging subcircuit stops charging the sensing node. The present application controls the on and off of the second transistor by the programming state of the first storage unit. When the programming state of the first storage unit is the first state, so that the second transistor is turned on, the control logic circuit controls the first transistor to realize that the first charging subcircuit charges the sensing node.

[0011] In some embodiments, the second charging subcircuit includes a third transistor, the first end of the third transistor is coupled to the first end of the second charging subcircuit, the second end of the third transistor is coupled to the second end of the second charging subcircuit, and the control end of the third transistor is coupled to the second output end of the control logic circuit; when the programming state of the first storage unit is the second state, the second transistor is disconnected; the control logic circuit is configured to: control the third transistor to be turned on, and the second charging subcircuit charges the sensing node; or, control the third transistor to be disconnected, and the second charging subcircuit stops charging the sensing node. The present application controls the on and off of the second transistor by the programming state of the first storage unit. When the programming state of the first storage unit is the second state and the second transistor is disconnected, the control logic circuit controls the third transistor to realize that the second charging subcircuit charges the sensing node. Among them, the third transistor is disconnected first, and the first transistor is disconnected later. Thereby, the second charging subcircuit stops charging the sensing node before the first charging subcircuit.

[0012] In some embodiments, the first latch circuit is coupled to a discharge circuit, and the discharge circuit includes a first discharge subcircuit and a second discharge subcircuit. The first end of the first discharge subcircuit is coupled to the first end of the discharge circuit, and the second end of the first discharge subcircuit is coupled to the second end of the discharge circuit. The first end of the second discharge subcircuit is coupled to the first end of the discharge circuit, and the second end of the second discharge subcircuit is coupled to the second end of the discharge circuit. When the programming state of the first storage unit is the first state, the first discharge subcircuit discharges the sensing node; when the programming state of the first storage unit is the second state, the second discharge subcircuit discharges the sensing node. The first discharge subcircuit and the second discharge subcircuit stop discharging the sensing node at different times, so that the discharge duration of the sensing node is different. Among them, since the moment when the second discharge subcircuit stops discharging the sensing node is after the moment when the first discharge subcircuit stops discharging the sensing node; that is, the first discharge subcircuit stops discharging the sensing node before the second discharge subcircuit. Therefore, the discharge duration (first duration) of the sensing node in the first state is less than the discharge duration (second duration) of the sensing node in the second state.

[0013] In some embodiments, the second discharge subcircuit includes a fourth transistor and a fifth transistor, the first end of the fourth transistor is coupled to the first end of the first discharge subcircuit, the second end of the fourth transistor is coupled to the first end of the fifth transistor, the second end of the fifth transistor is coupled to the second end of the first discharge subcircuit, and the control end of the fifth transistor is coupled to the output end of the first latch circuit; the peripheral circuit also includes a control logic circuit, the control end of the fourth transistor is coupled to the third output end of the control logic circuit; when the programming state of the first storage unit is the second state, the fifth transistor is turned on, and the control logic circuit is configured to: control the fourth transistor to be turned on, and the second discharge subcircuit discharges the sensing node; or, control the fourth transistor to be turned off, and the second discharge subcircuit stops discharging the sensing node. The present application controls the on and off of the fifth transistor by the programming state of the first storage unit. When the programming state of the first storage unit is the second state, so that when the fifth transistor is turned on, the control logic circuit controls the fourth transistor to discharge the sensing node by the second discharge subcircuit.

[0014] In some embodiments, the first discharge subcircuit includes a sixth transistor, the first end of the sixth transistor is coupled to the first end of the first discharge subcircuit, and the second end of the sixth transistor is coupled to the second end of the first discharge subcircuit; the control end of the sixth transistor is coupled to the fourth output end of the control logic circuit; when the programming state of the first storage unit is the first state, the fifth transistor is disconnected, and the control logic circuit is configured to: control the sixth transistor to be turned on, and the first discharge subcircuit discharges the sensing node; or, control the sixth transistor to be disconnected, and the first discharge subcircuit stops discharging the sensing node. The present application controls the on and off of the fifth transistor through the programming state of the first storage unit. When the programming state of the first storage unit is the first state, so that the fifth transistor is disconnected, the control logic circuit controls the sixth transistor to discharge the sensing node by the first discharge subcircuit. Among them, the sixth transistor is disconnected first, and the fourth transistor is disconnected later. Thereby, the first discharge subcircuit stops discharging the sensing node before the second discharge subcircuit.

[0015] In a second aspect, a method for operating a storage device is provided, wherein the storage device includes a storage cell array and a peripheral circuit coupled to the storage cell array; the peripheral circuit includes a page buffer circuit, and the operating method includes: latching the programming state of a first storage cell in the storage cell array; in the stage of programming and verifying a second storage cell in the storage cell array, discharging a sensing node in the page buffer circuit; wherein the discharge duration of the sensing node is related to the programming state of the first storage cell; the first storage cell and the second storage cell are adjacent and coupled to the same bit line, and the sensing node is coupled to the bit line; after the discharge duration, latching information on whether the second storage cell passes the programming verification according to the voltage value of the sensing node.

[0016] In some embodiments, discharging a sensing node in a page buffer circuit includes: charging the sensing node, the sensing node is coupled to a second end of a charging circuit, a first end of the charging circuit is configured as an input supply voltage; applying a bit line voltage to a bit line, the bit line is coupled to a first end of a discharge circuit, a second end of the discharge circuit is coupled to the sensing node; stopping charging the sensing node, the sensing node starts to discharge; stopping discharging the sensing node, the sensing node stops discharging.

[0017] In some embodiments, the programming state of the first storage cell includes a first state and a second state, and the threshold voltage of the first storage cell in the first state is greater than the threshold voltage in the second state; when the programming state of the first storage cell is the first state, the discharge duration of the sensing node is the first duration; the discharge duration of the sensing node is equal to the difference between the moment when the sensing node stops discharging and the moment when the sensing node stops charging; when the programming state of the first storage cell is the second state, the discharge duration is the second duration; the first duration is less than the second duration.

[0018] In some embodiments, the discharge duration of the sensing node is related to the programming state of the first storage unit, including: the moment of stopping charging the sensing node is related to the programming state of the first storage unit; wherein, when the programming state of the first storage unit is the first state, the first charging subcircuit in the charging circuit charges the sensing node; when the programming state of the first storage unit is the second state, the second charging subcircuit in the charging circuit charges the sensing node; the moment when the first charging subcircuit stops charging the sensing node is after the moment when the second charging subcircuit stops charging the sensing node.

[0019] In some embodiments, when the programming state of the first storage unit is the first state, the second transistor in the first charging subcircuit is turned on, and the first charging subcircuit charges the sensing node, including: turning on the first transistor in the first charging subcircuit, and the first charging subcircuit charges the sensing node; turning off the first transistor, and the first charging subcircuit stops charging the sensing node; the first end of the first transistor is configured as an input supply voltage, the second end of the first transistor is coupled to the first end of the second transistor, and the second end of the second transistor is coupled to the sensing node.

[0020] In some embodiments, when the programming state of the first storage unit is the second state, the second transistor in the first charging subcircuit is disconnected, and the second charging subcircuit charges the sensing node, including: turning on the third transistor in the second charging subcircuit, and the second charging subcircuit charges the sensing node; turning off the third transistor, and the second charging subcircuit stops charging the sensing node; the first end u of the third transistor is configured as an input supply voltage, and the second end of the third transistor is configured to be coupled to the sensing node.

[0021] In some embodiments, the first charging subcircuit stops charging the sensing node after the second charging subcircuit stops charging the sensing node, and includes: first turning off the third transistor and then turning off the first transistor.

[0022] In some embodiments, the discharge duration of the sensing node is related to the programming state of the first storage unit, including: the moment of stopping discharging the sensing node is related to the programming state of the first storage unit; wherein, when the programming state of the first storage unit is the first state, the first discharge sub-circuit in the discharge circuit discharges the sensing node; when the programming state of the first storage unit is the second state, the second discharge sub-circuit in the discharge circuit discharges the sensing node; the moment when the second discharge sub-circuit stops discharging the sensing node is after the moment when the first discharge sub-circuit stops discharging the sensing node.

[0023] In some embodiments, when the programming state of the first storage unit is the second state, the fifth transistor in the second discharge subcircuit is turned on, and the second discharge subcircuit discharges the sensing node, including: turning on the fourth transistor in the second discharge subcircuit, and the second discharge subcircuit discharges the sensing node; turning off the fourth transistor, and the second discharge subcircuit stops discharging the sensing node; the first end of the fourth transistor is coupled to the bit line, the second end of the fourth transistor is coupled to the first end of the fifth transistor, and the second end of the fifth transistor is coupled to the sensing node.

[0024] In some embodiments, when the programming state of the first storage unit is the first state, the fifth transistor in the second discharge subcircuit is disconnected, and the first discharge subcircuit discharges the sensing node, including: turning on the sixth transistor in the first discharge subcircuit, and the first discharge subcircuit discharges the sensing node; turning off the sixth transistor, and the first discharge subcircuit stops discharging the sensing node; the first end of the sixth transistor is coupled to the bit line, and the second end of the sixth transistor is coupled to the sensing node.

[0025] In some embodiments, the moment when the second discharge subcircuit stops discharging the sensing node is after the moment when the first discharge subcircuit stops discharging the sensing node, including: first turning off the sixth transistor and then turning off the fourth transistor.

[0026] In some embodiments, the operation method further includes: during the stage of programming and verifying the second storage cell in the storage cell array, discharging the sensing node multiple times; the discharge time increases gradually. Thus, in the next programming cycle, different bit line voltages can be applied to the second storage cells with different threshold voltages to achieve accurate programming of the second storage cells.

[0027] According to a third aspect, a storage system is provided. The storage system includes a storage controller and the storage device according to any one of the first aspects, wherein the memory controller is configured to control the storage device.

[0028] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, any one of the methods in the second aspect above can be implemented.

[0029] In a fifth aspect, a computer device is provided, comprising a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, any one of the methods in the second aspect can be implemented.

[0030] It can be understood that the technical effects of the second to fifth aspects refer to the technical effects of the first aspect and any embodiment thereof, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0032] Figure 1 A schematic diagram of the threshold voltage distribution of a memory cell provided in an embodiment of the present application;

[0033] Figure 2 A schematic diagram comparing the normal threshold voltage distribution and the threshold voltage distribution after charge loss provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram showing the effect of the programming state of adjacent memory cells on the parallel channel charge loss of any memory cell provided by an embodiment of the present application;

[0035] Figure 4 A schematic diagram of the structure of a storage system provided in an embodiment of the present application;

[0036] Figure 5 A schematic diagram of the structure of a storage device provided in an embodiment of the present application;

[0037] Figure 6 A schematic diagram of the structure of a storage unit block provided in an embodiment of the present application;

[0038] Figure 7 A partial cross-sectional view of a cross section of a memory cell string provided in an embodiment of the present application;

[0039] Figure 8 A schematic diagram of the structure of a storage device and peripheral circuits provided in an embodiment of the present application;

[0040] Fig. 9 A schematic diagram of the structure of a page buffer provided in an embodiment of the present application;

[0041] Fig.10 A schematic diagram of the structure of another page buffer provided in an embodiment of the present application;

[0042] Fig.11 A schematic diagram of a flow chart of a storage device operation method provided in an embodiment of the present application;

[0043] Fig.12 A schematic diagram of a discharge process of a sensing node provided in an embodiment of the present application;

[0044] Fig.13 A schematic diagram of a specific process of S120 provided in an embodiment of the present application;

[0045] Fig.14 A waveform diagram of a control signal for charging and discharging a sensing node provided in an embodiment of the present application;

[0046] Fig.15 Another specific flow chart of S120 provided in the embodiment of the present application;

[0047] Fig.16 A schematic diagram of another waveform of a control signal for charging and discharging a sensing node provided in an embodiment of the present application;

[0048] Fig.17 Another specific flow chart of S120 provided in the embodiment of the present application;

[0049] Fig.18 A schematic diagram of dividing regions for dividing the threshold voltage of the second storage unit in S130 provided in an embodiment of the present application;

[0050] Fig.19 A schematic diagram of the programming result of the next programming cycle provided in an embodiment of the present application.

[0051] Reference numerals: 100, storage system; 110, memory controller; 120, storage device; 200, storage cell array; 210, storage cell block; 220, storage cell string; 221, top selection transistor; 222, dummy storage cell; 223, storage cell; 224, bottom selection transistor; 300, peripheral circuit; 310, I / O interface; 320, control logic circuit; 330, row decoder; 340, voltage generator; 350, column decoder; 360, data bus; 370, register; 380, page buffer; 410, memory stack layer; 411, gate conductive layer; 412, dielectric layer; 420, substrate; 430, top selection line; 440, word line; 450, bottom selection line ;500, a first latch circuit;510, a first inverter;520, a second inverter;530, a seventh transistor;540, an eighth transistor;550, a ninth transistor;600, a charge and discharge circuit;610, a charging circuit;611, a first transistor;612, a second transistor;613, a third transistor;620, a discharge circuit;621, a fourth transistor;622, a fifth transistor;623, a sixth transistor;700, a second latch circuit;710, a third inverter;720, a fourth inverter;730, a tenth transistor;740, an eleventh transistor;750, a twelfth transistor;760, a thirteenth transistor;810, a fourteenth transistor;820, a fifteenth transistor;830, a sixteenth transistor. DETAILED DESCRIPTION

[0052] The following will be combined Figure 1-Figure 19 , the technical solutions in some embodiments of the present application are clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0053] Unless the context requires otherwise, throughout the specification and claims, the term "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0054] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0055] When describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. In this case, "coupled" may also be described as "connected". In addition, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0056] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0057] Flash memory is a non-volatile storage device that includes multiple memory cells that can be electrically erased and reprogrammed. The memory cells can be programmed to store charges, and the charges stored in the memory cells can be removed by erasing operations.

[0058] The electric field generated by the charge can affect the threshold voltage (Vt) of the memory cell. Generally, the more charge a memory cell stores, the greater the threshold voltage of the memory cell and the higher the programming level. Figure 1 As shown, according to different threshold voltage distributions, the memory cells can be divided into single-level cell (SLC) type, multi-level cell (MLC) type, trinary-level cell (TLC) type, etc. Among them, SLC has two programming levels, L0-L1; MLC has four programming levels, L0-L3; MLC has eight programming levels, L0-L7.

[0059] When performing a read operation, the programming level of the memory cell can be identified by the read voltage, thereby reading out the data. Taking SLC as an example, when the threshold voltage of the memory cell is greater than the read voltage, the programming level is identified as L1, and the read data is "0"; when the threshold voltage of the memory cell is less than the read voltage, the programming level is identified as L0, and the read data is "1".

[0060] The charge loss of a memory cell is one of the factors that affect the data retention performance of a memory device. Figure 2 As shown, charge loss will reduce the threshold voltage of the storage cell, which is manifested as a left shift of the threshold voltage and a widening of the threshold voltage distribution on the threshold voltage distribution diagram. As a result, after a long period of data retention, it will be difficult for the read voltage to identify the programming level of the storage cell, ultimately leading to data corruption.

[0061] Charge loss mainly includes vertical channel charge loss and parallel channel charge loss. The vertical channel charge loss is related to the threshold voltage of the memory cell. The larger the threshold voltage, the more serious the vertical channel charge loss of the memory cell. The parallel channel charge loss is not only related to the threshold voltage of the memory cell, but also to the programming level of the adjacent memory cells of the memory cell. Figure 3 As shown, for any memory cell, when the adjacent memory cells are at a high programming level, the parallel channel charge loss of the memory cell is small, and when the adjacent memory cells are at a low programming level, the parallel channel charge loss of the memory cell is large.

[0062] In order to compensate for the impact of large parallel channel charge loss on the data retention performance of the storage device, multiple verification voltages are used for each programming level in the verification stage after programming. Taking MLC as an example, the memory cell string includes a programmed first memory cell and an unprogrammed second memory cell, and the first memory cell and the second memory cell are adjacent. When verifying the second memory cell, if the programming level of the adjacent first memory cell is L0, the verification voltage V vfy_1 Verify; if the programming level of the adjacent first memory cell is L1, the verification voltage V vfy_2 Verify; if the programming level of the adjacent first memory cell is L2, the verification voltage V vfy_3 Verify; if the programming level of the adjacent first memory cell is L3, then the verification voltage V vfy_4 Verify; verify voltage V vfy_1 Greater than the verification voltage V vfy_2 Greater than the verification voltage V vfy_3 Greater than the verification voltage V vfy_4 .

[0063] That is to say, the lower the programming level of the programmed first storage cell, the larger the verification voltage is used in the multiple verification voltages to verify the second storage cell. Since the verification voltage is larger, the more charge is released by the sensing node (SO) in the page buffer coupled to the second storage cell within the sensing time Tsense, so that the voltage of the sensing node is lower. If the voltage of the sensing node is less than the threshold voltage, the second storage cell fails the verification. Then, in the next programming cycle, the second storage cell can continue to be programmed to increase the threshold voltage of the second storage cell (the second storage cell stores more charge). Therefore, at the same programming level, compared with the storage cell with smaller parallel channel charge loss, the storage cell with more serious parallel channel charge loss is verified using a larger verification voltage, so that after the programming operation is completed, the storage cell with more serious parallel channel charge loss can store more charge. Since more charge is stored after the programming operation, even if the parallel channel charge loss is more serious, the storage cell can keep the data intact for a long time, thereby improving the data retention performance of the storage device.

[0064] Further, according to the programming level of the first storage cell, the first storage cell can be divided into a plurality of programming states; for example, the first storage cell is divided into two programming states, namely, a first state and a second state. In some embodiments, if the programming level of the first storage cell is L2 or L3, the programming state of the first storage cell can be the first state, and if the programming level of the first storage cell is L0 or L1, the programming state of the first storage cell can be the second state. When verifying the second storage cell, if the adjacent first storage cell is in the first state, it is verified by the verification voltage Vvfy_1; if the adjacent first storage cell is in the second state, it can be verified by the verification voltage Vvfy_2. In order to reduce the number of verification voltages, while improving the data retention performance of the storage device, the programming time can be shortened as much as possible. However, for the same programming level, using multiple (not less than two) verification voltages for repeated verification in sequence (for example, applying the verification voltage Vvfy_1 and the verification voltage Vvfy_2 in sequence) still greatly increases the programming time of the storage cell.

[0065] In an embodiment of the present application, a first latch circuit for latching the programming level of the first storage unit is set in the page buffer, and the first latch circuit is coupled to the sensing node and the charge-discharge circuit configured to discharge the sensing node. When verifying the second storage unit adjacent to the first storage unit, the discharge time of the charge-discharge circuit to the sensing node is controlled according to the programming level latched by the first latch circuit. Under the same verification voltage, the longer the discharge time, the more charge released by the sensing node, thereby making the voltage of the sensing node lower. If the voltage of the sensing node is less than the threshold voltage, the storage unit fails the verification. Then, in the next programming cycle, the storage unit can continue to be programmed. Therefore, for the same programming level, the present application uses a verification voltage to complete the verification of the second storage unit, which greatly shortens the programming time while improving the data retention performance of the storage device.

[0066] like Figure 4 As shown, an embodiment of the present application provides a storage system 100, which includes a memory controller 110 and a storage device 120, and the memory controller 110 is configured to store data in the storage device 120 or read data from the storage device 120. The storage system 100 can be applied to and packaged in different types of electronic devices, such as mobile phones (such as mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, servers, and any other electronic devices that can store data.

[0067] Of course, the memory controller 110 may also perform any other suitable functions, such as formatting the storage device 120; for example, the memory controller 110 may communicate with an external device (e.g., a host) through at least one of various interface protocols. The interface protocol may include at least one of a universal serial bus (USB) protocol, a multi-media card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-E protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

[0068] Specifically, Figure 5 As shown, the memory device 120 includes a memory cell array 200 and a peripheral circuit 300 coupled to the memory cell array 200 .

[0069] In a three-dimensional (3D) NAND memory device 120, a memory cell array 200 may include a plurality of memory cell blocks 210 (blocks), such as Figure 6 As shown, each memory cell block 210 may include a plurality of memory cell strings 220. Each memory cell string 220 may include a top select gate (TSG) 221, a dummy (DMY) memory cell 222, a plurality of memory cells 223, and a bottom select gate (BSG) 224, which are sequentially stacked in series; wherein the memory cell 223 may be a floating gate transistor, or a charge trap field effect transistor or other device capable of storing data.

[0070] Figure 7A partial cross-sectional schematic diagram of a possible memory cell string 220 of the present application is shown. The memory cell string 220 may extend vertically through the memory stack layer 410 above the substrate 420. The substrate 420 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0071] The memory stack layer 410 may include alternating gate conductive layers 411 and dielectric layers 412 . The number of gate conductive layers 411 and dielectric layers 412 in the memory stack layer 410 may determine the number of memory cells 223 in the memory cell string 220 .

[0072] The gate conductive layer 411 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate conductive layer 411 includes a doped polysilicon layer. Each gate conductive layer 411 may include a control gate surrounding the memory cell 223, and the gate conductive layer 411 at the top of the memory stack layer 410 may extend laterally as a top select line 430 (string select line, SSL), the gate conductive layer 411 at the bottom of the memory stack layer 410 may extend laterally as a bottom select line 450 (ground select line, GSL), or the gate conductive layer 411 between the top select line 430 and the bottom select line 450 may extend laterally as a word line 440 (word line, WL).

[0073] It should be understood that although Figure 7 Not shown, but additional features of the memory cell string 220 may be formed, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0074] The peripheral circuit 300 is configured to control the memory cell array 200. Figure 8 As shown, the peripheral circuit 300 may include an I / O interface 310, a control logic circuit 320, a row decoder 330, a voltage generator 340, a column decoder 350, a data bus 360, a register 370, and a page buffer 380. It should be understood that in some examples, the peripheral circuit 300 may also include Figure 8The memory cell array 200 may be coupled to the peripheral circuit 300 through bit lines, common source lines, top selection lines 430, word lines 440, bottom selection lines 450, etc.; for example, the bit lines are coupled to the page buffer 380, and the word lines 440 are coupled to the row decoder 330.

[0075] I / O interface 310 may be coupled to control logic circuit 320 and act as a control buffer to buffer data from memory controller 110 (eg, Figure 4 The I / O interface 310 may receive control commands received from the memory controller 110 in the memory cell array 200 and relay them to the control logic circuit 320, and buffer status information received from the control logic circuit 320 and relay them to the memory controller 110. The I / O interface 310 may also be coupled to the page buffer 380 via the data bus 360, and act as a data I / O interface 310 and a data buffer to buffer data and relay them to or from the memory cell array 200.

[0076] The control logic circuit 320 may be coupled to the voltage generator 340, the page buffer 380, the column decoder 350, the row decoder 330, the I / O interface 310, etc., and is configured to control the operation of each peripheral circuit 300. The control logic circuit 320 may generate an operation signal to control the operation of the row decoder 330, the column decoder 350, the page buffer 380, and the voltage generator 340 in response to a command (CMD) or a control signal from the memory controller 110; wherein the command may be a program command, a read command, etc.

[0077] The row decoder 330 may supply the word line 440 voltage generated from the voltage generator 340 to the selected word lines 440 and the unselected word lines 440 of the memory cell array 200 in response to the operation signal of the control logic circuit 320. As described in detail below, the row decoder 330 is configured to perform a program operation on memory cells coupled to one or more selected word lines 440 in the memory cell array 200.

[0078] The voltage generator 340 can use an external power supply voltage or an internal power supply voltage to generate various voltages for performing operations such as erasing, programming, reading and verifying on the memory cell array 200, such as a programming voltage Vpgm, a pass voltage Vpass, a read voltage Vread and a verification voltage Vvfy applied to the word line 440, and a programming inhibit voltage Vinhibit, a programming select voltage Vss, etc. applied to the bit line, and their combinations.

[0079] The column decoder 350 may select one or more memory cell strings 220 in the memory cell array 200 in response to an operation signal of the control logic circuit 320 .

[0080] The register 370 may be coupled to the control logic circuit 320 and include a status register, a command register, and an address register to store status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit 300 .

[0081] The page buffer 380 may read data from the memory cell array 200 and program (write) data to the memory cell array 200 according to an operation signal from the control logic circuit 320. In one example, the page buffer 380 may store programming data (write data) to be programmed into the memory cell array 200. In another example, the page buffer 380 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 223 coupled to the selection word line 440. In yet another example, the page buffer 380 may also detect a low-power signal from a bit line representing a data bit stored in the memory cell 223, and amplify the small voltage to a recognizable logic level in a read operation.

[0082] like Fig. 9 or Fig.10 As shown, in the storage device provided by the embodiment of the present application, the circuit of the page buffer 380 may include a sensing node SO, a charge-discharge circuit 600, a first latch circuit 500, and a second latch circuit 700. The sensing node SO is coupled to the storage cell string 220 through a bit line, and a capacitor Cso for storing charge may be provided between the sensing node SO and the ground GND, or between the sensing node SO and any fixed potential; of course, a parasitic capacitor for storing charge may also be formed between the sensing node SO and the ground GND, or between the sensing node SO and any fixed potential. The storage cell string 220 includes a programmed first storage cell and an unprogrammed second storage cell, and the first storage cell is adjacent to the second storage cell.

[0083] It should be understood that the “grounding” described in the embodiments of the present application may also be coupled to any fixed potential.

[0084] Specifically, the charge-discharge circuit 600 is coupled to the sensing node SO, and includes a charge circuit 610 configured to charge the sensing node SO, and a discharge circuit 620 configured to discharge the sensing node SO.

[0085] In the embodiment of the present application, the first latch circuit 500 is configured to latch the programming state of the first storage unit. In the stage of verifying the second storage unit, the discharge duration of the sensing node SO is related to the programming state of the first storage unit; wherein the discharge duration of the sensing node SO is equal to the difference between the time when the discharge circuit 620 stops discharging the sensing node SO and the time when the charging circuit 610 stops charging the sensing node SO. That is, the first latch circuit 500 can be coupled to the charging circuit 610 to control the time when the charging circuit 610 stops charging the sensing node SO; or, the first latch circuit 500 can be coupled to the discharge circuit 620 to control the time when the discharge circuit 620 stops discharging the sensing node SO; or, the first latch circuit 500 can also be coupled to the charging circuit 610 and the discharge circuit 620 at the same time to simultaneously control the time when the discharge circuit 620 stops discharging the sensing node SO, and the time when the charging circuit 610 stops charging the sensing node SO.

[0086] The lower the programming state of the first storage cell, the longer the discharge time of the sensing node SO when verifying the second storage cell. Exemplarily, the programming state of the first storage cell includes a first state and a second state, and the threshold voltage of the first storage cell in the first state is greater than the threshold voltage in the second state. When the programming state of the first storage cell is the first state, the discharge time of the sensing node SO is the first time; when the programming state of the first storage cell is the second state, the discharge time is the second time; the first time is less than the second time. After the discharge time, the voltage value of the sensing node SO is configured to determine whether the second storage cell passes the programming verification.

[0087] like Fig. 9 As shown, in some embodiments, the output terminal of the first latch circuit 500 is coupled to the charging circuit 610, a first terminal of the charging circuit 610 is configured to input a supply voltage, and a second terminal of the charging circuit 610 is coupled to the sensing node SO.

[0088] Specifically, the charging circuit 610 may include a plurality of charging subcircuits, and the plurality of charging subcircuits correspond to a plurality of programming states of the first storage unit. Exemplarily, the charging circuit 610 includes a first charging subcircuit and a second charging subcircuit.

[0089] The first end of the first charging subcircuit is coupled to the first end of the charging circuit 610, and the second end of the first charging subcircuit is coupled to the second end of the charging circuit 610; wherein the first charging subcircuit includes a first transistor 611 and a second transistor 612. That is, the first end of the first transistor 611 is configured to input a supply voltage, the second end of the first transistor 611 is coupled to the first end of the second transistor 612, and the second end of the second transistor 612 is coupled to the sensing node SO. The control end of the first transistor 611 is coupled to the first output end of the control logic circuit 320, and the control end of the second transistor 612 is coupled to the output end of the first latch circuit 500.

[0090] In the embodiment of the present application, the first transistor 611 and the second transistor 612 are P-type transistors; for example, positive channel metal-oxide-semiconductor field-effect transistors (PMOS).

[0091] The first end of the second charging subcircuit is coupled to the first end of the charging circuit 610, and the second end of the second charging subcircuit is coupled to the second end of the charging circuit 610; wherein the second charging subcircuit includes a third transistor 613. That is, the first end of the third transistor 613 is configured to input the supply voltage, and the second end of the third transistor 613 is coupled to the sensing node SO. The control end of the third transistor 613 is coupled to the second output end of the control logic circuit 320. In the embodiment of the present application, the third transistor 613 is a P-type transistor.

[0092] The control logic circuit 320 is configured to control the first transistor 611 to be turned on or off, and to control the third transistor 613 to be turned on or off; and the control logic circuit 320 first controls the third transistor 613 to be turned off, and then controls the first transistor 611 to be turned off. In the embodiment of the present application, the control logic circuit 320 can control the third transistor 613 and the first transistor 611 to be turned on at the same time. The first latch circuit 500 is configured to control the second transistor 612 to be turned on or off. When the programming state of the first storage unit is the first state, the second transistor 612 is turned on, and then the first charging subcircuit and the second charging subcircuit charge the sensing node SO at the same time. Since the control logic circuit 320 controls the first transistor 611 to be turned off after the third transistor 613 is turned off, when the second charging subcircuit stops charging the sensing node SO, the first charging subcircuit continues to charge the sensing node SO. That is, when the programming state of the first storage unit is the first state, the first charging subcircuit essentially charges the sensing node SO. When the programming state of the first memory cell is the second state, the second transistor 612 is turned off, so the second charging sub-circuit can only charge the sensing node SO by turning on the third memory cell 223 .

[0093] like Fig.10 As shown, in some embodiments, the output terminal of the first latch circuit 500 is coupled to the discharge circuit 620, a first terminal of the discharge circuit 620 is coupled to the bit line, and a second terminal of the discharge circuit 620 is coupled to the sensing node SO.

[0094] Specifically, the discharge circuit 620 may include a plurality of discharge sub-circuits, and the plurality of discharge sub-circuits correspond to a plurality of programming states of the first storage unit. Exemplarily, the discharge circuit 620 includes a first discharge sub-circuit and a second discharge sub-circuit.

[0095] The first end of the second discharge subcircuit is coupled to the first end of the discharge circuit 620, and the second end of the second discharge subcircuit is coupled to the second end of the discharge circuit 620; wherein the second discharge subcircuit includes a fourth transistor 621 and a fifth transistor 622. That is, the first end of the fourth transistor 621 is coupled to the bit line, the second end of the fourth transistor 621 is coupled to the first end of the fifth transistor 622, and the second end of the fifth transistor 622 is coupled to the sensing node SO. The control end of the fourth transistor 621 is coupled to the third output end of the control logic circuit 320, and the control end of the fifth transistor 622 is coupled to the output end of the first latch circuit 500.

[0096] In the embodiment of the present application, the fourth transistor 621 is an N-type MOS transistor, and the fifth transistor 622 may include an N-type MOS transistor and a P-type MOS transistor, and the N-type MOS transistor and the P-type MOS transistor are connected in parallel.

[0097] The first end of the first discharge subcircuit is coupled to the first end of the discharge circuit 620, and the second end of the first discharge subcircuit is coupled to the second end of the discharge circuit 620; wherein the first discharge subcircuit includes a sixth transistor 623. That is, the first end of the sixth transistor 623 is coupled to the bit line, and the second end of the sixth transistor 623 is coupled to the sensing node SO. The control end of the sixth transistor 623 is coupled to the fourth output end of the control logic circuit 320. In the embodiment of the present application, the sixth transistor 623 is an N-type MOS.

[0098] The control logic circuit 320 is configured to control the fourth transistor 621 to be turned on or off, and to control the sixth transistor 623 to be turned on or off; and the control logic circuit 320 first controls the sixth transistor 623 to be turned off, and then controls the fourth transistor 621 to be turned off. In the embodiment of the present application, the control logic circuit can control the sixth transistor 623 and the fourth transistor 621 to be turned on at the same time. The first latch circuit 500 is configured to control the fifth transistor 622 to be turned on or off. When the programming state of the first memory cell is the second state, the fifth transistor 622 is turned on, and the sensing node SO applies the bit line voltage to the bit line through the first discharge sub-circuit and the second discharge sub-circuit, so that the sensing node SO is discharged. Since the control logic circuit 320 controls the first transistor 611 to be turned off after the third transistor 613 is turned off, when the second charging sub-circuit stops discharging the sensing node SO, the first charging sub-circuit continues to discharge the sensing node SO. That is, when the programming state of the first memory cell is the second state, the second discharge sub-circuit actually discharges the sensing node SO. When the programming state of the first memory cell is the first state, the fifth transistor 622 is turned off, and thus the sensing node SO can only be discharged through the first discharge subcircuit.

[0099] In some embodiments, the first latch circuit 500 is also coupled to the charging circuit 610 and the discharging circuit 620 at the same time; that is, the first latch circuit 500 simultaneously controls the moment when the charging circuit 610 stops charging the sensing node SO, and controls the moment when the discharging circuit 620 stops discharging the sensing node SO. This application will not be repeated here.

[0100] like Fig. 9As shown, the first latch circuit 500 is coupled to the sensing node SO; wherein the first latch circuit 500 includes a first inverter 510, a second inverter 520, a seventh transistor 530, an eighth transistor 540 and a ninth transistor 550. The output terminal of the first inverter 510 is coupled to the input terminal of the second inverter 520, and the input terminal of the first inverter 510 is coupled to the output terminal of the second inverter 520. The first terminal of the seventh transistor 530 is coupled to the output terminal of the first inverter 510, the first terminal of the eighth transistor 540 is coupled to the output terminal of the second inverter 520, the control terminal of the ninth transistor 550 is coupled to the sensing node SO, the first terminal of the ninth transistor 550 is coupled to the second terminal of the seventh transistor 530 and the second terminal of the eighth transistor 540, and the second terminal of the ninth transistor 550 is grounded GND. The control terminal of the seventh transistor 530 is configured to receive a set signal, and the control terminal of the seventh transistor 530 is configured to receive a reset signal.

[0101] Exemplarily, in the embodiment of the present application, the seventh transistor 530, the eighth transistor 540 and the ninth transistor 550 can all be N-type MOS tubes. When the ninth transistor 550 is turned on under the voltage of the sensing node SO, if the setting signal is high, the seventh transistor 530 is turned on, the output end of the first inverter 510 is low, and the output end of the first inverter 510 is high; if the reset signal is high, the eighth transistor 540 is turned on, the output end of the second inverter 520 is low, and the output end of the first inverter 510 is high; that is, the programming state of the first storage unit is distinguished by the high level and the low level. It should be understood that multiple programming states of the first storage unit can be distinguished by setting multiple first latch circuits 500.

[0102] The second latch circuit 700 (also referred to as a sense latch) is coupled to the sense node SO and is configured to latch information on whether the second storage unit passes programming verification according to the voltage value of the sense node after the discharge time. The second latch circuit 700 includes a third inverter 710, a fourth inverter 720, a tenth transistor 730, an eleventh transistor 740, a twelfth transistor 750, and a thirteenth transistor 760. The output of the third inverter 710 is coupled to the input of the fourth inverter 720, and the input of the third inverter 710 is coupled to the output of the fourth inverter 720. The first end of the tenth transistor 730 is coupled to the output end of the third inverter 710 and is configured to output information on whether the second storage unit passes the programming verification; the first end of the eleventh transistor 740 is coupled to the output end of the fourth inverter 720, the control end of the twelfth transistor 750 is coupled to the sensing node SO, the first end of the twelfth transistor 750 is coupled to the second end of the tenth transistor 730 and the second end of the eleventh transistor 740, and the second end of the twelfth transistor 750 is grounded GND; the thirteenth transistor 760 is connected in parallel to the twelfth transistor 750.

[0103] Usually, in Fig. 9 , some other examples of circuit structures are also shown, for example: a fourteenth transistor 810 and a fifteenth transistor 820 coupled between the power supply VDD and the charging circuit 610, and a sixteenth transistor 830 coupled between the bit line and the discharge circuit 620. The fourteenth transistor 810 and the fifteenth transistor 820 are P-type MOS transistors, the sixteenth transistor 830 is an N-type MOS transistor, and the fourteenth transistor 810 is configured to receive information on whether the second storage unit passes programming verification.

[0104] Since the embodiments of the present application do not make improvements to these structures, these structures should not be understood as limitations to the present application, but rather as an implementation method. In some examples, these structures may also adopt other specific circuit forms.

[0105] like Fig.11 As shown, the embodiment of the present application provides an operating method of a storage device, including steps S110-S140, as follows:

[0106] S110 , a first latch circuit latches a programming state of a first memory cell in a memory cell array.

[0107] Specifically, the first latch circuit 500 can latch the programming state of the first storage cell before programming the second storage cell. The first storage cell and the second storage cell are located on the same storage cell string 220, and the first storage cell and the second storage cell are adjacent.

[0108] For storage devices 120 of types such as MLC, TLC, and QLC, the first storage unit has multiple programming levels. Therefore, the present application method can divide the first storage unit into multiple programming states according to the programming level of the first storage unit to avoid setting too many first latch circuits 500 and causing the page buffer 380 circuit to occupy too much area. Exemplarily, the programming state of the first storage unit includes a first state and a second state, and the threshold voltage of the first storage unit in the first state is greater than the threshold voltage in the second state. Among them, the corresponding relationship between the programming state and the programming level of the first storage unit can be shown in Table 1 below:

[0109] Table 1

[0110]

[0111] S120 , in the stage of performing program verification on the second memory cell in the memory cell array, the charge-discharge circuit discharges the sensing node in the page buffer circuit.

[0112] Specifically, after the discharge time, if the voltage value of the sensing node SO is greater than the threshold voltage, the second storage unit passes the programming verification; if the voltage value of the sensing node SO is less than the threshold voltage, the second storage unit fails the programming verification. In the embodiment of the present application, during the stage of programming verification of the second storage unit, the discharge time of the sensing node SO is related to the programming state of the first storage unit. The lower the programming state of the first storage unit, the longer the discharge time of the sensing node SO when verifying the second storage unit. Fig.12 As shown, discharging the sensing node SO may include steps S210 to S240, as follows:

[0113] S210 : The charging circuit charges the sensing node.

[0114] Specifically, the first terminal of the charging circuit 610 is configured to input the supply voltage, and the second terminal of the charging circuit 610 is coupled to the sensing node SO. The first terminal and the second terminal of the charging circuit 610 are first turned on, and the charging circuit 610 applies the supply voltage to the sensing node SO to charge the sensing node SO.

[0115] S220 , applying a bit line voltage to the bit line.

[0116] Specifically, the bit line is coupled to the first end of the discharge circuit 620, and the second end of the discharge circuit 620 is coupled to the sensing node SO. Then the first end and the second end of the discharge circuit 620 are turned on, and the capacitor Cso coupled to the sensing node SO applies the bit line voltage to the bit line. At this time, since the charging circuit 610 is still charging the sensing node SO, the capacitor Cso (or parasitic capacitance) coupled to the sensing node SO does not start to discharge.

[0117] S230 : The charging circuit stops charging the sensing node.

[0118] Specifically, the first terminal and the second terminal of the charging circuit 610 are then disconnected. At this time, the charging circuit 610 stops charging the sensing node SO, and the capacitor Cso (or parasitic capacitance) coupled to the sensing node SO starts to discharge.

[0119] S240 , the discharge circuit stops discharging the sensing node.

[0120] Specifically, the first and second terminals of the discharge circuit 620 are finally disconnected, and the capacitor Cso (or parasitic capacitance) coupled to the sensing node SO stops discharging. That is, the discharge duration of the sensing node SO is equal to the difference between the time when the sensing node SO stops discharging and the time when the sensing node SO stops charging.

[0121] In some embodiments, the programming state of the first memory cell may be related to the moment when the charging circuit 610 stops charging the sensing node SO. Fig.13 As shown, step S120 may include steps S310 to S350, as follows:

[0122] S310 , turning on the first transistor in the first charging sub-circuit and the third transistor in the second charging sub-circuit.

[0123] Specifically, Fig. 9 As shown, the first terminal of the first transistor 611 is configured as an input power supply voltage, the second terminal of the first transistor 611 is coupled to the first terminal of the second transistor 612, and the second terminal of the second transistor 612 is coupled to the sensing node SO. The first terminal of the third transistor 613 is configured as an input power supply voltage, and the second terminal of the third transistor 613 is coupled to the sensing node SO.

[0124] The control end of the first transistor 611 is configured to receive the signal S1 outputted from the first output end of the control logic circuit 320, and the control end of the third transistor 613 is configured to receive the signal S2 outputted from the second output end of the control logic circuit 320. When the signal S1 is at a high level, the first transistor 611 is turned off; when the signal S1 is at a low level, the first transistor 611 is turned on. Similarly, when the signal S2 is at a high level, the third transistor 613 is turned off; when the signal S2 is at a low level, the third transistor 613 is turned on.

[0125] The control terminal of the second transistor 612 is coupled to the output terminal of the first latch circuit 500. When the programming state of the first memory cell is the first state, the second transistor 612 is turned on; when the programming state of the first memory cell is the second state, the second transistor 612 is turned off.

[0126] For example, Fig.14 FIG. 1 shows a waveform diagram of a control signal for charging and discharging a sensing node. Fig.14 As shown, first, the signal S1 and the signal S2 have falling edges at the same time; that is, a low level is applied to the gates of the first transistor 611 and the third transistor 613 at the same time, and the first transistor 611 and the third transistor 613 are turned on. In addition, the control logic circuit 320 outputs a signal S3, so that the fifteenth transistor 820 between the power supply VDD and the first end of the charging circuit 610 is turned on.

[0127] That is, when the falling edges of the signals S1 and S2 occur simultaneously, if the programming state of the first storage unit is the first state, the first charging subcircuit and the second charging subcircuit simultaneously charge the sensing node SO; if the programming state of the first storage unit is the second state, the second charging subcircuit can charge the sensing node SO. That is, the charging circuit 610 charges the sensing node SO.

[0128] S320 , applying a bit line voltage to the bit line.

[0129] Specifically, Fig. 9 As shown, the bit line is coupled to the first end of the discharge circuit 620, and the second end of the discharge circuit 620 is coupled to the sensing node SO. When the signal S5 is at a low level, the first end and the second end of the discharge circuit 620 are disconnected; when the signal S5 is at a high level, the first end and the second end of the discharge circuit 620 are connected. In addition, the control logic circuit 320 outputs a signal S4, and when the signal S4 is at a low level, the sixteenth transistor 830 between the first end of the discharge circuit 620 and the bit line is disconnected; when the signal S4 is at a high level, the sixteenth transistor 830 between the first end of the discharge circuit 620 and the bit line is turned on.

[0130] like Fig.14 As shown, the signal S4 and the signal S5 then have rising edges; that is, a high level is applied to the control terminal of the discharge circuit 620 and the gate of the sixteenth transistor 830. Thus, when the signal S4 and the signal S5 have rising edges, the capacitor Cso coupled to the sensing node SO applies a bit line voltage to the bit line. At this time, since the charging circuit 610 is still charging the sensing node SO, the capacitor Cso (or parasitic capacitance) coupled to the sensing node SO does not start to discharge.

[0131] S330, turning off the third transistor.

[0132] Specifically, the signal S2 then has a rising edge; that is, a high level is applied to the gate of the third transistor 613, and the third transistor 613 is turned off. At this time, if the programming state of the first storage unit is the first state, the third transistor 613 is turned off so that the second charging sub-circuit stops charging the sensing node SO, the first charging sub-circuit continues to charge the sensing node SO, and the sensing node SO does not start to discharge. If the programming state of the first storage unit is the second state, since only the second charging sub-circuit can charge the sensing node SO, when the third transistor 613 is turned off, the charging circuit 610 stops charging the sensing node SO, and the sensing node SO starts to discharge.

[0133] S340, turning off the first transistor.

[0134] Specifically, then the signal S1 has a rising edge; that is, a high level is applied to the gate of the first transistor 611, and the first transistor 611 is turned off. If the programming state of the first storage unit is the first state, the third transistor 613 is turned off in step S330, and only the second charging subcircuit stops charging the sensing node SO, and the first charging subcircuit still charges the sensing node SO. When the first transistor 611 is turned off, the first charging subcircuit stops charging the sensing node SO, and the sensing node SO starts to discharge. If the programming state of the first storage unit is the second state, since only the second charging subcircuit can charge the sensing node SO. Therefore, when the third transistor 613 is turned off in step S330, the sensing node SO starts to discharge.

[0135] S350 , the discharge circuit stops discharging the sensing node.

[0136] Specifically, the signal S5 finally has a falling edge; that is, a low level is applied to the control end of the discharge circuit 620, the first end and the second end of the discharge circuit 620 are disconnected, and the discharge circuit 620 stops discharging the sensing node SO.

[0137] like Fig.14 As shown, if step S310-step S350 is executed, when the programming state of the first storage unit is the first state, the discharge time length of the sensing node SO is the first time length, and the first time length is equal to the difference between the time when step S350 is executed and the time when step S340 is executed; when the programming state of the first storage unit is the second state, the discharge time length of the sensing node SO is the second time length, and the second time length is equal to the difference between the time when step S350 is executed and the time when step S330 is executed. It can be seen that the first time length is less than the second time length.

[0138] In some embodiments, the programming state of the first memory cell may also be related to the moment when the discharge circuit 620 stops discharging the sensing node SO. Fig.15As shown, step S120 may further include steps S410 to S450, as follows:

[0139] S410 : The charging circuit charges the sensing node.

[0140] Specifically, Fig.10 As shown, the first terminal of the charging circuit 610 is configured to input the supply voltage, and the second terminal of the charging circuit 610 is coupled to the sensing node SO. The charging circuit 610 is configured to receive the signal S8 output by the control logic circuit 320. When the signal S8 is at a low level, the first terminal and the second terminal of the charging circuit 610 are turned on; when the signal S8 is at a high level, the first terminal and the second terminal of the charging circuit 610 are turned off.

[0141] For example, Fig.16 FIG. 2 shows another waveform diagram of a control signal for charging and discharging a sensing node. Fig.16 As shown, first, the signal S8 has a falling edge; that is, a low level is applied to the control terminal of the charging circuit 610, and the first terminal and the second terminal of the charging circuit 610 are turned on. In addition, the control logic circuit 320 outputs a signal S3, so that the fifteenth transistor 820 between the power supply VDD and the first terminal of the charging circuit 610 is turned on. Therefore, when the signal S8 has a falling edge, the charging circuit 610 charges the sensing node SO.

[0142] S420, turning on the fourth transistor in the first discharge sub-circuit and the sixth transistor in the second discharge sub-circuit.

[0143] Specifically, Fig.10 As shown, a first terminal of the fourth transistor 621 is coupled to the bit line, a second terminal of the fourth transistor 621 is coupled to a first terminal of the fifth transistor 622, and a second terminal of the fifth transistor 622 is coupled to the sensing node SO. A first terminal of the sixth transistor 623 is coupled to the bit line, and a second terminal of the sixth transistor 623 is coupled to the sensing node SO.

[0144] The control end of the fourth transistor 621 is configured to receive the signal S6 outputted from the first output end of the control logic circuit 320, and the control end of the sixth transistor 623 is configured to receive the signal S7 outputted from the second output end of the control logic circuit 320. When the signal S6 is at a low level, the fourth transistor 621 is turned off; when the signal S2 is at a high level, the fourth transistor 621 is turned on. Similarly, when the signal S6 is at a low level, the sixth transistor 623 is turned off; when the signal S6 is at a high level, the sixth transistor 623 is turned on.

[0145] The control terminal of the fifth transistor 622 is coupled to the output terminal of the first latch circuit 500. When the programming state of the first memory cell is the second state, the fifth transistor 622 is turned on; when the programming state of the first memory cell is the first state, the fifth transistor 622 is turned off.

[0146] like Fig.16 As shown, the signal S6 and the signal S7 then have rising edges; that is, a high level is applied to the gates of the fourth transistor 621 and the sixth transistor 623 at the same time, and the fourth transistor 621 and the sixth transistor 623 are turned on. In addition, the control logic circuit 320 outputs the signal S4 and the signal S9, and when the signal S4 and the signal S9 are at a high level, the sixteenth transistor 830 between the bit line and the first end of the discharge circuit 620 is turned on.

[0147] At this time, since the charging circuit 610 is still charging the sensing node SO, that is, when the rising edges of the signals S6 and S7 appear at the same time, if the programming state of the first memory cell is the second state, the sensing node SO applies the bit line voltage to the bit line through the first discharge sub-circuit and the second discharge sub-circuit; if the programming state of the first memory cell is the first state, the sensing node SO can only apply the bit line voltage to the bit line through the first discharge sub-circuit.

[0148] S430 : The charging circuit stops charging the sensing node.

[0149] Specifically, the signal S8 then has a rising edge, that is, a high level is applied to the control terminal of the charging circuit 610. The first terminal and the second terminal of the charging circuit 610 are disconnected, the charging circuit 610 stops discharging the sensing node SO, and the capacitor Cso (or parasitic capacitance) coupled to the sensing node SO starts to discharge.

[0150] S440, disconnecting the sixth transistor.

[0151] Specifically, the signal S7 then has a falling edge; that is, a low level is applied to the gate of the sixth transistor 623, and the sixth transistor 623 is turned off. At this time, if the programming state of the first storage unit is the first state, only the first discharge sub-circuit can discharge the sensing node SO. When the sixth transistor 623 is turned off, the first discharge sub-circuit stops discharging the sensing node SO, so that the discharge circuit 620 stops discharging the sensing node SO. If the programming state of the first storage unit is the second state, the sixth transistor 623 is turned off so that the first discharge sub-circuit stops discharging the sensing node SO, and the second discharge sub-circuit continues to discharge the sensing node SO; that is, the sensing node SO does not stop discharging.

[0152] S450, turning off the fourth transistor.

[0153] Specifically, then the signal S6 has a falling edge; that is, a low level is applied to the gate of the fourth transistor 621, and the fourth transistor 621 is turned off. At this time, if the programming state of the first storage unit is the first state, since only the first discharge sub-circuit can discharge the sensing node SO. Therefore, when the sixth transistor 623 is turned off in step S440, the sensing node SO stops discharging. If the programming state of the first storage unit is the second state, the sixth transistor 623 is turned off in step S440, and only the first discharge sub-circuit stops discharging the sensing node SO, and the second discharge sub-circuit still discharges the sensing node SO. When the fourth transistor 621 is turned off, the second discharge sub-circuit stops discharging the sensing node SO, and the sensing node SO stops discharging.

[0154] like Fig.16 As shown, if step S410-step S450 is performed, when the programming state of the first storage unit is the first state, the discharge time length of the sensing node SO is the first time length, and the first time length is equal to the difference between the time when step S440 is performed and the time when step S430 is performed; when the programming state of the first storage unit is the second state, the discharge time length of the sensing node SO is the second time length, and the second time length is equal to the difference between the time when step S450 is performed and the time when step S430 is performed. It can be seen that the first time length is less than the second time length.

[0155] In addition, the programming state of the first memory cell may also be related to the moment when the charging circuit 610 stops charging the sensing node SO and the moment when the discharging circuit 620 stops discharging the sensing node SO. Fig.17 As shown, step S120 may also include step S510-step S560; wherein, step S510 is the same as step S310, step S520 is the same as step S420, step S530 is the same as step S330, step S540 is the same as step S340, step S550 is the same as step S440, and step S560 is the same as step S450, which will not be repeated in this application.

[0156] like Fig.17 As shown, if steps S510 to S560 are executed, when the programming state of the first storage unit is the first state, the discharge time length of the sensing node SO is the first time length, which is equal to the difference between the time when step S550 is executed and the time when step S540 is executed; when the programming state of the first storage unit is the second state, the discharge time length of the sensing node SO is the second time length, which is equal to the difference between the time when step S560 is executed and the time when step S530 is executed. It can be seen that the first time length is less than the second time length.

[0157] S130 , in the stage of programming and verifying the second memory cell in the memory cell array, the charge and discharge circuit discharges the sensing node multiple times, and the discharge time increases gradually.

[0158] Specifically, under the same verification voltage, the higher the threshold voltage of the second storage unit, the lower the discharge rate of the sensing node SO. Under the same verification voltage, the present application divides the threshold voltage of the second storage unit by discharging the sensing node SO multiple times with gradually increasing discharge durations.

[0159] For example, Fig.18 As shown in FIG. 1 , if the voltage of the sensing node SO is less than the threshold voltage after a short discharge time, it indicates that the discharge rate of the sensing node SO is high (more charge is released in a short discharge time), and the threshold voltage of the second storage unit is low; that is, the second storage unit is located at Fig.18 The a area in .

[0160] If the voltage of the sensing node SO is greater than the threshold voltage after a long discharge time, it indicates that the discharge rate of the sensing node SO is low (less charge is released during a long discharge time), and the threshold voltage of the second storage unit is high; that is, the second storage unit is located at Fig.18 The c region in .

[0161] If the voltage of the sensing node SO is greater than the threshold voltage after a shorter discharge time, and the voltage of the sensing node SO is less than the threshold voltage after a longer discharge time, it indicates that the threshold voltage of the second storage unit is between the threshold voltages of the above two cases; that is, the second storage unit is located in the case Fig.18 The b area in .

[0162] Among them, the second storage cell located in the c area is a storage cell that has passed the verification. Then, in the programming stage of the next programming cycle, different bit line voltages can be applied to the second storage cells located in different areas. For example, for the second storage cell located in the a area, in the next programming cycle, a bit line voltage of 0V is applied to the bit line coupled to the second storage cell to program the second storage cell; for the second storage cell located in the b area, in the next programming cycle, a bit line voltage of 0.5V is applied to the bit line coupled to the second storage cell to slightly prevent the second storage cell from being programmed; for the second storage cell located in the c area, in the next programming cycle, a bit line voltage of 2.2V is applied to the bit line coupled to the second storage cell to prevent the second storage cell from being programmed. Fig.19As shown, after the programming stage of the next programming cycle, the threshold voltage of the second storage cell located in area a increases greatly, the threshold voltage of the second storage cell located in area b increases less, and the threshold voltage of the second storage cell located in area c remains unchanged, so as to realize accurate programming of the second storage cell.

[0163] S140 , after the discharge time has elapsed, the second latch circuit latches information on whether the second storage unit passes programming verification according to the voltage value of the sensing node.

[0164] Specifically, if the second storage unit passes the verification, then after the discharge time, the sensing node SO will not have a significant voltage drop; that is, the voltage of the sensing node is greater than the preset threshold voltage. At this time, the second latch circuit 700 latches the first information indicating that the second storage unit has passed the verification. If the second storage unit fails to pass the verification, then after the discharge time, the sensing node SO will have a significant voltage drop; that is, the voltage of the sensing node is less than the preset threshold voltage. At this time, the second latch circuit 700 latches the second information indicating that the second storage unit has not passed the verification.

[0165] The present application also provides a computer-readable storage medium, which stores computer-executable instructions. After the computer-executable instructions are executed, each step in the above method embodiment can be implemented, such as executing Figure 11-Figure 17 The method shown.

[0166] The present application embodiment provides a computer device, including a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions. When the executable instructions are executed by the processor, the various steps in the above method embodiment can be implemented, such as executing Figure 11-Figure 17 The method shown.

[0167] A storage device, a storage device operation method and a storage system provided by an embodiment of the present application, by setting a first latch circuit 500 in a page buffer 380, the first latch circuit 500 is coupled to a sensing node SO and a charge-discharge circuit 600 configured to discharge the sensing node SO, and is configured to latch the programming state of the first storage unit. Thus, when verifying one of the programming states of the second storage unit (the second storage unit is adjacent to the first storage unit), the present application controls the discharge time of the charge-discharge circuit 600 to the sensing node SO according to the programming state of the first storage unit latched by the first latch circuit 500. Under the same verification voltage, the longer the discharge time, the more charge released by the sensing node SO, the greater the voltage reduction value of the sensing node SO, the more difficult it is for the second storage unit to pass the verification, and then continue to program the second storage unit, so that the second storage unit stores more charge. In other words, under the same verification voltage, different discharge times can make the second storage unit store different amounts of charge. Compared with the traditional solution of using multiple (not less than two) different verification voltages in sequence for repeated verification, the present application only uses one verification voltage to verify the second storage cell, which greatly shortens the programming time.

[0168] Those skilled in the art can clearly understand that, for the convenience and brevity of description, in the above embodiments, the description of each embodiment has different emphases, and for the parts not described in detail in a certain embodiment, reference can be made to the corresponding processes in the aforementioned method embodiments, which will not be repeated here.

[0169] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0170] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0171] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A storage device, characterized in that: The invention comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array comprises a first memory cell and a second memory cell coupled to the same bit line, and the first memory cell and the second memory cell are adjacent to each other; The peripheral circuit includes a page buffer circuit, and the page buffer circuit includes: a sensing node coupled to the bit line; a first latch circuit, coupled to the sensing node, configured to latch a programming state of the first memory cell; a charge-discharge circuit, coupled to the sensing node, configured to charge the sensing node and discharge the sensing node; the discharge duration of the sensing node is related to the programming state of the first storage unit; The second latch circuit is coupled to the sensing node and is configured to latch information on whether the second storage unit passes programming verification according to a voltage value of the sensing node after the discharge time.

2. The storage device according to claim 1, characterized in that The charging and discharging circuit comprises: a charging circuit, wherein a first terminal of the charging circuit is configured to input a supply voltage, and a second terminal of the charging circuit is coupled to the sensing node and configured to charge the sensing node; A discharge circuit has a first terminal coupled to the bit line and a second terminal coupled to the sensing node, and is configured to discharge the sensing node.

3. The storage device according to claim 2, characterized in that: The programming state of the first memory cell includes a first state and a second state, and the threshold voltage of the first memory cell in the first state is greater than the threshold voltage in the second state; When the programming state of the first storage unit is the first state, the discharge duration of the sensing node is the first duration; The discharge duration of the sensing node is equal to the difference between the time when the discharge circuit stops discharging the sensing node and the time when the charging circuit stops charging the sensing node; When the programming state of the first storage unit is the second state, the discharge time is the second time; The first duration is shorter than the second duration.

4. The storage device according to claim 3, characterized in that: The first latch circuit is coupled to the charging circuit, and the charging circuit includes: a first charging subcircuit, wherein a first terminal of the first charging subcircuit is coupled to a first terminal of the charging circuit, and a second terminal of the first charging subcircuit is coupled to a second terminal of the charging circuit; a second charging subcircuit, wherein a first terminal of the second charging subcircuit is coupled to the first terminal of the charging circuit, and a second terminal of the second charging subcircuit is coupled to the second terminal of the charging circuit; When the programming state of the first storage unit is the first state, the first charging subcircuit charges the sensing node; when the programming state of the first storage unit is the second state, the second charging subcircuit charges the sensing node.

5. The storage device according to claim 4, characterized in that: The first charging subcircuit includes a first transistor and a second transistor; a first end of the first transistor is coupled to a first end of the first charging subcircuit, a second end of the first transistor is coupled to a first end of the second transistor, a second end of the second transistor is coupled to a second end of the first charging subcircuit, and a control end of the second transistor is coupled to an output end of the first latch circuit; The peripheral circuit further includes a control logic circuit, and when the programming state of the first storage unit is the first state, the second transistor is turned on; the control logic circuit is configured as follows: controlling the first transistor to be turned on so that the first charging subcircuit charges the sensing node; or, The first transistor is controlled to be turned off, and the first charging sub-circuit stops charging the sensing node.

6. The storage device according to claim 5, characterized in that: The second charging subcircuit comprises a third transistor, a first terminal of the third transistor is coupled to the first terminal of the second charging subcircuit, and a second terminal of the third transistor is coupled to the second terminal of the second charging subcircuit; When the programming state of the first storage unit is the second state, the second transistor is turned off; The control logic circuit is configured to: controlling the third transistor to be turned on so that the second charging subcircuit charges the sensing node; or, The third transistor is controlled to be turned off, and the second charging sub-circuit stops charging the sensing node.

7. The storage device according to any one of claims 3 to 6, characterized in that: The first latch circuit is coupled to the discharge circuit, and the discharge circuit includes: a first discharge subcircuit, wherein a first end of the first discharge subcircuit is coupled to a first end of the discharge circuit, and a second end of the first discharge subcircuit is coupled to a second end of the discharge circuit; a second discharge subcircuit, wherein a first end of the second discharge subcircuit is coupled to the first end of the discharge circuit, and a second end of the second discharge subcircuit is coupled to the second end of the discharge circuit; When the programming state of the first storage unit is the first state, the first discharge sub-circuit discharges the sensing node; when the programming state of the first storage unit is the second state, the second discharge sub-circuit discharges the sensing node.

8. The storage device according to claim 7, characterized in that: The second discharge subcircuit comprises a fourth transistor and a fifth transistor, a first end of the fourth transistor is coupled to the first end of the first discharge subcircuit, a second end of the fourth transistor is coupled to the first end of the fifth transistor, a second end of the fifth transistor is coupled to the second end of the first discharge subcircuit, and a control end of the fifth transistor is coupled to the output end of the first latch circuit; The peripheral circuit further includes a control logic circuit. When the programming state of the first storage unit is the second state, the fifth transistor is turned on. The control logic circuit is configured as follows: controlling the fourth transistor to be turned on so that the second discharge subcircuit discharges the sensing node; or, The fourth transistor is controlled to be turned off, and the second discharge sub-circuit stops discharging the sensing node.

9. The storage device according to claim 8, characterized in that: The first discharge subcircuit comprises a sixth transistor, a first terminal of the sixth transistor is coupled to the first terminal of the first discharge subcircuit, and a second terminal of the sixth transistor is coupled to the second terminal of the first discharge subcircuit; When the programming state of the first storage unit is the first state, the fifth transistor is turned off, and the control logic circuit is configured as follows: controlling the sixth transistor to be turned on so that the first discharge subcircuit discharges the sensing node; or, The sixth transistor is controlled to be turned off, and the first discharge sub-circuit stops discharging the sensing node.

10. A method for operating a storage device, characterized in that: The storage device includes a storage cell array and a peripheral circuit coupled to the storage cell array; The peripheral circuit includes a page buffer circuit, and the operating method includes: latching a programming state of a first memory cell in the memory cell array; During the stage of programming and verifying the second memory cell in the memory cell array, the sensing node in the page buffer circuit is discharged; wherein the discharge duration of the sensing node is related to the programming state of the first memory cell; the first memory cell and the second memory cell are adjacent and coupled to the same bit line, and the sensing node is coupled to the bit line; After the discharge time has elapsed, information on whether the second storage unit has passed programming verification is latched according to the voltage value of the sensing node.

11. The operating method according to claim 10, characterized in that: The discharging the sensing node in the page buffer circuit includes: charging the sensing node; applying a bit line voltage to the bit line; Stop charging the sensing node, and start discharging the sensing node; The discharge of the sensing node is stopped, and the sensing node stops discharging.

12. The operating method according to claim 11, characterized in that: The programming state of the first memory cell includes a first state and a second state, and the threshold voltage of the first memory cell in the first state is greater than the threshold voltage in the second state; When the programming state of the first storage unit is the first state, the discharge duration of the sensing node is the first duration; the discharge duration of the sensing node is equal to the difference between the time when the sensing node stops discharging and the time when the sensing node stops charging; When the programming state of the first storage unit is the second state, the discharge time is the second time; The first duration is shorter than the second duration.

13. The operating method according to claim 12, characterized in that: The discharge time of the sensing node is related to the programming state of the first storage unit, including: The time of stopping charging the sensing node is related to the programming state of the first memory cell; Wherein, when the programming state of the first storage unit is the first state, the first charging subcircuit charges the sensing node; when the programming state of the first storage unit is the second state, the second charging subcircuit charges the sensing node; The time when the first charging sub-circuit stops charging the sensing node is after the time when the second charging sub-circuit stops charging the sensing node.

14. The operating method according to claim 13, characterized in that: When the programming state of the first storage unit is the first state, the second transistor in the first charging sub-circuit is turned on, and the first charging sub-circuit charges the sensing node; comprising: Turning on a first transistor in the first charging subcircuit, so that the first charging subcircuit charges the sensing node; The first transistor is turned off, and the first charging sub-circuit stops charging the sensing node.

15. The operating method according to claim 14, characterized in that: When the programming state of the first storage unit is the second state, the second transistor in the first charging sub-circuit is disconnected, and the second charging sub-circuit charges the sensing node; comprising: Turning on a third transistor in the second charging sub-circuit, so that the second charging sub-circuit charges the sensing node; The third transistor is turned off, and the second charging sub-circuit stops charging the sensing node.

16. The operating method according to claim 15, characterized in that: The time when the first charging sub-circuit stops charging the sensing node is after the time when the second charging sub-circuit stops charging the sensing node, comprising: The third transistor is turned off first, and then the first transistor is turned off.

17. The operating method according to any one of claims 12 to 16, characterized in that: The discharge time of the sensing node is related to the programming state of the first storage unit, including: The time of stopping discharging the sensing node is related to the programming state of the first memory cell; Wherein, when the programming state of the first storage unit is the first state, the first discharge sub-circuit discharges the sensing node; when the programming state of the first storage unit is the second state, the second discharge sub-circuit discharges the sensing node; The second discharge sub-circuit stops discharging the sensing node at a time later than the first discharge sub-circuit stops discharging the sensing node.

18. The operating method according to claim 17, characterized in that: When the programming state of the first storage unit is the second state, the fifth transistor in the second discharge sub-circuit is turned on, and the second discharge sub-circuit discharges the sensing node; comprising: turning on a fourth transistor in the second discharge sub-circuit, so that the second discharge sub-circuit discharges the sensing node; The fourth transistor is turned off, and the second discharge subcircuit stops discharging the sensing node.

19. The operating method according to claim 18, characterized in that: When the programming state of the first storage unit is the first state, the fifth transistor in the second discharge sub-circuit is turned off, and the first discharge sub-circuit discharges the sensing node, including: turning on a sixth transistor in the first discharge sub-circuit, so that the first discharge sub-circuit discharges the sensing node; The sixth transistor is turned off, and the first discharge subcircuit stops discharging the sensing node.

20. The operating method according to claim 19, characterized in that: The moment when the second discharge sub-circuit stops discharging the sensing node is after the moment when the first discharge sub-circuit stops discharging the sensing node, comprising: The sixth transistor is disconnected first, and then the fourth transistor is disconnected.

21. The operating method according to claim 10, characterized in that: The operation method also includes: During a stage of performing programming verification on a second memory cell in the memory cell array, discharging the sensing node multiple times; The discharge duration increases gradually.

22. A storage system, characterized in that: The invention comprises a memory controller and the storage device according to any one of claims 1 to 9, wherein the memory controller is configured to control the storage device.

23. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, the method described in any one of claims 10-21 can be implemented.

24. A computer device, characterized in that: It includes a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, the method described in any one of claims 10-21 can be implemented.

Images