Memory element with random digital generator for protecting memory cells and method for protecting memory element

Abstract

The invention provides a memory element and a protection method thereof. The memory element includes a controller configured to update at least one of a plurality of word lines during a first update period in response to an update signal; a random number generator configured to generate a first number; and the digital regulator is connected to the random digital generator. The digital adjuster is configured to modify the first number to a modified first number, and the modified first number is smaller than a first predetermined number. The memory element further includes a counter electrically coupled to the random number generator and configured to receive the modified first number as an initial value of the counter and to start counting from the initial value in response to the update signal; and an address register electrically coupled to the counter and configured to store an address of a first word line activated when the counter decreases to zero. The counter is configured to access the address register to obtain the address of the first word line and protect a second word line during a second update period, where an address of the second word line is adjacent to the address of the first word line. The counter is configured to decrement in response to an access signal indicating an access to one of the word lines.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 2023118401532, filed on December 28, 2023, with the invention name of “Memory Element and Method for Protecting Memory Element”. Application No. 2023118401532 claims priority and benefits of U.S. formal application No. 18 / 374,151 filed on September 28, 2023. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a memory element and a protection method thereof, and more particularly to a memory element including a protection circuit for protecting a word line. Background Art

[0003] Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor. The simplest DRAM cell consists of a single transistor and a single capacitor. If a charge is stored in the capacitor, the cell is said to store a logic HIGH, depending on the protocol used. If no charge is present, the cell is said to store a logic LOW. Since the charge in the capacitor dissipates over time, DRAM systems require additional refresh circuitry to periodically refresh the charge stored in the capacitor. Since a capacitor can only store a very limited amount of charge, in order to quickly distinguish the difference between a logic "1" and a logic "0", two bit-lines (BLs) are usually used for each bit, where the first of the bit-line pair is called bit line true (BLT) and the other is called bit line complement (BLC). The gate of the single transistor is controlled by the word line (WL).

[0004] Row hammer is a security issue that exploits an unintended and undesired side effect in DRAM, where memory cells electrically interact among themselves by leaking their charge, potentially changing the contents of nearby memory rows (word lines) that were not addressed in the original memory access. Row hammer can be triggered by a special memory access pattern that rapidly activates the same memory row (word line) multiple times. As a result, memory cells connected to adjacent word lines will leak their charge and will have difficulty maintaining the original content in the next periodic update cycle. An attacker (or hacker) can exploit the row hammer effect to change the contents of adjacent memory rows, causing memory element failure. Therefore, there is a need to develop a method of protecting memory elements (particularly word lines) to mitigate the problem.

[0005] The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0006] One aspect of the present disclosure provides a memory element. The memory element includes: a controller configured to update at least one of a plurality of word lines during a first update cycle in response to an update signal; a random number generator configured to generate a first number; and a digital adjuster connected to the random number generator. The digital adjuster is configured to modify the first number to a modified first number, and the modified first number is less than a first predetermined number. The memory element further includes a counter electrically coupled to the random number generator and configured to receive the modified first number as an initial value of the counter, and start counting from the initial value in response to the update signal; and an address register electrically coupled to the counter and configured to store an address of a first word line that is activated when the counter is decremented to zero. The counter is configured to access the address register to obtain the address of the first word line and protect a second word line during a second update cycle, wherein an address of the second word line is adjacent to the address of the first word line. The counter is responsive to an access signal for decrementing, wherein the access signal indicates an access to one of the word lines.

[0007] Another aspect of the present disclosure provides a method for protecting a memory element, wherein the memory element includes a plurality of word lines. The method includes: updating a first word line among the word lines during a first update cycle in response to an update signal; generating a first number using a random number generator; reducing the first number to a second number using a digital adjuster when the first number is greater than the first predetermined number; counting down from the second number using a counter in response to the update signal; obtaining an address of a second word line being accessed using a controller when the counter counts to zero; protecting a third word line during a second update cycle in response to the update signal, wherein an address of the third word line is adjacent to the address of the second word line.

[0008] The disclosed embodiment provides a memory element with a protection circuit for selecting and protecting bit lines that may be attacked. Specifically, the protection circuit of the memory element can protect word lines (memory cells) from row hammer attacks. In order to trigger the row hammer, the attacker quickly activates the same memory column so that the unactivated adjacent memory column may leak its charge. This protection circuit provides a random number generator and a counter to randomly select and protect possible memory columns. The counter can be configured to count down from the random number generated by the random number generator. When the counter counts to zero, the address of the activated memory column can be obtained. In other words, the memory column is selected from those activated memory columns between update cycles. In this case, the selection pool includes the memory columns that have been activated between update cycles. In addition, in order to avoid the random number generated by the random number generator exceeding the maximum number of activations between two update cycles, a digital adjuster is provided to modify the random number to a range of zero to a predetermined number (that is, the maximum number of activations between update cycles). Since the adjacent memory columns adjacent to those activated memory columns are more likely to experience the row hammer effect, they will become the protection target in the next update cycle.

[0009] Generally, the amount of activations that trigger a row hammer cannot be completed within two update cycles. For example, a memory device with 8192 columns may have approximately 170 activations between two update cycles, and the amount of activations that trigger a row hammer for the same column may be 10,000 or more. Therefore, protecting additional memory columns where row hammers may occur in each update cycle can eliminate the row hammer problem. In addition, the memory device may include a digital adjuster to determine whether the random number used to select a particular column from the memory columns exceeds the maximum number of activations between two update cycles (i.e., 170 in this case), and then reduce the random number to a range of 0 to 170. Therefore, the security and performance of the memory device can be improved.

[0010] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure will be described below. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims when considered in conjunction with the drawings, wherein like reference characters represent like elements throughout the drawings, and:

[0012] Figure 1 A schematic diagram of a memory element is shown according to some embodiments of the present disclosure.

[0013] Figure 2 A schematic diagram of a memory element is shown according to some embodiments of the present disclosure.

[0014] Figure 3 A schematic diagram showing activation of a word line between update cycles along a timeline according to some embodiments of the present disclosure.

[0015] Figure 3A A schematic diagram showing the word line meta-address accessed at each activation between refresh cycles along a timeline according to some embodiments of the present disclosure.

[0016] Figure 3B A schematic diagram showing the word line meta-address accessed at each activation between refresh cycles along a timeline according to some embodiments of the present disclosure.

[0017] Figure 3C A schematic diagram showing the word line meta-address accessed at each activation between refresh cycles along a timeline according to some embodiments of the present disclosure.

[0018] Figure 4 A schematic diagram showing a shift register included in a memory element according to some embodiments of the present disclosure is shown.

[0019] Figure 5 A schematic diagram showing a digital regulator included in a memory element according to some embodiments of the present disclosure.

[0020] Figure 6 A schematic diagram showing a digital regulator included in a memory element according to some embodiments of the present disclosure.

[0021] Figure 7A flow chart of a method for protecting a memory element is shown according to some embodiments of the present disclosure.

[0022] The reference numerals are described as follows:

[0023] 1: Memory components

[0024] 2: Memory components

[0025] 3: Schematic diagram

[0026] 3A: Schematic diagram

[0027] 3B: Schematic diagram

[0028] 3C: Schematic diagram

[0029] 7: Methods

[0030] 11: Memory cell array

[0031] 12: Sense Amplifier

[0032] 21: Memory cell array

[0033] 22: Controller

[0034] 23: Random Number Generator

[0035] 23A: First number

[0036] 23B: Modified first digit

[0037] 24: Counter

[0038] 25: Address register

[0039] 26: Digital Regulator

[0040] 26A: Digital regulator

[0041] 26B: Digital Regulator

[0042] 71: Operation

[0043] 72: Operation

[0044] 73: Operation

[0045] 74: Operation

[0046] 75: Operation

[0047] 76: Operation

[0048] 111: Memory column

[0049] 112: Memory column

[0050] 113: Memory column

[0051] 114: Memory column

[0052] 131: Column address decoder

[0053] 132: Row address decoder

[0054] 211: Character line

[0055] 212: Character line

[0056] 213: Character line

[0057] 214: Character line

[0058] 231: Logic Gate

[0059] 232: Logic Gate

[0060] 233: Shift register

[0061] 261: Judgment unit

[0062] 262: AND Gate

[0063] 2330: Trigger

[0064] 2331: Trigger

[0065] 2332: Trigger

[0066] 2333: Trigger

[0067] 2334: Trigger

[0068] 2335: Trigger

[0069] 2336: Trigger

[0070] 2337: Trigger

[0071] 2610: Judgment result

[0072] 2611: Part 1

[0073] 2612: Part 2

[0074] 2620: and output

[0075] act_1: Activation

[0076] act_2: Activation

[0077] act_3: Activation

[0078] act_4: Activation

[0079] act_N-1: Activation

[0080] act_N: activation

[0081] B0: Output terminal

[0082] B1: Output terminal

[0083] B5: Output terminal

[0084] B6: Output terminal

[0085] B7: Output terminal

[0086] Bit0: bit value

[0087] Bit1: Bit value

[0088] Bit2: Bit value

[0089] Bit3: Bit value

[0090] Bit4: Bit value

[0091] Bit5: Bit value

[0092] Bit6: Bit value

[0093] Bit7: Bit value

[0094] CBR: First update cycle

[0095] CBR+1: Second update cycle

[0096] CLKA: clock signal

[0097] CLKB: Clock signal

[0098] CLKC: Clock signal

[0099] CLKD: clock signal

[0100] CLKE: clock signal

[0101] D0: Data terminal

[0102] D1: Data terminal

[0103] D5: Data terminal

[0104] D6: Data terminal

[0105] D7: Data terminal

[0106] L1: AND gate

[0107] L2: AND gate

[0108] L3: OR gate

[0109] L4: AND gate

[0110] L5: AND gate

[0111] L6: AND gate

[0112] L7: AND gate

[0113] L8: Logic Gate

[0114] L10: Output

[0115] L20: Output

[0116] L30: Output

[0117] L40: Output

[0118] L50: Output

[0119] L60: Output

[0120] L70: Output

[0121] RS: Update signal

[0122] R / W: Read / Write signal

[0123] T act : Time period

[0124] T CBR : Time period

[0125] WL1: word line address

[0126] WL2: word line address

[0127] WL3: word line address DETAILED DESCRIPTION

[0128] The following uses specific language to describe the embodiments or examples of the present disclosure shown in the drawings. It should be understood that it is not intended to limit the scope of the present disclosure. Any changes or modifications to the embodiments, and any further application of the principles described herein, are considered to be normal for those with ordinary knowledge in the technical field related to the present disclosure. Reference symbols can be reused in all embodiments, but this does not necessarily mean that the components of one embodiment are applicable to another embodiment, even if they use the same reference symbols.

[0129] It should be understood that, although the first, second, third and other words can be used herein to describe various elements, components, regions, layers or parts, these elements, components, regions, layers or parts are not limited to these words. On the contrary, these words are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teaching of the present disclosure concept, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part.

[0130] The terms used herein are for the purpose of describing specific example embodiments only and are not intended to limit the concepts of the present disclosure. As used herein, the singular forms "a / an" and "the" also include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms "comprises" and "comprising" when used in this specification indicate the presence of the described parts, integers, steps, operations, elements, or components, but do not exclude the presence or increase of one or more parts, integers, steps, operations, elements, components, or combinations of the foregoing.

[0131] It should be noted that the word "approximately" to modify the amount of an ingredient, component, or reactant used in the present disclosure refers to numerical variations that may occur, for example, through typical measurements and liquid handling procedures used to prepare concentrates or solutions. In addition, variations may occur due to inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of the ingredients used to make the composition or implement the method. On the one hand, the word "approximately" means within 10% of the reported value. On the other hand, the word "approximately" means within 5% of the reported value. Again, on the other hand, the word "approximately" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0132] Figure 1 is a schematic diagram of a memory element 1 according to some embodiments of the present disclosure. The memory element 1 may include a memory cell array 11, a sense amplifier 12, a column address decoder 131, and a row address decoder 132. In some embodiments, the memory element 1 may be a DRAM.

[0133] like Figure 1 As shown, the memory cell array 11 may include a plurality of rows and columns. Each row of memory cells may share a bit line or a pair of bit lines. Each column of memory cells may share a word line. In some embodiments, a single memory cell may include a capacitor and a transistor and is configured to store data bits therein. The charge state (charged or discharged) of the capacitor may determine whether the memory cell stores "1" or "0" as a binary value.

[0134] In some embodiments, the memory address applied to the memory cell array 11 can be expressed as a column address and a row address, which are processed by a column address decoder 131 and a row address decoder 132. When the column address decoder 131 selects a particular column (e.g., memory column 114) for a read operation (this selection is also referred to as row activation), bits from all memory cells in the particular column can be transferred to the sense amplifier 12. In some embodiments, one sense amplifier 12 temporarily holds data for each row of memory cells. In some embodiments, the row address decoder 132 can select the exact bit from the sense amplifier 12. In some embodiments, the sense amplifier 12 can be configured to receive or transmit data in response to a read / write signal R / W. A write operation decodes the address in a similar manner, but an entire column can be rewritten to change the value of a single bit.

[0135] Since the data bits are stored in capacitors with a natural discharge rate, the state stored in the memory cell 11 may be lost over time, so all memory cells need to be periodically rewritten to save information, which is a known refresh process. Each memory refresh cycle can update one or more columns of memory cells, and all memory cells can be repeatedly updated in consecutive cycles. Memory updates can be accomplished in a variety of ways. In some embodiments, memory updates can be performed through signals of different modes, such as column address strobe (RAS) updates, column CAS-before-RAS updates (also referred to as CBR updates), and hidden refreshes.

[0136] To trigger the hammer, the same memory rank 111 may be activated at high frequency and in large quantities. When the activation frequency and activation amount of the memory rank 111 are large enough, the unactivated adjacent memory ranks 112 and 113 may leak their charges, resulting in the data / content stored therein being lost.

[0137] The protection circuit provides a random number generator and a counter (the detailed description of which can be found in Figure 2) to randomly select and protect possible memory columns. The counter can be configured to count down from the random number generated by the random number generator. When the counter counts to zero, the address of the activated memory column (such as memory column 111) can be obtained. In other words, the memory column is selected from those memory rows that have been activated between refresh cycles. Since the neighboring memory columns 112 and 113 adjacent to the activated memory column 111 have a higher probability of row hammering, they will be protected in the next refresh cycle. In some embodiments, memory columns 112 and 113 and the planned update memory column 114 can be updated in the next refresh cycle.

[0138] Figure 2 is a schematic diagram of a memory element 2 according to some embodiments of the present disclosure. Figure 2 , the memory element 2 may include a memory cell array 21, a controller 22, a random number generator 23, a counter 24, an address register 25, and a digital adjuster 26. In some embodiments, the memory element 2 may be a dynamic random access memory (DRAM).

[0139] In some embodiments, the memory cell array 21 may include a plurality of word lines. In some embodiments, the memory cell array 21 may include a possible target word line 211 to be accessed, two adjacent word lines 212 and 213 close to the possible target word line 211, and a general word line 214. The general word line 214 may be located at any position of the memory cell array 21. For example, the general word line 214 may be an edge word line or a word line sandwiched between two word lines. In one embodiment, the general word line 214 may be separated from the possible target word line 211. In another embodiment, the general word line 214 may be adjacent to the possible target word line 211 (not shown).

[0140] The controller 22 may be configured to update at least one word line during a first update cycle in response to the update signal RS. In some embodiments, the update signal RS may be a RAS update instruction or a CBR update instruction. The controller 22 may be configured to update one or more word lines during an update cycle. In some embodiments, the controller 22 may be configured to update one, two, three, four, or more word lines simultaneously. In some embodiments, the controller 22 may be configured to update all memory cell arrays 21 cycle by cycle.

[0141] The random number generator 23 may be configured to generate a first number 23A. The first number 23A may be a positive integer. In some embodiments, the first number 23A may be binary. The first number 23A may be represented by a binary sequence having more than 2 bits. For example, the first number 23A may be represented by a binary sequence having 8 bits. That is, the first number 23A may be a number in the range of 0 to 255.

[0142] Reference Figure 2 , the random number generator may include logic gates 231 and 232 and a shift register 233 .

[0143] In some embodiments, the logic gate 231 may have a first input terminal, a second input terminal, and an output terminal. In some embodiments, the logic gate 231 may be configured to receive a first clock signal CLKA and a second clock signal CLKB through the first input terminal and the second input terminal. In some embodiments, the frequency of the first clock signal CLKA is different from the frequency of the second clock signal CLKB. The logic gate 231 may be configured to generate a third clock signal CLKC in response to the first clock signal CLKA and the second clock signal CLKB. In some embodiments, the logic gate 231 may output the third clock signal CLKC through the output terminal of the logic gate 231.

[0144] The logic gate 231 may be an OR gate, an AND gate, an XOR gate, an XNOR gate, etc. In another embodiment, the logic gates 231 and 232 may be other types of logic gates (not shown).

[0145] In some embodiments, the third clock signal CLKC may be unpredictable compared to the first clock signal CLKA and the second clock signal CLKB because it is obtained based on a predetermined calculation in response to the first clock signal CLKA and the second clock signal CLKB. Taking the logic gate 231 as an XOR gate as an example, in principle, regardless of its value, the output of the two-input exclusive OR (XOR) is true only when the two input values ​​are different, and the output is false if the two input values ​​are equal. Based on this calculation of the XOR gate, the third clock signal CLKC may have an uneven frequency.

[0146] In some embodiments, the logic gate 232 may have a first input terminal, a second input terminal, and an output terminal electrically connected to the logic gate 231. The second input terminal and the output terminal of the logic gate 232 may both be electrically connected to the shift register 233. The logic gate 232 may be configured to receive the third clock signal CLKC through the first input terminal of the logic gate 232. In some embodiments, the second input terminal of the logic gate 232 may be configured to receive a bit value associated with the first digit 23A output from the shift register 233. The logic gate 232 may be configured to generate a fourth clock signal CLKD in response to the third clock signal CLKC and the bit value associated with the first digit 23A. In some embodiments, the logic gate 232 may output the fourth clock signal CLKD through the output terminal of the logic gate 232.

[0147] The logic gate 232 may be an OR gate, an AND gate, an XOR gate, an XNOR gate, etc. In some embodiments, the logic gates 231 and 232 may be the same or different logic gates. For example, the logic gates 231 and 232 may both be exclusive OR (XOR) gates. In another embodiment, the logic gates 231 and 232 may be other types of logic gates (not shown).

[0148] In some embodiments, by feeding back the bit value associated with the first number 23A to the logic gate 232 , the fourth clock signal CLKD can be less predictable than the third clock signal CLKC.

[0149] The shift register 233 may include a first input terminal electrically connected to the output terminal of the logic gate 232, a second input terminal configured to receive a fifth clock signal CLKE, and an output terminal connected to the counter 24. In some embodiments, the shift register 233 is an 8-bit shift register. Therefore, the output terminal of the shift register 233 may have 8 bits (such as Figure 2 In other embodiments, the shift register 233 may have more or less than 8 bits.

[0150] In some embodiments, the first input terminal of the shift register 233 may be configured to receive the fourth clock signal CLKD. In some embodiments, the first input terminal of the shift register 233 may be a data terminal. In some embodiments, the second input terminal of the shift register 233 may be a clock terminal.

[0151] The shift register 233 may be configured to generate the first digital 23A in response to the fourth clock signal CLKD and the fifth clock signal CLKE. In some embodiments, the output of the shift register 233 may be configured to output the first digital 23A in response to the fourth clock signal CLKD.

[0152] The output of the shift register 233 may be connected to the second input of the logic gate 232, so that the bit value associated with the first number 23A is fed back to the logic gate 232. For example, the 3-bit output of the shift register 233 may be connected to the second input of the logic gate 232. In some embodiments, the logic gate 232 may be configured to generate a fourth clock signal CLKD in response to the third clock signal and the bit value (e.g., the bit value of the 3-bit output). The fourth clock signal CLKD may be associated with the current number output from the shift register 233.

[0153] The shift register 233 may be configured to generate a random number (i.e., the first number 23A) in response to the fourth clock signal CLKD as a data input and the fifth clock signal CLKE as a clock input. By feeding back the bit value associated with the first number 23A to the logic gate 232, the random number generator 23 may be non-pseudo. Therefore, the first number 23A may be more difficult to predict. Thus, the security of the memory element 2 may be improved.

[0154] The digital adjuster 26 may be connected to the random number generator 23 and configured to receive the first number 23A. The digital adjuster 26 may be a circuit for reducing the first number 23A to a value less than a threshold value. In some embodiments, the digital adjuster 26 may be configured to generate a modified first number 23B (or second number 23B) based on the first number 23A. In some embodiments, when the first number 23A is greater than a first predetermined number, the first number 23A may be modified to a modified first number 23B by the digital adjuster 26. In some embodiments, the first predetermined number is the maximum number of accesses between update cycles (a detailed description of which may be referred to in Figure 3 ). After modification, the modified first number 23B is smaller than the first predetermined number. The modified first number 23B may be smaller than the first number 23A.

[0155] Modified first numeral 23B can be represented by the form identical with first numeral 23A.In certain embodiments, first numeral and modified numeral can be binary.For example, if first numeral 23A is represented by the binary sequence with 8 bits, then modified first numeral 23B is also represented by the binary sequence with 8 bits.In certain embodiments, first numeral 23A can be represented by the binary sequence with Bit7, Bit6, Bit5, Bit4, Bit3, Bit2, Bit1 and Bit0. Modified first numeral 23B can be represented by the binary sequence with Bit7', Bit6', Bit5', Bit4', Bit3', Bit2', Bit1' and Bit0'.

[0156] The difference between the first number 23A and the modified first number 23B may be one bit of a binary sequence. For example, the most significant bit (msb) of the first number 23A may be different from the most significant bit of the modified first number 23B. That is, Bit7' of the modified first number 23B is different from Bit7 of the first number 23A. In some embodiments, Bit6' to Bit0' of the modified first number 23B may be the same as Bit6 to Bit0 of the first number 23A. In another embodiment, the modified first number 23B may be reset to zero by the digital adjuster 26. Therefore, Bit7' to Bit0' of the modified first number 23B are logical "0".

[0157] On the contrary, when the first number 23A is less than the first predetermined number, the digital adjuster 26 will not take any action on the first number 23A. In this case, the modified first number 23B will be the same as the original first number 23A.

[0158] The counter 24 may be electrically coupled to the random number generator 23 and the digital adjuster 26. In some embodiments, the counter 24 may be electrically coupled to the random number generator 23 via the digital adjuster 26. The counter 24 may be configured to receive the modified first number 23B as an initial value of the counter 24. In one embodiment, when the first number 23A is less than the first predetermined number, the modified first number 23B is the same as the first number 23A, and the counter 24 is decremented from the modified first number 23B (i.e., the first number 23A). In another embodiment, when the first number 23A is greater than the first predetermined number, the first number 23A is modified to be a modified first number 23B that is less than the first predetermined number, and the counter 24 is decremented from the modified first number 23B, which is different from the first number 23A.

[0159] In some embodiments, the counter 24 is configured to start in response to an update signal RS received from the controller 22. In other words, the counter 24 may be configured to start counting down in response to the update signal RS. The counter 24 may be configured to count down (count down) from an initial value (ie, the modified first number 23B).

[0160] In some embodiments, counter 24 may be configured to decrement in response to an accessing signal indicating an access to one of the word lines.

[0161] The address register 25 may be electrically coupled to the counter 24. The address register 25 may be configured to obtain the address of the first word line 211 (or possible target word line 211) activated when the counter 24 decrements to zero, and store the address.

[0162] The controller 22 may be configured to access the address register 25 during the second update cycle to obtain the address of the first word line and protect the second bit line 212 / 213 (i.e., the adjacent word line 212 or 213). To protect the second word line 212 / 213, the controller may be configured to update the second word line 212 / 213 during the second update cycle in response to the update signal. In some embodiments, the second update cycle is after the first update cycle. For example, the second update cycle is the next update cycle of the first update cycle. In some embodiments, the address of the second word line 212 / 213 is adjacent to the address of the first word line 211.

[0163] The controller 22 may be configured to update one or more word lines during one update cycle. In some embodiments, the controller 22 may be configured to update one, two, three, four, or more word lines simultaneously. The controller 22 may be configured to update adjacent word lines 212 and 213 during the same update cycle. In some embodiments, in addition to the second word lines 212 / 213, the controller 22 may be further configured to update a third word line 214 during the second update cycle in response to the update signal RS, wherein the address of the third word line 214 is separate from the address of the first word line 211.

[0164] In some embodiments, the controller 22 may be configured to update a word line adjacent to the possible target word line 211 and another word line other than the possible target word line 211. For example, the word line 212 and the word line 214 may be updated during the second update cycle. In some embodiments, in one update cycle, the controller 22 may be configured to update two normal word lines (such as the word line 214) and two high-risk word lines (such as the word lines 212 and 213), which are determined by the random number generator 23 and the counter 24.

[0165] In the present disclosure, the address of the first word line 211 (or possible target word line 211) to be activated can be obtained when the counter 24 is decremented to zero. In this case, the address of the word line to be protected can be randomly selected from those word lines that are activated during two update cycles. In addition, a digital adjuster 26 is provided to modify the first number 23A to be within the range of 0 to a first predetermined number, thereby avoiding the first number 23A being greater than the maximum number of activations between two update cycles.

[0166] Figure 3is a schematic diagram showing activation of a word line between update cycles along a timeline according to some embodiments of the present disclosure Figure 3 .

[0167] Reference Figure 3 , along the timeline (i.e., x-axis), time period T CBR Between the first update period CBR and the second update period CBR+1. In some embodiments, the second update period CBR+1 immediately follows the first update period CBR. In some embodiments, N activations (act_1, act_2, act_3, ..., act_N-1, act_N) occur between the first update period CBR and the second update period CBR+1. Each activation act_1, act_2, act_3, act_N-1, and act_N represents an access to a word line. act is the time period between two activations. For example, the time period T act In some embodiments, the time period T act It may be the minimum necessary time to access a word line (such as the first activation act_1).

[0168] For the purpose of clarifying the present disclosure, a memory array with 8k word lines is used as an example. The memory array may include 8192 word lines. In some embodiments, the time to update all word lines (i.e., 8192 word lines) may be 64 ms. In this case, the time period T CBR , that is, the time required to update each word line, can be calculated as 64ms / 8192, so the time period T CBR In other words, for a total of 8k word lines, the time period T CBR The share between the two update cycles can be 7.8125 μs. Assuming that the time period T act is 45.75ns, then the maximum number of accesses between two update cycles is N max According to the formula N max =T CBR / T act Therefore, the maximum number of access times N max It can be 7.8125μs / 45.75ns=170.765≈170, that is Figure 3 The number N in is 170. In this embodiment, 170 word lines can be accessed between two update cycles. Accordingly, the first number 23A received by the counter 24 can be adjusted to be lower than a predetermined value (eg, 170 in this embodiment).

[0169] In some embodiments, the first number 23A may be smaller than a predetermined number that is related to the time period T used to access the word line. act and the time period T between the first update period CBR and the second update period CBR+1 CBR In some embodiments, the counter 24 may be configured to reset the initial value when the first number 23A is greater than a predetermined number. For example, the initial value of the counter 24 may be reset to zero or a constant may be subtracted to make it less than a predetermined number to reset the initial value of the counter 24. Thus, the counter 24 may start counting down from an initial value within a range of 0 to a predetermined number (i.e., the maximum number of accesses between two update cycles), and when it is decremented to zero, a word line to be protected during the next update cycle may be selected.

[0170] Figure 3A Schematic diagram showing the word line address accessed at each activation between update periods CBR and CBR+1 along a timeline according to some embodiments of the present disclosure Figure 3A .

[0171] Reference Figure 3A , each time act_1, act_2, act_3, act_4, ... and act_N are activated, the word line address WL1 is accessed. In this case, no matter what the initial value of the counter 24 is, the address register 25 will store the most accessed word line address WL1. In other words, the word line address WL1 is most likely to be the target of the attacker. Therefore, selecting the word line adjacent to the word line address WL1 for protection can well prevent the occurrence of the hammer effect.

[0172] Figure 3B A schematic diagram B2 is shown showing the word line address accessed at each activation between the update periods CBR and CBR+1 along the timeline according to some embodiments of the present disclosure.

[0173] Reference Figure 3B , word line address WL1 is accessed when act_1 is activated. Word line address WL2 is accessed when act_2 is activated. Word line address WL1 is accessed when act_3 is activated. Word line address WL2 is accessed when act_4 is activated. Word line address WL2 is accessed when act_N is activated. That is, only word line addresses WL1 and WL2 are accessed. In this case, regardless of the initial value of counter 24, address register 25 will store the most accessed word line address WL1 or WL2. In some embodiments, the probability of word line addresses WL1 and WL2 being attacked is 50%. In other words, word line addresses WL1 and WL2 are most likely to be targeted by attackers. Therefore, selecting word lines adjacent to word line address WL1 or WL2 for protection can effectively prevent the occurrence of the hammer effect.

[0174] Figure 3C Schematic diagram showing the word line address accessed for each activation between update periods CBR and CBR+1 along a timeline according to some embodiments of the present disclosure Figure 3C .

[0175] Reference Figure 3C , access word line address WL1 when act_1 is activated. Access word line address WL2 when act_2 is activated. Access word line address WL3 when act_3 is activated. Access word line address WL1 when act_4 is activated. Access word line address WL2 when act_N-1 is activated. Access word line address WL3 when act_N is activated. In some embodiments, word line addresses WL1, WL2, and WL3 are repeatedly accessed in sequence. That is, only word line addresses WL1, WL2, and WL3 are accessed between two update cycles. In this case, address register 25 will store one of word line addresses WL1, WL2, and WL3. In some embodiments, the probability that word line addresses WL1, WL2, and WL3 are attacked can be approximately 33.33%. In other words, word line addresses WL1, WL2, and WL3 are most likely to be targeted by attackers. Therefore, the word line adjacent to the word line address WL1, WL2, or WL3 is selected for protection, which can effectively prevent the hammer effect from occurring.

[0176] Figure 4 A schematic diagram showing a shift register 233 included in a memory element according to some embodiments of the present disclosure.

[0177] Reference Figure 4 , the shift register 233 may include one or more flip-flops 2330, 2331, ..., 2335, 2336, and 2337. In some embodiments, the flip-flops 2330, 2331, ..., 2335, 2336, and 2337 may be any type of flip-flops, for example, D flip-flops. In some embodiments, the 8-bit shift register 233 may include eight flip-flops 2330, 2331, ..., 2335, 2336, and 2337. In some embodiments, the shift register 233 may be a serial-in parallel-out configuration.

[0178] Each flip-flop 2330, 2331, ..., 2335, 2336, and 2337 may have a data terminal, a clock terminal, a reset terminal, and an output terminal. In some embodiments, the clock terminal of the flip-flops 2330, 2331, ..., 2335, 2336, and 2337 is connected and configured to receive a clock signal CLKE (e.g., Figure 2. As shown). That is, the flip-flops 2330, 2331, ..., 2335, 2336, and 2337 can operate at a given clock frequency of the clock signal CLKE. The reset terminals of the flip-flops 2330, 2331, ..., 2335, 2336, and 2337 are connected and configured to receive a reset signal. In some embodiments, the flip-flops 2330, 2331, ..., 2335, 2336, and 2337 can be reset in response to the reset signal. In some embodiments, each of the flip-flops 2330, 2331, ..., 2335, 2336, and 2337 can have a set terminal (not shown).

[0179] In some embodiments, the data terminal D7 of the flip-flop 2337 may be configured to receive a clock signal CLKD (eg, Figure 2 In response to the clock signals CLKD and CLKE, the output terminal B7 of the flip-flop 2337 may be configured to output the bit value Bit7, which is transmitted to the counter 24 and the data terminal D6 of the flip-flop 2336. In response to the bit value Bit7 and the clock signal CLKE, the output terminal B6 of the flip-flop 2336 may be configured to output the bit value Bit6, which is transmitted to the counter 24 and the data terminal D5 of the flip-flop 2335. In response to the bit value Bit6 and the clock signal CLKE, the output terminal B5 of the flip-flop 2335 may be configured to output the bit value Bit5, which is transmitted to the counter 24 and the data terminal (not shown) of the flip-flop 2334. In some embodiments, the omitted flip-flops 2334, 2333, and 2332 may be configured between the flip-flops 2335 and 2331 in a manner similar to the flip-flops 2336 and 2335. In response to the bit value Bit2 and the clock signal CLKE received at the data terminal D1 of the flip-flop 2331, the output terminal B1 of the flip-flop 2331 may be configured to output the bit value Bit1, which is transmitted to the counter 24 and the data terminal D0 of the flip-flop 2330. In response to the bit value Bit1 and the clock signal CLKE, the output terminal B0 of the flip-flop 2330 may be configured to output the bit value Bit0, which is transmitted to the counter 24.

[0180] The data input of the shift register 233 is serial. Once the data is input, it can be read out at each output terminal at the same time, or it can be shifted out. Each input bit reaches the Nth output after N clock cycles, thus forming a parallel output. The bit values ​​Bit7, Bit6, Bit5, ..., Bit1, and Bit0 can form the first number 23A in 8-bit form. Back to reference Figure 2, the output of the shift register 233 can be connected to the second input of the logic gate 232, so that the bit value associated with the first number 23A is fed back to the logic gate 232. In some embodiments, the fed back bit value can be Figure 4 The bit values ​​shown are one of Bit7, Bit6, Bit5, ..., Bit1, and Bit0.

[0181] The shift register 233 may be configured to generate a random number (such as the first number 23A) in response to a data signal (i.e., clock signal CLKD) and a clock signal CLKE. The unpredictable clock signal CLKC is generated based on the asynchronous clock signals CLKA and CLKB through the logic gate 231. In addition, the clock signal CLKD may be more unpredictable because it is generated based on the unpredictable clock signal CLKC and the feedback bit value associated with the first number 23A. In this case, the clock signal CLKD may be more unpredictable. In the absence of any pseudo-algorithm, the random number generator 23 may be configured to generate a more unpredictable number. Therefore, the hammer attacker cannot predict or know the word line address that the memory element will protect.

[0182] Figure 5 A schematic diagram showing a digital adjuster 26A included in a memory element according to some embodiments of the present disclosure. The digital adjuster 26A is Figure 2 An embodiment of the digital adjuster 26 is shown. The digital adjuster 26A is configured to reset the most significant bit (MSB) of the first number 23A when the first number 23A is greater than a first predetermined number.

[0183] Reference Figure 5 , the digital adjuster 26A may include a judgment unit 261 and an AND gate 262. The judgment unit 261 may be configured to receive the first number 23A from the random number generator 23. In some embodiments, the judgment unit 261 may be configured to judge whether the first number 23A is greater than a first predetermined number, and output a judgment result 2610.

[0184] The AND gate 262 may have one input terminal connected to the random number generator 23, another input terminal connected to the judgment unit 261, and an output terminal connected to the counter 24. In some embodiments, the AND gate 262 may be configured to receive the most significant bit Bit7 of the first number 23A and the judgment result 2610, and generate an AND output 2620 in response to the most significant bit Bit7 of the first number 23A and the judgment result 2610. In some embodiments, the AND gate 262 may be configured to transmit the AND output 2620 to the counter 24 as the most significant bit Bit7' of the modified first number 23B.

[0185] In principle, the output of the two-input AND gate is true only when all input values ​​are logic "1". If not all inputs to the AND gate are logic "1", the output is false. Based on this calculation of the AND gate 262, the output 2620 can be represented as a truth table 1.

[0186] Truth Table 1

[0187] Bit7 2610 2620 / Bit7' 0 0 0 0 1 0 1 0 0 1 1 1

[0188] In some embodiments, when the judgment result 2610 is a logic high level (logic high), it indicates that the first number 23A is less than a predetermined number. Conversely, when the judgment result 2610 is a logic low level (logic low), it indicates that the first number 23A is greater than the predetermined number. Therefore, when the judgment result 2610 is a logic low level (logic "0") and Bit7 of the first number 23A is a logic high level (logic "1"), the output 2620 will be a logic low level to reduce the first number 23A to a modified first number 23B. That is, the most significant bit (msb) of the first number 23A can be reset to logic "0". In some embodiments, when the first number 23A is greater than the first predetermined number, the digital adjuster 26A can be configured to subtract 128 (that is, 2 7 ) to obtain the modified first number 23B. For example, when the first number 23A is 171, which is greater than the first predetermined number 170, the digital adjuster 26A can subtract 128 from the first number 23A to generate a modified first number 23B of 42.

[0189] The determination unit 261 may be a circuit including one or more logic gates. In some embodiments, the determination unit 261 may include a first portion 2611, a second portion 2612, and a logic gate L8.

[0190] In some embodiments, the first part 2611 may include two AND gates L6 and L7. AND gate L6 has two input terminals connected to the shift register 233 of the random number generator 23, which is configured to receive Bit5 and Bit7 of the first digit 23A respectively. AND gate L6 is configured to generate output L60 at the output terminal in response to Bit5 and Bit7 of the first digit 23A. AND gate L7 may have three input terminals connected to the shift register 233 of the random number generator 23, which is configured to receive Bit4, Bit5, and Bit7 of the first digit 23A respectively. AND gate L7 is configured to generate output L70 at the output terminal in response to Bit4, Bit5, and Bit7 of the first digit 23A.

[0191] The first part 2611 can be configured to determine whether the first part of the binary sequence of the first number 23A is greater than the first threshold value. In some embodiments, when the first number 23A is represented by a binary sequence having 8 bits, the first part of the binary sequence of the first number 23A can be 4 bits (e.g., the first four digits). In some embodiments, the first threshold value can be represented by a 4-bit binary sequence (e.g., the first four digits of the first predetermined number). For example, if the first predetermined number is 170, which can be represented by 10101010 in binary, the first threshold value can be represented by 1010 in binary.

[0192] In some embodiments, the second part 2612 includes AND gates L1, L2, L4, L5, and OR gate L3. AND gate L1 may have three inputs connected to the shift register 233 of the random number generator 23, which is configured to receive Bit0, Bit1, and Bit3 of the first digit 23A, respectively. AND gate L1 is configured to generate output L10 at the output terminal in response to Bit0, Bit1, and Bit3 of the first digit 23A. AND gate L2 may have two inputs connected to the shift register 233 of the random number generator 23, which is configured to receive Bit2 and Bit3 of the first digit 23A, respectively. AND gate L2 is configured to generate output L20 at the output terminal in response to Bit2 and Bit3 of the first digit 23A. The outputs of AND gates L1 and L2 are connected to OR gate L3 as input. OR gate L3 is configured to generate output L30 at the output terminal in response to outputs L10 and L20.

[0193] The AND gate L4 may have two input terminals connected to the shift register 233 of the random number generator 23, which are configured to receive Bit5 and Bit7 of the first number 23A, respectively. The AND gate L4 is configured to generate an output L40 at the output terminal in response to Bit5 and Bit7 of the first number 23A. The AND gate L5 may have two input terminals connected to the OR gate L3 and the AND gate L4, respectively, which are configured to receive outputs L30 and L40, respectively. The AND gate L5 is configured to generate an output L50 at the output terminal in response to outputs L30 and L40.

[0194] The second part 2612 can be configured to determine whether the second part of the binary sequence of the first digit 23A is greater than or equal to the first threshold value when the first part of the binary sequence of the first digit 23A is greater than or equal to the first threshold value. In some embodiments, when the binary sequence of the first digit 23A has 8 bits, the second part of the binary sequence of the first digit 23A can be 4 bits (for example, the last four digits). In some embodiments, the second threshold value can be represented by a 4-bit binary sequence (for example, the last four digits of the first predetermined number). For example, if the first predetermined number is 170, it can be represented by 10101010 in binary, and the second threshold value can be represented by 1010 in binary. In some embodiments, the AND gate L4 is configured to determine whether the first part of the binary sequence of the first digit 23A is greater than or equal to the first threshold value.

[0195] In some embodiments, each of the first part 2611 and the second part 2612 can compare a portion of the first number 23A with a corresponding portion of the first predetermined number. Then, the logic gate L8 can combine the results of the first part 2611 and the second part 2612 and output a final judgment result (ie, judgment result 2610).

[0196] In some embodiments, the logic gate L8 may be a NOR gate. The logic gate L8 may be connected to the first portion 2611 and the second portion 2612. In some embodiments, the logic gate L8 may have three input terminals connected to the AND gates L5, L6, and L7, respectively, which are configured to receive outputs L50, L60, and L70, respectively. In some embodiments, the logic gate L8 is configured to generate a judgment result 2610 at the output terminal in response to the outputs L50, L60, and L70. Based on this calculation of the logic gate L8, the judgment result 2610 can be represented as a truth table 2.

[0197] Truth Table 2

[0198] L50 L60 L70 2610 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 1 0

[0199] Only when the outputs L50, L60, and L70 are all logic "0", the logic gate L8 will output logic "1". In some embodiments, when the judgment result 2610 is a logic high level, it means that the first number 23A is less than the predetermined number. Conversely, when the judgment result 2610 is a logic low level, it means that the first number 23A is greater than the predetermined number. In this case, when the judgment result 2610 is a logic low level and Bit7 of the first number 23A is a logic high level, the most significant bit (msb) of the first number 23A can be reset to logic "0".

[0200] Taking the first predetermined number being 170 as an example, when the first number 23A is 127, 128, 170, 171, and 187, the logic gate outputs of the digital adjuster 26A can be represented by Tables 1 to 5, respectively.

[0201] Table 1

[0202] 23A Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 127 0 1 1 1 1 1 1 1 L10 L20 L30 L40 L50 L60 L70 2610 2620 1 1 1 0 0 0 0 1 0

[0203] Table 2

[0204] 23A Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 128 1 0 0 0 0 0 0 0 L10 L20 L30 L40 L50 L60 L70 2610 2620 0 0 0 0 0 0 0 1 1

[0205] Table 3

[0206] 23A Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 170 1 0 1 0 1 0 1 0 L10 L20 L30 L40 L50 L60 L70 2610 2620 0 0 0 1 0 0 0 1 1

[0207] Table 4

[0208] 23A Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 171 1 0 1 0 1 0 1 1 L10 L20 L30 L40 L50 L60 L70 2610 2620 1 0 1 1 1 0 0 0 0

[0209] Table 5

[0210] 23A Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 187 1 0 1 1 1 0 1 1 L10 L20 L30 L40 L50 L60 L70 2610 2620 1 0 1 1 1 0 1 0 0

[0211] Figure 5 The judgment unit 261 shown is an exemplary circuit for judging whether the first number 23A is greater than the first predetermined number. In some embodiments, the judgment unit 261 can also be implemented by other configurations to judge whether the first number 23A is greater than the same first predetermined number. In other embodiments, in order to compare the first number with different first predetermined numbers, the judgment unit 261 can be implemented by different configurations as needed.

[0212] A digital adjuster 26A is provided to determine whether the random number (i.e., the first number 23A) exceeds a first predetermined number (i.e., the maximum number of activations between two update cycles), and then to modify the random number to be within the range of 0 to the first predetermined number. The digital adjuster 26A modifies the most significant bit of the first number 23A so that the first number 23A can be slightly modified to maintain randomness. The operation of the digital adjuster 26A is independent of the processing of the random number generator 23 and therefore does not affect the randomness of the first number 23A.

[0213] Figure 6 A schematic diagram showing a digital regulator 26B included in a memory element according to some embodiments of the present disclosure. The digital regulator 26B is Figure 2 An embodiment of the digital adjuster 26 is shown. The digital adjuster 26B is configured to reset the shift register 233 (ie, the random number generator 23) when the first number 23A is greater than the first predetermined number, so that the modified first number 23B can be reset to zero.

[0214] Digital regulator 26B is similar to digital regulator 26A, except that Figure 6 In the embodiment, the output terminal of the logic gate L8 is directly connected to the reset terminal of the shift register 233 to reset the shift register 233. In some embodiments, the difference between the digital adjuster 26A and the digital adjuster 26B is that the digital adjuster 26A includes an AND gate 262.

[0215] As described above, the configuration of the digital adjuster 26B can be used to determine whether the first number 23A is greater than the first predetermined number. When the first number 23A is determined to be greater than the first predetermined number (e.g., 170), the output of the logic gate L8 (i.e., the determination result 2610) can be transmitted to the shift register 233 to reset the shift register 233. Therefore, the modified first number 23B can be reset to zero.

[0216] A digital adjuster 26B is provided to determine whether the random number (i.e., the first number 23A) exceeds a first predetermined number (i.e., the maximum number of activations between two update cycles), and then reset the random number generator 23 so that the random number will be zero, which is less than the first predetermined number. Therefore, using the digital adjuster 26B can have a higher probability of obtaining the first word line accessed after the previous update cycle.

[0217] Figure 7 According to some embodiments of the present disclosure, a flowchart of method 7 for protecting a memory element is shown. In some embodiments, method 7 is used to protect a word line included in a memory element. In some embodiments, the memory may include a plurality of word lines.

[0218] In operation 71, a first word line of the plurality of word lines may be updated during a first update cycle in response to an update signal. In some embodiments, a controller (e.g., Figure 2 The controller 22 shown in FIG. 1 may update one or more word lines in each update cycle in response to an update signal. Figure 2 The controller 22 is shown to perform operation 71 .

[0219] In operation 72, a first number may be generated using a random number generator. In some embodiments, the random number generator (e.g., Figure 2 The random number generator 23 shown in FIG. 2 can be configured to generate a random number based on different signals. In some embodiments, the random number generator 23 can be configured to generate a random number based on different signals. Figure 2 The random number generator 23 is shown to perform operation 72 .

[0220] In operation 73, when the first number is greater than a first predetermined number, the first number may be reduced to a second number using a digital adjuster. In some embodiments, the second number may be a modified first number. In some embodiments, the first number and the second number may be binary. The difference between the first number and the second number may be a bit of a binary sequence. For example, the most significant bit (MSB) of the first number may be different from the most significant bit of the second number. In another embodiment, the second number may be zero. In some embodiments, the second number may be a modified first number. Figure 2 The digital adjuster 26 is shown to perform operation 73 .

[0221] In operation 74, a counter may be configured to start counting down from the second number in response to the update signal. In some embodiments, the counter may be configured to start counting in response to the update signal. The counter may start counting down from the second number. In some embodiments, each countdown may be triggered by an access signal indicating access to a word line. In some embodiments, the access signal may be configured to start counting down from the second number. Figure 2 Counter 24 is shown to perform operation 74.

[0222] In operation 75, when the counter counts to zero, an address of a second word line to be accessed can be obtained by the controller. In some embodiments, when the counter counts down to zero, the address of the second word line can be obtained and stored in the address register (e.g., Figure 2 The controller (eg, Figure 2 The controller 22 shown in FIG. 1 may be configured to access the address register and obtain the address of the second word line. In some embodiments, the controller 22 may be configured to access the address register and obtain the address of the second word line. Figure 2 Operation 75 is performed in the case of address register 25 as shown.

[0223] In operation 76, in response to the update signal, the third word line may be updated to protect the third word line during the second update cycle, wherein the address of the third word line is adjacent to the address of the second word line. Figure 2 Controller 22 is shown performing operation 76 .

[0224] To achieve hammering, the memory attacker tends to access one or more target word lines at a high frequency. A large number of accesses to the target word lines may cause hammering effect on word lines adjacent to the target word lines. That is, under the hammering effect, even if the adjacent word lines are not accessed, the contents of the adjacent word lines may be changed by leaking their charges.

[0225] The present disclosure provides a memory element, which can determine a target word line that may be attacked, and then protect the word line adjacent to the possible target word line. A random number generator can generate a random number as the initial value of a counter, and when the counter counts to zero, the address of the target word line to be accessed can be obtained. In addition, in order to prevent the random number generated by the random number generator from being greater than the maximum number of activations between two update cycles, a digital adjuster is provided to modify the random number to be within the range of zero to a predetermined number (that is, the maximum number of activations between two update cycles). Therefore, the word line adjacent to the frequently accessed target word line can be updated to maintain the same content.

[0226] One aspect of the present disclosure provides a memory element. The memory element includes: a plurality of word lines; a controller configured to update at least one of the word lines during a first update cycle in response to an update signal; a random number generator configured to generate a first number; and a digital adjuster connected to the random number generator. The digital adjuster is configured to generate a modified first number based on the first number, wherein the modified first number is less than a first predetermined number. The memory element further includes a counter electrically coupled to the random number generator and the digital adjuster, wherein the counter is configured to receive the modified first number as an initial value of the counter and is configured to be turned on in response to the update signal. The controller is further configured to obtain an address of a first word line being accessed when the counter counts to zero, and to update a second word line during a second update cycle, wherein an address of the second word line is adjacent to the address of the first word line.

[0227] Another aspect of the present disclosure provides a memory element. The memory element includes: a controller configured to update at least one of a plurality of word lines during a first update cycle in response to an update signal; a random number generator configured to generate a first number; and a digital adjuster connected to the random number generator. The digital adjuster is configured to modify the first number to a modified first number, and the modified first number is less than a first predetermined number. The memory element further includes a counter electrically coupled to the random number generator and configured to receive the modified first number as an initial value of the counter and start counting from the initial value in response to the update signal; and an address register electrically coupled to the counter and configured to store an address of a first word line activated when the counter is decremented to zero. The counter is configured to access the address register to obtain the address of the first word line and protect a second word line during a second update cycle, wherein an address of the second word line is adjacent to the address of the first word line. The counter is responsive to an access signal for decrementing, wherein the access signal indicates an access to one of the word lines.

[0228] Another aspect of the present disclosure provides a method for protecting a memory element, wherein the memory element includes a plurality of word lines. The method includes: updating a first word line among the word lines during a first update cycle in response to an update signal; generating a first number using a random number generator; reducing the first number to a second number using a digital adjuster when the first number is greater than the first predetermined number; counting down from the second number using a counter in response to the update signal; obtaining an address of a second word line being accessed using a controller when the counter counts to zero; protecting a third word line during a second update cycle in response to the update signal, wherein an address of the third word line is adjacent to the address of the second word line.

[0229] The disclosed embodiment provides a memory element with a protection circuit for selecting and protecting bit lines that may be attacked. Specifically, the protection circuit of the memory element can protect word lines (memory cells) from row hammer attacks. In order to trigger the row hammer, the attacker quickly activates the same memory column so that the unactivated adjacent memory column may leak its charge. This protection circuit provides a random number generator and a counter to randomly select and protect possible memory columns. The counter can be configured to count down from the random number generated by the random number generator. When the counter counts to zero, the address of the activated memory column can be obtained. In other words, the memory column is selected from those activated memory columns between update cycles. In this case, the selection pool includes the memory columns that have been activated between update cycles. In addition, in order to avoid the random number generated by the random number generator exceeding the maximum number of activations between two update cycles, a digital adjuster is provided to modify the random number to a range of zero to a predetermined number (that is, the maximum number of activations between update cycles). Since the adjacent memory columns adjacent to those activated memory columns are more likely to experience the row hammer effect, they will become the protection target in the next update cycle.

[0230] Generally, the amount of activations that trigger a row hammer cannot be completed within two update cycles. For example, a memory device with 8192 columns may have approximately 170 activations between two update cycles, and the amount of activations that trigger a row hammer for the same column may be 10,000 or more. Therefore, protecting additional memory columns where row hammers may occur in each update cycle can eliminate the row hammer problem. In addition, the memory device may include a digital adjuster to determine whether the random number used to select a particular column from the memory columns exceeds the maximum number of activations between two update cycles (i.e., 170 in this case), and then reduce the random number to a range of 0 to 170. Therefore, the security and performance of the memory device can be improved.

[0231] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations of the above processes may be substituted for many of the above processes.

[0232] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A memory element, comprising: a controller configured to update at least one of the plurality of word lines during a first update cycle in response to a refresh signal; a random number generator configured to generate a first number; a digital adjuster connected to the random number generator, wherein the digital adjuster is configured to modify the first number into a modified first number, wherein the modified first number is smaller than a first predetermined number; as well as a counter electrically coupled to the random number generator and configured to receive the modified first number as an initial value of the counter and start counting in response to the update signal; as well as an address register electrically coupled to the counter and configured to store an address of a first word line activated when the counter decrements to zero, wherein the counter is configured to access the address register to obtain the address of the first word line and to protect a second word line during a second update cycle, wherein an address of the second word line is adjacent to the address of the first word line, The counter is configured to decrement in response to an access signal, wherein the access signal indicates an access to one of the word lines. 2 . The memory device of claim 1 , wherein the digital adjuster is configured to reset the random number generator so that the modified first number is reset to zero. The memory device as claimed in claim 1 , wherein the first number is a positive integer.

4. The memory device of claim 1, wherein the first number is binary and is greater than 2 bits. The memory device of claim 4 , wherein the first number is 8 bits. 6 . The memory device of claim 4 , wherein when the first number is greater than the first predetermined number, the digital adjuster is configured to reset a most significant bit of the first number.

7. The memory device of claim 6, wherein the digital adjuster comprises: a determination unit configured to receive the first number and determine whether the first number is greater than the first predetermined number, and output a determination result; as well as an AND gate configured to receive the most significant bit of the first digit and the judgment result, and generate an AND output in response to the most significant bit of the first digit and the judgment result, The AND gate is configured to transmit the AND output to the counter as a most significant bit of the modified first number.

8. The memory device as claimed in claim 7, wherein the determination unit comprises: a first part configured to determine whether a first part of the binary sequence of the first number is greater than a first threshold; a second part, configured to determine whether a second part of the binary sequence of the first number is greater than a second threshold value when a first part of the binary sequence of the first number is greater than or equal to the first threshold value; as well as A first logic gate is connected to the first portion and the second portion, wherein the first logic gate is configured to generate the determination result.

9. The memory device of claim 1, wherein the digital regulator comprises one or more logic gates.

10. The memory device of claim 1, wherein the first predetermined number is associated with a first time period for accessing a word line and a second time period between the first update cycle and the second update cycle.

11. A method for protecting a memory element, wherein the memory element comprises a plurality of word lines, the method comprising: updating a first word line of the plurality of word lines during a first update cycle in response to an update signal; Generate a first number using a random number generator; When the first number is greater than a first predetermined number, reducing the first number to a second number by a digital adjuster; In response to the update signal, using a counter to count down from the second number; When the counter counts to zero, obtaining an address of a second word line to be accessed by a controller; and A third word line is protected during a second refresh cycle in response to the refresh signal, wherein an address of the third word line is adjacent to the address of the second word line.

12. The method of claim 11, wherein the digital adjuster is configured to reset the random number generator so that the second number is reset to zero. The method of claim 11 , wherein the first number is a positive integer.

14. The method of claim 11, wherein the first number is represented by a binary sequence having more than 2 bits.

15. The method of claim 14, wherein the first number is represented by a binary sequence having 8 bits. 16 . The method of claim 14 , wherein when the first number is greater than the first predetermined number, the digital adjuster is configured to reset a most significant bit of the first number.

17. The method of claim 16, wherein the digital adjuster comprises: a determination unit configured to receive the first number, determine whether the first number is greater than the first predetermined number, and output a determination result; as well as an AND gate configured to receive the most significant bit of the first digit and the judgment result, and generate an AND output in response to the most significant bit of the first digit and the judgment result, The AND gate is configured to transmit the AND output to the counter as a most significant bit of the second number.

18. The method of claim 17, wherein the determining unit comprises: a first part configured to determine whether a first part of the binary sequence of the first number is greater than a first threshold; a second part, configured to determine whether a second part of the binary sequence of the first number is greater than a second threshold value when a first part of the binary sequence of the first number is greater than or equal to the first threshold value; as well as A first logic gate is connected to the first portion and the second portion, wherein the first logic gate is configured to generate the determination result.

19. The method of claim 11, wherein the first predetermined number is associated with a first time period for accessing a word line and a second time period between the first update cycle and the second update cycle.

20. The method of claim 11, wherein the countdown is triggered by an access signal indicating an access to one of the word lines.

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