Memory device using data strobe signal and method thereof

Abstract

The invention relates to a memory device using a data strobe signal and a method for compensating for skew of the data strobe signal thereof. A memory device includes a core die including an array of memory cells, and a buffer die electrically connected to the core die through one or more through silicon vias. The buffer die includes a DQS generation circuit that receives an external clock signal from an external device and generates a data strobe signal for communicating data with the core die based on the external clock signal, a DQS calibration circuit, and a coefficient decision circuit, a DQS calibration circuit detects a delay of each of a plurality of memory block signals received from a core die, respectively, based on a data strobe signal, and a coefficient determination circuit detects a threshold voltage code of a buffer die. A weight is applied to the latency of each memory block signal based on the threshold voltage code to generate a weighted calibration code for each memory block signal, and the weighted calibration code is transmitted to a respective one of the core dies.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0129800 filed in the Korean Intellectual Property Office on September 26, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Apparatus, devices, and methods consistent with the present invention relate to semiconductor memory devices, and more particularly, to memory devices using data strobe signals and skew compensation methods for the data strobe signals. Background Art

[0004] Semiconductor memory can be mainly classified as volatile memory or nonvolatile memory. Volatile memory (e.g., DRAM or SRAM) has a fast read and write speed, but when the power is turned off, the data stored in the volatile memory disappears. In contrast, nonvolatile memory can retain data even when the power is turned off. Therefore, nonvolatile semiconductor memory devices can be used to store content that must be saved regardless of whether power is supplied or not.

[0005] The development of new IT technologies such as artificial intelligence (AI), big data, or 5G has led to an increase in demand for high-performance, highly integrated memory semiconductors. As the memory bandwidth required by the system increases, memory bottlenecks emerge. To address this problem, TSV (through silicon via) I / O technology is used for three-dimensional stacked memory, which significantly improves integration and bandwidth. High-bandwidth memory (HBM) technology has been developed. However, during TSV transmission between three-dimensional stacked memory cores, the specified phase difference of the data selection signal may not be maintained, and data collision errors may occur. Summary of the invention

[0006] One aspect is to provide a memory device that reduces data conflicts caused by data strobe signals used in a plurality of core dies by generating a skew calibration code from a buffer die in an integrated manner.

[0007] According to one aspect of one or more example embodiments, a memory device is provided, comprising: a plurality of core dies including a memory cell array; and a buffer die electrically connected to the plurality of core dies through at least one through silicon via (TSV). The buffer die comprises a DQS generation circuit configured to receive an external clock signal from an external device and generate a plurality of data strobe signals based on the external clock signal for communicating data with the plurality of core dies; a DQS calibration circuit configured to detect a delay of each of a plurality of memory block (rank) signals, the plurality of memory block signals being received from the plurality of core dies respectively based on the plurality of data strobe signals; and a coefficient determination circuit configured to detect a threshold voltage code of the buffer die, apply a weight to the delay of each of the plurality of memory block signals based on the threshold voltage code to generate a weighted calibration code for each of the plurality of memory block signals, and send the weighted calibration code to a corresponding core die among the plurality of core dies.

[0008] According to another aspect of one or more example embodiments, a skew compensation method for a memory device is provided, the skew compensation method comprising: sending a plurality of memory block signals from a plurality of core die to a buffer die through at least one through silicon via (TSV), the plurality of memory block signals corresponding to a plurality of data selection signals generated in the buffer die based on an external clock signal received from an external device; detecting an order of the plurality of memory block signals based on a phase of the plurality of memory block signals; detecting a delay of each of the plurality of memory block signals; generating a weighted calibration code for each of the plurality of core die based on a threshold voltage of the buffer die and a delay of each of the plurality of memory block signals; and compensating for the skew of the plurality of memory block signals of the plurality of core die based on the weighted calibration code.

[0009] According to another aspect of one or more example embodiments, a memory device is provided, comprising: a plurality of core dies including a memory cell array; and a buffer die electrically connected to the plurality of core dies through at least one through silicon via (TSV). The buffer die comprises a DQS generation circuit configured to receive an external clock signal from an external device and generate a plurality of data strobe signals based on the external clock signal for communicating data with the plurality of core dies; a DQS calibration circuit configured to detect a delay of each of a plurality of storage block signals, the plurality of storage block signals being received from the plurality of core dies respectively based on the plurality of data strobe signals; and a coefficient determination circuit configured to detect a threshold voltage code of the buffer die, apply a weight to the delay of each of the plurality of storage block signals based on the threshold voltage code to generate a weighted calibration code for each of the plurality of storage block signals, and send the weighted calibration code to the plurality of core dies. The DQS calibration circuit is configured to generate an error detection feedback signal based on the threshold voltage code, and the DQS generation circuit is configured to correct the timing errors of the plurality of data strobe signals based on the error detection feedback signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects will become apparent by describing in detail embodiments thereof with reference to the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a memory system according to an example embodiment;

[0012] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of a memory device of a memory system;

[0013] Figure 3 is a diagram showing a method according to an example embodiment Figure 2 A more detailed diagram of a memory device including Figure 2 components in a buffer die and a first core die of a memory device of;

[0014] Figure 4 is a diagram showing a method of including Figure 2 a diagram of a circuit in a buffer die of a memory device of FIG.

[0015] Figure 5 is a diagram showing a method for Figure 2 A timing diagram of an example of a data strobe signal in a memory device of;

[0016] Figure 6 is a diagram showing a method according to an example embodiment Figure 4 A diagram of an example of a DQS calibration circuit of a circuit of;

[0017] Figure 7 is a diagram showing a method according to an example embodiment Figure 6 A diagram of an example of a delay detection operation of a DQS calibration circuit;

[0018] Figure 8 is a diagram showing a method according to an example embodiment Figure 6 Schematic diagram of an example of a sequence detection circuit of a DQS calibration circuit;

[0019] Fig. 9 is a diagram showing a method according to an example embodiment Figure 6 A diagram of an example of a delay detection circuit of a DQS calibration circuit;

[0020] Fig.10 is a diagram showing a method according to an example embodiment Figure 4 A diagram showing an example of a coefficient determination circuit of a circuit;

[0021] Fig.11 is a diagram showing a method according to an example embodiment Fig.10 A diagram of one of a plurality of weight control circuits of a coefficient determination circuit;

[0022] Fig.12 is a diagram showing a method of Fig.10 The threshold voltage code output by the threshold voltage detection circuit of the coefficient determination circuit and the Fig.10 A table showing examples of weight ratios used in a weight control circuit of a coefficient determination circuit;

[0023] Fig.13 is a diagram showing a method of including Figure 2 an illustration of components in a first core die of a memory device of;

[0024] Fig.14 is a diagram showing a method according to an example embodiment Fig.13 a diagram of an example of a transmitter circuit of a first core die;

[0025] Fig.15 is a diagram showing an example embodiment according to Fig.14 a diagram of an example of a multiplexer of a transmitter circuit;

[0026] Fig.16 is a diagram showing an example embodiment according to Fig.14 Schematic diagram of an example of an adaptive equalizer for a transmitter circuit of ;

[0027] Fig.17 is a diagram showing an example embodiment according to Fig.16 Schematic diagram of an example of an adaptive capacitor of an adaptive equalizer;

[0028] Fig.18is a flow chart illustrating a method of compensating for a skew of a data strobe signal of a memory device according to example embodiments;

[0029] Fig.19 is a diagram showing a method of performing a Figure 4 ; and

[0030] Fig. 20 is a diagram showing an example embodiment according to Fig.19 A diagram of an example of a DQS calibration circuit. DETAILED DESCRIPTION

[0031] Below, various exemplary embodiments will be described in detail and clearly so that those having ordinary skill in the art can easily implement the various exemplary embodiments.

[0032] Below, DRAM will be used as an example for illustrating the features and functions of various example embodiments. However, those of ordinary skill in the art can easily understand other features and performances based on the information disclosed herein. The present disclosure can be implemented by other embodiments or can be applied to other embodiments. In addition, the detailed description can be modified or changed according to the viewpoint and application without departing from the scope, spirit and other purposes of the present disclosure.

[0033] Figure 1 is a block diagram illustrating a memory system according to an example embodiment. Figure 1 , the memory system 1000 may include a memory controller 1100 and a memory device 1200 .

[0034] According to example embodiments, the memory controller 1100 may perform an access operation to write data into the memory device 1200 or read data stored in the memory device 1200. For example, the memory controller 1100 may generate a command CMD and an address ADDR for writing data into the memory device 1200 or reading data stored in the memory device 1200. The memory controller 1100 may include at least one of a system on chip (SoC) such as an application processor (AP), a central processing unit (CPU), a digital signal processor (DSP), and a graphics processing unit (GPU).

[0035] According to example embodiments, the memory controller 1100 may provide various signals to the memory device 1200 to control the overall operation of the memory device 1200. For example, the memory controller 1100 may control memory access operations, such as read operations and write operations, of the memory device 1200. The memory controller 1100 may provide a command CMD and an address ADDR to the memory device 1200 to write data into the memory device 1200 or read data from the memory device 1200.

[0036] According to example embodiments, the memory controller 1100 may generate various types of commands CMD to control the memory device 1200. For example, the memory controller 1100 may generate a memory bank request corresponding to a memory bank operation that changes the state of a memory bank among the memory banks to read or write data. As an example, the memory bank request may include an activity request for changing the state of a memory bank among the memory banks to an active state. The memory device 1200 may activate a row, such as a word line, included in the memory bank in response to the activity request. The memory bank request may include a precharge request for changing a memory bank from an active state to a standby state after completing the reading or writing of data.

[0037] The memory controller 1100 may generate an input / output (I / O) request (e.g., a column address strobe (CAS) request) for the memory device 1200 to perform a read operation or a write operation of data. As an example, the I / O request may include a read request for reading data from an activated memory bank. The I / O request may include a write request for writing data in an activated memory bank. The memory controller 1100 may generate a refresh command to control a refresh operation on a memory bank. However, the types of commands CMD described herein are merely exemplary, and in some example embodiments, other types of commands CMD may exist.

[0038] According to example embodiments, the memory device 1200 may output data requested to be read by the memory controller 1100 to the memory controller 1100, or may store data requested to be written by the memory controller 1100 in a memory cell of the memory device 1200. The memory device 1200 may input and output data based on a command CMD and an address ADDR. The memory device 1200 may include a plurality of memory banks.

[0039] In some example embodiments, the memory device 1200 may be a volatile memory device such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate (DDR) DRAM, a DDR SDRAM, a low power double data rate (LPDDR) SDRAM, a graphic double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), and a static random access memory (SRAM), etc. In some example embodiments, the memory device 1200 may be implemented as a non-volatile memory device such as a resistive RAM (RRAM), a phase change memory (PRAM), a magnetoresistive memory (MRAM), a ferroelectric memory (FRAM), a spin transfer torque RAM (STT-RAM), or the like. In this specification, the advantages of the present disclosure have been described with respect to DRAM by way of example, but example embodiments are not limited thereto.

[0040] According to example embodiments, the memory device 1200 may include a memory cell array divided in units of memory banks, a row decoder, a column decoder, a sense amplifier, a write driver, etc. The memory bank may store data requested to be written into the memory device 1200 through the write driver, and may read data requested to be read using the sense amplifier. The memory device 1200 may also include a component for a refresh operation to store and maintain data in the cell array, or an address-based selection circuit.

[0041] According to an example embodiment, the memory controller 1100 may provide a system clock signal CK to the memory device 1200. The memory device 1200 may generate a plurality of internal clock signals based on the system clock signal CK. The memory controller 1100 and the memory device 1200 may exchange a data input / output signal DQ and a data strobe signal DQS. During a write operation, the memory controller 1100 may send the data input / output signal DQ and the data strobe signal DQS to the memory device 1200. During a read operation, the memory device 1200 may send the data input / output signal DQ and the data strobe signal DQS to the memory controller 1100. The data strobe signal DQS may be used to sample the data input / output signal DQ.

[0042] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 1200 is a diagram of a memory device 1200. Figure 2, the memory device 1200 may include a high bandwidth memory (HBM). For example, the memory device 1200 may include a buffer die 1210 (also referred to as a logic die) and a plurality of core dies stacked on the buffer die 1210. As an example, in some example embodiments, the plurality of core dies may include a first core die 1220, a second core die 1230, and / or a third core die 1240. However, Figure 2 The number of core dies shown in is exemplary, and in some example embodiments, the memory device 1200 may include at least two or more core dies.

[0043] According to example embodiments, a plurality of via holes may be formed in the buffer die 1210 and each of the plurality of core dies, and the interior of the via holes may be filled with through silicon vias (TSVs) (e.g., through electrodes). Therefore, data may be easily sent between the buffer die 1210 and the plurality of core dies through TSVs. In some example embodiments, the memory device 1200 may be, for example, a high-bandwidth memory, and may not only achieve high-speed data transfer through TSVs, but also reduce power consumption. However, due to the increase in the data rate at the data input / output pins, a data conflict may occur when the phase difference between the data selection signals DQS of the plurality of core dies exceeds a specified phase difference. For example, a data conflict may occur when the phase difference between the data selection signals DQS received at the plurality of core dies exceeds a specified phase difference.

[0044] Figure 3 It is shown that the Figure 2 FIG. 1 is a diagram of components in the buffer die 1210 and the first core die 1220. Figure 3 , the buffer die 1210 may include an address (ADDR) buffer 1211, a command (CMD) decoder (DEC) 1212, a control logic 1213, a bit line sense amplifier (BLSA) 1214, and an input / output (I / O) circuit 1215. The first core die 1220 may include a memory cell array 1221, a row decoder (ROW DEC) 1222, and a column decoder (COL DEC) 1223. Each of the plurality of core dies may include Figure 3 The components of the first core die 1220 described are similar components and thus repeated descriptions thereof are omitted for the sake of brevity.

[0045] According to example embodiments, the memory cell array 1221 may include a plurality of memory cells arranged in a matrix of rows and columns. For example, the memory cell array 1221 may include a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL may be connected to the rows of the memory cells, and the plurality of bit lines BL may be connected to the columns of the memory cells.

[0046] According to an example embodiment, the address (ADDR) buffer 1211 may be Figure 1 The memory controller 1100 receives the address ADDR. For example, the address ADDR may include a row address RA for addressing a row of the memory cell array 1221 and a column address CA for addressing a column of the memory cell array 1221. The address buffer 1211 may send the row address RA to the row decoder 1222 and may send the column address CA to the column decoder 1223.

[0047] According to example embodiments, a row decoder (ROW DEC) 1222 may select one of a plurality of word lines WL connected to the memory cell array 1221. The row decoder 1222 may decode a row address RA received from the address buffer 1211 to select a single word line corresponding to the row address RA and may activate the selected word line.

[0048] According to example embodiments, the column decoder (COL DEC) 1223 may select a predetermined bit line from among a plurality of bit lines BL of the memory cell array 1221. The column decoder 1223 may decode a column address CA received from the address buffer 1211 to select a predetermined bit line corresponding to the column address CA.

[0049] According to example embodiments, a bit line sense amplifier (BLSA) 1214 may be connected to a bit line BL of the memory cell array 1221. For example, the bit line sense amplifier 1214 may sense a change in voltage of a selected bit line among a plurality of bit lines BL, and may amplify and output the change in voltage.

[0050] According to example embodiments, the command CMD may include a write enable signal, a row address strobe signal, a column address strobe signal, and / or a chip select signal. According to example embodiments, the command decoder (CMD DEC) 1212 may decode the write enable signal, the row address strobe signal, the column address strobe signal, and the chip select signal received from the memory controller 1100 and provide a control signal corresponding to the command CMD to the control logic 1213. In some example embodiments, the command CMD may include an activity request, a read request, a write request, and / or a precharge request.

[0051] The control logic 1213 may control the overall operation of the bit line sense amplifier 1214 through a control signal corresponding to the command CMD. The control logic 1213 may control the overall operation of the memory device 1200.

[0052] According to example embodiments, the input / output (I / O) circuit 1215 may exchange a data input / output signal DQ with the memory controller 1100 based on a data strobe signal DQS, the data input / output signal DQ being output based on a sensed and amplified voltage from the bit line sense amplifier 1214. For example, in some example embodiments, the input / output circuit 1215 may include an input buffer and / or an output buffer. In some example embodiments, the input buffer and / or the output buffer may be connected to a data pad. In some example embodiments, the input / output circuit 1215 may perform a serialization or parallelization operation of data.

[0053] Figure 4 is a diagram showing a method of including Figure 2 Schematic diagram of the circuit in buffer die 1210. Figure 5 is a diagram showing a method for Figure 2 An example timing diagram of a data strobe signal in a memory device is shown in FIG. Figure 4 , the buffer die 1210 may include a DQS calibration circuit 100 , a coefficient determination circuit 200 , and a DQS generation circuit 300 .

[0054] According to example embodiments, the DQS calibration circuit 100 may be configured to provide a plurality of DQS calibration circuits from the DQS calibration circuit 100 through at least one TSV. Figure 2 Each of the plurality of core dies of the DQS calibration circuit 100 receives a memory block signal (also referred to as a data strobe signal). For example, in some example embodiments, the DQS calibration circuit 100 may receive a first memory block signal RK1 from the first core die 1220 through a first TSV. The DQS calibration circuit 100 may receive a second memory block signal RK2 from the second core die 1230 through a second TSV. The DQS calibration circuit 100 may receive a third memory block signal RK3 from the third core die 1240 through a third TSV.

[0055] According to an example embodiment, the DQS calibration circuit 100 may detect a delay LAT of each of the memory block signals (e.g., the first memory block signal RK1, the second memory block signal RK2, and the third memory block signal RK3) of a plurality of core dies. The coefficient determination circuit 200 may receive the delay LAT from the DQS calibration circuit 100 and generate a weighted calibration code CALw for each of the plurality of memory block signals based on the delay LAT, respectively. The weighted calibration code CALw may be sent to the plurality of core dies and used to compensate for the skew between the data strobe signals of the core dies.

[0056] According to an example embodiment, the DQS generation circuit 300 may be configured from Figure 1 The memory controller 1100 receives a first clock signal CK1 and a second clock signal CK2 having different phases. The DQS generation circuit 300 may generate a plurality of data strobe signals based on the first clock signal CK1 and the second clock signal CK2. For example, in some example embodiments, the plurality of data strobe signals may be an orthogonal data strobe signal DQSq, in which case the orthogonal data strobe signal DQSq may include a first strobe signal DQS1, a second strobe signal DQS2, a third strobe signal DQS3, and a fourth strobe signal DQS4. However, the orthogonal data strobe signal is merely an example, and in some example embodiments, more or fewer data strobe signals may be used.

[0057] refer to Figure 5 , the orthogonal data selection signals DQSq may have a phase difference of 90 degrees with each other. For example, the first selection signal DQS1 may have a phase difference of 90 degrees with the second selection signal DQS2. The second selection signal DQS2 may have a phase difference of 90 degrees with the third selection signal DQS3. The third selection signal DQS3 may have a phase difference of 90 degrees with the fourth selection signal DQS4. The fourth selection signal DQS4 may have a phase difference of 90 degrees with the first selection signal DQS1.

[0058] Figure 6 is a diagram showing a method according to an example embodiment Figure 4 FIG. 1 is a diagram of an example of a DQS calibration circuit 100 . Figure 4 and Figure 6 The DQS calibration circuit 100 may include a multiplexer 101 , a sequence detection circuit 110 , a delay line (DL) circuit 120 , a replica delay line (DL) circuit 130 , a bang-bang phase detector (BBPD) 140 , a calibration control circuit 150 , and a delay detection circuit 160 .

[0059] According to example embodiments, the sequence detection circuit 110 may detect the order of memory block signals (e.g., the first memory block signal RK1, the second memory block signal RK2, and the third memory block signal RK3) of the plurality of core dies. For example, the sequence detection circuit 110 may compare the phases of the first memory block signal RK1, the second memory block signal RK2, and the third memory block signal RK3 to generate a memory block selection signal RKSEL based on the order of the first memory block signal RK1, the second memory block signal RK2, and the third memory block signal RK3.

[0060] According to an example embodiment, the multiplexer 101 may output a selected storage block signal SRK, and the selected storage block signal SRK is selected in the order of a fast phase among the first storage block signal RK1, the second storage block signal RK2, and the third storage block signal RK3 based on the storage block selection signal RKSEL. For example, the storage block selection signal RKSEL may include 2 bits. When the storage block selection signal RKSEL is "01", the multiplexer 101 may output a storage block signal with the fastest phase. When the storage block selection signal RKSEL is "10", the multiplexer 101 may output a storage block signal with an intermediate phase. When the storage block selection signal RKSEL is "11", the multiplexer 101 may output a storage block signal with the slowest phase.

[0061] According to example embodiments, the delay line (DL) circuit 120 may receive the reference strobe signal DQSref and delay the reference strobe signal DQSref by a specified amount. The delay line circuit 120 may adjust the delay amount based on the count value CNT. As the count value CNT increases, the delay line circuit 120 may delay the reference strobe signal DQSref more. As an example, in some example embodiments, the reference strobe signal DQSref may be set to be Figure 4 The DQS generation circuit 300 generates one of the first selection signal DQS1, the second selection signal DQS2, the third selection signal DQS3, and the fourth selection signal DQS4. In some example embodiments, a complementary signal of the first selection signal DQS1 may be set as a reference selection signal DQSref.

[0062] According to example embodiments, the replica delay line (DL) circuit 130 may have the same delay amount as that of the delay line circuit 120. In some example embodiments, the replica delay line circuit 130 may have a delay amount corresponding to a delay amount when the delay line circuit 120 has an input of 0 as the count value CNT. In some example embodiments, the replica delay line circuit 130 may delay the selected memory block signal SRK by a specified amount.

[0063] According to an example embodiment, the switch-mode phase detector 140 may compare the phase of the signal output by the delay line circuit 120 with the phase of the signal output by the replica delay line circuit 130, and output the phase detection signal PDout according to the comparison result. For example, when the phase of the signal output by the delay line circuit 120 is faster than the phase of the signal output by the replica delay line circuit 130, the phase detection signal PDout may be at a first level (e.g., a low level or logic 0). When the phase of the signal output by the delay line circuit 120 is slower than or equal to the phase of the signal output by the replica delay line circuit 130, the phase detection signal PDout may be at a second level (e.g., a high level or logic 1).

[0064] According to example embodiments, the calibration control circuit 150 may generate a count control signal CTcon based on the phase detection signal PDout. For example, when the phase detection signal PDout is at a first level, the count control signal CTcon may be at a first level. When the phase detection signal PDout is at a second level, the count control signal CTcon may be at a second level.

[0065] According to example embodiments, the delay detection circuit 160 may output a count value CNT and / or a delay LAT based on the count control signal CTcon. For example, when the count control signal CTcon is at a first level, the delay detection circuit 160 may increase the count value CNT by a specified amount (e.g., 1). When the count control signal CTcon is at a second level, the delay detection circuit 160 may store and output the delay LAT. However, the specified amount is merely an example, and in some example embodiments, the specified amount may be greater than 1.

[0066] According to example embodiments, the first memory block signal RK1, the second memory block signal RK2, and the third memory block signal RK3 may be input to the replica delay line circuit 130 as the selected memory block signal SRK based on the memory block selection signal RKSEL in rapid order. The reference strobe signal DQSref may be input to the delay line circuit 120. The count value CNT may be initially set to 0.

[0067] According to an example embodiment, the switch-mode phase detector 140 may compare the phase of the signal output by the delay line circuit 120 with the phase of the signal output by the replica delay line circuit 130. When the phase of the signal output by the delay line circuit 120 is faster than the phase of the signal output by the replica delay line circuit 130, the switch-mode phase detector 140 may output a first level as the phase detection signal PDout. The delay detection circuit 160 may increase the count value CNT until the phase of the signal output by the delay line circuit 120 becomes the same as the phase of the signal output by the replica delay line circuit 130.

[0068] According to an example embodiment, when the phase of the signal output by the delay line circuit 120 is the same as the phase of the signal output by the replica delay line circuit 130, the switch-mode phase detector 140 may output the second level as the phase detection signal PDout. When the phase of the signal output by the delay line circuit 120 is the same as the phase of the signal output by the replica delay line circuit 130, the delay detection circuit 160 may store the delay LAT at this time as the delay of the core die corresponding to the currently selected memory block signal SRK (e.g., one of the first memory block signal RK1, the second memory block signal RK2, and the third memory block signal RK3).

[0069] According to an example embodiment, the DQS calibration circuit 100 may repeatedly perform the above-described delay detection operation for each of the first memory block signal RK1, the second memory block signal RK2, and the third memory block signal RK3. The DQS calibration circuit 100 may send the delay LAT from the first core die to each of the third core dies 1220, 1230, and 1240 measured by the delay detection operation to the coefficient determination circuit 200 (see Figure 4 ).

[0070] Figure 7 is a diagram showing a method according to an example embodiment Figure 6 FIG. 1 is a diagram showing an example of a time delay detection operation. Figure 6 and Figure 7 , the DQS calibration circuit 100 may receive the second storage block signal RK2 and the third storage block signal RK3 having a phase earlier than the second storage block signal RK2 and the first storage block signal RK1 having a phase earlier than the third storage block signal RK3 from the first core die to the third core die 1220, 1230 and 1240 respectively. The reference selection signal DQSref may be set to a data selection signal having a phase faster than the first storage block signal RK1 among the first selection signal DQS1, the second selection signal DQS2, the third selection signal DQS3 and the fourth selection signal DQS4.

[0071] According to an example embodiment, since the first memory block signal RK1 is the fastest among the memory block signals, the sequence detection circuit 110 may output "01" as the memory block selection signal RKSEL, and the multiplexer 101 may output the first memory block signal RK1 as the selected memory block signal SRK. The count value CNT may continue to increase through the operations of the above-mentioned switch-type phase detector 140, the calibration control circuit 150, and the delay detection circuit 160. The reference selection signal DQSref may be progressively delayed based on the count value CNT.

[0072] According to an example embodiment, when the phase of the reference selection signal DQSref passing through the delay line circuit 120 is the same as the phase of the first storage block signal RK1 passing through the replica delay line circuit 130, the count value CNT can become a first count C1, and the delay detection circuit 160 can store and output the first delay L1 of the first core die 1220 corresponding to the first storage block signal RK1 based on the first count C1.

[0073] According to example embodiments, when the first time delay L1 corresponding to the first memory block signal RK1 is output, the sequence detection circuit 110 may output "10" as the memory block selection signal RKSEL, and the multiplexer 101 may output the third memory block signal RK3 as the selected memory block signal SRK. The count value CNT may continue to increase through the operation of the switch phase detector 140, the calibration control circuit 150, and the time delay detection circuit 160. The reference selection signal DQSref may be continuously delayed based on the count value CNT.

[0074] According to an example embodiment, when the phase of the reference selection signal DQSref passing through the delay line circuit 120 is the same as the phase of the third storage block signal RK3 passing through the replica delay line circuit 130, the count value CNT can be changed to a second count C2, and the delay detection circuit 160 can store and output the second delay L2 based on the second count C2 by matching the third core die 1240 corresponding to the third storage block signal RK3.

[0075] According to example embodiments, when the second delay L2 corresponding to the third storage block signal RK3 is output, the sequence detection circuit 110 may output "11" as the storage block selection signal RKSEL, and the multiplexer 101 may output the second storage block signal RK2 as the selected storage block signal SRK. The count value CNT may continue to increase through the switch phase detector 140, the calibration control circuit 150, and the delay detection circuit 160. The reference selection signal DQSref may be continuously delayed based on the count value CNT.

[0076] According to an example embodiment, when the phase of the reference selection signal DQSref passing through the delay line circuit 120 is the same as the phase of the second storage block signal RK2 passing through the replica delay line circuit 130, the count value CNT can be changed to a third count C3, and the delay detection circuit 160 can store and output the third delay L3 of the second core die 1230 corresponding to the second storage block signal RK2 based on the third count C3.

[0077] Figure 8 is a diagram showing a method according to an example embodiment Figure 6 FIG. 1 is a diagram of an example of a sequence detection circuit 110. Figure 6 and Figure 8 , the sequence detection circuit 110 may include a plurality of flip-flops 111 and a sequence logic 112 .

[0078] According to example embodiments, each of the first storage block signal RK1, the second storage block signal RK2, and the third storage block signal RK3 may be input to an input terminal of a corresponding one of the plurality of flip-flops 111. The first storage block signal RK1 may be input to a clock terminal of a flip-flop to which the third storage block signal RK3 is input. The second storage block signal RK2 may be input to a clock terminal of a flip-flop to which the first storage block signal RK1 is input to an input terminal. The third storage block signal RK3 may be input to a clock terminal of a flip-flop to which the second storage block signal RK2 is input to an input terminal.

[0079] According to an example embodiment, the sequence logic 112 may receive an output signal from each of the plurality of flip-flops 111. The sequence logic 112 may output a storage block selection signal RKSEL based on the output signals of the plurality of flip-flops 111. As an example, the storage block selection signal RKSEL may include 2 bits. When the storage block selection signal RKSEL is "01", the multiplexer 101 may output a storage block signal having the fastest phase. When the storage block selection signal RKSEL is "10", the multiplexer 101 may output a storage block signal having an intermediate phase. When the storage block selection signal RKSEL is "11", the multiplexer 101 may output a storage block signal having the slowest phase.

[0080] Fig. 9 is a diagram showing a method according to an example embodiment Figure 6 FIG. 1 is a diagram of an example of a delay detection circuit 160. Figure 6 and Fig. 9 The delay detection circuit 160 may include a delay counter 161 and a delay register 162 .

[0081] According to example embodiments, the delay counter 161 may receive a count control signal CTcon from the calibration control circuit 150. When the count control signal CTcon is at a first level (e.g., a low level or logic 0), the delay counter 161 may increase the count value CNT by a specified amount (e.g., 1). When the count control signal CTcon is at a second level (e.g., a high level or logic 1), the delay counter 161 may output a delay LAT at this time based on the count value CNT.

[0082] According to example embodiments, the delay register 162 may store the delay LAT received from the delay counter 161. The delay register 162 may store the delay LAT by matching a core die corresponding to a selected memory block signal SRK (e.g., one of the first memory block signal RK1, the second memory block signal RK2, and the third memory block signal RK3) upon receiving the second level as the count control signal CTcon.

[0083] Fig.10 is a diagram showing a method according to an example embodiment Figure 4 FIG. 2 is a diagram showing an example of a coefficient determination circuit 200. Fig.10 The coefficient determination circuit 200 may include a threshold voltage (Vth) detection circuit 210 and a plurality of weight control circuits 220. The plurality of weight control circuits 220 may include circuits corresponding to a plurality of core dies (eg, Figure 2 The weight control circuit of the first core die to the third core die 1220, 1230 and 1240). Figure 2 The transistors in the buffer die 1210 may have slightly different threshold voltages depending on the product. The coefficient determination circuit 200 may detect the influence of the average threshold voltage of the transistors included in the buffer die 1210 based on the memory block signal, and may apply a weight to the delay LAT of each core die detected by the DQS calibration circuit 100.

[0084] According to example embodiments, the threshold voltage (Vth) detection circuit 210 may generate a threshold voltage code VTHCD of the buffer die 1210 based on the reference strobe signal DQSref. Figure 6 In the embodiment, when the average threshold voltage of the transistors included in the buffer die 1210 is greater than the reference voltage, the delay line circuit 120 may have a larger delay width as the count value CNT increases. When the average threshold voltage of the transistors included in the buffer die 1210 is less than the reference voltage, the delay line circuit 120 may have a smaller delay width as the count value CNT increases. Therefore, the threshold voltage detection circuit 210 may generate a threshold voltage code VTHCD so that as the count value CNT of the delay line circuit 120 increases, the delay width may converge to a value when the average threshold voltage of the transistors included in the buffer die 1210 is the reference voltage.

[0085] According to example embodiments, the threshold voltage code VTHCD may include a code corresponding to a P-type transistor (hereinafter referred to as a P code) and a code corresponding to an N-type transistor (hereinafter referred to as an N code). As an example, the threshold voltage code VTHCD may include a 6-bit code. The threshold voltage code VTHCD may include a 3-bit P code (e.g., P<0:2>) and a 3-bit N code (e.g., N<0:2>).

[0086] According to example embodiments, each of the plurality of weight control circuits 220 may apply a weight according to a threshold voltage code VTHCD to a delay LAT corresponding to a corresponding one of the first core die to the third core die 1220, 1230, and 1240 to output a weighted calibration code CALw corresponding to the first core die to the third core die 1220, 1230, and 1240. For example, one of the plurality of weight control circuits 220 may apply a weight to a first memory block delay LAT_rk1 corresponding to a first memory block signal RK1, and transmit the first weighted calibration code CALw_rk1 to the first core die 1220. Another of the plurality of weight control circuits 220 may apply a weight to a second memory block delay LAT_rk2 corresponding to a second memory block signal RK2 to transmit the second weighted calibration code CALw_rk2 to the second core die 1230. Another one of the plurality of weight control circuits 220 may apply a weight to a third memory block delay LAT_rk3 corresponding to the third memory block signal RK3 and transmit a third weighted calibration code CALw_rk3 to the third core die 1240 .

[0087] Fig.11 is a diagram showing a method according to an example embodiment Fig.10 A diagram of one of the weight control circuits. Fig.11 , the weight control circuit 220 may include a threshold voltage code decoder 221 and a multiple selector 222 .

[0088] According to example embodiments, the threshold voltage code decoder 221 may receive the threshold voltage code VTHCD. The threshold voltage code decoder 221 may decode the threshold voltage code VTHCD and output a weight selection signal WTSEL.

[0089] According to an example embodiment, the multiple selector 222 may output a weight WT based on a weight selection signal WTSEL. For example, the multiple selector 222 may include a plurality of multiple lines and a multiplexer MUX. The time delay LAT_rk# of each storage block signal may be sent to the multiplexer through a corresponding multiple line in the plurality of multiple lines. The weights according to the plurality of weight ratios may be sent to the multiplexer. The multiplexer may output a weight WT corresponding to the weight selection signal WTSEL. One of the plurality of weight control circuits 220 may apply the weight WT to the time delay LAT_rk# of each storage block signal to output a weighted calibration code CALw_rk# of each core die.

[0090] Fig.12 is a diagram showing the Fig.10 The threshold voltage code output by the threshold voltage detection circuit 210 and the Fig.10 A table showing examples of weight ratios used in weight control circuits. Fig.12 , the threshold voltage code VTHCD may include a 3-bit P code (eg, P<0:2>) and a 3-bit N code (eg, N<0:2>). Fig.12 The threshold voltage code VTHCD is shown in three stages, but this is an example, and in some example embodiments, the threshold voltage code VTHCD may have at least two or more stages.

[0091] According to example embodiments, the slow code SS having a small delay variation due to a threshold voltage of a transistor included in the buffer die 1210 being higher than a reference voltage may be set to “111”. The fast code FF having a large delay variation due to a threshold voltage lower than a reference voltage may be set to “000”. The normal code TT having a delay variation range between the slow code SS and the fast code FF may be set to “100”.

[0092] According to example embodiments, a weight corresponding to the threshold voltage code VTHCD may be set. The slow code SS may be converted to a maximum weight (e.g., 2.35 times). The fast code FF may be converted to a minimum weight (e.g., 1.00 times). The normal code TT may be converted to a weight between the weight of the slow code SS and the weight of the fast code FF (e.g., 1.50 times).

[0093] Fig.13 is a diagram showing a method according to an example embodiment including Figure 2 FIG. 12 is a diagram of components in the first core die 1220. Figure 2 and Fig.13 , the first core die 1220 may include a calibration code register 400 , a DQS skew compensator 500 , and a transmitter (TX) circuit 600 . Fig.13 The first core die 1220 is shown as an example, but the remaining core dies (eg, the second core die 1230 and the third core die 1240 ) have the same configuration as the first core die 1220 , and thus repeated descriptions thereof are omitted for the sake of brevity.

[0094] According to an example embodiment, the calibration code register 400 may receive the weighted calibration code CALw from the coefficient determination circuit 200 of the buffer die 1210 through TSV and store the weighted calibration code CALw. The calibration code register 400 may transmit the weighted calibration code CALw to the DQS skew compensator 500 and the transmitter circuit 600.

[0095] According to example embodiments, the DQS skew compensator 500 may receive the orthogonal data strobe signal DQSq from the DQS generation circuit 300 of the buffer die 1210 through TSVs. The orthogonal data strobe signal DQSq may include first, second, third, and fourth strobe signals DQS1, DQS2, DQS3, and DQS4.

[0096] According to an example embodiment, the DQS skew compensator 500 may calibrate the orthogonal data strobe signal DQSq based on the weighted calibration code CALw. The DQS skew compensator 500 may output a calibrated data strobe signal DQSc. The calibrated data strobe signal DQSc may include calibrated signals of the first strobe signal DQS1, the second strobe signal DQS2, the third strobe signal DQS3, and the fourth strobe signal DQS4. Therefore, when Figure 2 The data conflict occurs when the phase difference between the data selection signals of the first core die to the third core die 1220, 1230 and 1240 deviates from the specified phase difference. Figure 2 The skew among the data select signals of the first core die to the third core die 1220, 1230 and 1240 is shown.

[0097] According to an example embodiment, the transmitter (TX) circuit 600 may be configured to receive a Figure 3 The memory cell array 1221 receives input data Din and outputs a transmitter output signal TXout based on a calibrated data select signal DQSc. The input data Din may include first input data D1, second input data D2, third input data D3, and fourth input data D4. The transmitter circuit 600 may sample the input data Din based on the calibrated data select signal DQSc. For example, the transmitter circuit 600 may sample the first input data D1 based on a calibrated signal of the first select signal DQS1, may sample the second input data D2 based on a calibrated signal of the second select signal DQS2, may sample the third input data D3 based on a calibrated signal of the third select signal DQS3, and may sample the fourth input data signal D4 based on a calibrated signal of the fourth select signal DQS4. The transmitter output signal TXout may be transmitted to the buffer die 1210 through the TSV.

[0098] Fig.14 is a diagram showing a method according to an example embodiment Fig.13 FIG. 6 is a diagram of an example of a transmitter (TX) circuit 600 . Fig.13 and Fig.14 , the transmitter circuit 600 may include a multiplexer (MUX) 610 , an adaptive equalizer (EQ) 620 , an AEQ control decoder 630 , and an output driver 640 . Fig.15is a diagram showing a method according to an example embodiment Fig.14 Schematic diagram of an example of a multiplexer (MUX) 610 . Fig.16 is a diagram showing a method according to an example embodiment Fig.14 A diagram of an example of an adaptive equalizer (EQ).

[0099] According to an example embodiment, the multiplexer 610 may sample the input data Din and transmit the output data Dout based on the calibrated data strobe signal DQSc. Fig.15 , the multiplexer 610 may include a first multiplexer 611, a second multiplexer 612, and a third multiplexer 613. The first multiplexer 611 may sample the first data D1 and the second data D2 based on the first calibration selection signal DQSc1 and the third calibration selection signal DQSc3, and may output the first intermediate data D12. The second multiplexer 612 may sample the third data D3 and the fourth data D4 based on the first calibration selection signal DQSc1 and the third calibration selection signal DQSc3, and may output the second intermediate data D34. The third multiplexer 613 may sample the first intermediate data D12 and the second intermediate data D34 based on the second calibration selection signal DQSc2 and the fourth calibration selection signal DQSc4, and may output the output data Dout. The output data Dout may be serialized data of the first to fourth data D1, D2, D3, and D4.

[0100] According to an example embodiment, the adaptive equalizer (EQ) 620 may boost the voltage level of the output data Dout and transmit the boosted output data Dout to the output driver 640. The AEQ control decoder 630 may convert the weighted calibration code CALw into an equalization code EQCD and provide the equalization code EQCD to the adaptive equalizer 620. The adaptive equalizer 620 may adaptively boost the voltage level of the output data Dout based on the equalization code EQCD.

[0101] As an example, refer to Fig.16 , the adaptive equalizer 620 may include a first N-type transistor MN1, a second N-type transistor MN2, a third N-type transistor MN3, a first P-type transistor MP1, a second P-type transistor MP2, a third P-type transistor MP3, a pre-charge capacitor Cpre, a booster capacitor Cb, an inverter INV and an adaptive capacitor (CAP) 621.

[0102] The adaptive equalizer 620 may generate a boost pull-up signal OUTb and a hold pull-up signal OUTh. The boost pull-up signal OUTb may pull up the transmitter output signal TXout of the output driver 640 to the power supply voltage VDD of the output driver 640. When the level of the boost pull-up signal OUTb is fixed within a specified time and leakage current occurs, the hold pull-up signal OUTh may have the same polarity as the boost pull-up signal OUTb. The hold pull-up signal OUTh may be sent to the output driver 640 to maintain the transmitter output signal TXout. The adaptive equalizer 620 may receive an input signal IN (e.g., Fig.14 The output data Dout of the output signal is obtained, and a boosted pull-up signal OUTb and a held pull-up signal OUTh are generated based on the power supply voltage VDD.

[0103] The adaptive equalizer 620 may have a precharge state and a booster state. When the power supply voltage VDD is input as the input signal IN, the adaptive equalizer 620 may be in a precharge state. The input signal IN may pass through the inverter INV, and the ground voltage VSS may be applied to the first node N1. A voltage lower than the voltage of the first node N1 may be applied to the second node N2 by the voltage of the precharge capacitor Cpre. The second N-type transistor MN2 may be turned on by the input signal IN, and a voltage identical to the voltage of the second node N2 may be applied to the hold pull-up signal OUTh. Since a voltage lower than the ground voltage VSS is applied to the second node N2, the second P-type transistor MP2 may be turned on, and the power supply voltage VDD may be applied to the third node N3. Due to the input signal IN, the third N-type transistor MN3 may be turned on, and the ground voltage VSS may be applied to the boost pull-up signal OUTb.

[0104] When the ground voltage VSS is input as the input signal IN, the adaptive equalizer 620 can be in a booster state. The input signal IN can be applied to the first node N1 by the inverter INV, and then the power supply voltage VDD can be applied to the first node N1. The first N-type transistor MN1 can be turned on by the first node N1, and the ground voltage VSS can be applied to the second node N2. The first P-type transistor MP1 can be turned on by the input signal IN, and the power supply voltage VDD can be applied to the pull-up signal OUTh. A voltage higher than the power supply voltage VDD by the voltage value of the booster capacitor Cb can be applied to the third node N3. The third P-type transistor MP3 can be turned on by the input signal IN, and a voltage identical to the voltage of the third node N3 can be applied to the boost pull-up signal OUTb.

[0105] Therefore, by adding the adaptive equalizer 620, when the power supply voltage VDD is input as the input signal IN, the adaptive equalizer 620 can be in a precharge state, and the boost pull-up signal OUTb can be set to the ground voltage VSS, and the hold pull-up signal OUTh can have a value lower than the ground voltage VSS. When the ground voltage VSS is input as the input signal IN, the adaptive equalizer 620 can be in a booster state, and the boost pull-up signal OUTb can be set to a voltage higher than the power supply voltage VDD, and the hold pull-up signal OUTh can have the power supply voltage VDD. As a result, the amplitudes of the two pull-up signals (boost pull-up signal OUTb and hold pull-up signal OUTh) can both have values ​​greater than the amplitude of the input signal IN. Therefore, by adding the adaptive equalizer 620, the transmitter circuit 600 can compensate for the reduction in the slew rate of the output driver 640 caused by the low power supply voltage.

[0106] In some example embodiments, the adaptive equalizer 620 may include an adaptive capacitor (CAP) 621 connected between the first node N1 and the third node N3. The adaptive capacitor 621 may be connected in parallel with the booster capacitor Cb. The adaptive capacitor 621 may change its capacitance based on the equalization code EQCD. The adaptive equalizer 620 may adaptively adjust the boosting strength of the output data Dout by adjusting the capacitance of the adaptive capacitor 621.

[0107] Fig.17 is a diagram showing a method according to an example embodiment Fig.16 As an example, refer to Fig.17 , the adaptive capacitor (CAP) 621 may include a transmission gate 6211 and a MOS capacitor 6212. The transmission gate 6211 may be turned on by a specified amount based on the equalization code EQCD. The capacitance of the MOS capacitor 6212 may be determined based on the magnitude of the conduction of the transmission gate 6211. The AEQ control decoder 630 may convert a 3-bit weighted calibration code CALw (e.g., 000, 100, 111) into a 4-bit equalization code EQCD (e.g., 0000, 1000, 1111) to be applied to the transmission gate 6211.

[0108] Fig.18 is a flow chart illustrating a method of compensating for a skew of a data strobe signal of a memory device according to example embodiments. Figures 2 to 18, the memory device 1200 can generate a calibration code (e.g., a weighted calibration code CALw) for the data selection signal of each of the first to third core dies 1220, 1230, and 1240 in the buffer die 1210, and can compensate for the skew of the data selection signal by applying the generated calibration code to each of the first to third core dies 1220, 1230, and 1240.

[0109] According to example embodiments, in operation S110, the memory device 1200 may transmit memory block signals from the plurality of core dies to the buffer die. For example, the memory device 1200 may transmit memory block signals (e.g., first memory block signal RK1, second memory block signal RK2, and third memory block signal RK3) from the plurality of core dies (e.g., the first core die to the third core dies 1220, 1230, and 1240) to the buffer die 1210 through TSVs. For example, a plurality of through-holes may be formed in each of the buffer die 1210 and the plurality of core dies 1220, 1230, and 1240, and the insides of the through-holes may be filled with TSVs, respectively.

[0110] Therefore, data can be easily transferred between the buffer die 1210 and the plurality of core dies through TSV. The memory device 1200 (e.g., a high bandwidth memory) can not only achieve high-speed data transfer through TSV, but also reduce power consumption. However, due to the increase in the data rate at the data input / output pin, when the phase difference between the data selection signals DQS of the plurality of core dies exceeds the specified phase difference, data collision may occur.

[0111] According to an example embodiment, in operation S120, the memory device 1200 may detect a sequence of storage block signals. For example, the memory device 1200 may detect a sequence according to a phase of the storage block signal. For example, the sequence detection circuit 110 of the DQS calibration circuit 100 may compare the phases of the first storage block signal RK1, the second storage block signal RK2, and the third storage block signal RK3, and may generate a storage block selection signal RKSEL based on the sequence of the first storage block signal RK1, the second storage block signal RK2, and the third storage block signal RK3. The multiplexer 101 of the DQS calibration circuit 100 may output a storage block signal SRK selected from the first storage block signal RK1, the second storage block signal RK2, and the third storage block signal RK3 in a fast phase sequence based on the storage block selection signal RKSEL.

[0112] According to an example embodiment, in operation S130, the memory device 1200 may detect the delay of the memory block signal. For example, the memory device 1200 may detect the delay of each of the memory block signals. For example, the delay line circuit 120 of the DQS calibration circuit 100 may receive the reference selection signal DQSref and delay the reference selection signal DQSref by a specified amount. The delay line circuit 120 may adjust the delay amount based on the count value CNT. The replica delay line circuit 130 of the DQS calibration circuit 100 may delay the selected memory block signal SRK by a specified amount.

[0113] The switch-mode phase detector 140 of the DQS calibration circuit 100 can compare the phase of the signal output by the delay line circuit 120 with the phase of the signal output by the replica delay line circuit 130, and can output a phase detection signal PDout according to the comparison result. The calibration control circuit 150 of the DQS calibration circuit 100 can generate a count control signal CTcon based on the phase detection signal PDout.

[0114] The delay detection circuit 160 of the DQS calibration circuit 100 may output a count value CNT and / or a delay LAT based on the count control signal CTcon. For example, when the count control signal CTcon is at a first level, the delay detection circuit 160 may increase the count value CNT by a specified amount (e.g., 1). When the count control signal CTcon is at a second level, the delay detection circuit 160 may store and output the delay LAT. The DQS calibration circuit 100 may store and output the delay LAT of each of the first storage block signal RK1, the second storage block signal RK2, and the third storage block signal RK3.

[0115] According to an example embodiment, in operation S140, the memory device 1200 may generate a weighted calibration code CALw based on a delay of a memory block signal and a threshold voltage (Vth) of the buffer die 1210. For example, the memory device 1200 may generate a weighted calibration code CALw based on a delay of each of the memory block signals and a threshold voltage (Vth) of the buffer die 1210. For example, the threshold voltage detection circuit 210 of the coefficient determination circuit 200 may generate a threshold voltage code VTHCD of the buffer die 1210 based on the reference selection signal DQSref. The threshold voltage detection circuit 210 may generate the threshold voltage code VTHCD so that as the count value CNT of the delay line circuit 120 increases, the delay width may converge to a value when the average threshold voltage of the transistors included in the buffer die 1210 is the reference voltage.

[0116] Each of the plurality of weight control circuits 220 of the coefficient determination circuit 200 may apply a weight according to the threshold voltage code VTHCD to the delay LAT corresponding to a corresponding one of the plurality of core dies 1220, 1230, and 1240 to output a weighted calibration code CALw corresponding to each of the first core die to the third core die 1220, 1230, and 1240. The threshold voltage code decoder 221 of each of the plurality of weight control circuits 220 may decode the threshold voltage code VTHCD and output a weight selection signal WTSEL. The multiple selector 222 of each of the plurality of weight control circuits 220 may output a weight WT based on the weight selection signal WTSEL.

[0117] According to an example embodiment, in operation S150, the memory device 1200 may compensate for DQS skew based on a weighted calibration code CALw in each core die. For example, the memory device 1200 may compensate for DQS skew of a data strobe signal in each of the first core die to the third core die 1220, 1230, and 1240 based on the weighted calibration code CALw. For example, the calibration code register 400 of each of the first core die to the third core die 1220, 1230, and 1240 may receive and store the weighted calibration code CALw from the coefficient determination circuit 200 of the buffer die 1210 through the TSV.

[0118] The calibration code register 400 may transmit the weighted calibration code CALw to the DQS skew compensator 500. The DQS skew compensator 500 of each of the first to third core dies 1220, 1230, and 1240 may receive the quadrature data strobe signal DQSq from the DQS generation circuit 300 of the buffer die 1210 through the TSV. The DQS skew compensator 500 may calibrate the quadrature data strobe signal DQSq based on the weighted calibration code CALw and transmit the calibrated data strobe signal DQSc to the transmitter circuit 600.

[0119] According to an example embodiment, in operation S160, the memory device 1200 may perform adaptive equalization of the transmitter circuit 600 based on the weighted calibration code CALw in each of the first to third core dies 1220, 1230, and 1240. For example, the multiplexer 610 of the transmitter circuit 600 may sample the input data Din, and may output the output data Dout based on the calibrated data strobe signal DQSc. The adaptive equalizer 620 of the transmitter circuit 600 may boost the voltage level of the output data Dout and transmit the boosted output data Dout to the output driver 640 of the transmitter circuit 600. The AEQ control decoder 630 of the transmitter circuit 600 may convert the weighted calibration code CALw into an equalization code EQCD. The adaptive equalizer 620 may adaptively boost the voltage level of the output data Dout based on the equalization code EQCD. The adaptive equalizer 620 may include an adaptive capacitor 621, and may adaptively adjust the boosting strength of the output data Dout by adjusting the capacitance of the adaptive capacitor 621.

[0120] Fig.19 is a diagram illustrating an example of performing error detection of a quadrature data strobe signal in a DQS calibration circuit according to example embodiments. Fig.19 , the buffer die 1210 may include a DQS calibration circuit 100a, a coefficient determination circuit 200a, and a DQS generation circuit 300a. The DQS calibration circuit 100a, the coefficient determination circuit 200a, and the DQS generation circuit 300a are similar to Figure 4 The DQS calibration circuit 100, coefficient determination circuit 200, and DQS generation circuit 300 are respectively described in detail, and therefore the differences will be mainly described. The DQS calibration circuit 100a can be connected to the DQS calibration circuit 100a through TSV. Figure 2 Each of the multiple core dies receives a memory block signal (or a data strobe signal). The DQS calibration circuit 100a can calculate the delay LAT of each of the memory block signals (e.g., the first memory block signal RK1, the second memory block signal RK2, and the third memory block signal RK3) of the multiple core dies. The DQS generation circuit 300a can generate multiple data strobe signals (e.g., orthogonal data strobe signals DQSq) based on the first clock signal CK1 and the second clock signal CK2.

[0121] According to an example embodiment, the coefficient determination circuit 200a may detect the influence of the average threshold voltage of the transistors included in the buffer die 1210 based on the memory block signal, and apply the weight to the delay LAT of each core die detected by the DQS calibration circuit 100a. The threshold voltage detection circuit 210 may generate a threshold voltage code VTHCD of the buffer die 1210 based on the reference selection signal DQSref. The coefficient determination circuit 200 may apply the weight according to the threshold voltage code VTHCD to the delay LAT corresponding to each of the first core die to the third core die 1220, 1230, and 1240, and output a weighted calibration code CALw corresponding to each of the first core die to the third core die 1220, 1230, and 1240.

[0122] According to an example embodiment, the coefficient determination circuit 200a may send a threshold voltage code VTHCD to the DQS calibration circuit 100a. The DQS calibration circuit 100a may simplify the error detection operation of the quadrature data strobe signal based on the threshold voltage code VTHCD. The DQS calibration circuit 100a may send an error detection feedback signal QECout to the DQS generation circuit 300a. The DQS generation circuit 300a may generate an error-calibrated quadrature data strobe signal DQSq based on the error detection feedback signal QECout.

[0123] Fig. 20 is a diagram showing a method according to an example embodiment Fig.19 FIG. 1 is a diagram of an example of a DQS calibration circuit 100 a. Fig.19 and Fig. 20 , the DQS calibration circuit 100 may include a first multiplexer 101a, a second multiplexer 102, a third multiplexer 103, a fourth multiplexer 104, a sequence detection circuit 110, a first delay line (DL) circuit 121, a second delay line (DL) circuit 122, a replica delay line (DL) circuit 130, a switch-mode phase detector (BBPD) 140, a calibration control circuit 150a, a delay detection circuit 160, and a QEC counter 170. The first multiplexer 101a, the first delay line (DL) circuit 121, the sequence detection circuit 110, the replica delay line (DL) circuit 130, the BBPD 140, and the delay detection circuit 160 are similar to Figure 6 The multiplexer 101, delay line (DL) circuit 120, sequence detection circuit 110, replica delay line (DL) circuit 130, BBPD 140 and delay detection circuit 160 in the DQS calibration circuit 100a are shown in FIG. 1 , and thus the main differences will be described below. The DQS calibration circuit 100a can operate in a delay detection mode or an error detection mode of a data strobe signal based on a mode selection signal MDSEL.

[0124] First, the DQS calibration circuit 100a may operate in a delay detection mode.

[0125] According to example embodiments, the sequence detection circuit 110 may detect the order of memory block signals (e.g., the first memory block signal RK1, the second memory block signal RK2, and the third memory block signal RK3) of the plurality of core dies. For example, the sequence detection circuit 110 may compare the phases of the first memory block signal RK1, the second memory block signal RK2, and the third memory block signal RK3 to generate a memory block selection signal RKSEL based on the order of the first memory block signal RK1, the second memory block signal RK2, and the third memory block signal RK3.

[0126] According to an example embodiment, the first multiplexer 101a may output a storage block signal SRK selected in order of a fast phase among the first storage block signal RK1, the second storage block signal RK2, and the third storage block signal RK3 based on the storage block selection signal RKSEL. For example, the storage block selection signal RKSEL may include 2 bits. When the storage block selection signal RKSEL is "01", the first multiplexer 101a may output a storage block signal with the fastest phase. When the storage block selection signal RKSEL is "10", the first multiplexer 101a may output a storage block signal with an intermediate phase. When the storage block selection signal RKSEL is "11", the first multiplexer 101a may output a storage block signal with the slowest phase.

[0127] According to an example embodiment, the fourth multiplexer 104 may output the reference selection signal DQSref as the first mode signal MD1 based on the mode selection signal MDSEL. The first delay line circuit 121 may receive the first mode signal MD1 and delay the first mode signal MD1 by a specified amount. The first delay line circuit 121 may adjust the delay amount based on the count value CNT. As the count value CNT increases, the first delay line circuit 121 may delay the first mode signal MD1 more. As an example, in some example embodiments, the first mode signal MD1 may be set to be Figure 4 The DQS generation circuit 300 generates one of the first selection signal DQS1, the second selection signal DQS2, the third selection signal DQS3, and the fourth selection signal DQS4. In some example embodiments, a complementary signal of the first selection signal DQS1 may be set as the first mode signal MD1.

[0128] According to example embodiments, the second multiplexer 102 may output the selected memory block signal SRK as the second mode signal MD2 based on the mode selection signal MDSEL. The replica delay line circuit 130 may have a delay amount equal to the sum of the first delay amount of the first delay line circuit 121 and the second delay amount of the second delay line circuit 122. The replica delay line circuit 130 may delay the selected memory block signal SRK by a specified amount.

[0129] According to example embodiments, the switch-mode phase detector (BBPD) 140 may compare the phase of the signal output by the second delay line circuit 122 and the phase of the signal output by the replica delay line circuit 130, and output a phase detection signal PDout according to the comparison result. For example, when the phase of the signal output by the second delay line circuit 122 is faster than the phase of the signal output by the replica delay line circuit 130, the phase detection signal PDout may be at a first level (e.g., a low level or logic 0). When the phase of the signal output by the second delay line circuit 122 is slower than or equal to the phase of the signal output by the replica delay line circuit 130, the phase detection signal PDout may be at a second level (e.g., a high level or logic 1).

[0130] According to example embodiments, the calibration control circuit 150a may generate a first count control signal CTcon1 based on the phase detection signal PDout. For example, when the phase detection signal PDout is at a first level, the first count control signal CTcon1 may be at a first level. When the phase detection signal PDout is at a second level, the first count control signal CTcon1 may be at a second level.

[0131] According to example embodiments, the delay detection circuit 160 may output a count value CNT and / or a delay LAT based on the first count control signal CTcon1. For example, when the first count control signal CTcon1 is at a first level, the delay detection circuit 160 may increase the count value CNT by a specified amount (e.g., 1). When the first count control signal CTcon1 is at a second level, the delay detection circuit 160 may store and output the delay LAT.

[0132] According to an example embodiment, the DQS calibration circuit 100a may repeatedly perform the above-mentioned delay detection operation for each of the first memory block signal RK1, the second memory block signal RK2, and the third memory block signal RK3. The DQS calibration circuit 100 may send the delay LAT from the first core die to each of the third core dies 1220, 1230, and 1240 measured by the delay detection operation to the coefficient determination circuit 200a.

[0133] Second, the DQS calibration circuit 100a may operate in an error detection mode of the data strobe signal.

[0134] According to example embodiments, the third multiplexer 103 may select two of the first selection signal DQS1, the second selection signal DQS2, the third selection signal DQS3, and the fourth selection signal DQS4 based on the multiplexer selection signal MXSEL, and output the selected two selection signals as the first selection selection signal SDQS1 and the second selection selection signal SDQS2. The fourth multiplexer 104 may output the first selection selection signal SDQS1 as the first mode signal MD1 based on the mode selection signal MDSEL. The second multiplexer 102 may output the second selection selection signal SDQS2 as the second mode signal MD2 based on the mode selection signal MDSEL.

[0135] According to example embodiments, the first delay line (DL) circuit 121 may receive the first mode signal MD1 and delay the first mode signal MD1 by a specified amount. At this time, the count value CNT may be fixed to “0”. The delay amount of the second delay line circuit 122 may be determined based on the error check signal TQ (see below).

[0136] According to example embodiments, the replica delay line (DL) circuit 130 may have a delay amount equal to a sum of a first delay amount of the first delay line circuit 121 and a second delay amount of the second delay line circuit 122. The replica delay line circuit 130 may delay the second mode signal MD2 by a designated amount.

[0137] According to an example embodiment, the switch-mode phase detector (BBPD) 140 may compare the phase of the signal output by the second delay line circuit 122 and the phase of the signal output by the replica delay line circuit 130, and may output a phase detection signal PDout according to the comparison result. As an example, when the phase of the signal output by the second delay line circuit 122 is faster than the phase of the signal output by the replica delay line circuit 130, the phase detection signal PDout may be at a first level (e.g., a low level or logic 0). When the phase of the signal output by the second delay line circuit 122 is slower than or equal to the phase of the signal output by the replica delay line circuit 130, the phase detection signal PDout may be at a second level (e.g., a high level or logic 1).

[0138] According to example embodiments, the calibration control circuit 150a may generate a second count control signal CTcon2 based on the phase detection signal PDout. For example, when the phase detection signal PDout is at a first level, the second count control signal CTcon2 may be at a first level. When the phase detection signal PDout is at a second level, the second count control signal CTcon2 may be at a second level.

[0139] According to an example embodiment, the QEC counter 170 may receive the second count control signal CTcon2 and generate an error check signal TQ based on the second count control signal CTcon2. As an example, when the second count control signal CTcon2 is at a first level, the QEC counter 170 may increase the error check signal TQ. When the second count control signal CTcon2 is at a second level, the QEC counter 170 may output an error detection feedback signal QECout. The QEC counter 170 may adjust the error check signal TQ based on the threshold voltage code VTHCD and simplify the error detection operation of the data strobe signal.

[0140] According to various example embodiments, a buffer die may generate a skew compensation code for a data strobe signal used in each of a plurality of core dies.

[0141] According to various example embodiments, characteristics caused by a change in a threshold voltage of a buffer die may be reflected in a skew compensation code.

[0142] Although various example embodiments have been described with reference to the accompanying drawings, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims.

Claims

1. A memory device, comprising: a plurality of core dies including an array of memory cells; as well as a buffer die electrically connected to the plurality of core dies through at least one through silicon via TSV, Wherein, the buffer die comprises: A DQS generation circuit configured to receive an external clock signal from an external device and generate a plurality of data strobe signals based on the external clock signal for communicating data with the plurality of core dies; a DQS calibration circuit configured to detect a delay of each of a plurality of memory block signals received from the plurality of core dies based on the plurality of data strobe signals, respectively; and A coefficient determination circuit is configured to detect a threshold voltage code of the buffer die, apply a weight to the delay of each of the multiple storage block signals based on the threshold voltage code to generate a weighted calibration code for each of the multiple storage block signals, and send the weighted calibration code to a corresponding core die among the multiple core dies.

2. The memory device according to claim 1, wherein: Each of the plurality of core dies includes a DQS skew compensator configured to calibrate the plurality of data strobe signals based on the weighted calibration code to generate a plurality of calibrated data strobe signals and transmit the plurality of calibrated data strobe signals to a transmitter circuit.

3. The memory device according to claim 2, wherein: The transmitter circuit comprises: a multiplexer configured to convert data read from each of the memory cell arrays into output data based on the plurality of calibrated data strobe signals; an adaptive equalizer configured to adaptively boost the level of the output data based on an equalization code; and The AEQ control decoder is configured to decode the weighted calibration code to generate the equalization code and output the equalization code to the adaptive equalizer.

4. The memory device according to claim 1, wherein: The DQS calibration circuit comprises: a sequence detection circuit configured to detect an order of the plurality of storage block signals based on phases of the plurality of storage block signals and output a storage block selection signal based on the order; a multiplexer configured to output a selected memory block signal, the selected memory block signal being selected from among the plurality of memory block signals based on the memory block selection signal; a delay line circuit configured to delay a reference strobe signal based on the count value, the reference strobe signal being set to one of the plurality of data strobe signals; a replica delay line circuit configured to delay the selected memory block signal by a delay amount equal to a default delay amount of the delay line circuit; a phase detector configured to detect a phase difference between a first output signal of the delay line circuit and a second output signal of the replica delay line circuit, and output a phase detection signal based on the phase difference; a calibration control circuit configured to output a count control signal based on the phase detection signal; and The delay detection circuit is configured to output the count value or the delay of the selected storage block signal based on the count control signal.

5. The memory device according to claim 4, wherein: The sequence detection circuit comprises: a plurality of flip-flops, an input terminal of each of the plurality of flip-flops receiving a corresponding one of the plurality of storage block signals, and a clock terminal of each of the plurality of flip-flops receiving another corresponding one of the plurality of storage block signals; and The sequence logic is configured to generate the memory block selection signal based on the output values ​​of the plurality of flip-flops.

6. The memory device according to claim 4, wherein: The time delay detection circuit comprises: a delay counter configured to output the count value when the count control signal is at a first level, and to output the delay of the selected memory block signal when the count control signal is at a second level; and A delay register is configured to store the delay of the selected storage block signal and send the delay of the selected storage block signal to the coefficient determination circuit.

7. The memory device according to claim 1, wherein: The coefficient determination circuit comprises: A threshold voltage detection circuit is configured to generate the threshold voltage code based on one of the plurality of data strobe signals, the threshold voltage code corresponding to a difference between an average threshold voltage of transistors included in the buffer die and a reference threshold voltage.

8. The memory device according to claim 7, wherein: The coefficient determination circuit comprises: A plurality of weight control circuits are each configured to apply the weight to the delay of a corresponding one of the plurality of storage block signals based on the threshold voltage code to generate the weighted calibration code for the corresponding one of the plurality of storage block signals, and the plurality of weight control circuits are configured to send the weighted calibration code corresponding to the plurality of core dies to the plurality of core dies through the at least one TSV.

9. The memory device according to claim 8, wherein: Each of the plurality of weight control circuits comprises: a threshold voltage code decoder configured to decode the threshold voltage code and output a weight selection signal; and A multiple selector is configured to select one of a plurality of weights based on the weight selection signal.

10. The memory device of claim 1, wherein: The plurality of data strobe signals include: A first strobe signal; a second strobe signal configured to have a phase difference of 90 degrees with the first strobe signal; a third selection signal configured to have a phase difference of 90 degrees with the second selection signal; and The fourth selection signal is configured to have a phase difference of 90 degrees with the third selection signal.

11. A skew compensation method for a memory device, the skew compensation method comprising: transmitting a plurality of memory block signals from a plurality of core dies to a buffer die through at least one through silicon via (TSV), the plurality of memory block signals corresponding to a plurality of data strobe signals generated in the buffer die based on an external clock signal received from an external device; detecting an order of the plurality of storage block signals based on phases of the plurality of storage block signals; detecting a delay of each of the plurality of storage block signals; generating a weighted calibration code for each of the plurality of core dies based on a threshold voltage of the buffer die and the delay of each of the plurality of memory block signals; as well as Skew of the plurality of memory block signals of the plurality of core dies is compensated based on the weighted calibration code.

12. The skew compensation method according to claim 11, further comprising: Adaptive equalization is performed on each of the plurality of core dies based on the weighted calibration code.

13. The skew compensation method according to claim 12, further comprising: calibrating the plurality of data strobe signals based on the weighted calibration code to generate a plurality of calibrated data strobe signals; converting data read from each of the plurality of core dies into output data based on the plurality of calibrated data strobe signals; Adaptively boosting the level of the output data based on the equalization code; as well as The weighted calibration code is decoded and the equalized code is output.

14. The skew compensation method according to claim 11, wherein: Detecting the time delay of each of the plurality of storage block signals comprises: delaying a reference strobe signal based on the count value to generate a first output signal, the reference strobe signal being one of the plurality of data strobe signals; delaying a selected memory block signal by a delay amount that is the same as a default delay amount of the reference strobe signal to generate a second output signal, the selected memory block signal being selected from among the plurality of memory block signals according to the determined order; detecting a phase difference between the first output signal and the second output signal, and outputting a phase detection signal based on the phase difference; outputting a count control signal based on the phase detection signal; and The count value or the selected memory block signal is output based on a delay of the count control signal.

15. The skew compensation method according to claim 14, wherein: The delay of outputting the count value or the selected storage block signal includes: When the counting control signal is at a first level, outputting the counting value; When the count control signal is at a second level, outputting the delay of the selected memory block signal; and The time delay of the selected memory block signal is stored.

16. The skew compensation method according to claim 11, wherein: Generating the weighted calibration code for each of the plurality of core dies comprises: generating a threshold voltage code based on one of the plurality of data strobe signals, the threshold voltage code corresponding to a difference between an average threshold voltage of transistors included in the buffer die and a reference threshold voltage; and The weighted calibration codes respectively corresponding to the plurality of core dies are generated by applying a weight to the time delay of each of the plurality of memory block signals based on the threshold voltage code.

17. The skew compensation method according to claim 16, wherein: Generating the weighted calibration codes corresponding to the plurality of core dies respectively comprises: decoding the threshold voltage code and outputting a weight selection signal; and One of a plurality of weights is selected based on the weight selection signal.

18. The skew compensation method according to claim 16, further comprising: The skew of the plurality of storage block signals is compensated by: sending the weighted calibration code to the plurality of core dies through the at least one TSV; as well as The plurality of data strobe signals in the plurality of core dies are calibrated based on the weighted calibration code.

19. A memory device comprising: a plurality of core dies including an array of memory cells; as well as a buffer die electrically connected to the plurality of core dies through at least one through silicon via TSV, Wherein, the buffer die comprises: A DQS generation circuit configured to receive an external clock signal from an external device and generate a plurality of data strobe signals based on the external clock signal for communicating data with the plurality of core dies; a DQS calibration circuit configured to detect a delay of each of a plurality of memory block signals received from the plurality of core dies based on the plurality of data strobe signals, respectively; and a coefficient determination circuit configured to detect a threshold voltage code of the buffer die, apply a weight to the delay of each of the plurality of memory block signals based on the threshold voltage code to generate a weighted calibration code for each of the plurality of memory block signals, and send the weighted calibration code to the plurality of core dies, wherein the DQS calibration circuit is configured to generate an error detection feedback signal based on the threshold voltage code, and The DQS generation circuit is configured to correct timing errors of the plurality of data strobe signals based on the error detection feedback signal.

20. The memory device of claim 19, wherein: The DQS calibration circuit comprises: a sequence detection circuit configured to detect a sequence of the plurality of memory block signals based on phases of the plurality of memory block signals and output a memory block selection signal; a first multiplexer configured to output a selected memory block signal, the selected memory block signal being selected from among the plurality of memory block signals based on the memory block selection signal; a second multiplexer configured to output a first selection strobe signal and a second selection strobe signal selected from among the plurality of data strobe signals based on a multiplexer selection signal; a third multiplexer configured to output one of the first selection strobe signal and the reference strobe signal as a first mode signal based on a mode selection signal; a fourth multiplexer configured to output one of the second selection strobe signal and the selected memory block signal as a second mode signal based on the mode selection signal; a first delay line circuit configured to delay the first mode signal by a first delay amount based on a count value; a second delay line circuit configured to delay an output signal of the first delay line circuit by a second delay amount based on an error check signal; a replica delay line circuit configured to delay the second pattern signal by a delay amount corresponding to a delay amount of a combination of the first delay amount and the second delay amount; a phase detector configured to detect a phase difference between a first output signal of the second delay line circuit and a second output signal of the replica delay line circuit, and output a phase detection signal based on the phase difference; a calibration control circuit configured to generate the multiplexer selection signal, output the mode selection signal according to an operation mode, and output a first count control signal and a second count control signal based on the phase detection signal; a delay detection circuit configured to receive the first count control signal and output the count value or the delay of the selected memory block signal based on the first count control signal; and An error detection counter is configured to generate the error check signal based on the second count control signal and send the error detection feedback signal to the DQS generation circuit.

Images