Memory device and operating method for memory device
By performing the second erase operation on at least part of the memory cell string in the memory device, the problem of large differences in the charge loss of the memory cell is solved, the accuracy of data reading and error correction operations of the memory device is improved, and high-performance and large-capacity storage effect is achieved.
Patent Information
- Application Number
- CN202410014176.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-26
- Filing Date
- 2024-01-04
- Publication Date
- 2025-03-28
AI Technical Summary
The charge loss of multiple memory cells in the memory device varies greatly, which affects the accuracy of programming error correction operations and read operations, especially in multi-stage memory cell applications.
After the programming operation, a second erase operation is performed on at least a portion of the memory cells of the target memory cell string, and the charge loss of the memory cell is adjusted using the second erase voltage (below the first erase voltage).
The difference between charge losses of multiple memory cells is reduced, and the accuracy of error correction operations of data reading operations and programming is improved, thereby providing a high-performance, large-capacity storage medium.
Smart Images
Figure CN119724294A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a memory device and an operating method for the memory device, and more particularly to a memory device and an operating method for reducing a difference between charge losses of memory cells in the memory device. Background Art
[0002] Generally speaking, charge retention or data retention plays an important role in product identification of memory devices. Different charge losses of multiple memory cells of a memory device may affect the error-correcting operation or reading operation of programming. When the charge losses of the multiple memory cells are different, the read windows of the multiple memory cells of the memory device will be different. In particular, for the application of multi-level memory cells (e.g., triple-level cells, TLC), errors in data reading operations or programming error correction operations may occur. Therefore, how to reduce the differences between the charge losses of memory cells is one of the research focuses of those skilled in the art. Summary of the invention
[0003] The present disclosure provides a memory device and an operating method for reducing a difference between charge losses of memory cells in the memory device.
[0004] The memory device includes a memory array and a control circuit. The memory array includes a plurality of memory blocks. The control circuit is coupled to the memory array. The control circuit provides a first erase voltage to perform a first erase operation on a plurality of target memory cell strings of a selected memory block among the plurality of memory blocks, performs a programming operation on the plurality of target memory cell strings after the first erase operation, and provides a second erase voltage after the programming operation to perform a second erase operation on at least a portion of memory cells of each of the plurality of target memory cell strings. The second erase voltage is less than the first erase voltage.
[0005] The operating method is used for a memory device. The memory device includes a memory array. The memory array includes a plurality of memory blocks. The operating method includes: providing a first erase voltage to perform a first erase operation on a plurality of target memory cell strings of a selected memory block among the plurality of memory blocks; performing a programming operation on the plurality of target memory cell strings after the first erase operation; and providing a second erase voltage after the programming operation to perform a second erase operation on at least a portion of memory cells of each of the plurality of target memory cell strings, wherein the second erase voltage is less than the first erase voltage.
[0006] Based on the above, the memory device performs a second erase operation on at least a portion of the memory cells of each of the plurality of target memory cell strings after the programming operation. The second erase operation adjusts the charge loss of the memory cells after the programming operation. The difference between the charge losses of the plurality of memory cells is reduced. In this way, the difference between the charge losses of the plurality of memory cells can be reduced.
[0007] In order to make the above content clearer and easier to understand, several embodiments are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 is a schematic diagram of a memory device according to an embodiment of the present disclosure.
[0009] Figure 2 is a schematic diagram of a memory block according to an embodiment of the present disclosure.
[0010] Figure 3 is a schematic diagram of waveforms of a first erasing voltage and a second erasing voltage according to an embodiment of the present disclosure.
[0011] Figure 4 is a schematic diagram of waveforms of word line signals and a second erase voltage corresponding to the remaining memory cells according to an embodiment of the present disclosure.
[0012] Figure 5 is a schematic diagram of a memory block according to an embodiment of the present disclosure.
[0013] Figure 6 is a schematic diagram of charge distribution according to an embodiment of the present disclosure.
[0014] Figure 7 is a schematic diagram of charge distribution and threshold voltage corresponding to different second erase voltages according to an embodiment of the present disclosure.
[0015] Figure 8 is a schematic diagram of a target storage cell string according to an embodiment of the present disclosure.
[0016] Fig. 9 is a schematic diagram of a target storage cell string according to an embodiment of the present disclosure.
[0017] Fig.10 is a schematic diagram of a target storage cell string according to an embodiment of the present disclosure.
[0018] Fig.11 is a flow chart of an operating method shown according to an embodiment of the present disclosure.
[0019] Description of Reference Numerals
[0020] 100: Memory device
[0021] 110: Memory array
[0022] 120: Control circuit
[0023] BL1~BLn: bit lines
[0024] CD1, CD2, CD2', CD3, CD4, CD5: Charge distribution
[0025] CSL: Shared Source Line
[0026] DWL1~DWL3: Virtual word lines
[0027] M0~M95: storage unit
[0028] MBK: Memory Block
[0029] MBK_T: Select memory block
[0030] MCG1: First storage unit group
[0031] MCG2: Second storage unit group
[0032] MD1~MD3: Virtual unit
[0033] NB: Threshold charge number
[0034] P1, P2: intersection points
[0035] RDG: Determination voltage
[0036] S100: How to operate
[0037] S110~S130: Steps
[0038] SS1, SS2: selection signal
[0039] ST1~STp: storage cell string
[0040] STT1~STT4: target storage unit string
[0041] TC1~TCp: Source selection transistor
[0042] TS1~TSp: string selection transistor
[0043] V1: First erase voltage
[0044] V2: Second erase voltage
[0045] VCSL: Source Line Signal
[0046] VT1, VT2, VT3: Threshold voltage
[0047] VWL: word line signal
[0048] WL0~WL95、WLm:word line
[0049] WLG1: first word line group
[0050] WLG2: second word line group
[0051] X: First direction
[0052] Y: Second direction
[0053] Z: Third direction DETAILED DESCRIPTION
[0054] The present disclosure may be understood by reference to the following detailed description in conjunction with the accompanying drawings as described below. It should be noted that for the purpose of clear description and ease of understanding by the reader, the various drawings of the present disclosure illustrate a portion of an electronic device, and certain elements in the various drawings may not be drawn to scale. In addition, the number and size of each device shown in the drawings are merely illustrative and are not intended to limit the scope of the present disclosure.
[0055] Please refer to Figure 1 , Figure 1 1 is a schematic diagram of a memory device according to an embodiment of the present disclosure. In the present embodiment, the memory device 100 includes a memory array 110 and a control circuit 120. The memory array 110 includes a plurality of memory blocks MBK. For example, each memory block MBK may be a NAND flash memory block, but the present disclosure is not limited thereto.
[0056] In the present embodiment, the control circuit 120 is coupled to the memory array 110. The control circuit 120 provides a first erase voltage V1 to perform a first erase operation on target memory cell strings STT1-STT4 of a selected memory block MBK_T among a plurality of memory blocks MBK. For example, the control circuit 120 selects a selected memory block MBK_T among the memory blocks MBK in response to a command, and then performs a first erase operation on the target memory cell strings STT1-STT4 of the selected memory block MBK_T. The control circuit 120 performs a program operation on the target memory cell strings STT1-STT4 after the first erase operation.
[0057] In this embodiment, the control circuit 120 provides a second erase voltage V2 after the programming operation to perform a second erase operation on at least a portion of the memory cells of each of the plurality of target memory cell strings STT1 to STT4. The second erase voltage V2 is lower than the first erase voltage V1. In this embodiment, the "at least a portion of the memory cells" includes at least one memory cell.
[0058] It should be noted that after performing the programming operation, the memory device 100 performs a second erase operation on at least a portion of the memory cells of each of the multiple target memory cell strings STT1 to STT4 in the selected memory block MBK_T. The second erase operation can adjust the charge loss of the memory cells after the programming operation. The difference between the charge losses of the multiple memory cells can be reduced. In this way, the difference between the charge losses of the multiple memory cells can be reduced. In addition, for the application of triple-level cells (TLC), because the difference between the read windows can be reduced, the errors of data reading operations or programming error correction operations can also be reduced. In this way, the memory device 100 provides a high-performance, large-capacity storage medium.
[0059] In this embodiment, the at least a portion of the memory cells to which the second erase operation is performed may be determined by a verification operation or an error-correcting operation. Generally speaking, a verification operation or an error-correcting operation is performed during or after a programming operation. In this embodiment, the at least a portion of the memory cells to which the second erase operation is performed may be determined by selecting different regions and / or different layers in the memory block MBK_T.
[0060] For example, based on different regions, different layers and / or yields, a first portion of memory cells in the selected memory block MBK_T has a first charge loss. A second portion of memory cells in the selected memory block MBK_T has a second charge loss. The first charge loss is different from the second charge loss. The control circuit 120 performs a second erase operation on the second portion of memory cells. Therefore, the second charge loss is adjusted to the first charge loss.
[0061] Please also refer to Figure 1 , Figure 2 as well as Figure 3 , Figure 2 is a schematic diagram of a memory block according to an embodiment of the present disclosure. Figure 3Schematic diagram of the waveforms of the first erase voltage and the second erase voltage according to an embodiment of the present disclosure. In the present embodiment, the memory block MBK includes string selection transistors TS1-TS4, source selection transistors TC1-TC4 and memory cell strings ST1-ST4. The memory block MBK may be a 2D NAND flash memory block, but the present disclosure is not limited thereto. The first end of the string selection transistor TS1 is connected to the bit line BL1. The second end of the string selection transistor TS1 is connected to one end of the memory cell string ST1. The control end of the string selection transistor TS1 receives the selection signal SS1. The memory cell string ST1 includes memory cells M0-Mm connected in series. The control end of the memory cell M0 is connected to the word line WL0. The control end of the memory cell M1 is connected to the word line WL1, and so on. The first end of the source selection transistor TC1 is connected to the other end of the memory cell string ST1. The first end of the source selection transistor TC1 is connected to the shared source line CSL. The control end of the source selection transistor TC1 receives the selection signal SS2.
[0062] In other words, the string selection transistor TS1 , the source selection transistor TC1 , and the memory cell string ST1 are connected in series between the bit line BL1 and the common source line CSL.
[0063] Similarly, string selection transistor TS2, source selection transistor TC2, and memory cell string ST2 are connected in series between bit line BL2 and common source line CSL. String selection transistor TS3, source selection transistor TC3, and memory cell string ST3 are connected in series between bit line BL3 and common source line CSL. String selection transistor TS4, source selection transistor TC4, and memory cell string ST4 are connected in series between bit line BL4 and common source line CSL. String selection transistors TS1 to TS4 receive selection signal SS1. Source selection transistors TC1 to TC4 receive selection signal SS2. In addition, memory cell strings ST1 to ST4 are connected to word lines WL0 to WLm. Therefore, multiple memory cells corresponding to the same word line WL0 in memory cell strings ST1 to ST4 can be a memory page. Multiple memory cells corresponding to the same word line WL1 in memory cell strings ST1 to ST4 can be another memory page.
[0064] In the present embodiment, each of the memory cell strings ST1 ˜ ST4 may be a NAND flash memory cell string, but the present disclosure is not limited thereto.
[0065] In this embodiment, string selection transistors TS1-TS4 and source selection transistors TC1-TC4 are turned on. Figure 2 The memory block MBK in is selected. Therefore, the memory block MBK is the selected memory block MBK_T. Figure 2The memory cell strings ST1 to ST4 in are target memory cell strings STT1 to STT4, respectively. When performing the first erase operation, the control circuit 120 applies the first erase voltage V1 to the shared source line CSL. Therefore, when performing the first erase operation, the voltage of the shared source line signal VCSL provided to the shared source line CSL is substantially equal to the first erase voltage V1. In the present embodiment, when performing the first erase operation, the control circuit 120 applies the word line signal VWL having a voltage of substantially 0 to the word lines WL0 to WLm. When performing the first erase operation, the data of all memory cells of each memory cell string ST1 to ST4 are erased based on the first erase voltage V1.
[0066] When performing the second erase operation, the control circuit 120 applies the second erase voltage V2 to the shared source line CSL. When performing the second erase operation, the voltage of the shared source line signal VCSL is substantially equal to the second erase voltage V2. The control circuit 120 applies substantially zero voltage to the corresponding word lines of the at least a portion of the memory cells.
[0067] In some embodiments, when performing a first erase operation, the control circuit 120 applies a first erase voltage V1 to the bit lines BL1 ˜ BL4 . When performing a second erase operation, the control circuit 120 applies a second erase voltage V2 to the bit lines BL1 ˜ BL4 .
[0068] In some embodiments, when performing the first erase operation, the control circuit 120 applies the first erase voltage V1 to the bit lines BL1-BL4 and the shared source line CSL. When performing the second erase operation, the control circuit 120 applies the second erase voltage V2 to the bit lines BL1-BL4 and the shared source line CSL.
[0069] In the present embodiment, the second erase voltage V2 is lower than the first erase voltage V1. Therefore, the first erase operation is referred to as a "normal erase operation". The second erase operation is referred to as a "weak erase operation". For example, the difference between the second erase voltage V2 and the first erase voltage V1 is in the range of 7 to 13 volts. For example, the second erase voltage V2 is approximately 8 volts, but the present disclosure is not limited thereto. The first erase voltage V1 is approximately 20 volts, but the present disclosure is not limited thereto.
[0070] In addition, please also refer to Figure 1 , Figure 3 as well as Figure 4 , Figure 4It is a schematic diagram of the waveform of the word line signal corresponding to the remaining memory cells and the second erase voltage according to an embodiment of the present disclosure. In the second erase operation, the remaining memory cells are excluded from the aforementioned at least a portion of the memory cells of the target memory cell string. In this embodiment, the control circuit 120 does not perform the second erase operation on the remaining memory cells of each target memory cell string ST1~ST4. When performing the second erase operation, the control circuit 120 floats (or floats) the remaining memory cells. For example, when performing the second erase operation, the word line corresponding to the remaining memory cells is floated. Therefore, the voltage of the word line signal VWL follows the second erase voltage V2 based on the capacitive coupling effect in the remaining memory cells.
[0071] Please also refer to Figure 1 , Figure 3 as well as Figure 5 , Figure 5 It is a schematic diagram of a memory block shown in accordance with an embodiment of the present disclosure. The memory block MBK may be a 3D NAND flash memory block. In the present embodiment, the memory block MBK at least includes a shared source line CSL, bit lines BL1-BLn, word lines WL0-WLm, string selection transistors TS1-TSp, source selection transistors TC1-TCp, and memory cell strings ST1-STp. Each memory cell string ST1-STp is respectively coupled to the corresponding bit lines of the bit lines BL1-BLn and the shared source line CSL. The memory cells of each memory cell string ST1-STp are connected in series along a third direction Z. The memory cells of each memory cell string ST1-STp are respectively coupled to the corresponding word lines of the word lines WL0-WLm.
[0072] In the present embodiment, the string selection transistor TS1, the memory cell string ST1, and the source selection transistor TC1 are connected in series between the bit line BL1 and the common source line CSL. The string selection transistor TS2, the memory cell string ST2, and the source selection transistor TC2 are connected in series between the bit line BL2 and the common source line CSL. Similarly, the string selection transistor TSp, the memory cell string STp, and the source selection transistor TCp are connected in series between the bit line BLp and the common source line CSL.
[0073] In this embodiment, the bit lines BL1-BLn extend along a first direction X. The bit lines BL1-BLn are arranged along a second direction Y. The word lines WL0-WLm extend along a plane defined by the first direction X and the second direction Y. The word lines WL0-WLm are arranged along a third direction Z. The first direction X, the second direction Y and the third direction Z are not parallel to each other.
[0074] In this embodiment, the memory cells corresponding to the same word line WL0 in different memory cell strings may be one memory page, and the memory cells corresponding to the same word line WLm in different memory cell strings may be another memory page.
[0075] In the present embodiment, the string selection transistors TS1 ˜TSp and the source selection transistors TC1 ˜TCp are turned on. Figure 5 The memory block MBK in is selected. Therefore, the memory block MBK is the selected memory block MBK_T. The memory cell strings ST1~STp are respectively the target memory cell strings. When performing the first erase operation, the control circuit 120 applies the first erase voltage V1 to the shared source line CSL. When performing the first erase operation, the voltage of the shared source line signal VCSL is substantially equal to the first erase voltage V1. The control circuit 120 applies substantially 0 voltage to the word lines WL0~WLm. Therefore, when performing the first erase operation, all data of the memory cells of the memory cell strings ST1~STp are erased based on the first erase voltage V1.
[0076] When performing the second erase operation, the control circuit 120 applies the second erase voltage V2 to the common source line CSL. When performing the second erase operation, the voltage of the common source line signal VCSL is substantially equal to the second erase voltage V2. The control circuit 120 applies substantially zero voltage to the corresponding word lines connected to at least a portion of the memory cells.
[0077] In some embodiments, when performing a first erase operation, the control circuit 120 applies a first erase voltage V1 to the corresponding bit line. When performing a second erase operation, the control circuit 120 applies a second erase voltage V2 to the corresponding bit line.
[0078] In some embodiments, when performing a first erase operation, the control circuit 120 applies a first erase voltage V1 to the corresponding bit line and the shared source line CSL. When performing a second erase operation, the control circuit 120 applies a second erase voltage V2 to the corresponding bit line and the shared source line CSL.
[0079] In the second erase operation, the remaining memory cells are excluded from the aforementioned at least a portion of the memory cells of the target memory cell string. Therefore, the control circuit 120 does not perform the second erase operation on the remaining memory cells of each target memory cell string ST1-STp. When the second erase operation is performed, the remaining memory cells are floated. For example, when the second erase operation is performed, the word lines corresponding to the remaining memory cells are floated.
[0080] Please also refer to Figure 1 as well as Figure 6 , Figure 6is a schematic diagram of charge distribution according to an embodiment of the present disclosure. In this embodiment, Figure 6 A charge distribution CD1 of a first memory cell with a first charge loss and a charge distribution CD2 of a second memory cell with a second charge loss are shown.
[0081] In this embodiment, the first charge loss and the second charge loss are as follows: Figure 6 As shown. The first charge loss is represented as a larger amount of charge loss after the programming operation. The second charge loss is represented as a smaller amount of charge loss after the programming operation. It should be noted that after the programming operation, the intersection P2 of the determination voltage RDG and the charge distribution CD2 is higher than the intersection P1 of the determination voltage RDG and the charge distribution CD1. In other words, the amount of charge in the charge distribution CD2 that exceeds the determination voltage RDG is higher than the amount of charge in the charge distribution CD1 that exceeds the determination voltage RDG. This means that the charge distribution CD2 has a smaller amount of charge loss. The second memory cell has a poor ECC result. In order to improve the ECC result of the second memory cell. The intersection P2 must be lowered
[0082] In this embodiment, the control circuit 120 performs a second erase operation on the second storage cell. After performing the second erase operation, the second charge loss of the second storage cell is adjusted to the first charge loss. Therefore, the charge distribution CD2 of the second storage cell is adjusted to be similar to the charge distribution CD2′ of the charge distribution CD1. The amount of charge exceeding the determination voltage RDG in the charge distribution CD2′ is similar to the amount of charge exceeding the determination voltage RDG in the charge distribution CD1. Therefore, the ECC result of the second storage cell is improved.
[0083] For details, please also refer to Figure 1 as well as Figure 7 , Figure 7 is a schematic diagram of charge distribution and threshold voltage corresponding to different second erase voltages according to an embodiment of the present disclosure. Figure 7 Charge distributions CD3 to CD5 of memory cells corresponding to a single data state are shown. Charge distribution CD3 is represented as a charge distribution before the second erase operation is performed. Charge distribution CD3 is a charge distribution after the programming operation. Charge distributions CD4 and CD5 are each represented as a different charge distribution after the second erase operation. After the second erase operation is performed, based on a fixed threshold charge number NB, the threshold voltage of the memory cell is adjusted from a threshold voltage VT1 corresponding to charge distribution CD3 to a threshold voltage VT2 corresponding to charge distribution CD4. Threshold voltage VT2 is lower than threshold voltage VT1.
[0084] In addition, if the second erase voltage V2 is increased, the threshold voltage of the memory cell is adjusted from the threshold voltage VT1 corresponding to the charge distribution CD3 to the threshold voltage VT3 corresponding to the charge distribution CD5. The threshold voltage VT3 is lower than the threshold voltage VT2.
[0085] Therefore, based on actual conditions, the second erase voltage V2 can be adjusted.
[0086] Please also refer to Figure 1 as well as Figure 8 , Figure 8 FIG. 1 is a schematic diagram of a target storage cell string according to an embodiment of the present disclosure. In this embodiment, the target storage cell string STT1 is in the selected memory block MBK_T. The selected memory block MBK_T may be as follows: Figure 5 The 3D NAND flash memory block shown. The target memory cell string STT1 includes dummy cells MD1-MD3 and memory cells M0-M95. The selected memory block MBK_T includes word lines WL0-WL95 and dummy word lines DWL1-DWL3.
[0087] In this embodiment, the virtual word lines DWL1 and DWL2 are arranged along a first direction (ie, Figure 5 The virtual word line DWL3 is arranged between the virtual word line DWL1 and the virtual word line DWL2. The virtual word line DWL3 extends along the second direction Y.
[0088] In the present embodiment, the storage cells M0 to M95 are divided into a first storage cell group MCG1 and a second storage cell group MCG2 by the virtual cell MD3. For example, the first storage cell group MCG1 is disposed between the virtual cell MD1 and the virtual cell MD3. The first storage cell group MCG1 includes storage cells M0 to M47. The second storage cell group MCG2 is disposed between the virtual cell MD2 and the virtual cell MD3. The second storage cell group MCG2 includes storage cells M48 to M95, but the present disclosure is not limited thereto. The first storage cell group MCG1 can be the first deck in a 3-dimensional NAND flash memory block. The second storage cell group MCG2 can be the second deck different from the first deck in a 3-dimensional NAND flash memory block.
[0089] In the present embodiment, the virtual word line DWL1 is connected to the virtual cell MD1. The virtual word line DWL2 is connected to the virtual cell MD2. The virtual word line DWL3 is connected to the virtual cell MD3. The word line WL0 is connected to the memory cell M0. The word line WL1 is connected to the memory cell M1, and so on. The word lines WL0 to WL95 are divided into a first word line group WLG1 and a second word line group WLG2 by the virtual word line DWL3. The first word line group WLG1 includes word lines WL1 to WL47. The second word line group WLG2 includes word lines WL48 to WL95.
[0090] In the present embodiment, when the second erase operation is performed, the control circuit 120 applies the second erase voltage V2 to the bit line and / or the shared source line corresponding to the target memory cell string STT1. When the second erase operation is performed, the control circuit 120 applies the word line signal VWL having a voltage of substantially 0 to the first word line group WLG1 and the second word line group WLG2. Therefore, the control circuit 120 performs the second erase operation on all memory cells M0 to M95.
[0091] Please also refer to Figure 1 as well as Fig. 9 , Fig. 9 FIG. 1 is a schematic diagram of a target memory cell string according to an embodiment of the present disclosure. In this embodiment, the connection between the target memory cell string STT1, the word lines WL0 to WL95, and the virtual word lines DWL1 to DWL3 is already Figure 8 The embodiments of the present invention are clearly described in detail, so they will not be repeated here. In the present embodiment, when the second erase operation is performed, the control circuit 120 applies the second erase voltage V2 to the bit line and / or shared source line corresponding to the target memory cell string STT1. When the second erase operation is performed, the control circuit 120 applies a word line signal VWL having a voltage of approximately 0 to the second word line group WLG2. In addition, the control circuit 120 floats the first word line group WLG1. Therefore, the control circuit 120 performs the second erase operation on the memory cells M48 to M95. Therefore, the control circuit 120 does not perform the second erase operation on the memory cells M0 to M47 (i.e., the remaining memory cells).
[0092] In some embodiments, when performing the second erase operation, the control circuit 120 applies a word line signal VWL having a voltage of substantially 0 to the first word line group WLG1 and floats the second word line group WLG2. Therefore, the control circuit 120 performs the second erase operation M0-M47 on the memory cells M0-M47.
[0093] based on Figure 8 as well as Fig. 9 , the control circuit 120 may apply substantially 0 voltage to at least one of the first word line group WLG1 and the second word line group WLG2 .
[0094] Please refer to Figure 1 as well as Fig.10 , Fig.10 FIG. 1 is a schematic diagram of a target memory cell string according to an embodiment of the present disclosure. In this embodiment, the connection between the target memory cell string STT1, the word lines WL0 to WL95, and the virtual word lines DWL1 to DWL3 is already Figure 8 The embodiments of the present invention are clearly described in detail, so they will not be repeated here. In the present embodiment, when performing the second erase operation, the control circuit 120 floats at least one word line in the first word line group WLG1 and the second word line group WLG2 adjacent to the third virtual word line DWL3 and applies a word line signal. For example, the word line WL47 in the first word line group WLG1 and the word line WL48 in the second word line group WLG2 are adjacent to the third virtual word line DWL3. When performing the second erase operation, the control circuit 120 applies the second erase voltage V2 to the bit line and / or shared source line corresponding to the target memory cell string STT1. When performing the second erase operation, the control circuit 120 applies the word line signal VWL having a voltage of approximately 0 to the word lines WL0~WL46, WL49~WL95. Therefore, the control circuit 120 performs the second erase operation on the memory cells M0~M46, M49~M95. When performing the second erase operation, the control circuit 120 floats the word lines WL47 and WL48 adjacent to the third dummy word line DWL3. Therefore, the control circuit 120 does not perform the second erase operation on the memory cells M47 and M48 adjacent to the dummy cell MD3 (ie, the remaining memory cells).
[0095] Please also refer to Figure 1 as well as Fig.11 , Fig.11 It is a flow chart of an operation method shown in accordance with an embodiment of the present disclosure. In the present embodiment, the operation method S100 is used for the memory device 100. The operation method S100 includes steps S110 to S130. In step S110, the control circuit 120 provides a first erase voltage V1 to perform a first erase operation on the target memory cell strings STT1 to STT4 of the selected memory block MBK_T in the memory block MBK. In step S120, the control circuit 120 performs a programming operation on the target memory cell strings STT1 to STT4 after the first erase operation. In step S130, the control circuit 120 provides a second erase voltage V2 after the programming operation to perform a second erase operation on at least a portion of the memory cells of each of the multiple target memory cell strings STT1 to STT4. The second erase voltage V2 is lower than the first erase voltage V1. The first erase operation and the second erase operation have been performed on the target memory cell strings STT1 to STT4. Figures 1 to 10 The above is clearly described in at least one of the embodiments, so it will not be repeated here.
[0096] In summary, after performing a programming operation, the memory device 100 performs a second erasing operation on at least a portion of the memory cells of each of the plurality of target memory cell strings. The second erasing operation adjusts the charge loss of the memory cells after performing the programming operation. The difference between the charge losses of the plurality of memory cells can be reduced. In this way, the difference between the charge losses of the plurality of memory cells can be reduced. In addition, for the application of multi-level memory cells, since the difference between the read windows can be reduced, the error of the data reading operation or the error correction operation of programming can also be reduced. In this way, the memory device provides a high-performance, large-capacity storage medium.
[0097] Although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the scope of the appended claims.
Claims
1. A memory device, comprising: a memory array comprising a plurality of memory blocks; as well as a control circuit coupled to the memory array and configured to provide a first erase voltage to perform a first erase operation on a plurality of target memory cell strings of a selected memory block among the memory blocks, perform a program operation on the target memory cell strings after the first erase operation, and provide a second erase voltage to perform a second erase operation on at least a portion of memory cells in each of the target memory cell strings after the program operation, The second erasing voltage is lower than the first erasing voltage.
2. The memory device of claim 1, wherein a difference between the second erase voltage and the first erase voltage is in a range of 7 to 13 volts.
3. The memory device of claim 1, wherein when performing the second erase operation, the control circuit applies substantially zero voltage to one or more corresponding word lines connected to the at least a portion of the memory cells.
4. The memory device according to claim 1, wherein the selected memory block comprises: a common source line; A plurality of bit lines extending along a first direction and arranged along a second direction; as well as A plurality of word lines extend along a plane defined by the first direction and the second direction and are arranged along a third direction, wherein the first direction, the second direction and the third direction are not parallel to each other, each of the target memory cell strings is respectively coupled between a corresponding bit line among the bit lines and the shared source line, a plurality of memory cells of each of the target memory cell strings are connected in series along the third direction, and each of the memory cells of each of the target memory cell strings is respectively coupled to a corresponding word line of the word lines.
5. The memory device of claim 4 , wherein the control circuit applies the first erase voltage to the shared source line and at least one of the bit lines to perform the first erase operation, and applies the second erase voltage to the shared source line and at least one of the bit lines to perform the second erase operation. 6 . The memory device according to claim 4 , wherein a remaining portion of the target memory cell strings on which the second erasing operation is not performed are floated.
7. The memory device according to claim 4, wherein the selected memory block further comprises: a first virtual word line extending along the plane defined by the first direction and the second direction; as well as A second virtual word line extends along the plane defined by the first direction and the second direction, and the word lines are arranged between the first virtual word line and the second virtual word line.
8. The memory device according to claim 7, wherein the selected memory block further comprises: A third virtual word line is disposed between the first virtual word line and the second virtual word line, and the word lines are divided into a first word line group and a second word line group by the third virtual word line. 9 . The memory device of claim 8 , wherein when performing the second erase operation, the control circuit applies a word line signal to at least one of the first word line group and the second word line group. 10 . The memory device of claim 8 , wherein when performing the second erase operation, the control circuit floats at least one word line in the first word line group and the second word line group that is adjacent to the third dummy word line.
11. An operating method for a memory device, wherein the memory device comprises a memory array, wherein the memory array comprises a plurality of memory blocks, wherein the operating method comprises: providing a first erasing voltage to perform a first erasing operation on a plurality of target memory cell strings of a selected memory block among the memory blocks; performing a programming operation on the target memory cell strings after the first erasing operation; as well as A second erasing voltage is provided after the programming operation to perform a second erasing operation on at least a portion of the memory cells in each of the target memory cell strings, wherein the second erasing voltage is lower than the first erasing voltage. 12 . The operating method according to claim 11 , wherein a difference between the second erase voltage and the first erase voltage is in a range of 7 to 13 volts.
13. The operating method according to claim 11, wherein the step of providing the second erasing voltage after the programming operation to perform the second erasing operation on the at least a portion of the memory cells of each of the target memory cell strings comprises: When performing the second erase operation, substantially zero voltage is applied to one or more corresponding word lines connected to the at least a portion of the memory cells.
14. The operating method according to claim 11, wherein the selected memory block comprises: a common source line; A plurality of bit lines extending along a first direction and arranged along a second direction; as well as A plurality of word lines extend along a plane defined by the first direction and the second direction and are arranged along a third direction, wherein the first direction, the second direction and the third direction are not parallel to each other, each of the target memory cell strings is respectively coupled between a corresponding bit line among the bit lines and the shared source line, a plurality of memory cells of each of the target memory cell strings are connected in series along the third direction, and each of the memory cells of each of the target memory cell strings is respectively coupled to a corresponding word line of the word lines.
15. The operating method according to claim 14, wherein: The step of providing the first erase voltage to perform the first erase operation on the target memory cell strings of the selected memory block in the memory blocks includes: applying the first erase voltage to the shared source line and at least one of the bit lines to perform the first erase operation; and The step of providing the second erase voltage to perform the second erase operation on the at least a portion of the memory cells of each of the target memory cell strings comprises: The second erase voltage is applied to the shared source line and at least one of the bit lines to perform the second erase operation.
16. The operating method according to claim 14, wherein the step of providing the second erasing voltage after the programming operation to perform the second erasing operation on the at least a portion of the memory cells of each of the target memory cell strings comprises: A remaining portion of the memory cells of the target memory cell strings, in which the second erasing operation is not performed, is floated.
17. The operating method according to claim 14, wherein the selected memory block further comprises: a first virtual word line extending along the plane defined by the first direction and the second direction; as well as A second virtual word line extends along the plane defined by the first direction and the second direction, and the word lines are arranged between the first virtual word line and the second virtual word line.
18. The operating method according to claim 17, wherein the selected memory block further comprises: A third virtual word line is disposed between the first virtual word line and the second virtual word line, and the word lines are divided into a first word line group and a second word line group by the third virtual word line.
19. The operating method according to claim 18, wherein the step of providing the second erasing voltage after the programming operation to perform the second erasing operation on the at least a portion of the memory cells of each of the target memory cell strings comprises: When performing the second erasing operation, a word line signal is applied to at least one of the first word line group and the second word line group.
20. The operating method according to claim 18, wherein the step of providing the second erasing voltage after the programming operation to perform the second erasing operation on the at least a portion of the memory cells of each of the target memory cell strings comprises: When performing the second erasing operation, at least one word line in the first word line group and the second word line group adjacent to the third dummy word line is floated.