Memory device

Abstract

A memory device includes a built-in self-test circuit configured to select a first target bank and a second target bank for each of a plurality of row addresses such that each of a plurality of memory banks is selected as the first target bank and the second target bank at least once, and performing a parallel test on the first target bank and the second target bank for each of the plurality of row addresses; a comparator configured to compare first data output from the first target bank and second data output from the second target bank, and output a failure signal according to a comparison result thereof; and a built-in analysis circuit configured to update a faulty memory body surface indicating fault information of each of the plurality of memory banks in response to the fault signal, and configured to determine a defective bank by referring to the faulty memory body surface.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0130894 filed on September 27, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a memory device and a testing method for the memory device. Background Art

[0004] Semiconductor memory devices are manufactured through semiconductor manufacturing processes and then tested in a wafer state, a bare die state, or a package state by test equipment. Defective memory devices can be selected through testing, and when some memory cells are defective, the memory devices can be retained by performing repair operations on these memory cells. With microprocessing, the possibility of errors occurring in the manufacturing process of memory devices such as dynamic random access memory (DRAM) increases. In addition, even if no errors are detected in the initial test stage, errors may occur during chip operation.

[0005] Therefore, the importance of built-in self-test (BIST) of memory devices is increasing. As the capacity of memory devices increases, overhead may occur in order for the memory devices to perform self-tests and analyze test results thereof. Summary of the invention

[0006] An aspect of the present invention is to provide a memory device for performing a self-test and reducing overhead for analyzing a test result, and a test method for the memory device.

[0007] According to one aspect of the present invention, a memory device includes: a plurality of memory banks, each memory bank having a plurality of rows corresponding to a plurality of row addresses; a built-in self-test (BIST) circuit configured to select a first target bank and a second target bank for each of the plurality of row addresses, so that each of the plurality of memory banks is selected as the first target bank and the second target bank at least once, and a parallel test is performed on the first target bank and the second target bank for each of the plurality of row addresses; a comparator configured to compare first data output from the first target bank and second data output from the second target bank, and output a fault signal according to a comparison result thereof; and a built-in analysis circuit configured to update a fault bank table indicating fault information of each of the plurality of memory banks in response to the fault signal, and determine a defective bank by referring to the fault bank table.

[0008] According to one aspect of the present invention, a memory device includes: a base die; and a plurality of core dies stacked on the base die and connected to the base die through a plurality of through silicon vias (TSVs). Each of the plurality of core dies includes: a plurality of memory banks, each memory bank having a plurality of rows corresponding to a plurality of row addresses, and the base die includes: a built-in self-test (BIST) circuit configured to select a target bank from the plurality of memory banks in various combinations with respect to each of the plurality of row addresses, and to perform parallel testing on the target bank with respect to each of the plurality of row addresses; a comparator configured to compare data output from the target bank and output a fault signal according to the comparison result thereof; and a built-in analysis circuit configured to determine a defective bank by referring to the fault signal and the target bank of each of the plurality of row addresses.

[0009] According to one aspect of the present invention, a memory device includes: a plurality of memory storage bodies, each memory storage body having a plurality of rows corresponding to a plurality of row addresses; and a test circuit, which is configured to: determine a target storage body table indicating a target storage body selected from the plurality of memory storage bodies with respect to each of the plurality of row addresses; repeatedly perform operations of writing the same data to the target storage body, reading the data stored in the target storage body, and outputting a fault signal based on a result of comparing the data read from the target storage body with respect to each of the plurality of row addresses; update fault information of each of the plurality of memory storage bodies by referring to the fault signal and the target storage body table; and determine a defective storage body by referring to the fault information.

[0010] According to one aspect of the present invention, a method for manufacturing a memory device using a method for testing a memory device, the memory device including a plurality of memory banks, each memory bank having a plurality of rows corresponding to a plurality of row addresses, the method for manufacturing the memory device including providing a memory device to be tested. The method for testing the memory device includes: determining a target bank table indicating a target bank selected from a plurality of memory banks with respect to each of a plurality of row addresses; repeatedly performing operations of writing the same data to a target bank, reading data stored in the target bank, and outputting a fault signal according to a result of comparing the data read from the target bank with respect to each of a plurality of row addresses; updating fault information of each of a plurality of memory banks by referring to the fault signal and the target bank table; and determining a defective bank by referring to the fault information.

[0011] A memory device and a test method for the memory device according to example embodiments of the present disclosure may perform parallel testing on target memory banks selected in various combinations from a plurality of memory memory banks, and specify a defective memory bank among the plurality of memory memory banks by combining parallel test results thereof.

[0012] In a memory device and a test method for a memory device according to an example embodiment of the present disclosure, since a comparator can compare data output from a target memory body and a built-in analysis circuit can use a fault signal output from the comparator to analyze a defective memory body, the overhead of analyzing test results can be reduced.

[0013] Aspects to be solved by the present disclosure are not limited to the above-mentioned aspects, and other aspects not mentioned herein will be clearly understood by those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a diagram illustrating a memory system according to an example embodiment of the present disclosure;

[0016] Figure 2 is a diagram illustrating a memory device according to an example embodiment of the present disclosure;

[0017] Figure 3 is an operation timing diagram of a comparator according to an example embodiment of the present disclosure;

[0018] Figure 4A and Figure 4B is a diagram illustrating a method for selecting a target memory bank according to an example embodiment of the present disclosure;

[0019] Figure 5 is a flow chart illustrating a method of testing a memory device according to an example embodiment of the present disclosure;

[0020] Figure 6 is a diagram illustrating a BIRA circuit according to an example embodiment of the present disclosure;

[0021] Fig. 7A and Figure 7B is a diagram illustrating a method for detecting a defective memory bank according to an example embodiment of the present disclosure;

[0022] Fig. 8A and Figure 8B is a diagram illustrating a method for detecting a defective memory bank according to an example embodiment of the present disclosure;

[0023] Fig. 9 is a diagram illustrating a BIRA circuit according to an example embodiment of the present disclosure;

[0024] Fig.10 is a diagram illustrating a memory device according to an example embodiment of the present disclosure;

[0025] Fig.11A and Fig. 11B is a diagram illustrating in detail a memory device according to an example embodiment of the present disclosure; and

[0026] Fig.12 is a block diagram illustrating a system to which a memory device according to an example embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0027] Hereinafter, example embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0028] Figure 1 is a diagram illustrating a memory system according to an example embodiment of the present disclosure.

[0029] Reference Figure 1 , the system 10 may be a data center including many host devices or servers. According to some example embodiments, the system 10 may be, for example, a computing device (such as a laptop computer, a desktop computer, a server computer, a workstation, a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, a tablet PC, and other suitable computers), a virtual machine or a virtual computing device thereof. Alternatively, the system 10 may be some components included in a computing system, such as a graphics card.

[0030] System 10 has the following references Figure 1 A plurality of hardware configurations are described in more detail, but the present invention is not limited thereto. The system 10 may include a host device 20 and a memory system 30. The host device 20 and the memory system 30 may be connected to each other according to various standard interfaces.

[0031] The host device 20 includes a processor 22 and may execute an operating system (OS) and / or various application programs. The processor 22 may be communicatively connected to a memory system 30. The memory system 30 connected to the processor 22 may be referred to as a system memory.

[0032] The processor 22 is a functional block that performs general computer operations in the system 10, and may be a central processing unit (CPU), a digital signal processor (DSP), a network processor, an application processor (AP), or any type of processor, such as another device for executing code. The processor 22 may be configured to execute instructions or software, firmware, or a combination thereof that can be executed with one or more machines. The processor 22 may include any number of processor cores. For example, the processor 22 may include a single core or multiple cores, such as dual cores, quad cores, and hexa cores. Figure 1 The system 10 is shown including one processor 22, but according to example embodiments, the system 10 may include multiple processors.

[0033] The memory system 30 may include a memory controller 110, a memory device 120, and a memory interface 130. The memory controller 110 may control a memory access operation (e.g., a write operation or a read operation) for the memory device 120 in response to a request from a host device 20 connected to the memory system 30. The memory device 120 may be used as a working memory for recording or loading data for the operation of the processor 22. Figure 1 2 and 3. The memory system 30 including one memory device 120 is shown in FIG. 4, but according to example embodiments, the memory system 30 may include a plurality of memory devices.

[0034] To simplify the drawings, the memory interface 130 is shown as being connected between the memory controller 110 and the memory device 120 as a single signal line, but in fact it may be connected via a plurality of signal lines. The memory interface 130 includes a connector for connecting the memory controller 110 and the memory device 120, and the connector may be implemented as a pin, a ball, a signal line, or other hardware component. For example, a clock signal CLK, a command / address signal CMD / ADDR, and a data signal DQ may be sent and received between the memory controller 110 and the memory device 120 via the memory interface 130. The memory interface 130 may be implemented as a channel including a plurality of signal lines, or may be implemented as a plurality of channels. The memory interface 130 may be referred to as a channel, and in the following embodiments, the terms "memory interface 130" and "channel" may be used interchangeably.

[0035] The memory controller 110 may access the memory device 120 through a memory request from the processor 22, and may be provided with a system physical address for memory access. The memory controller 110 may include a memory physical layer interface (i.e., memory PHY 112) for memory interfacing (such as selecting a row and column corresponding to a memory cell), recording data in a memory cell, or reading recorded data from a memory cell.

[0036] The memory PHY 112 may take many shapes of actual physical implementations of the memory controller 110 that perform the functions described above. For example, the memory controller 110 may include a physical configuration for exchanging data with the memory device 120, and may include at least one transmitter and at least one receiver. The memory controller 110 may include one or more hardware components (e.g., analog circuits and logic circuits). The memory controller 110 may be implemented as program code of software and / or firmware. The memory controller 110 may be integrated into (one or more) processors 22 to ensure consistent access of (one or more) processors 22 to (one or more) memory devices 120.

[0037] The memory device 120 may be a DRAM device. However, the scope of the present invention is not limited thereto, and the memory device 120 may be any one of a volatile memory device such as a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), a low power double data rate SDRAM (LPDDR SDRAM), a graphic double data rate SDRAM (GDDR SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a DDR4 SDRAM, a DDR5 SDRAM, a wide I / O DRAM, a high bandwidth memory (HBM), and a hybrid memory cube (HMC). According to another example embodiment, the memory device 120 may be any one of a plurality of memory devices installed in a memory module. The memory module may be implemented as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), a small outline DIMM (SODIMM), etc.

[0038] The memory device 120 may include a memory core 121 , a built-in self-test (BIST) circuit 124 , a built-in redundancy analysis (BIRA) circuit 125 , and a control circuit 126 .

[0039] The memory core 121 may include a plurality of memory cell arrays. Each of the plurality of memory cell arrays may constitute a memory bank. Each of the plurality of memory cells may be formed by a DRAM cell including a single access transistor and a single storage capacitor. Each of the memory cell arrays may include a normal memory cell and a redundant memory cell.

[0040] The control circuit 126 may control access to the memory core 121 based on commands and addresses received by the memory device 120 . For example, the control circuit 126 may control read operations, write operations, and refresh operations of the memory core 121 based on commands and addresses received through the memory interface 130 .

[0041] In addition, the control circuit 126 may control the testing of the memory device 120 in conjunction with the BIST circuit 124 , and control the analysis of the test results of the memory device 120 in conjunction with the BIRA circuit 125 .

[0042] The BIST circuit 124 may perform a test of the memory device 120. Specifically, the BIST circuit 124 may test whether there is a defective memory cell in the memory core 121, or test whether there is a defect in a data path of the memory device 120. For example, the BIST circuit 124 may perform a test by writing data to the memory core 121 and reading the written data from the memory core 121.

[0043] The BIRA circuit 125 may analyze the test results performed by the BIST circuit 124. Specifically, the BIRA circuit 125 may specify the address of a defective memory cell of the memory core 121 and repair the defective memory cell with a redundant memory cell. In addition, when a defect is detected in a data path, the BIRA circuit 125 may specify the data path in which the defect is detected. The circuit for analyzing defects in a data path in the BIRA circuit 125 may be referred to as a built-in analysis circuit.

[0044] Meanwhile, the memory device 120 may support bank interleaving for accessing in parallel a row specified by the same row address in each of the plurality of memory banks. When the memory device 120 supports bank interleaving, the BIST circuit 124 may perform a parallel test to test the plurality of memory banks. The parallel test may be a test for writing the same data pattern into rows specified by the same row address of the plurality of memory banks, and determining a pass or a fail based on whether the data patterns match by comparing the data patterns read from the rows.

[0045] If the BIRA circuit 125 needs to detect a defect in a memory bank by comparing data patterns read from a plurality of banks with each other and specify a bank address of a defective memory bank, an overhead may occur. As the frequency of a data signal increases with an increase in the speed of the memory device 120, and the number of memory banks increases according to a high capacity of the memory device 120, an overhead for specifying a bank address may increase. In addition, connecting a plurality of data paths associated with a plurality of banks to the BIRA circuit 125 may also be a large burden in terms of area and performance of the memory device 120.

[0046] According to an example embodiment of the present disclosure, the BIST circuit 124 may select two target memory banks in various combinations with respect to each of a plurality of row addresses, and perform parallel testing on the target memory banks. The data patterns read from the two target memory banks may be compared in a comparator, and the comparator may provide a fault signal to the BIRA circuit 125 according to its comparison result. The BIRA circuit 125 may specify a defective memory bank address by analyzing the fault signal for each of a plurality of row addresses and various combinations of target memory banks.

[0047] According to example embodiments of the present disclosure, an overhead of the BIRA circuit 125 comparing data patterns read from a plurality of memory banks with each other may be reduced, and a burden of connecting a plurality of data paths to the BIRA circuit 125 may be reduced.

[0048] In the following, reference will be made to Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9 , Fig.10 , Fig.11A and Fig. 11B A memory device according to example embodiments of the present disclosure is described in detail.

[0049] Figure 2 is a diagram illustrating a memory device according to an example embodiment of the present disclosure.

[0050] Figure 2 The memory device 120 may correspond to the reference Figure 1 The memory device 120 may include a memory core 121 , a comparator 122 , a signal bus or a data bus (RWBUS) 123 , a BIST circuit 124 , and a BIRA circuit 125 . Figure 2 Reference omitted Figure 1 The control circuit 126 is described.

[0051] The memory core 121 may include a plurality of memory banks 121a to 121d. Each of the plurality of memory banks 121a to 121d may include a memory cell array (MCA), a row decoder (R / D), a column decoder (C / D), and a sense amplifier (not shown). The memory cells included in the memory cell array MCA may be specified by a row address and a column address. The plurality of memory banks 121a to 121d may have the same row address and column address. For example, when bank interleaving is performed, a row specified by a row address may be sequentially accessed in each of the plurality of memory banks 121a to 21d based on a single row address.

[0052] At the same time, Figure 2 In the example of FIG. 1 , the memory core 121 may include four memory banks 121 a to 121 d , but the number of memory banks in the present invention is not limited thereto.

[0053] The data bus 123 may provide a data path between the plurality of memory banks 121 a to 121 d and the memory interface 130 . Figure 2 Data lines between a data bus 123 and a plurality of memory banks 121a to 121d are shown.

[0054] The BIST circuit 124 may provide write commands and read commands to test data paths of the plurality of memory banks 121 a to 121 d .

[0055] According to an example embodiment of the present disclosure, the BIST circuit 124 may select two target memory banks for parallel testing with respect to each of a plurality of row addresses. The target memory banks may be selected in various combinations with respect to each of a plurality of row addresses. The BIST circuit 124 may store a target memory bank table TB_TBL indicating a mapping of the row addresses and the target memory banks. In an embodiment, the target memory bank table TB_TBL may be included in the BIST circuit 124 or the BIRA circuit 125.

[0056] The BIST circuit 124 can perform parallel testing on the plurality of memory banks 121a to 121d by referring to the target bank table TB_TBL. Specifically, the BIST circuit 124 can control the same data pattern to be written to the row specified by the row address in the target bank corresponding to the specific row address with respect to each of the plurality of row addresses, and can perform parallel testing to control the data stored in the row to be read.

[0057] The data read from the target memory bank may be provided to the comparator 122. The comparator 122 may compare the data provided from the two target memory banks and output a fault signal FAILS according to the comparison result thereof. For example, the fault signal FAILS may be a flag signal. Specifically, the comparator 122 may compare the first data output from the first target memory bank with the second data output from the second target memory bank for each bit, and when the first data and the second data differ from each other by even one bit, the fault signal FAILS is output by converting the flag signal.

[0058] When the BIST circuit 124 performs a parallel test on a plurality of row addresses, a fail signal FAILS corresponding to each of the plurality of row addresses may be sequentially output from the comparator 122 .

[0059] The BIRA circuit 125 can determine a defective memory bank with a defect in the data path based on the row address RA, the fault signal FAILS and the target memory bank table TB_TBL, and output the test result to the external memory controller. Specifically, the BIRA circuit 125 can determine whether the fault signal FAILS has occurred when performing parallel testing on which target memory banks based on the row address RA, the fault signal FAILS and the target memory bank table TB_TBL. Based on whether the fault signal FAILS occurs according to various combinations of target memory banks, it can be determined which memory bank among the multiple memory memory banks 121a to 121d is tested to generate the fault signal FAILS. In addition, the memory memory bank that causes the occurrence of the fault signal FAILS can be determined as a defective memory bank.

[0060] According to an example embodiment of the present disclosure, the BIRA circuit 125 may determine a defective memory bank using a fail signal FAILS having a relatively low frequency instead of using a data signal DQ having a high frequency, thereby alleviating the overhead of the BIRA circuit 125 .

[0061] In addition, since the comparator 122 may include a plurality of XOR (exclusive OR) circuits, the comparator 122 may be implemented in a relatively simple and repetitive structure. Compared to the BIRA circuit 125, the plurality of XOR circuits forming the comparator 122 may be disposed adjacent to the data line. Therefore, compared to a case where the data line is directly connected to the BIRA circuit 125, the structure of the comparator 122 may reduce the area and performance burden of the memory device 120.

[0062] Hereinafter, the frequencies of the data signal and the fail signal FAILS will be briefly described.

[0063] Figure 3 is an operation timing diagram of a comparator according to an example embodiment of the present disclosure.

[0064] During a first period P1 in which a parallel test is performed on a first target memory bank and a second target memory bank selected with respect to a single row address, reference is made to Figure 2 The described comparator 122 may compare first data output from a first target memory bank with second data output from a second target memory bank.

[0065] Reference Figure 3 , a first data signal (DQ1: D11 to D1X) output from a first data line connected to a first target memory bank may be sequentially compared with a second data signal (DQ2: D21 to D2X) output from a second data line connected to a second target memory bank.

[0066] The first data signals D11 to D1X and the second data signals D21 to D2X may be compared in real time in the order in which the signals are received. The first data lines and the second data lines may transmit signals in synchronization with a high frequency (eg, a frequency of several thousand MHz).

[0067] When even one bit of the first data signals D11 to D1X and the second data signals D21 to D2X is different from each other, the comparator 122 may output the fault signal FAILS. Specifically, the fault signal FAILS may be initialized to a logic low state, and when a different bit is detected as a result of comparing the first data signals D11 to D1X with the second data signals D21 to D2X, the fault signal FAILS may be converted to a logic high state, thereby outputting the fault signal FAILS. For example, when it is detected at a first time point T1 that the first data signal D13 and the second data signal D23 are different, the fault signal FAILS at the first time point T1 may be converted from a logic low state to a logic high state, and the logic state of the fault signal FAILS may be maintained until it is initialized in the next cycle.

[0068] Reference Figure 3 , the frequency of the fail signal FAILS may be lower than the frequencies of the first data signals D11 to D1X and the second data signals D21 to D2X. Therefore, the overhead of the BIRA circuit for detecting a defective memory bank by processing the fail signal FAILS may be reduced.

[0069] Hereinafter, a method of selecting a target memory bank through a BIST circuit is described in detail so that the BIRA circuit can detect a defective memory bank based on a fail signal FAILS.

[0070] Figure 4A and 4B is a diagram illustrating a method for selecting a target memory bank according to an example embodiment of the present disclosure.

[0071] Figure 4A is a diagram showing a bank address BA of a memory bank selected as a target bank in each of a plurality of row addresses RA. Figure 4A , “1” indicates a memory bank selected as a target memory bank, and “0” may indicate a memory bank not selected as a target memory bank.

[0072] The target memory banks in each row address RA may be selected in various combinations. However, in all row addresses RA, all memory banks may be selected as target memory banks at least twice. According to example embodiments, when the number of row addresses RA is large enough, all possible combinations of target memory banks may be selected at least once.

[0073] Figure 4B is a diagram showing a row in which parallel testing is performed in a plurality of memory banks 121a to 121d. Figure 4B , the shaded area indicates the rows where parallel testing is performed.

[0074] According to an example embodiment of the present disclosure, parallel testing may be performed in the order of row addresses RA. Figure 4A and Figure 4B , when the target memory bank address of the first row address RA1 is selected as the first memory bank address BA1 and the second memory bank address BA2, a parallel test may be performed on the first row of the first memory bank 121a and the second memory bank 121a. In addition, when the target memory bank address of the second row address RA2 is selected as the second memory bank address BA2 and the third memory bank address BA3, a parallel test may be performed on the second row of the second memory bank 121b and the second row of the third memory bank 121c. Similarly, parallel tests may be performed on the target memory banks for the remaining rows.

[0075] Meanwhile, in the plurality of memory banks 121a to 121d, parallel testing may not be performed on all rows. However, even if any row of the memory bank is accessed, a defect in the data path of the memory bank may cause an error in the data, and therefore, even when parallel testing is performed on some rows, a defective memory bank may be detected by combining the parallel test results.

[0076] Figure 5 is a flowchart illustrating a method of testing a memory device according to an example embodiment of the present disclosure.

[0077] Reference Figure 5 , the method for testing a memory device may include a plurality of steps S11 to S17. In step S11, a target memory bank table may be determined. The target memory bank table may refer to a table for storing information about a target memory bank selected for each of a plurality of row addresses RA. Information of the target memory bank table may be permanently stored in a BIST circuit during manufacturing of the memory device, or received from the outside at the BIST circuit during testing of the memory device.

[0078] In step S12 , a parallel test may be performed on target memory banks TB1 and TB2 of a target row address among a plurality of row addresses, and in step S13 , it may be determined whether the parallel test fails.

[0079] When the parallel test result for the target row address is determined to be a failure ("Yes" in step S13), in step S14, the failed bank table may be updated by referring to the target bank table. The failed bank table may store information on whether each of the memory banks is failed or store a failure count.

[0080] When the parallel test result for the target row address is determined to be qualified (“No” in step S13 ), in step S15 , it may be determined whether the test for all row addresses has been completed.

[0081] When the test for all row addresses has not been completed (No in step S15), in operation S16, the next row address of the target row address is determined as a new target row address, and steps S12 to S15 may be repeatedly performed.

[0082] When the test for all row addresses has been completed ("Yes" in step S15), in step S17, a defective memory bank can be detected based on the test results for all row addresses. After the defective memory bank is detected in step S17, the memory device can be remedied by performing a repair operation thereon. The structure of the BIRA circuit for detecting a defective memory bank and the method for detecting a defective memory bank will be described in detail below.

[0083] although Figure 5 Although not shown in the flowchart, the flowchart may be a method of manufacturing a memory device using the method of testing a memory device. For example, the flowchart showing the method of manufacturing a memory device may include step S10 (not shown) before performing steps S11 to S17. For example, in step S10, a memory device may be provided for testing. The memory device may be Figure 1 and one of the memory devices 120 and 400 of FIG. 4 .

[0084] Figure 6 is a diagram illustrating a BIRA circuit according to an example embodiment of the present disclosure.

[0085] Figure 6 The BIRA circuit 125a may correspond to the reference Figure 2 The BIRA circuit 125 a may include a target memory bank table 201 , a first selector 202 , a fail address input gate 203 , a fail memory bank table 204 , a second selector 205 , and a defect memory bank detector 206 .

[0086] The target storage table 201 may store information about the target storage banks TB1 and TB2 for each of the plurality of row addresses (RA1, RA2, RA3, RA4, RA5, ...). In an embodiment, the target storage table 201 may include a latch, a static RAM (SRAM), or a register. For example, information about the target storage banks TB1 and TB2 for each of the plurality of row addresses may be stored in a latch, an SRAM, or a register of the target storage table 201. The target storage banks TB1 and TB2 may include a first target storage bank TB1 and a second target storage bank TB2. Figure 6In the example, the first target memory bank TB1 and the second target memory bank TB2 can be distinguished from each other. For example, it can be distinguished that the first memory bank and the second memory bank are selected as the first target memory bank TB1 and the second target memory bank TB2, respectively, and the second memory bank and the first memory bank are selected as the first target memory bank TB1 and the second target memory bank TB2, respectively.

[0087] exist Figure 6 In the example of , the target memory banks TB1 and TB2 may be selected to interlock with each other between consecutive row addresses. For example, in the previous and subsequent row addresses of any consecutive row address, the first target memory bank of the subsequent row address may be selected as the same memory bank as the second target memory bank of the previous row address, and the second target memory bank of the subsequent row address may be selected as a memory bank different from the first target memory bank of the previous row address. However, the present invention is not limited thereto, and various combinations of target memory banks may be selected in various orders.

[0088] The first selector 202 may output the selected target bank addresses TBA1 and TBA2 in response to the input of the fail address input gate 203. The fail address input gate 203 may output the selected target bank addresses TBA1 and TBA2 in response to the fail signal FAILS. Figure 2 The described BIST circuit 124 outputs the row address RA. That is, the fail address input gate 203 can input the row address RA determined to be failed among the row addresses on which the parallel test has been performed to the first selector 202.

[0089] The first selector 202 may output target bank addresses TBA1 and TBA2 corresponding to the row address RA among the bank addresses of the target banks TB1 and TB2. For example, when the first row address RA1 from the fail address input gate 203 is input, the first selector 202 may output the first bank address BA1 and the second bank address BA2 as the target bank addresses of the first row address RA1.

[0090] The fault memory table 204 may store information about whether a fault occurs for each memory address. In an example embodiment, the fault memory table 204 may include a latch, an SRAM, or a register. For example, the information about whether a fault occurs for each memory address may be stored in a latch, an SRAM, or a register of the fault memory table 204. Figure 6In the example of , the faulty memory table 204 may store information about whether a fault occurs when the memory address is selected as the first target memory bank TB1 and when the memory address is selected as the second target memory bank TB2, respectively. In the faulty memory table 204, "1" may indicate a memory address in which a fault has occurred, and "0" may indicate a memory address in which no fault has occurred. The faulty memory table 204 may be updated based on the target memory bank addresses TBA1 and TBA2 received from the first selector 202.

[0091] In response to the input of the memory bank address BA, the second selector 205 may output information about the occurrence of a failure by corresponding to the input memory bank address. The information about whether a failure occurs may include a first target memory bank flag TBF1 and a second target memory bank flag TBF2 indicating whether a failure occurs when the input memory bank address is selected as the first target memory bank TB1 and when the input memory bank address is selected as the second target memory bank TB2, respectively.

[0092] The defective memory bank detector 206 can determine whether the memory bank corresponding to the input memory bank address is a defective memory bank by combining the logic values ​​of the first target memory bank flag TBF1 and the second target memory bank flag TBF2. For example, a memory bank in which both the values ​​of the first target memory bank flag TBF1 and the second target memory bank flag TBF2 are "1" can be determined as a defective memory bank DB, and a memory bank in which any one of the values ​​of the first target memory bank flag TBF1 and the second target memory bank flag TBF2 is "1" can be determined as a noise memory bank NB with a defect possibility. For example, the defective memory bank detector 206 can output a defect flag determined as a defective memory bank DB or a noise memory bank NB to the memory controller 110.

[0093] Fig. 7A and Figure 7B is a diagram illustrating a method for detecting a defective memory bank according to an example embodiment of the present disclosure.

[0094] Fig. 7A and Figure 7BThe result of the parallel test when there is a defect in the data path of the second memory bank 121b among the plurality of memory banks 121a to 121d is shown. Specifically, when there is a permanent defect in the data path of any memory bank, the data read from the memory bank may include an error. Due to the defect of the second memory bank 121b, the defect test RA1T of the first memory bank 121a and the second memory bank 121b with respect to the first row address RA1 may be determined as a fault, and the defect test RA2T of the second memory bank 121b and the third memory bank 121c with respect to the second row address RA2 may be determined as a fault. According to the results of the defect tests RA1T and RA2T, the faulty bank table 204 may be updated.

[0095] exist Figure 7B In the example of FIG. 1 , in both the case of the first target memory bank TB1 and the case of the second target memory bank TB2, the second memory bank address BA2 may be determined as a defective memory bank. Therefore, the second memory bank 121b corresponding to the second memory bank address BA2 may be determined as a defective memory bank.

[0096] On the other hand, the first memory bank address BA1 and the third memory bank address BA3 may be determined as a failure only when tested together with the second memory bank address BA2, and in other cases, the first memory bank address BA1 and the third memory bank address BA3 may be determined as a pass. Therefore, the first memory bank 121a and the third memory bank 121c corresponding to the first memory bank address BA1 and the third memory bank address BA3 may be determined as noise banks.

[0097] Fig. 8A and Figure 8B is a diagram illustrating a method for detecting a defective memory bank according to an example embodiment of the present disclosure.

[0098] Fig. 8A and Figure 8B The results of the parallel test when there are no defects in the data paths of the plurality of memory banks 121a to 121d are shown. Even when there are no permanent defects in the data paths of any memory bank, the data read from the memory bank may include intermittent errors due to various factors such as the order in which rows are read from the memory bank, the temperature of the memory device, and the voltage applied to the memory device.

[0099] For example, during the defect test RA2T of the second memory bank 121b and the third memory bank 121c with respect to the second row address RA2, an error may intermittently occur in the second memory bank 121b, and the defect test RA2T may be determined as a failure.

[0100] The second memory bank address BA2 and the third memory bank address BA3 may be determined to be failed only in one test result, and in other cases, the second memory bank address BA2 and the third memory bank address BA3 may be determined to be qualified. Therefore, the second memory bank 121b and the third memory bank 121c corresponding to the second memory bank address BA2 and the third memory bank address BA3 may be determined to be noise banks.

[0101] At the same time, Fig. 7A , Figure 7B , Fig. 8A and Figure 8B In the example, when the first memory bank 121a or the third memory bank 121c is tested in parallel with the second memory bank 121b, the first memory bank 121a or the third memory bank 121c may be determined as a noisy bank even though no error occurs in the data paths of the first memory bank 121a and the third memory bank 121c.

[0102] According to an example embodiment of the present disclosure, a target memory bank can be selected so that all combinations of the target memory banks are tested in parallel, and a fault memory bank table can count the number of faults that occur in each of the memory banks. In addition, a defective memory bank and a noisy memory bank can be determined based on the fault occurrence count, thereby improving the accuracy of defect detection of the memory bank.

[0103] Fig. 9 is a diagram illustrating a BIRA circuit according to an example embodiment of the present disclosure.

[0104] Fig. 9 The BIRA circuit 125b may correspond to the reference Figure 2 The BIRA circuit 125, BIRA circuit 125b may include a target memory bank table 301, a first selector 302, a faulty address input gate 303, a faulty memory bank table 304, a second selector 305 and a defective memory bank detector 306. Fig. 9 The BIRA circuit 125b may have a configuration similar to Figure 6 The structure of the BIRA circuit 125a is as follows, except that the fault memory table 304 counts the number of faults occurring for each memory address. Fig. 9 The BIRA circuit 125b is Figure 6 The BIRA circuit 125a is different.

[0105] exist Fig. 9In the example, parallel testing may be performed an even number of times for all possible combinations of target banks, and a plurality of bank addresses BA1 to BA4 may be uniformly selected as the first target bank TB1 and the second target bank TB2.

[0106] When multiple memory bank addresses BA1 to BA4 are uniformly selected, the fault count can be concentrated on the memory bank with actual defects, and the fault counts of the remaining memory banks can be dispersed. For example, when there is a defect in the data path of the second memory bank, the results of the parallel test for the first memory bank and the second memory bank, the parallel test for the second memory bank and the third memory bank, and the parallel test for the second memory bank and the fourth memory bank can all be determined as a fault. As a result of the parallel test, the fault count of the second memory bank can be counted several times, but the fault counts of the first memory bank, the third memory bank, and the fourth memory bank can be counted only once. Therefore, the memory bank with actual defects can be distinguished more accurately.

[0107] In response to the signal of the storage body address BA, a first target storage body count TBC1 and a second target storage body count TBC2 indicating each of the failure counts when the input storage body address is selected as the first target storage body TB1 and when the input storage body address is selected as the second target storage body TB2 can be input to the defective storage body detector 306.

[0108] The defective memory bank detector 306 can determine whether the memory bank corresponding to the input memory bank address is a defective memory bank by combining the logic values ​​of the first target memory bank flag TBF1 and the second target memory bank flag TBF2. Each of the first target memory bank flag TBF1 and the second target memory bank flag TBF2 can be set according to whether each of the first target memory bank count TBC1 and the second target memory bank count TBC2 is greater than or equal to a threshold value. That is, when both the first target memory bank count TBC1 and the second target memory bank count TBC2 are greater than or equal to the threshold value, the memory bank can be determined as a defective memory bank, and when any one of the first target memory bank count TBC1 and the second target memory bank count TBC2 is greater than or equal to the threshold value, the memory bank can be determined as a noise memory bank.

[0109] According to an example embodiment of the present disclosure, a memory device can perform parallel testing on two target memory banks selected from a plurality of memory memory banks in various combinations. For each parallel test, only data output from the two target memory banks can be compared with each other, thereby alleviating the overhead of data comparison, and the memory bank address of a defective memory bank can be specified by combining the parallel test results.

[0110] Meanwhile, when the memory device is implemented as a high bandwidth memory (HBM) including thousands of data lines, the overhead of the BIRA circuit specifying the bank address of the defective bank can be greatly reduced. Hereinafter, the case where the memory device according to the example embodiment of the present disclosure is implemented as HBM will be described in detail.

[0111] Fig.10 is a diagram illustrating a memory device according to an example embodiment of the present disclosure.

[0112] The memory device 400 may be implemented as HBM. Fig.10 , the memory device 400 may include a base die 410 and a plurality of core dies 420a to 420d.

[0113] The plurality of core dies 420a to 420d may be stacked on the base die 410 and may be electrically connected to the base die 410 through a plurality of through silicon vias or through substrate vias (TSVs). The plurality of TSVs may be electrically connected through micro bumps (MCBs) formed between the plurality of core dies 420a to 420d and the base die 410.

[0114] Each of the plurality of core dies 420a to 420d may include a plurality of memory banks 421a to 421d. The plurality of memory banks 421a to 421d may have the same Figure 2 The structures of the memory banks 121a to 121d described above are similar in structure.

[0115] The basic die 410 may transmit control signals to the plurality of core dies 420a to 420d, and may exchange data with the plurality of core dies 420a to 420d. The plurality of memory banks 421a to 421d may exchange data with the outside through the basic die 410. Therefore, the BIST circuit 411, the BIRA circuit 412, and the comparator 413 may be included in the basic die 410 to test the data path. However, the present invention is not limited thereto, and the comparator 413 may be included in each of the plurality of core dies 420a to 420d.

[0116] The BIST circuit 411, the BIRA circuit 412, and the comparator 413 may correspond to the reference Figure 2 The BIST circuit 124, the BIRA circuit 125, and the comparator 122 described above. According to an example embodiment of the present disclosure, the BIST circuit 411 may select a target memory bank in various combinations for each of a plurality of row addresses, and may perform a parallel test on the target memory bank, and the comparator 413 may provide a failure signal to the BIRA circuit 412 according to the parallel test result. The BIRA circuit 412 may detect a defective memory bank by analyzing a combination of the failure signal and the target memory bank.

[0117] Meanwhile, in order to select a core die of the memory device 400, a die address SID may be further defined. In order to select a target bank from a plurality of memory banks 421a to 421d included in the plurality of core dies 420a to 420d, the die address SID and the bank address BA may be further defined.

[0118] According to an example embodiment, the plurality of core dies 420a to 420d may be sequentially executed as described with reference to Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B and Fig. 9 When the parallel test and defective bank detection are sequentially performed, the complexity of the target bank table and the failed bank table can be reduced compared to the case where the parallel test and defective bank detection are performed on all of the plurality of core dies 420a to 420d.

[0119] According to an example embodiment of the present disclosure, the BIRA circuit 412 may detect a defective memory bank without directly comparing data signals having a high frequency received from a plurality of data lines, thereby alleviating the overhead of the BIRA circuit 412 .

[0120] To reduce the area and performance burden of the memory device 400 , the comparator 413 may be disposed closer to the data line than the BIRA circuit 412 .

[0121] Fig.11A and Fig. 11B is a diagram illustrating in detail a memory device according to an example embodiment of the present disclosure.

[0122] Fig.11A can correspond to the reference Fig.10 A top view of a core die 420 of any one of the core dies 420a to 420d is depicted, and Fig. 11B It is a reference Fig.10 A top view of base die 410 is depicted.

[0123] Reference Fig.11A , the core die 420 may include a plurality of memory banks 421 and a plurality of TSVs. Fig.11A In the example of FIG. 4 , a plurality of TSVs may penetrate the center of the core die 420 , and a plurality of memory banks 421 may be disposed adjacent to the plurality of TSVs capable of providing data lines.

[0124] Reference Fig. 11BThe basic die 410 may include a BIST circuit 411, a BIRA circuit 412, and a plurality of comparison units COMP1 and COMP2. The plurality of comparison units COMP1 and COMP2 may form a reference Fig.10 Comparator 413 is depicted. Other control circuits that may be included in base die 410 may be omitted.

[0125] exist Fig. 11B In the example of , multiple TSVs of the core die 420 may also penetrate the base die 410. In addition, multiple comparison units COMP1 and COMP2 may be disposed adjacent to the multiple TSVs. The comparator 413 may be implemented as an XOR tree including multiple XOR circuits. Multiple XOR circuits may be distributed around multiple data lines so as to be disposed adjacent to the TSVs providing the data lines to be compared.

[0126] When the memory device 400 is an HBM, the number of data lines included in the memory device 400 may reach several thousand. A plurality of XOR circuits disposed adjacent to the plurality of data lines may perform a comparison operation involved in a parallel test, and may provide only a failure signal generated as a result of the comparison operation to the BIRA circuit 412. Therefore, the area and performance burden for connecting the plurality of data lines to the BIRA circuit 412 may be reduced.

[0127] Fig.12 is a block diagram illustrating a system to which a memory device according to an example embodiment of the present disclosure is applied.

[0128] Reference Fig.12 , the system 1000 may include a camera 1100, a display 1200, an audio processing unit 1300, a modem 1400, DRAMs 1500a and 1500b, storage devices 1600a and 1600b, I / O devices 1700a and 1700b, and an application processor 1800 (hereinafter referred to as "AP"). The system 1000 may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a health care device, or an Internet of Things (IoT) device. In addition, the system 1000 may be implemented as a server or a personal computer.

[0129] The camera 1100 can capture still images or moving images under the control of the user, and can store the captured image / image data or send it to the display 1200. The audio processing unit 1300 can process the audio data included in the storage devices 1600a and 1600b or the content of the network. The modem 1400 can modulate and transmit a signal for wired / wireless data transmission and reception, and can demodulate the signal to restore it to the original signal on the receiving side. The I / O devices 1700a and 1700b may include devices configured to provide digital input and / or output functions, such as a universal serial bus (USB) or a storage device, a digital camera, a secure digital (SD) card, a digital versatile disc (DVD), a network adapter, a touch screen, etc.

[0130] The AP 1800 may control the overall operation of the system 1000. The AP 1800 may control the display 1200 so that a portion of the content stored in the storage devices 1600a and 1600b is displayed on the display 1200. When a user input is received through the I / O devices 1700a and 1700b, the AP 1800 may perform a control operation corresponding to the user input. The AP 1800 includes an accelerator block as a dedicated circuit for calculating artificial intelligence (AI) data, or may have an accelerator chip 1820 separated from the AP 1800. The DRAM 1500b may be additionally mounted on the accelerator block or the accelerator chip 1820. The accelerator is a functional block dedicated to performing a specific function of the AP 1800, and may include: a GPU, which is a functional block dedicated to performing graphic data processing; a neural network processing unit (NPU), which is a block dedicated to performing AI calculations and reasoning; and a data processing unit (DPU), which is a block dedicated to data transmission.

[0131] The system 1000 may include a plurality of DRAMs 1500a and 1500b. The AP 1800 may communicate with the DRAMs 1500a and 1500b by controlling the DRAMs 1500a and 1500b via a mode register setting (MRS) and a command conforming to the Joint Electron Device Engineering Council (JEDEC) standard, or by setting a DRAM interface protocol to use company-specific functions such as low voltage / high speed / reliability and cyclic redundancy check (CRC) / error correction code (ECC) functions. For example, the AP 1800 may communicate with the DRAM 1500a through an interface conforming to the JEDEC standard such as LPDDR4 and LPDDR5, and the accelerator block or accelerator chip 1820 may communicate with the DRAM 1500b by setting a new DRAM interface protocol so as to control the DRAM 1500b for an accelerator having a higher bandwidth than that of the DRAM 1500a.

[0132] although Fig.12 Only DRAM 1500a and 1500b are shown, but the present invention is not limited thereto, and any memory such as phase RAM (PRAM), static RAM (SRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), or hybrid RAM (HRAM) may be used as long as it satisfies the bandwidth, response speed, and voltage conditions of the AP 1800 or the accelerator chip 1820. The DRAM 1500a and 1500b have relatively smaller latency and bandwidth than the I / O devices 1700a and 1700b or the storage devices 1600a and 1600b. The DRAM 1500a and 1500b may be initialized at the power-on time of the system 1000, and may be used as a temporary storage space for an operating system and application data by loading the operating system and application data therein, or may be used as an execution space for various software codes.

[0133] In DRAM 1500a and 1500b, four arithmetic operations such as addition / subtraction / multiplication / division, vector operations, address operations, or fast Fourier transform (FFT) operations may be performed. In addition, functions for inferring performance may be performed in DRAM 1500a and 1500b. Here, inference may be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm may include training operations through various data learning models and inference operations for identifying data using the learned model. According to an example embodiment, an image captured by a user through camera 1100 is signal processed and stored in DRAM 1500b, and an accelerator block or accelerator chip 1820 may perform AI data operations for identifying data using data stored in DRAM 1500b and functions for inference.

[0134] Each of DRAMs 1500a and 1500b may include a plurality of memory banks and may include reference Figure 1 , Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9 , Fig.10 , Fig.11A and Fig. 11BEach of the DRAMs 1500a and 1500b can perform parallel testing of selected target memory banks in various combinations with respect to a plurality of row addresses, and can detect a defective memory bank having a defect in a data path based on a combination of target memory banks and a parallel test result for each of a plurality of row addresses.

[0135] The system 1000 may include multiple memory units or multiple storage devices 1600a and 1600b having a larger capacity than DRAM 1500a and 1500b. The accelerator block or accelerator chip 1820 may use the storage devices 1600a and 1600b to perform training operations and AI data calculations. In an example embodiment, the storage devices 1600a and 1600b may use the computing device provided in the memory controller 1610 and the calculation of the inferred AI data to more efficiently perform the training operations performed by the AP 1800 and / or the accelerator chip 1820. Each of the storage devices 1600a and 1600b may include a memory controller 1610 and a flash memory 1620. The storage devices 1600a and 1600b may store photos captured by the camera 1100, or may store data sent to a data network. For example, the storage devices 1600a and 1600b may store augmented reality / virtual reality, high definition (HD) or ultra high definition (UHD) content.

[0136] The present invention is not limited to the above-mentioned embodiments and drawings, but is limited by the appended claims. Therefore, those skilled in the art can make various substitutions, modifications or changes without departing from the scope of the present invention defined by the appended claims, and these substitutions, modifications or changes should be interpreted as being included in the scope of the present invention.

Claims

1. A memory device, comprising: a plurality of memory banks, each memory bank having a plurality of rows corresponding to a plurality of row addresses; Built-in self-test circuit, which is configured to: selecting a first target memory bank and a second target memory bank for each of the plurality of row addresses, so that each of the plurality of memory banks is selected as the first target memory bank and the second target memory bank at least once, and performing parallel testing on the first target memory bank and the second target memory bank for each of the plurality of row addresses; a comparator configured to compare first data output from the first target memory bank with second data output from the second target memory bank, and output a fault signal according to a comparison result thereof; as well as A built-in analysis circuit is configured to update a failed memory bank table indicating failure information of each of the plurality of memory banks in response to the failure signal, and is configured to determine a defective memory bank by referring to the failed memory bank table.

2. The memory device according to claim 1, wherein: In any previous row address and subsequent row address of any consecutive row addresses among the multiple row addresses, the first target storage body of the subsequent row address is the same as the second target storage body of the previous row address, and the second target storage body of the subsequent row address is different from the first target storage body of the previous row address.

3. The memory device according to claim 1, wherein: The built-in self-test circuit is configured to select the first target memory bank and the second target memory bank so that all combinations of the first target memory bank and the second target memory bank are selected from the plurality of row addresses.

4. The memory device according to claim 1, wherein: The comparator is configured as: Initialize the fault signal, and The fail signal is switched when different bits are detected in the first data and the second data.

5. The memory device according to claim 1, wherein: The built-in analysis circuit is configured to: obtaining a target row address corresponding to the failure signal from the built-in self-test circuit, and The failed bank table is updated by referring to a target bank table including information of the first target bank and the second target bank selected for each of the plurality of row addresses.

6. The memory device according to claim 1, wherein: The failure bank table includes information on whether each failure occurs in a case where each of the plurality of memory banks is a first target bank and in a case where each of the plurality of memory banks is a second target bank.

7. The memory device according to claim 6, wherein: The built-in analysis circuit is configured to determine, as the defective memory bank, a memory bank among the plurality of memory banks in which the failure occurs both in the case of the first target memory bank and in the case of the second target memory bank.

8. The memory device according to claim 6, wherein: The built-in analysis circuit is configured to determine a memory bank among the plurality of memory banks in which the failure occurs in the case of the first target bank or in the case of the second target bank as a noisy bank.

9. The memory device according to claim 6, wherein: The fault bank table includes a plurality of latches for storing information on whether the fault occurs.

10. The memory device according to claim 1, wherein: The failure bank table includes each failure count information in a case where each of the plurality of memory banks is a first target bank and in a case where each of the plurality of memory banks is a second target bank.

11. The memory device according to claim 10, wherein: The built-in analysis circuit is also configured to determine a memory bank among the plurality of memory banks in which both a first failure count in the case of the first target bank and a second failure count in the case of the second target bank are greater than or equal to a threshold as the defective bank.

12. The memory device according to claim 11, wherein: The built-in analysis circuit is also configured to determine a memory bank among the plurality of memory banks whose first failure count in the case of the first target bank or the second failure count in the case of the second target bank is greater than or equal to the threshold as a noisy bank.

13. The memory device according to claim 1, wherein: The failure bank table includes information on whether each failure occurs in a case where each of the plurality of memory banks is a first target bank and in a case where each of the plurality of memory banks is a second target bank, and Wherein, the built-in analysis circuit comprises: a target memory bank table configured to store information about the first target memory bank and the second target memory bank for each of the plurality of row addresses; a first selector configured to output a first target memory bank address and a second target memory bank address of the target row address from the target memory bank table to the fail memory bank table in response to the fail signal and the target row address; a second selector configured to output, in response to a bank address of one of the plurality of memory banks, information on whether failures of a first target bank and a second target bank corresponding to the bank address occur from the fail bank table; and A defective bank detector is configured to output a fail flag indicating whether the bank address corresponds to the defective bank by performing a logic operation on the information on whether the fail occurs.

14. The memory device according to claim 1, wherein: The built-in self-test circuit is configured to perform the parallel test by: writing the same data into the first target memory bank and the second target memory bank, and The data stored in the first target storage body and the second target storage body are read.

15. The memory device according to claim 1, wherein: The comparator includes a plurality of XOR circuits, and The multiple XOR circuits are arranged to be closer to the data paths of the multiple memory banks than the built-in analysis circuit.

16. The memory device of claim 1, wherein: The built-in analysis circuit comprises: a target memory bank table configured to store information about the first target memory bank and the second target memory bank for each of the plurality of row addresses, and The target memory table information is stored when the memory device is manufactured, or is received from outside the memory device.

17. A memory device comprising: Basic die; as well as a plurality of core dies stacked on the base die and connected to the base die through a plurality of through silicon vias, Wherein, each of the plurality of core dies comprises: a plurality of memory banks, each memory bank having a plurality of rows corresponding to a plurality of row addresses, and Wherein, the basic bare chip comprises: Built-in self-test circuit, which is configured to: selecting a target bank from the plurality of memory banks in various combinations with respect to each of the plurality of row addresses, and performing parallel testing on the target memory bank with respect to each of the plurality of row addresses; a comparator configured to compare the data output from the target memory bank and output a failure signal according to the comparison result; and A built-in analysis circuit is configured to determine a defective memory bank by referring to the fail signal and the target memory bank of each of the plurality of row addresses.

18. The memory device of claim 17, wherein: The comparator includes a plurality of XOR circuits, and Each of the plurality of XOR circuits is disposed adjacent to a through silicon via element providing a data line to be compared among the plurality of through silicon via elements.

19. The memory device of claim 17, wherein: The built-in self-test circuit is configured to sequentially perform the parallel test for each of the plurality of row addresses with respect to the plurality of core dies.

20. A memory device comprising: a plurality of memory banks, each memory bank having a plurality of rows corresponding to a plurality of row addresses; as well as The test circuit is configured as: determining, with respect to each of the plurality of row addresses, a target bank table indicating a target bank selected from the plurality of memory banks; With respect to each of the plurality of row addresses, repeatedly performing operations of writing the same data to the target memory bank, reading the data stored in the target memory bank, and outputting a failure signal according to a result of comparing the data read from the target memory bank; updating fault information of each of the plurality of memory banks by referring to the fault signal and the target bank table; as well as A defective memory bank is detected by referring to the failure information.

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