Memory repair circuit and memory repair method

Abstract

The invention provides a memory repairing circuit and a memory repairing method, and the memory repairing circuit comprises a first-stage marking module which is used for judging whether a bit is in a breakdown state or not, and carrying out the first-stage marking of the bit in the breakdown state; the flipping judgment module is used for judging whether flipping bits exist in a bit group or not, the bit group comprises a plurality of bits on the same bit line, and the flipping bits are bits with data to be written being 1 and subjected to first-level marking; the secondary marking module is used for providing overturning flag bits, the overturning flag bits are in one-to-one correspondence with the bit groups, and the overturning flag bits are used for performing secondary marking on the bit groups with overturning bits; and the data reading module is used for outputting data obtained by negating the data read out from the flipped bits subjected to the secondary marking, and outputting data read out from the bits subjected to the primary marking and data read out from the bits not subjected to the primary marking. According to the invention, the cost of bit repair can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular to a memory repair circuit and a memory repair method. Background Art

[0002] Under the condition that the existing MRAM (non-volatile magnetic random access memory) manufacturing process is not mature enough, the array will form many bits that cannot work properly. For example, some tail bits are difficult to flip and need to apply a write voltage higher than the normal bit to use it normally. Another example is that some bits have been broken down or even in an irreversible breakdown state, which also cannot be used normally. This will seriously affect the yield of the array.

[0003] To use the array function normally, the problematic bits must be removed or replaced with units that can be read and written normally.

[0004] The commonly used method is to use redundant cells in rows and columns for repair. However, in the process of using this method for repair, only the bits in the entire row or column of the array can be replaced each time. In this way, when a single-digit tailing state bit or / and a bit in an irreversible breakdown state appear in a row or a column in the array, thousands of bits in the entire row or column need to be replaced, that is, thousands of normally usable bits need to be replaced. This undoubtedly causes a waste of resources, increases the cost of bit repair, and reduces the efficiency of bit repair. Summary of the invention

[0005] To solve the above problems, the memory repair circuit and memory repair method provided by the present invention reduce the cost of bit repair and improve the bit repair efficiency by setting a primary marking module, a flip judgment module, a secondary marking module and a data reading module.

[0006] In a first aspect, the present invention provides a memory repair circuit, comprising:

[0007] A primary marking module, electrically connected to the bit on the memory, for determining whether the bit is in a breakdown state and performing a primary marking on the bit in the breakdown state;

[0008] A flip judgment module is electrically connected to the byte and the primary marking module, and is used to judge whether there is a flip bit in the byte, wherein the byte includes a plurality of bits on the same bit line, and the flip bit is a bit whose data to be written is 1 and has been marked by the primary marking;

[0009] A secondary marking module is electrically connected to the flip judgment module and is used to provide a flip flag bit, the flip flag bit corresponds to the byte one by one, and the flip flag bit is used to perform secondary marking on the byte with the flip bit;

[0010] The data reading module is electrically connected to the bit, the primary marking module and the secondary marking module, and is used to output the inverted data read from the flipped bit that has passed the secondary marking, and output the data read from the bit that has only passed the primary marking and the data read from the bit that has not passed the primary marking.

[0011] Optionally, the memory repair circuit further includes:

[0012] The write breakdown module is connected to the bit and is used to break down the burned bit and / or the tailing state bit. The tailing state bit is a bit in the memory whose required read / write voltage is greater than the normal read / write voltage used by the memory in application.

[0013] Optionally, the write breakdown module includes: a first control switch unit, a second control switch unit and a third control switch unit;

[0014] The first control switch unit is connected in series to the common bit line of the byte, the second control switch unit is connected in series to the common source line of the byte, one end of the third control switch unit is connected to the power supply end, and the other end of the third control switch is connected to the output end of the first control switch unit;

[0015] The first control switch is connected to the first control terminal, the second control switch is connected to the second control terminal, and the third control switch is connected to the third control terminal;

[0016] When a bit is broken down and burned or a bit is in a tailing state, the first control terminal controls the first control switch to be turned off, the second control terminal controls the second control switch to be turned on, and the third control terminal controls the third control switch to be turned on;

[0017] When using normal read / write voltages to read and write bits, the first control terminal controls the first control switch to be turned on, the second control terminal controls the second control switch to be turned on, and the third control terminal controls the third control switch to be turned off;

[0018] When the bit is not read, written or punctured, the third control terminal controls the third control switch to be closed.

[0019] Optionally, the primary marking module includes: a current mirror, a first voltage amplifier and a first reference resistor;

[0020] The current mirror comprises: a first current output terminal and a second current output terminal, the current outputted by the first current output terminal is equal to the current outputted by the second current output terminal;

[0021] The first voltage type amplifier comprises: a first voltage input terminal and a second voltage input terminal;

[0022] The first current output terminal is electrically connected to one end of the bit group and the first voltage input terminal respectively, the second current output terminal is electrically connected to one end of the first reference resistor and the second voltage input terminal respectively, and the other end of the first reference resistor and the other end of the bit group have the same potential;

[0023] The resistance value of the first reference resistor is greater than the resistance value of the bit in the breakdown state and less than the resistance value of the bit in the low resistance state;

[0024] The first voltage type amplifier is used to compare the potentials of the first voltage input terminal and the second voltage input terminal;

[0025] The primary marking module is also used to perform primary marking on the bit connected to the first voltage input terminal when the potential of the first voltage input terminal is less than the potential of the second voltage input terminal.

[0026] Optionally, the primary marking module further includes: a second voltage-type amplifier and a second reference resistor;

[0027] The second voltage-type amplifier includes: a third voltage input terminal and a fourth voltage input terminal, and the current mirror further includes: a third current output terminal, and the current output by the third current output terminal is equal to the current output by the first current output terminal;

[0028] The third current output terminal is electrically connected to one end of the second reference resistor and the third voltage input terminal respectively, the third voltage input terminal is electrically connected to the first current output terminal, and the other end of the second reference resistor and the other end of the bit group have the same potential;

[0029] The resistance value of the second reference resistor is greater than the resistance value of the bit in the low resistance state and less than the resistance value of the bit in the high resistance state;

[0030] The second voltage type amplifier is used for comparing the potentials of the first voltage input terminal and the third voltage input terminal;

[0031] The primary marking module is also used to output data read from the bit connected to the first voltage input terminal according to the comparison result of the second voltage type amplifier.

[0032] Optionally, the primary marking module is further used to assign a value of 1 to the judgment bit corresponding to the bit in the breakdown state, so as to perform a primary marking on the bit in the breakdown state, and assign a value of 0 to the judgment bit corresponding to the bit not in the breakdown state;

[0033] The flip judgment module includes: an OR gate and multiple AND gates;

[0034] The plurality of AND gates correspond to the bits in the byte group one by one, and one input end of the plurality of AND gates is electrically connected to the primary marking module respectively to obtain the data written in the judgment bit corresponding to the corresponding bit; the other input ends of the plurality of AND gates are respectively connected to the data writing end of the corresponding bit to obtain the data to be written corresponding to the bit;

[0035] The OR gate is electrically connected to the output ends of the plurality of AND gates; the output end of the OR gate is electrically connected to the secondary marking module to write the output value into the flip flag bit.

[0036] Optionally, the secondary marking module is further used to vote on the values ​​read from the multiple marking bits, and output the majority of the same values ​​as the flip flag value, and the flip flag value is used to distinguish whether there is a flip bit in the corresponding byte group;

[0037] The data reading module is also used to output data according to the flip flag value and the marking result of the first-level marking module.

[0038] Optionally, the data reading module includes: a bit reader, a buffer, an inverter, a logic judge and a multiplexer;

[0039] The input end of the bit reader is electrically connected to the bit, the output end of the bit reader is electrically connected to the input end of the buffer and the input end of the inverter respectively, the input end of the multiplexer is electrically connected to the output end of the buffer and the output end of the inverter respectively, the enable end of the multiplexer is electrically connected to the output end of the logic determiner, and the input end of the logic determiner is electrically connected to the secondary marking module and the primary marking module respectively;

[0040] The multi-logic judge is used to judge whether the bit connected to the bit reader is a flip bit through the secondary marking module and the primary marking module; if so, output a first enable signal; if not, output a second enable signal;

[0041] The multiplexer is used to be connected to the inverter when receiving the first enable signal, and to be connected to the buffer when receiving the second enable signal.

[0042] In a second aspect, the present invention provides a method for repairing a memory, comprising:

[0043] Reading the value in the judgment bit of the bit to judge whether the bit is in a breakdown state according to the value in the judgment bit, the judgment bit is used to perform a primary mark on the bit in the breakdown state;

[0044] Determine whether there is a flip bit in the byte; if so, perform secondary marking on the byte by flipping the flag bit; wherein the byte includes multiple bits on the same bit line, and the flip bit is a bit whose data to be written is 1 and has been marked by the primary level;

[0045] When performing a read operation on a bit, the judgment bit and the flip flag bit corresponding to the bit are read to determine whether the bit is in a breakdown state and whether the byte group where the bit is located is secondarily marked; if the bit is in a breakdown state and the byte group where the bit is located is secondarily marked, the data obtained by inverting the data read from the flip bit that has been secondarily marked is output; if the bit is not in a breakdown state or the byte group where the bit is located is not secondarily marked, the data read from the bit is output.

[0046] Optionally, before the step of reading the value in the determination bit of the bit to determine whether the bit is in a breakdown state according to the value in the determination bit, the method further includes:

[0047] Identify whether a bit in the memory is a burned bit or a tailing bit, and perform breakdown on the burned bit and / or the tailing bit.

[0048] Optionally, the determination bit has a value of 1 for a bit mark in a breakdown state and a value of 0 for a bit mark not in a breakdown state;

[0049] The flip flag has a value of 1 for bytes marked with secondary marking and a value of 0 for bytes not marked with secondary marking.

[0050] Optionally, the step of reading a value in a determination bit of a bit to determine whether the bit is in a breakdown state according to the value in the determination bit includes:

[0051] Equal currents are respectively passed through the bit and the first reference resistor, and the relative sizes of the resistance value of the bit and the resistance value of the first reference resistor are compared. The resistance value of the first reference resistor is greater than the resistance value of the bit in the breakdown state and less than the resistance value of the bit in the low resistance state. If the resistance value of the bit is less than the resistance value of the first reference resistor, it is determined that the bit is in the breakdown state; if the resistance value of the bit is greater than the resistance value of the first reference resistor, it is determined that the bit is not in the breakdown state.

[0052] Optionally, when performing a read operation on a bit, reading a determination bit and a flip flag bit corresponding to the bit to determine whether the bit is in a breakdown state and whether the byte group where the bit is located is secondarily marked; if the bit is in a breakdown state and the byte group where the bit is located is secondarily marked, outputting data obtained by inverting the data read from the flipped bit that has been secondarily marked; if the bit is not in a breakdown state or the byte group where the bit is located is not secondarily marked, the step of outputting the data read from the bit comprises:

[0053] Equal currents are respectively passed through the bit and the second reference resistor, and the relative sizes of the resistance value of the bit and the resistance value of the second reference resistor are compared. The resistance value of the second reference resistor is greater than the resistance value of the bit in the low resistance state and less than the resistance value of the bit in the high resistance state. If the resistance value of the bit is less than the resistance value of the second reference resistor, it is determined that the data read from the bit is 0; if the resistance value of the bit is greater than the resistance value of the second reference resistor, it is determined that the data read from the bit is 1.

[0054] Optionally, determining whether there is a flip bit in the byte; if so, performing a secondary marking on the byte where the bit is located by flipping the flag bit includes:

[0055] Determine whether there is a flip bit in the byte; if so, set the flip flag to 1 to mark the byte secondary through the flip flag; if not, set the flip flag to 0 low.

[0056] Optionally, the flip flag bit includes a plurality of marking bits;

[0057] The step of determining whether there is a flip bit in the byte; if so, setting the flip flag to 1 to perform secondary marking on the byte by the flip flag; if not, setting the flip flag to 0 includes:

[0058] Determine whether there is a flip bit in the byte; if so, set multiple flag bits to high to perform secondary marking on the byte through multiple flip bits; if not, set multiple flip bits to 0;

[0059] When performing a read operation on a bit, the step of reading the judgment bit and the flip flag bit corresponding to the bit to judge whether the bit is in a breakdown state and whether the byte group where the bit is located has been secondary marked includes:

[0060] By voting on the values ​​read from multiple mark bits, the majority of the same values ​​are output as the flip flag value, and the flip flag value is used to distinguish whether there is a flip bit in the corresponding byte.

[0061] The memory repair circuit and memory repair method provided by the embodiments of the present invention can accurately mark the flipped bits by setting a primary marking module, a flip judgment module, a secondary marking module and a data reading module, and flip the data originally stored in the bits when reading data. There is no need to set redundant bits to replace the bits in the breakdown state, thereby reducing the cost of bit repair and improving the efficiency of bit repair. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0063] Figure 1 is a schematic structural diagram of a memory repair circuit according to an embodiment of the present application;

[0064] Figure 2 is a schematic structural diagram of a write breakdown module according to an embodiment of the present application;

[0065] Figure 3 This is a schematic structural diagram of a primary marking module according to an embodiment of the present application;

[0066] Figure 4 is a schematic structural diagram of a flip judgment module according to an embodiment of the present application;

[0067] Figure 5 A schematic structural diagram of a data reading module according to an embodiment of the present application;

[0068] Figure 6 A schematic diagram of relative positions of bits according to an embodiment of the present application;

[0069] Figure 7 A schematic diagram of the corresponding relationship between the determination bit and the bit unit according to an embodiment of the present application;

[0070] Figure 8 A diagram showing the corresponding relationship of data stored in each bit after data is written in an embodiment of the present application;

[0071] Fig. 9 A diagram showing the corresponding relationship of data stored in each bit after data is written in an embodiment of the present application;

[0072] Fig.10 A logic diagram of inverting and reading out data according to an embodiment of the present application;

[0073] Fig.11 A logical diagram of normal data reading according to an embodiment of the present application;

[0074] Fig.12 A schematic flowchart of a memory repair method according to an embodiment of the present application. DETAILED DESCRIPTION

[0075] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0076] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0077] In a first aspect, an embodiment of the present invention provides a memory repair circuit, see Figure 1 , the memory repair circuit comprises:

[0078] A primary marking module 1 is electrically connected to the bit on the memory, and is used to determine whether the bit is in a breakdown state, and to perform a primary marking on the bit in the breakdown state;

[0079] The flip judgment module 2 is electrically connected to the byte 6 and the primary marking module 1, and is used to judge whether there is a flip bit in the byte 6, wherein the byte 6 includes a plurality of bits on the same bit line, and the flip bit is a bit whose data to be written is 1 and has been marked by the primary mark;

[0080] The secondary marking module 3 is electrically connected to the flip judgment module 2 and is used to provide a flip flag bit, the flip flag bit corresponds to the byte 6 one by one, and the flip flag bit is used to perform secondary marking on the byte 6 with the flip bit;

[0081] The data reading module 4 is electrically connected to the bit, the primary marking module 1 and the secondary marking module 3, and is used to output the inverted data read from the flipped bit that has passed the secondary marking, and output the data read from the bit that has only passed the primary marking and the data read from the bit that has not passed the primary marking.

[0082] The memory repair circuit can accurately mark the flipped bits by setting a primary marking module 1, a flip judgment module 2, a secondary marking module 3 and a data reading module 4, and flip the data originally stored in the bits when reading data. There is no need to set redundant bits to replace the bits in the breakdown state, thereby reducing the cost of bit repair and improving the efficiency of bit repair.

[0083] Furthermore, the memory repair circuit further includes: a write breakdown module 5. The write breakdown module 5 is connected to the bit and is used to break down the burned bit and / or the tailing state bit, and the tailing state bit is a bit in the memory whose required read / write voltage is greater than the normal read / write voltage used by the memory when it is used. Among them, one write breakdown module 5 can break down the bits in one or more groups of bits, and this embodiment does not specifically limit this.

[0084] In this embodiment, the write breakdown module 5 is used to break down the burned bits and the tailing bits. By setting the write breakdown module 5, it is possible to prevent the burned bits and the tailing bits from being read and written as normal bits, thereby affecting the yield of the data storage array. Specifically, after the burned bits and the tailing bits are broken down by the write breakdown module 5, the memory repair circuit can invert the data read from the bits where the data to be written is 1 and is in the breakdown state when reading data, thereby ensuring the yield of the data storage array.

[0085] Combination Figure 2 The write breakdown module 5 includes: a first control switch unit M1, a second control switch unit M2 and a third control switch unit M3.

[0086] The first control switch unit M1 is connected in series to the common bit line of the byte 6, the second control switch unit M2 is connected in series to the common source line of the byte 6, one end of the third control switch unit M3 is connected to the power supply end, and the other end of the third control switch is connected to the output end of the first control switch unit M1.

[0087] The first control switch is connected to the first control terminal, the second control switch is connected to the second control terminal, and the third control switch is connected to the third control terminal.

[0088] When the bit is broken down and burned or the bit is in the tailing state, the first control terminal controls the first control switch to be turned off, the second control terminal controls the second control switch to be turned on, and the third control terminal controls the third control switch to be turned on. When the bit is read and written using the normal read and write voltage, the first control terminal controls the first control switch to be turned on, the second control terminal controls the second control switch to be turned on, and the third control terminal controls the third control switch to be turned off. When the bit is not read and written and broken down, the third control terminal controls the third control switch to be turned off.

[0089] In other words, in this embodiment, the first control end controls the on and off of the first control switch by receiving the CSL1 signal, the second control end controls the on and off of the second control switch by receiving the CSL2 signal, and the third control end controls the on and off of the third control switch by receiving the Break_down_EN signal.

[0090] Specifically, when the CSL1, CSL2 and Break_down_EN signals are all low, the first control switch, the second control switch and the third control switch are all in the off state, and at this time, the bits in the byte group 6 are not read or written.

[0091] When the CSL1 and CSL2 signals are both high and the Break_down_EN signal is low, the first control switch and the second control switch are both in the open state, and the third control switch is in the closed state. At this time, normal read and write operations can be performed on the bits in byte group 6.

[0092] When the CSL1 signal is low, and the CSL2 and Break_down_EN signals are both high, the first control switch is in the closed state, and the second control switch and the third control switch are both in the open state. At this time, the bit of byte group 6 can be written and destroyed. In this state, the voltage loaded on both ends of the selected MTJ can break down the selected MTJ for a short time, thereby realizing the write-destroy function.

[0093] Combination Figure 3 The first-level marking module 1 includes: a current mirror 11, a first voltage-type amplifier SA2 and a first reference resistor 12.

[0094] The current mirror 11 includes: a first current output terminal and a second current output terminal, and the current output by the first current output terminal is equal to the current output by the second current output terminal; the first voltage type amplifier SA2 includes: a first voltage input terminal and a second voltage input terminal.

[0095] The first current output terminal is electrically connected to one end of the byte group 6 and the first voltage input terminal respectively, and the second current output terminal is electrically connected to one end of the first reference resistor 12 and the second voltage input terminal respectively. The other end of the first reference resistor 12 and the other end of the byte group 6 have the same potential.

[0096] The resistance of the first reference resistor 12 is greater than the resistance of the bit in the breakdown state and less than the resistance of the bit in the low resistance state; the first voltage amplifier SA2 is used to compare the potentials of the first voltage input terminal and the second voltage input terminal; the first-level marking module 1 is also used to perform a first-level marking on the bit connected to the first voltage input terminal when the potential of the first voltage input terminal is less than the potential of the second voltage input terminal.

[0097] It should be noted that the other end of the first reference resistor 12 and the other end of the byte group 6 can be connected to the same connection point to achieve the same potential, or they can be connected to different circuit structures to achieve the same potential. In this embodiment, when the first voltage amplifier SA2 is used to compare the potentials of the first voltage input terminal and the second voltage input terminal, the other end of the first reference resistor 12 and the other end of the byte group 6 are both grounded.

[0098] Similarly, in addition to using the current mirror 11 to ensure that the current input to the first reference resistor 12 and the byte 6 is the same, the first reference resistor 12 and the byte 6 can also be connected in series to achieve the same input current to the two. However, this method requires adjustment of the specific circuit structure of the primary marking module 1, including a first voltage-type amplifier SA2 that respectively detects the voltage drop across the first reference resistor 12 and the voltage drop across the byte 6, and when the voltage drop across the byte 6 is greater than the voltage drop across the first reference resistor 12, the bit connected to the first voltage input terminal is marked at the primary level. This embodiment does not elaborate on the circuit structure of this method.

[0099] In this embodiment, the current mirror 11 is used to ensure that the currents input to the first reference resistor 12 and the byte 6 are the same, and the structure of the primary marking module 1 is simplified, thereby reducing the complexity of manufacturing the memory repair circuit.

[0100] In an optional embodiment, the primary marking module 1 further includes: a second voltage-type amplifier SA1 and a second reference resistor 13 .

[0101] The second voltage amplifier SA1 includes: a third voltage input terminal and a fourth voltage input terminal. The current mirror 11 also includes: a third current output terminal. The current output by the third current output terminal is equal to the current output by the first current output terminal.

[0102] The third current output terminal is electrically connected to one end of the second reference resistor 13 and the third voltage input terminal respectively, the third voltage input terminal is electrically connected to the first current output terminal, and the other end of the second reference resistor 13 has the same potential as the other end of the bit group 6. The resistance of the second reference resistor 13 is greater than the resistance of the bit in the low resistance state, and less than the resistance of the bit in the high resistance state.

[0103] The second voltage amplifier SA1 is used to compare the potentials of the first voltage input terminal and the third voltage input terminal. The primary marking module 1 is also used to output the data read from the bit connected to the first voltage input terminal according to the comparison result of the second voltage amplifier SA1.

[0104] It should be noted that the other end of the second reference resistor 13 and the other end of the byte group 6 can be connected to the same connection point to achieve the same potential, or they can be connected to different circuit structures to achieve the same potential. In this embodiment, when the second voltage-type amplifier SA1 is used to compare the potentials of the third voltage input terminal and the fourth voltage input terminal, the other end of the second reference resistor 13 and the other end of the byte group 6 are both grounded.

[0105] Similarly, in addition to using the current mirror 11 to ensure that the current input to the second reference resistor 13 and the byte 6 is the same, the second reference resistor 13 and the byte 6 can also be connected in series to achieve the same input current to the two. However, this method requires adjustment of the specific circuit structure of the first-level marking module 1, including the second voltage-type amplifier SA1 that respectively detects the voltage drop across the second reference resistor 13 and the voltage drop across the byte 6. This embodiment does not elaborate on the circuit structure of this method.

[0106] In this embodiment, the current mirror 11 is used to ensure that the current input to the second reference resistor 13 and the current input to the byte 6 are the same, and the structure of the primary marking module 1 is simplified, thereby reducing the complexity of manufacturing the memory repair circuit.

[0107] Furthermore, the primary marking module 1 uses two voltage-type sensitive amplifiers, namely the first voltage-type amplifier SA2 and the second voltage-type amplifier SA1, the first reference resistor 12, the second reference resistor 13 and the current mirror 11 to realize the function. The working principle of the primary marking module 1 is described in detail below.

[0108] The primary marking module 1 separates the array current Iarray flowing into the byte 6, the determination bit reference current Ired flowing into the first reference resistor 12, and the array reference current Iref flowing into the second reference resistor 13 through the current mirror 11. Due to the action of the current mirror 11, the values ​​of the three currents are the same at this time. The branch where the array current Iarray is located and the branch where the array reference current Iref is located are connected to the second voltage amplifier SA1, and the branch where the array current Iarray and the determination bit reference current Ired are connected to the first voltage amplifier SA2, wherein the resistance value of the second reference resistor 13 connected to the branch of the array reference current Iref is less than the resistance value of the MTJ RAP state (high resistance state of the magnetic tunnel junction) and greater than the resistance value of the MTJ RP state (high resistance state of the magnetic tunnel junction), wherein the resistance value of the first reference resistor 12 connected to the branch of the determination bit reference current Ired is greater than the resistance value of the MTJ break down state (breakdown state of the magnetic tunnel junction) and less than the reference resistance of the MTJ RP state, and the resistance relationship is: MTJ RAP state>MTJ RP state>MTJ breakdown state.

[0109] Since the resistance downstream of each branch is different, the voltage at the access point is also different. The voltages at two points can be compared through the corresponding voltage-type sensitive amplifier. When the voltage at the access point of the branch where the array current Iarray is located is higher than the access point of the branch where Iref is located, it means that the resistance in the array current Iarray is greater than the second reference resistor 13. At this time, the connected bit is in the RAP state, and the second voltage-type amplifier SA1 reads the data as 1. When the voltage at the access point of the branch where the array current Iarray is located is lower than the access point of the branch where the array reference current Iref is located, it means that the resistance in the array current Iarray is less than the second reference resistor 13. At this time, the connected bit is in the RP state. The second voltage-type amplifier SA1 reads the data as 0.

[0110] Similarly, the first voltage amplifier SA2 can output the comparison result between the array resistance and the judgment bit reference resistance. If the array resistance is greater than the first reference resistance 12, it means that the connected bit is a normal bit, and the first voltage amplifier SA2 outputs 0. If the array resistance is less than the first reference resistance 12, it means that the bit is in a break down state, and the first voltage amplifier SA2 outputs 1. That is, the primary marking module 1 is also used to assign a value of 1 to the judgment bit corresponding to the bit in the breakdown state, so as to perform a primary marking on the bit in the breakdown state; and assign a value of 0 to the judgment bit corresponding to the bit not in the breakdown state.

[0111] It should be noted that the judgment bit can be provided by an additional storage module, such as a register, or by the bit corresponding to the judgment bit itself. In this embodiment, the judgment bit is provided by the corresponding bit itself. It can be understood that the bit stores the judgment bit and the data bit at the same time. In other words, the bit in the memory has three storage states, namely, 0 state, 1 state and X state. Among them, the data bit in the bit corresponds to the 0 state and 1 state of the bit; the judgment bit in the bit corresponds to the X state of the bit.

[0112] The resistance value provided by the bit in different storage states is different; the X state is also called the short state, and the resistance value of the bit will be very small at this time, such as 10kOhm when the bit is in the 1 state, 3kOhm when the bit is in the 0 state, and only 200Ohm when the bit is in the X state, but not limited to this. When the first-level mark is performed on the bit in the breakdown state, the bit is in the X state.

[0113] In this embodiment, the advantage of using two voltage-type sense amplifiers is that the voltage of the connected bit can be compared with the voltage of the first reference resistor 12 and the second reference resistor 13 at the same time, and two results can be output. For example, when SA1=1, SA2=1, it can be determined that the connected bit is in the rap state; when SA1=0, SA2=1, it can be determined that the connected bit is in the rp state; when SA1=0, SA2=0, it can be determined that the connected bit is in the break down state. It should be noted that in this embodiment, there is no such situation that SA1=1, SA2=0, and no further elaboration is made on this.

[0114] It can be understood that a primary marking module 1 can perform primary marking on bits in one or more groups of bytes 6. Specifically, when the data storage array is small, the primary marking module 1 can be electrically connected to a group of bytes 6. For example, if the size of the data storage array is 30*30 and its bit width is 30 bits, the data storage array includes 30 groups of bytes and 30 primary marking modules 1, and each group of bytes is electrically connected to a primary marking module 1, so that each primary marking module 1 performs primary marking on the corresponding bytes.

[0115] When the data storage array is large, the primary marking module 1 can be electrically connected to multiple groups of bytes 6. Figure 3 , if the size of the data storage array is 1024*1024 and its bit width is 16bit, then the data storage array includes 30 groups of bytes and 30 first-level marking modules 1, and every 64 groups of bytes are electrically connected to a first-level marking module 1, so that each first-level marking module 1 performs first-level marking on the corresponding 64 groups of bytes. It should be noted that in order to ensure that the first-level marking module 1 can orderly perform first-level marking on the bits in the corresponding 64 groups of bytes, the 64 groups of bytes are selectively electrically connected to the corresponding first-level marking module 1 through a multiplexer (MUX). It can be understood that in the data storage array, 64 groups of bytes correspond to one bit width. When reading the data stored in the bit, the multiplexer will connect the byte where the word line selected bit is located as the target byte to the first-level marking module 1.

[0116] In this embodiment, it is taken as an example that one primary tag module 1 corresponds to 64 groups of bytes 6, but the present invention is not limited thereto.

[0117] Combination Figure 4 , the flip judgment module 2 includes: an OR gate and multiple AND gates.

[0118] Multiple AND gates correspond to the bits in the byte group 6 one by one, and one input end of the multiple AND gates is electrically connected to the primary marking module 1 to obtain the data written in the judgment bit corresponding to the corresponding bit; the other input ends of the multiple AND gates are connected to the data writing end of the corresponding bit to obtain the data to be written corresponding to the bit. The OR gate is electrically connected to the output ends of the multiple AND gates; the output end of the OR gate is electrically connected to the secondary marking module 3 to write the output value into the flip flag bit.

[0119] In this embodiment, the flip judgment module 2 corresponds to the byte group 6 one by one. One input end of the plurality of AND gates is electrically connected to the output end of the first voltage amplifier SA2 in the primary marking module 1. It should be noted that when the first voltage amplifier SA2 is electrically coupled to different bits in the byte group 6, the first voltage amplifier SA2 will receive different enable signals (SA_flag0, SA_flag1, SA_flag2, ..., SA_flagn) to electrically couple the first voltage amplifier SA2 with the corresponding AND gate to transmit the judgment bit data (X DATA0, X DATA1, XDATA2, ..., X DATAn) output by the first voltage amplifier SA2 to the corresponding AND gate. At the same time, the AND gate will receive the storage data that the write driver is ready to write into the corresponding bit.

[0120] It should be noted that n is determined by the bit width of the data storage array. For example, when the bit width of the data storage array is 16, n is 16.

[0121] By setting the flip judgment module 2, the result of the read judgment bit is used to select the data written to the flip flag bit. Specifically, if the judgment bits in the group are all low, that is, the data stored in all the judgment bits in byte group 6 are all 0, then the flip flag bit is written as 0; if there is a high bit in the judgment bit in the group, that is, there is a judgment bit in which the data stored in all the judgment bits in byte group 6 are all 1, and the data to be written in the bit corresponding to the high judgment bit is 0, then the flip flag bit is still written as 0. If there is a high bit in the judgment bit in the group, and the data to be written in the bit corresponding to the high judgment bit is 1, then the flip flag bit of this group is written as 1. The reason is that the broken-down bit can only read 0. When the data to be written is 1, it is inverted by flipping the flag bit when reading, so that the purpose of repairing the broken-down bit can be achieved.

[0122] Combination Figure 5 The data reading module 4 includes: a bit reader 41, a buffer 42, an inverter 43, a logic judge 44 and a multiplexer 45.

[0123] Among them, the input end of the bit reader 41 is electrically connected to the bit; the output end of the bit reader 41 is electrically connected to the input end of the buffer 42 and the input end of the inverter 43 respectively; the input end of the multiplexer 45 is electrically connected to the output end of the buffer 42 and the output end of the inverter 43 respectively; the enable end of the multiplexer 45 is electrically connected to the output end of the logic judge 44; the input end of the logic judge 44 is electrically connected to the secondary marking module 3 and the primary marking module 1 respectively; the output end of the multiplexer 45 outputs data as the output end of the data reading module 4.

[0124] The multi-logic determiner 44 is used to determine whether the bit connected to the bit reader 41 is a flip bit through the secondary marking module 3 and the primary marking module 1; if so, output a first enable signal; if not, output a second enable signal. The multiplexer 45 is used to connect to the inverter 43 when receiving the first enable signal, and connect to the buffer 42 when receiving the second enable signal.

[0125] A data reading module 4 can read data from bits in one or more groups of bytes. In this embodiment, the data reading module 4 corresponds to multiple groups of bytes, that is, the data reading module 4 corresponds to the primary tag module one by one. Among them, the logic determiner 44 is an AND gate device; the input end of the bit reader 41 is electrically coupled to the output end of the second voltage amplifier SA1 to achieve electrical connection with the bit; the multi-logic determiner 44 is electrically coupled to the output end of the first voltage amplifier SA2 to determine whether the connected bit is in a breakdown state.

[0126] It can be understood that in this embodiment, the bit reader 41 is the second voltage-type amplifier SA1 .

[0127] Furthermore, the secondary marking module 3 is also used to vote on the values ​​read from the multiple marking bits, and output the majority of the same values ​​as the flip flag value. The flip flag value is used to distinguish whether there is a flip bit in the corresponding byte group 6. The data reading module 4 is also used to output data according to the flip flag value and the marking result of the primary marking module 1.

[0128] In this embodiment, the secondary marking module 3 outputs three sets of flip flag values ​​from a three-mode redundant (3-bit) array in the data storage array of the memory, but is not limited thereto. This three-mode redundant array is consistent with the normal data storage array, and a result (1 bit) is obtained by voting through three flip flag bits, and this result is output as the final flip flag bit. By setting up a three-mode redundant array, the accuracy of the memory repair circuit can be guaranteed, and the occurrence of misjudgment of data inversion caused by damage to the bit occupied by a single flip flag bit affecting the read operation can be avoided.

[0129] In this embodiment, combined with Figure 6, eight array bits (Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7) are configured with three flip flags (Flag0, Flag1, Flag2), which is a data group, to illustrate the working principle of the memory repair circuit mentioned above. Among them, eight array bits are a group of bytes 6; the number of array bits and judgment flags can be positioned at any number of bits, and this embodiment does not specifically limit this; array bit Data2 is found to be a tailing state bit after testing.

[0130] First, the array bit Data2 is written and destroyed. Specifically, the array bit Data2 is selected and M1 is driven to close, M2 to open, and M3 to open. After the path is formed, the voltage loaded on the MTJ is too high, causing the MTJ (magnetic tunnel junction) in the array bit Data2 to burn out. The remaining unselected cells are not written. At this time, the resistance value of the array bit Data2 drops from several thousand ohms to several hundred ohms, which is much smaller than the resistance value of the normal MTJ. In this way, the write and destroy operation of the array bit Data2 is completed. The subsequent read and write operations on the byte group 6 can be carried out normally.

[0131] After that, when performing a write operation, the operation of reading the judgment bit is performed first. The judgment bit read out of the normal bit is 0, and the judgment bit read out of the bit in the breakdown state is 1. Figure 7 . Since the array bit Data2 was previously written out, the judgment bit corresponding to the array bit Data2 is high in the read judgment bit. At this time, it is necessary to compare the data to be written into the array bit Data2. At this time, the data to be written corresponding to the array bit Data2 is 1. According to the corresponding logic circuit, when the judgment bit corresponding to the bit is high and the data to be written to the bit corresponding to this judgment bit is high, the three flip flag bits of this group are all set to 1 and written. Figure 8 However, when the judgment bit is high and the data written to the bit corresponding to this judgment bit is low, or when all the judgment bits in the group are low, the three flip flag bits are set to 0 and written, and the data is directly written to the corresponding array bits. Fig. 9 .

[0132] Finally, when performing a read operation, the three flip flags and the data stored in the eight array bits need to be read and processed, so as to output according to the conditions of the three flip flags in the group. Fig.10, even if one of the three flip flags is damaged, resulting in the read Flag0=1, Flag1=1, Flag2=0, at this time, through the triple-module redundant array, the final FLAG=1 is obtained, and the read data needs to be inverted before output. In this way, the actual output data can be kept consistent with the actual written data, that is, the data to be written, and the memory repair is completed.

[0133] Similarly, combined Fig.11 , when FLAG=0, the data stored in the array bit can be directly output. It should be noted that in practical applications, the number of flip flag bits and data bits can be configured according to the yield of the actual data storage array. In addition, the memory repair circuit can also be used in conjunction with ECC (error checking and correction) technology to improve the yield of the data storage array. This embodiment does not specifically limit this.

[0134] The memory repair circuit provided by the present invention can promptly repair the corresponding bits during each read operation, effectively solving the errors of damaged bits that occur during the life of the memory, improving the reliability of the memory, and greatly improving the repair efficiency. In addition, the memory repair circuit occupies a small area of ​​the memory, which improves the chip yield while reducing the cost of the memory.

[0135] It should be noted that the memory repair circuit can also repair multiple broken down and burned bits and / or tailing bits in the same bit group 6. In the specific implementation process, corresponding logic selection circuits need to be added, which is not specifically limited in this embodiment.

[0136] In a second aspect, an embodiment of the present invention provides a method for repairing a memory, Fig.12 , the repair method includes steps S101 to S103:

[0137] Step S101: Read the value in the determination bit of the bit to determine whether the bit is in a breakdown state according to the value in the determination bit.

[0138] The judgment bit is used to mark the bits in the breakdown state at the first level;

[0139] Step S102: Determine whether there is a flip bit in byte 6; if so, perform secondary marking on byte 6 by using the flip flag bit.

[0140] Among them, byte 6 includes multiple bits on the same bit line, and the flip bit is a bit whose data to be written is 1 and has been marked at the first level. In this embodiment, the second-level marking of byte 6 by flipping the flag bit is to set the value of the flip flag bit corresponding to byte 6 to 1; if it is determined that there is no flip bit in byte 6, the value of the flip flag bit corresponding to byte 6 is set to 0.

[0141] Step S103: when performing a read operation on a bit, read the judgment bit and the flip flag bit corresponding to the bit to judge whether the bit is in a breakdown state and whether the byte group 6 where the bit is located is secondarily marked; if the bit is in a breakdown state and the byte group 6 where the bit is located is secondarily marked, output the data obtained by inverting the data read from the flipped bit that has been secondarily marked; if the bit is not in a breakdown state or the byte group 6 where the bit is located is not secondarily marked, output the data read from the bit.

[0142] In an optional embodiment, before the step of reading the value in the determination bit of the bit to determine whether the bit is in a breakdown state according to the value in the determination bit, the repair method further includes:

[0143] Identify whether a bit in the memory is a burned bit or a tailing bit, and perform breakdown on the burned bit and / or the tailing bit.

[0144] In an optional embodiment, the determination bit marks a value of 1 for a bit in a breakdown state and a value of 0 for a bit not in a breakdown state;

[0145] The flip flag has a value of 1 for byte 6 marked with secondary marking and a value of 0 for byte 6 marked without secondary marking.

[0146] In an optional embodiment, the step of reading a value in a determination bit of a bit to determine whether the bit is in a breakdown state according to the value in the determination bit includes:

[0147] Equal currents are respectively passed through the bit and the first reference resistor 12, and the relative sizes of the resistance value of the bit and the resistance value of the first reference resistor 12 are compared. The resistance value of the first reference resistor 12 is greater than the resistance value of the bit in the breakdown state and less than the resistance value of the bit in the low resistance state. If the resistance value of the bit is less than the resistance value of the first reference resistor 12, it is determined that the bit is in the breakdown state; if the resistance value of the bit is greater than the resistance value of the first reference resistor 12, it is determined that the bit is not in the breakdown state.

[0148] In an optional embodiment, when performing a read operation on a bit, reading a determination bit and a flip flag bit corresponding to the bit to determine whether the bit is in a breakdown state and whether the byte group 6 where the bit is located is secondarily marked; if the bit is in a breakdown state and the byte group 6 where the bit is located is secondarily marked, outputting data obtained by inverting the data read from the flipped bit that has been secondarily marked; if the bit is not in a breakdown state or the byte group 6 where the bit is located is not secondarily marked, the step of outputting the data read from the bit includes:

[0149] Equal currents are respectively passed through the bit and the second reference resistor 13, and the relative sizes of the resistance value of the bit and the resistance value of the second reference resistor 13 are compared. The resistance value of the second reference resistor 13 is greater than the resistance value of the bit in the low resistance state and less than the resistance value of the bit in the high resistance state; if the resistance value of the bit is less than the resistance value of the second reference resistor 13, it is determined that the data read from the bit is 0; if the resistance value of the bit is greater than the resistance value of the second reference resistor 13, it is determined that the data read from the bit is 1.

[0150] In an optional embodiment, determining whether there is a flip bit in byte 6; if so, performing a secondary marking on byte 6 where the bit is located by using a flip flag bit includes:

[0151] Determine whether there is a flip bit in byte 6; if so, set the flip flag to 1 to perform secondary marking on byte 6 through the flip flag; if not, set the flip flag to 0 low.

[0152] In an optional embodiment, the flip flag bit includes a plurality of mark bits;

[0153] The step of determining whether there is a flip bit in byte 6; if so, setting the flip flag to 1 to perform secondary marking on byte 6 by the flip flag; if not, setting the flip flag to 0 includes:

[0154] Determine whether there is a flip bit in byte 6; if so, set multiple flag bits to high to perform secondary marking on byte 6 through multiple flip bits; if not, set multiple flip bits to 0;

[0155] When performing a read operation on a bit, the step of reading the judgment bit and the flip flag bit corresponding to the bit to judge whether the bit is in a breakdown state and whether the byte group 6 where the bit is located is secondary marked includes:

[0156] By voting on the values ​​read from the multiple mark bits, the majority of the same values ​​are output as the flip flag value, and the flip flag value is used to distinguish whether there is a flip bit in the corresponding byte 6.

[0157] The repair method of this memory takes into account that the repair ability of redundancy repair is not high, and the use of ECC repair is relatively wasteful of area. Therefore, the repair method of flip flag bit inversion is adopted. After marking the damaged bit, the data to be written is compared, and the flip flag bit is written according to the comparison result. When reading, the flip flag bit is used as logic to replace the bits in the breakdown state bit by bit. Because the flip flag bit is also part of the data storage array, there is a certain probability of error. In order to prevent the flip flag bit from being written incorrectly, a triple-module redundant flip flag bit function is added, that is, as long as two judgment bits are not wrong at the same time, the function can be normal.

[0158] At the same time, when the chip performs a write operation, the repair method first reads the judgment bit. When the judgment bit finds that there is a bit in the breakdown state in the read data group, the judgment bit is high. At this time, it is judged whether the data to be written to the bit corresponding to this flag bit is 0. If so, it is written normally. If not, the three flip flag bits of this group of data are set high. When the chip performs a read operation, if at least two of the flip flag bits are high, the read data is inverted. If at least two of the flip flag bits are low, it is read normally, thereby completing the repair of the memory.

[0159] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0160] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0161] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A memory repair circuit, characterized in that: include: A primary marking module, electrically connected to the bit on the memory, for determining whether the bit is in a breakdown state and performing a primary marking on the bit in the breakdown state; A flip judgment module, electrically connected to the byte group and the primary marking module, for judging whether there is a flip bit in the byte group, wherein the byte group includes a plurality of bits on the same bit line, and the flip bit is a bit whose data to be written is 1 and has been marked by the primary marking; A secondary marking module, electrically connected to the flip judgment module, for providing a flip flag, wherein the flip flag corresponds to the byte one-to-one, and the flip flag is used to perform secondary marking on the byte with the flip bit; A data reading module is electrically connected to the bit, the primary marking module and the secondary marking module, and is used to output data that is the inversion of the data read from the flipped bit that has been secondary marked, and to output data read from the bit that has only been primary marked and data read from the bit that has not been primary marked.

2. The memory repair circuit according to claim 1, characterized in that: The memory repair circuit also includes: A write breakdown module is connected to the bit and is used to break down the burned bit and / or the tailing state bit. The tailing state bit is a bit in the memory that requires a read / write voltage greater than a normal read / write voltage used by the memory during application.

3. The memory repair circuit according to claim 2, characterized in that: The write breakdown module includes: a first control switch unit, a second control switch unit and a third control switch unit; The first control switch unit is connected in series to the common bit line of the bit group, the second control switch unit is connected in series to the common source line of the bit group, one end of the third control switch unit is connected to the power supply end, and the other end of the third control switch is connected to the output end of the first control switch unit; The first control switch is connected to a first control terminal, the second control switch is connected to a second control terminal, and the third control switch is connected to a third control terminal; When the burned bit or the tailing bit is broken down, the first control end controls the first control switch to be turned off, the second control end controls the second control switch to be turned on, and the third control end controls the third control switch to be turned on; When a normal read / write voltage is used to read and write a bit, the first control terminal controls the first control switch to be turned on, the second control terminal controls the second control switch to be turned on, and the third control terminal controls the third control switch to be turned off; When the bit is not read, written or punctured, the third control terminal controls the third control switch to be closed.

4. The memory repair circuit according to any one of claims 1 to 3, characterized in that: The primary marking module includes: a current mirror, a first voltage amplifier and a first reference resistor; The current mirror comprises: a first current output terminal and a second current output terminal, the current output by the first current output terminal is equal to the current output by the second current output terminal; The first voltage type amplifier comprises: a first voltage input terminal and a second voltage input terminal; The first current output terminal is electrically connected to one end of the bit group and the first voltage input terminal respectively, the second current output terminal is electrically connected to one end of the first reference resistor and the second voltage input terminal respectively, and the other end of the first reference resistor and the other end of the bit group have the same potential; The resistance value of the first reference resistor is greater than the resistance value of the bit in the breakdown state and less than the resistance value of the bit in the low resistance state; The first voltage type amplifier is used to compare the potentials of the first voltage input terminal and the second voltage input terminal; The primary marking module is further used to perform primary marking on a bit connected to the first voltage input terminal when the potential of the first voltage input terminal is less than the potential of the second voltage input terminal.

5. The memory repair circuit according to claim 4, characterized in that: The primary marking module further includes: a second voltage-type amplifier and a second reference resistor; The second voltage-type amplifier includes: a third voltage input terminal and a fourth voltage input terminal, and the current mirror also includes: a third current output terminal, and the current output by the third current output terminal is equal to the current output by the first current output terminal; The third current output terminal is electrically connected to one end of the second reference resistor and the third voltage input terminal respectively, the third voltage input terminal is electrically connected to the first current output terminal, and the other end of the second reference resistor and the other end of the bit group have the same potential; The resistance value of the second reference resistor is greater than the resistance value of the bit in the low resistance state and less than the resistance value of the bit in the high resistance state; The second voltage type amplifier is used to compare the potentials of the first voltage input terminal and the third voltage input terminal; The primary marking module is also used to output data read from the bit connected to the first voltage input terminal according to the comparison result of the second voltage-type amplifier.

6. The memory repair circuit according to any one of claims 1 to 3, characterized in that: The primary marking module is also used to assign a value of 1 to the judgment bit corresponding to the bit in the breakdown state, so as to perform a primary marking on the bit in the breakdown state, and assign a value of 0 to the judgment bit corresponding to the bit not in the breakdown state; The flip judgment module includes: an OR gate and multiple AND gates; The plurality of AND gates correspond to the bits in the byte group one by one, and one input end of the plurality of AND gates is electrically connected to the primary marking module respectively to obtain the data written in the judgment bit corresponding to the corresponding bit; the other input ends of the plurality of AND gates are connected to the data writing end of the corresponding bit respectively to obtain the data to be written corresponding to the bit; The OR gate is electrically connected to the output ends of the plurality of AND gates; the output end of the OR gate is electrically connected to the secondary marking module so as to write the output value into the flip flag bit.

7. The memory repair circuit according to any one of claims 1 to 3, characterized in that: The secondary marking module is further used to vote on the values ​​read from the multiple marking bits and output the majority of the same values ​​as the flip flag value, and the flip flag value is used to distinguish whether there is a flip bit in the corresponding byte group; The data reading module is also used to output data according to the flip flag value and the marking result of the first-level marking module.

8. The memory repair circuit according to any one of claims 1 to 3, characterized in that: The data reading module includes: a bit reader, a buffer, an inverter, a logic judge and a multiplexer; The input end of the bit reader is electrically connected to the bit, the output end of the bit reader is electrically connected to the input end of the buffer and the input end of the inverter respectively, the input end of the multiplexer is electrically connected to the output end of the buffer and the output end of the inverter respectively, the enable end of the multiplexer is electrically connected to the output end of the logic determiner, and the input end of the logic determiner is electrically connected to the secondary marking module and the primary marking module respectively; The multi-logic determiner is used to determine whether the bit connected to the bit reader is flipped through the secondary marking module and the primary marking module; if so, output a first enable signal; if not, output a second enable signal; The multiplexer is used to communicate with the inverter when receiving a first enable signal, and to communicate with the buffer when receiving a second enable signal.

9. A method for repairing a memory, characterized in that: include: Reading a value in a determination bit of a bit to determine whether the bit is in a breakdown state according to the value in the determination bit, wherein the determination bit is used to perform a primary mark on the bit in the breakdown state; Determine whether there is a flip bit in the byte; if so, perform secondary marking on the byte by flipping the flag bit; wherein the byte includes a plurality of bits on the same bit line, and the flip bit is a bit whose data to be written is 1 and has been marked by the primary level; When performing a read operation on a bit, read the judgment bit and the flip flag bit corresponding to the bit to determine whether the bit is in a breakdown state and whether the byte group where the bit is located is secondarily marked; if the bit is in a breakdown state and the byte group where the bit is located is secondarily marked, output data that is the inversion of the data read from the flip bit that has been secondarily marked; if the bit is not in a breakdown state or the byte group where the bit is located is not secondarily marked, output the data read from the bit.

10. The method according to claim 9, characterized in that Before the step of reading the value in the determination bit of the bit to determine whether the bit is in a breakdown state according to the value in the determination bit, the method further includes: Identify whether a bit in the memory is a burned bit or a tailing bit, and perform breakdown on the burned bit and / or the tailing bit.

11. The method according to claim 9, characterized in that The value of the judgment bit for the bit mark in the breakdown state is 1, and the value of the bit mark not in the breakdown state is 0; The flip flag has a value of 1 for byte markings that are subject to secondary marking, and a value of 0 for byte markings that are not subject to secondary marking.

12. The method according to any one of claims 9 to 11, characterized in that The step of reading the value in the determination bit of the bit to determine whether the bit is in a breakdown state according to the value in the determination bit includes: Equal currents are respectively passed through the bit and the first reference resistor, and the relative sizes of the resistance value of the bit and the resistance value of the first reference resistor are compared, the resistance value of the first reference resistor is greater than the resistance value of the bit in the breakdown state and less than the resistance value of the bit in the low resistance state; if the resistance value of the bit is less than the resistance value of the first reference resistor, it is determined that the bit is in the breakdown state; if the resistance value of the bit is greater than the resistance value of the first reference resistor, it is determined that the bit is not in the breakdown state.

13. The method according to any one of claims 9 to 11, characterized in that When performing a read operation on a bit, reading the judgment bit and the flip flag bit corresponding to the bit to judge whether the bit is in a breakdown state and whether the byte group where the bit is located is secondary marked; if the bit is in a breakdown state and the byte group where the bit is located is secondary marked, outputting data obtained by inverting the data read from the flip bit that has been secondary marked; If the bit is not in a breakdown state or the byte group where the bit is located is not secondary marked, the step of outputting the data read from the bit comprises: Passing equal currents through the bit and the second reference resistor, respectively, and comparing the relative magnitudes of the resistance of the bit and the resistance of the second reference resistor, wherein the resistance of the second reference resistor is greater than the resistance of the bit in the low resistance state and less than the resistance of the bit in the high resistance state; If the resistance value of the bit is less than the resistance value of the second reference resistor, the data read from the bit is determined to be 0; if the resistance value of the bit is greater than the resistance value of the second reference resistor, the data read from the bit is determined to be 1.

14. The method according to any one of claims 9 to 11, characterized in that The determination of whether there is a flip bit in the byte; If yes, the step of performing secondary marking on the byte group where the bit is located by flipping the flag bit includes: Determine whether there is a flip bit in the byte; if so, set the flip flag to 1 to perform secondary marking on the byte through the flip flag; if not, set the flip flag to 0 low.

15. The method according to claim 14, characterized in that The flip flag bit includes a plurality of marking bits; The determining whether there is a flip bit in the byte; if so, setting the flip flag to 1 to perform secondary marking on the byte through the flip flag; If not, the step of setting the flip flag position to 0 includes: Determine whether there is a flip bit in the byte; if so, set the multiple flag bits to high to perform secondary marking on the byte through the multiple flip bits; if not, set the multiple flip bits to 0; The step of reading the determination bit and the flip flag bit corresponding to the bit when performing a read operation on the bit to determine whether the bit is in a breakdown state and whether the byte group where the bit is located has been secondary marked includes: By voting on the values ​​read from the multiple mark bits, the majority of the same values ​​are output as the flip flag value, and the flip flag value is used to distinguish whether there is a flip bit in the corresponding byte group.

Images