Control device, detection method, and detection program

Abstract

The invention provides a control device, a detection method, and a detection program, which can detect whether a power supply is cut off when writing data is written into a non-rewritable storage part, and can repair the stored writing data. In a control device, a processor acquires write data, assigns an error detection code to the write data as first write data and stores the write data in a first region of a non-volatile storage unit, and stores the first write data as second write data in a second region of a non-rewritable storage unit. The second write data is stored as third write data in a third region of the non-volatile storage unit.

Description

Technical Field

[0001] The present disclosure relates to a control device, a detection method and a detection program. Background Art

[0002] Generally, as a medium for storing data that is not to be erased, such as logs, data is sometimes stored in advance in a non-rewritable storage unit such as an OTP (One Time Programmable ROM). Sometimes, the power is cut off when the non-rewritable storage unit is storing write data. When the power is cut off when writing write data to the non-rewritable storage unit, the data may be stored in an abnormal state such as an incomplete state or an erroneous state.

[0003] For such a situation, a technique for checking whether normal write data is stored is known. For example, Patent Document 1 describes the following technique: a first area for storing circuit information and a second area for storing circuit information different from the circuit information in the first area are provided, and when power is turned on, the circuit information is read from the first area, and the circuit information is checked based on the circuit information to see whether normal circuit information is stored in the second area.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 01-265343

[0005] However, in the prior art, it is sometimes impossible to determine whether the stored write data is normal. For example, in the technology described in Patent Document 1, when the power supply is cut off while the circuit information is stored in the first area, and the stored circuit information becomes abnormal, it is impossible to detect whether the circuit information stored in the second area is normal. In this way, if the detection of whether it is normal is inappropriate, the problem of not repairing the abnormal write data arises. Therefore, a technology that can properly detect whether the stored write data is abnormal due to the power supply being cut off during the writing of the write data is desired. Summary of the invention

[0006] The present disclosure aims to provide a control device, a detection method, and a detection program that detect whether power is turned off when writing write data to a non-rewritable storage unit and can restore the stored write data.

[0007] In order to achieve the above-mentioned purpose, in the control device disclosed in the present invention, the processor obtains write data, the processor assigns an error detection code to the write data as first write data and stores it in the first area of ​​the non-volatile storage unit, the processor stores the first write data as second write data in the second area of ​​the non-writable storage unit, and the processor stores the second write data as third write data in the third area of ​​the non-volatile storage unit.

[0008] In addition, in order to achieve the above-mentioned purpose, the detection method disclosed in the present invention is a detection method in which a processor of a control device detects whether power is cut off when a non-rewritable storage unit is processing to store write data, obtains write data; assigns an error detection code to the above-mentioned write data as first write data and stores it in a first area of ​​a non-volatile storage unit; stores the above-mentioned first write data as second write data in a second area of ​​the non-rewritable storage unit; stores the above-mentioned second write data as third write data in a third area of ​​the non-volatile storage unit; and determines whether power is cut off during writing based on a comparison result of the above-mentioned first write data, the above-mentioned second write data and the above-mentioned third write data.

[0009] In addition, in order to achieve the above-mentioned purpose, the detection program disclosed in the present invention is used to cause the processor of the control device that detects whether the power is cut off when the non-rewritable storage unit is storing write data to execute the following processing: obtaining write data; assigning an error detection code to the above-mentioned write data as first write data and storing it in the first area of ​​the non-volatile storage unit; storing the above-mentioned first write data as second write data in the second area of ​​the non-rewritable storage unit; storing the above-mentioned second write data as third write data in the third area of ​​the non-volatile storage unit; and judging whether the power is cut off during writing based on the comparison result of the above-mentioned first write data, the above-mentioned second write data and the above-mentioned third write data.

[0010] According to the present disclosure, it is possible to detect whether power is turned off when writing write data to a non-rewritable storage unit, and to restore the stored write data. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a block diagram showing an example of the structure of a memory system according to an embodiment.

[0012] Figure 2 This is a flowchart showing an example of the flow of the write process.

[0013] Figure 3 This is a flowchart showing an example of the flow of the detection process.

[0014] Figure 4 This is a flowchart showing an example of the flow of normal determination processing.

[0015] Figure 5 : is a flowchart showing an example of the flow of the first write determination process.

[0016] Figure 6 : is a flowchart showing an example of the flow of the second writing determination process.

[0017] Figure 7 : is a flowchart showing an example of the flow of the third write determination process.

[0018] Description of Reference Numerals

[0019] 1…memory system; 10…control device; 11…CPU; 12…nonvolatile memory; 14…OTP; 20…first area; 22…second area; 23…third area. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, the following embodiments do not limit the technology of the present disclosure.

[0021] First, refer to Figure 1 An example of the configuration of the memory system according to the present embodiment will be described. Figure 1 A block diagram showing an example of the structure of the memory system 1 of the present embodiment is shown. The memory system 1 of the present embodiment includes a control device 10, a nonvolatile memory 12, and an OTP (One Time Programmable ROM) 14. In addition, the nonvolatile memory 12 of the present embodiment is an example of a nonvolatile storage unit disclosed in the present invention, and the OTP 14 of the present embodiment is an example of a non-rewritable storage unit disclosed in the present invention.

[0022] In the memory system 1, the write data WD is stored in the OTP 14 under the control of the control device 10. The write data stored in the OTP 14 is output to the outside of the memory system 1 and is used by an external device of the memory system 1.

[0023] The control device 10 includes a CPU (Central Processing Unit) 11, and the CPU 11 performs processing for writing the write data WD into the OTP 14. The CPU 11 of the present embodiment is an example of a processor of the present disclosure.

[0024] The nonvolatile memory 12 and the OTP 14 are provided in the same semiconductor device (not shown). The nonvolatile memory 12 includes a first area 20 and a third area 23 as areas for writing data. Under the control of the CPU 11 of the control device 10, the write data WD is written to the first area 20. In the present embodiment, a checksum such as CRC (Cyclic Redundancy Checking) is given and the write data WD is stored in the first area 20. In the present embodiment, the write data WD stored in the first area 20 is referred to as "first write data WD_1". In addition, the checksum of the present embodiment is an example of an error detection code disclosed in the present invention.

[0025] In addition, the second write data WD_2 read from the second area 22 of the OTP 14 is written to the third area 23 under the control of the CPU 11 of the control device 10. In the present embodiment, the second write data WD_2 stored in the third area 23 is referred to as "third write data WD_3". In the present embodiment, a checksum such as CRC is added and the second write data WD_2 is stored in the third area 23.

[0026] In the present embodiment, the addresses of the first area 20 and the third area 23 are output to the control device 10. The CPU 11 can identify the areas where the first write data WD_1 and the third write data WD_3 are stored by referring to the addresses.

[0027] The OTP 14 is a storage unit in which written data cannot be rewritten. The OTP 14 includes a second area 22. Under the control of the CPU 11 of the control device 10, the first write data WD_1 read from the first area 20 of the nonvolatile memory 12 is written to the second area 22. In this embodiment, the write data WD stored in the second area 22 is referred to as "second write data".

[0028] In addition, in the present embodiment, the address of the second area 22 is output to the control device 10. The CPU 11 can identify the area where the second write data WD_2 is stored by referring to the address.

[0029] In the following, when the write data WD, the first write data WD_1 , the second write data WD_2 , and the third write data WD_3 are collectively referred to as “write data” without distinguishing each from the others.

[0030] Thus, in the memory system 1 of the present embodiment, first, under the control of the CPU 11 of the control device 10, the write data WD is written to the first area 20 of the nonvolatile memory 12 and stored as the first write data WD_1. Next, under the control of the CPU 11, the first write data WD_1 read from the first area 20 of the nonvolatile memory 12 is written to the second area 22 of the OTP 14 and stored as the second write data WD_2. Furthermore, under the control of the CPU 11, the second write data WD_2 read from the second area 22 of the OTP 14 is written to the third area 23 of the nonvolatile memory 12 and stored as the third write data WD_3.

[0031] When all writing is performed normally, the write data WD, the first write data WD_1, the second write data WD_2, and the third write data WD_3 become the same data. On the other hand, there is a case where normal data is not written because the power is cut off during writing. For example, sometimes the write data is not written at all, or it becomes an incomplete state of being written, and the read value (0 or 1) will be different each time it is read. That is, when an abnormality such as power cut occurs during the writing process, at least one of the first write data WD_1, the second write data WD_2, and the third write data WD_3 is abnormal. Therefore, by comparing the first write data WD_1, the second write data WD_2, and the third write data WD_3, it is possible to determine whether the power is cut off when writing the write data to any area. In addition, for the written data, in other words, the stored data, in addition to the cases such as "abnormal" and "abnormal", the case where the data is different from the original data, there is also a case where the data does not exist.

[0032] Specifically, in the memory system 1 of the present embodiment, when power is shut off during writing, the following occurs.

[0033] (1) A case where the power supply is not turned off when writing the write data in any of the first area 20 , the second area 22 , and the third area 23 , that is, a case where the write data is normally written in any of the areas.

[0034] In this case, the first write data WD_1 and the third write data WD_3 are the same.

[0035] (2) A case where the power supply is turned off when the write data WD is written into the first area 20 of the nonvolatile memory 12 as the first write data WD_1.

[0036] In this case, the second write data WD_2 is different from the first write data WD_1 and is the same as the third write data WD_3, and the first write data WD_1 is abnormal. In this case, the control device 10 writes the write data to the first area 20, the second area 22, and the third area 23 to repair the write data stored in each area.

[0037] (3) A case where the power supply is turned off when the first write data WD_1 is written into the second area 22 of the OTP 14 as the second write data WD_2.

[0038] In this case, the second write data WD_2 is different from the first write data WD_1 and is the same as the third write data WD_3, and the first write data WD_1 is normal, or the first write data WD_1, the second write data WD_2, and the third write data WD_3 are all different, and the first write data WD_1 is normal. In this case, the control device 10 repairs the write data stored in the second area 22 and the third area 23 by writing the write data to the second area 22 and the third area 23.

[0039] (4) A case where the power supply is turned off when the second write data WD_2 is written into the third area 23 of the nonvolatile memory 12 as the third write data WD_3.

[0040] In this case, the first write data WD_1 is identical to the second write data WD_2 and different from the third write data WD_3 . In this case, the control device 10 writes the write data to the third area 23 to repair the write data stored in the third area 23 .

[0041] Therefore, the control device 10 of this embodiment compares the first write data WD_1, the second write data WD_2, and the third write data WD_3 to determine in which area the power supply was shut off when writing the write data, and repairs the stored write data as necessary.

[0042] The operation of the control device 10 of this embodiment will be described with reference to the drawings. Figure 2 , a write process of writing the write data WD by the CPU 11 of the control device 10 will be described. Figure 2 A flowchart showing an example of the flow of the write process executed by the CPU 11 is shown. In the present embodiment, the CPU 11 executes a write process program (not shown) stored in the control device 10 to execute the write process. Figure 2 The write process shown.

[0043] exist Figure 2 In step S100 , the CPU 11 acquires the write data WD. The acquisition source of the write data WD is not limited, and the CPU 11 acquires the write data WD from outside the memory system 1 , for example.

[0044] In the next step S102, as described above, the CPU 11 writes the write data WD into the first area 20 of the nonvolatile memory 12. As a result, the first write data WD_1 is stored in the first area 20 of the nonvolatile memory 12.

[0045] In the next step S104, as described above, the CPU 11 writes the first write data WD_1 into the second area 22 of the OTP 14. As a result, the second write data WD_2 is stored in the second area 22 of the OTP 14.

[0046] In the next step S106, as described above, the CPU 11 writes the second write data WD_2 into the third area 23 of the nonvolatile memory 12. As a result, the third write data WD_3 is stored in the third area 23 of the nonvolatile memory 12. When the processing of step S106 is completed, Figure 2 The writing process shown ends.

[0047] Next, refer to Figure 3 , a detection process is described for detecting whether a power outage has occurred and repairing the write data as needed. Figure 3 FIG. 1 is a flowchart showing an example of the flow of the detection process executed by the CPU 11. In the present embodiment, the CPU 11 executes a detection process program (not shown) stored in the control device 10 to execute the detection process program. Figure 3 The detection process shown. Figure 3 The detection process shown is executed, for example, when the control device 10 is powered on.

[0048] exist Figure 3 In step S200, the CPU 11 executes the following detailed description. Figure 4 The normal determination process is a process for determining whether or not the write data is normally stored in all of the first area 20, the second area 22, and the third area 23 without power failure.

[0049] In the next step S202 , the CPU 11 determines whether the power source is not turned off.

[0050] If the power is not turned off, the process of step S200 becomes affirmative and ends. Figure 3 On the other hand, if the power is turned off, the determination in step S202 becomes negative, and the process moves to step S204.

[0051] In step S204, the CPU 11 executes the following detailed description. Figure 5 The first write determination process is a process for determining whether power is turned off when writing write data WD into the first area 20 of the nonvolatile memory 12 as first write data WD_1, and repairing the stored write data as necessary.

[0052] In the next step S206, the CPU 11 determines whether the power supply is turned off when writing the write data WD into the first area 20 of the nonvolatile memory 12 as the first write data WD_1. If the power supply is turned off, the determination in step S206 becomes affirmative, and the process ends. Figure 3 On the other hand, if the power supply is not turned off, the determination in step S206 becomes negative, and the process moves to step S208.

[0053] In step S208, the CPU 11 executes the following detailed description. Figure 6 The second write determination process is a process for determining whether the power supply is turned off when the first write data WD_1 is written into the second area 22 of the OTP 14 as the second write data WD_2, and repairing the stored write data as necessary.

[0054] In the next step S210, the CPU 11 determines whether the power supply is turned off when the first write data WD_1 is written into the second area 22 of the OTP 14 as the second write data WD_2. If the power supply is turned off, the determination of step S210 becomes positive, and the process ends. Figure 3 On the other hand, if the power supply is not turned off, the determination in step S210 becomes negative, and the process moves to step S212.

[0055] In step S212, the CPU 11 executes the following detailed description. Figure 7 The third write determination process is to determine whether the power supply is cut off when the second write data WD_2 is written into the third area 23 of the nonvolatile memory 12 as the third write data WD_3, and to repair the stored write data as needed. If the process of step S212 is completed, then Figure 3 The detection process shown ends.

[0056] Next, refer to Figure 4The above-mentioned normality determination process will be described.

[0057] exist Figure 4 In step S300 of the normal determination process, the CPU 11 determines whether the first write data WD_1 and the third write data WD_3 are the same. If the first write data WD_1 and the third write data WD_3 are not the same, the determination in step S300 becomes a negative determination, and the process ends. Figure 4 The normal determination process shown in FIG. 1 moves to step S202 of the detection process described above (see FIG. 1 ). Figure 3 ) On the other hand, when the first write data WD_1 and the third write data WD_3 are the same, the determination in step S300 becomes affirmative, and the process moves to step S302.

[0058] In step S302, the CPU 11 determines that the power supply is not turned off when writing the write data to any of the first area 20, the second area 22, and the third area 23. In other words, the CPU 11 determines that the write data is normally written to any of the first area 20, the second area 22, and the third area 23. If the processing of step S302 is completed, the process ends. Figure 4 The normal determination process shown in FIG. 1 moves to step S202 of the detection process described above (see FIG. 1 ). Figure 3 ).

[0059] Next, refer to Figure 5 The above-mentioned first write determination process will be described.

[0060] exist Figure 5 In step S320 of the first write determination process, the CPU 11 determines whether the second write data WD_2 is different from the first write data WD_1 and is the same as the third write data WD_3. If the second write data WD_2 is different from the first write data WD_1 and is the same as the third write data WD_3, the determination in step S320 becomes affirmative, and the process ends. Figure 5 The first write determination process shown in FIG. 1 moves to step S206 of the detection process described above (see FIG. 1 ). Figure 3 ). On the other hand, if the determination in step S320 is negative, the process proceeds to step S322.

[0061] In step S322, the CPU 11 determines whether the first write data WD_1 is normal. Specifically, the CPU 11 uses the checksum assigned to the first write data WD_1 to determine whether the first write data WD_1 is normal. If the first write data WD_1 is normal, the step S320 is determined to be positive, and the process ends. Figure 5The first write determination process shown in FIG. 1 moves to step S206 of the detection process described above (see FIG. 1 ). Figure 3 ). On the other hand, if the determination in step S322 is negative, the process proceeds to step S324.

[0062] In step S324 , the CPU 11 determines that the power supply is turned off when writing the write data WD into the first area 20 of the nonvolatile memory 12 as the first write data WD_1 .

[0063] In the next step S326, the CPU 11 writes the write data to all of the first area 20, the second area 22, and the third area 23. That is, the CPU 11 executes the Figure 2 The writing process shown in the figure repairs the writing data stored in the first area 20, the second area 22 and the third area 23. If the processing of step S326 is completed, the process ends. Figure 5 The first write determination process shown in FIG. 1 moves to step S206 of the detection process described above (see FIG. 1 ). Figure 3 ).

[0064] Next, refer to Figure 6 The second write determination process described above will be described.

[0065] exist Figure 6 In step S340 of the second write determination processing, CPU 11 determines whether the second write data WD_2 is different from the first write data WD_1 and is the same as the third write data WD_3, or whether the first write data WD_1, the second write data WD_2, and the third write data WD_3 are all different. When the second write data WD_2 is different from the first write data WD_1 and is the same as the third write data WD_3, or when the first write data WD_1, the second write data WD_2, and the third write data WD_3 are all different, the determination of step S340 becomes an affirmative determination, and the process ends. Figure 6 The second write determination process shown in FIG. 1 moves to step S210 of the detection process described above (see FIG. 14 ). Figure 3 ). On the other hand, if the determination in step S340 is negative, the process proceeds to step S342.

[0066] In step S342, the CPU 11 determines whether the first write data WD_1 is normal. Specifically, the CPU 11 uses the checksum assigned to the first write data WD_1 to determine whether the first write data WD_1 is normal. If the first write data WD_1 is not normal, the step S340 is determined to be negative, and the process ends. Figure 6 The second write determination process shown in FIG. 1 moves to step S210 of the detection process described above (see FIG. 14 ). Figure 3 ). On the other hand, if the determination in step S342 is affirmative, the process proceeds to step S344.

[0067] In step S344 , the CPU 11 determines that the power supply is turned off when writing the first write data WD_1 into the second area 22 of the OTP 14 as the second write data WD_2 .

[0068] In the next step S346 , the CPU 11 writes the first write data WD_1 into the second area 22 of the OTP 14 , thereby repairing the second write data WD_2 stored in the second area 22 .

[0069] In the next step S348, the CPU 11 writes the second write data WD_2 into the third area 23 of the nonvolatile memory 12, thereby repairing the third write data WD_3 stored in the third area 23. When the processing of step S348 is completed, the process ends. Figure 6 The second write determination process shown in FIG. 1 moves to step S210 of the detection process described above (see FIG. 14 ). Figure 3 ).

[0070] Furthermore, refer to Figure 7 The third write determination process described above will be described.

[0071] exist Figure 7 In step S360 of the third write determination process, the CPU 11 determines whether the first write data WD_1 is the same as the second write data WD_2 and different from the third write data WD_3. If the first write data WD_1 is the same as the second write data WD_2 and different from the third write data WD_3, the determination in step S360 becomes affirmative, and the process ends. Figure 7 The third writing determination process shown in FIG. 1 is also completed in this case. On the other hand, if the determination in step S360 is negative, the process proceeds to step S362.

[0072] In step S362 , the CPU 11 determines that the power supply is turned off when writing the second write data WD_2 into the third area 23 of the nonvolatile memory 12 as the third write data WD_3 .

[0073] In the next step S364, the CPU 11 writes the second write data WD_2 into the third area 23 of the nonvolatile memory 12, thereby repairing the third write data WD_3 stored in the third area 23. When the processing of step S364 is completed, the process ends. Figure 7 In this case, the above-mentioned detection process is also terminated.

[0074] As described above, the CPU 11 of the control device 10 of the above embodiment acquires the write data WD, adds a checksum to the write data WD as the first write data WD_1, and stores it in the first area 20 of the nonvolatile memory 12. In addition, the CPU 11 stores the first write data WD_1 as the second write data WD_2 in the second area 22 of the OTP 14. Furthermore, the CPU 11 stores the second write data WD_2 as the third write data WD_3 in the third area 23 of the nonvolatile memory 12.

[0075] With the above configuration, the CPU 11 of the control device 10 of the present embodiment can compare the first write data WD_1 stored in the first area 20, the second write data WD_2 stored in the second area 22, and the third write data WD_3 stored in the third area 23. Therefore, the CPU 11 can detect, based on the comparison result, in which of the first area 20, the second area 22, and the third area 23 the power supply is cut off when writing the write data, and can repair the stored write data as needed.

[0076] Therefore, according to the control device 10 of the present embodiment, it is possible to detect whether the power supply is turned off when writing the write data to the non-rewritable storage unit, and to restore the stored write data.

[0077] When the power is cut off while writing the write data to the non-rewritable storage unit, the write data may be stored in an abnormal state such as incomplete or erroneous. In such a case, the control device 10 according to the present embodiment can detect whether the power is cut off while writing the write data to the non-rewritable storage unit as described above, and can repair the stored write data.

[0078] In the above-described embodiment, the CPU 11 may store the write data indicating whether the power supply is turned off, where the power supply is turned off, and in which area the repair data is stored in the control device 10 or output it to the outside.

[0079] In addition, in the present embodiment, the second write data WD_2 is assigned a checksum as the third write data WD_3 and stored in the third area 23 of the nonvolatile memory 12, but the assignment of the checksum to the third write data WD_3 is not essential. In addition, as in the present embodiment, by assigning a checksum in advance to the third write data WD_3 pre-stored in the third area 23, the checksum can be used to determine whether data damage occurs when data is forwarded from the outside. In addition, the checksum can be used to determine whether data is abnormal due to a write error when writing data, or data rewriting due to some reasons.

[0080] In the above-mentioned embodiment, the method using the OTP 14 is described as an example of a non-rewritable storage unit, but the present invention is not limited to this method. For example, a method using a fuse as a non-rewritable storage unit may be adopted.

[0081] Regarding the above-mentioned embodiment, the following supplementary notes are also disclosed.

[0082] (Supplementary Note 1) A control device,

[0083] The processor obtains the data for writing,

[0084] The processor adds an error detection code to the write data as first write data and stores the data in a first area of ​​a nonvolatile storage unit.

[0085] the processor causes the first write data to be stored as second write data in a second area of ​​the non-rewritable storage unit,

[0086] The processor stores the second write data as third write data in a third area of ​​the nonvolatile storage unit.

[0087] (Supplement 2) A control device according to Supplement 1, wherein:

[0088] The processor further determines whether power is turned off during writing based on a comparison result of the first write data, the second write data, and the third write data.

[0089] (Supplement 3) The control device according to Supplement 2, wherein:

[0090] The processor determines that power is not turned off during writing, when determining that the first write data is identical to the third write data.

[0091] (Supplement 4) A control device according to Supplement 2 or 3, wherein:

[0092] The processor determines that power is cut off when writing the first write data into the first area when the first write data is different from the second write data, the second write data is the same as the third write data, and the first write data is determined to be abnormal based on the error detection code.

[0093] (Supplement 5) The control device according to Supplement 4, wherein:

[0094] When the processor determines that the power supply is cut off,

[0095] Get the above write data,

[0096] The third write data is assigned an error detection code as the first write data and is stored in the first area.

[0097] (Supplementary Note 6) The control device according to any one of Supplementary Notes 2 to 5, wherein:

[0098] When the first write data and the second write data are different, the second write data and the third write data are the same, and it is determined based on the error detection code that the first write data is normal,

[0099] Alternatively, when the first write data, the second write data, and the third write data are all different and it is determined based on the error detection code that the first write data is normal,

[0100] The processor determines that power is turned off when writing the second write data into the second area.

[0101] (Supplementary Note 7) The control device according to Supplementary Note 6, wherein:

[0102] When the processor determines that the power supply is cut off,

[0103] storing the first write data as the second write data in the second area,

[0104] The second write data is stored in the third region as the third write data.

[0105] (Supplementary Note 8) The control device according to any one of Supplementary Notes 2 to 7, wherein:

[0106] When the first write data and the second write data are the same and the first write data and the third write data are different,

[0107] The processor determines that power is turned off when writing the third write data into the third area.

[0108] (Supplement 9) The control device according to Supplement 8, wherein:

[0109] When the processor determines that the power supply is cut off,

[0110] The second write data is stored in the third region as the third write data.

[0111] (Supplementary Note 10) A detection method in which a processor of a control device detects whether power is turned off during a process of causing a non-rewritable storage unit to store write data,

[0112] Get data for writing;

[0113] The write data is assigned an error detection code as first write data and stored in a first area of ​​a nonvolatile storage unit;

[0114] storing the first write data as second write data in a second area of ​​the non-rewritable storage unit;

[0115] storing the second write data as third write data in a third area of ​​the nonvolatile storage unit; and

[0116] Whether or not power is turned off during writing is determined based on a comparison result of the first write data, the second write data, and the third write data.

[0117] (Supplementary Note 11) A detection program for causing a processor of a control device to detect whether power is turned off during a process of causing a non-rewritable storage unit to store write data to execute the following process:

[0118] Get data for writing;

[0119] The write data is assigned an error detection code as first write data and stored in a first area of ​​a nonvolatile storage unit;

[0120] storing the first write data as second write data in a second area of ​​the non-rewritable storage unit;

[0121] storing the second write data as third write data in a third area of ​​the nonvolatile storage unit; and

[0122] Whether or not power is turned off during writing is determined based on a comparison result of the first write data, the second write data, and the third write data.

Claims

1. A control device, The processor obtains the data for writing, The processor adds an error detection code to the write data as first write data and stores the data in a first area of ​​a nonvolatile storage unit. the processor storing the first write data as second write data in a second area of ​​the non-rewritable storage unit, The processor stores the second write data as third write data in a third area of ​​the nonvolatile storage unit.

2. The control device according to claim 1, wherein: The processor further determines whether power is turned off during writing based on a comparison result of the first write data, the second write data, and the third write data.

3. The control device according to claim 2, wherein: The processor determines that power is not turned off during writing, when determining that the first write data is identical to the third write data.

4. The control device according to claim 2, wherein: The processor determines that power is cut off when writing the first write data into the first area when the first write data is different from the second write data, the second write data is the same as the third write data, and the first write data is determined to be abnormal based on the error detection code.

5. The control device according to claim 4, wherein: When the processor determines that the power supply is cut off, Get the above write data, The third write data is assigned an error detection code as the first write data and is stored in the first area.

6. The control device according to claim 2, wherein: When the first write data and the second write data are different, the second write data and the third write data are the same, and it is determined based on the error detection code that the first write data is normal, Alternatively, when the first write data, the second write data, and the third write data are all different and it is determined based on the error detection code that the first write data is normal, The processor determines that power is turned off when writing the second write data into the second area.

7. The control device according to claim 6, wherein: When the processor determines that the power supply is cut off, storing the first write data as the second write data in the second area, The second write data is stored in the third region as the third write data.

8. The control device according to claim 2, wherein: When the first write data is the same as the second write data and the first write data is different from the third write data, The processor determines that power is turned off when writing the third write data into the third area.

9. The control device according to claim 8, wherein: When the processor determines that the power supply is cut off, The second write data is stored in the third region as the third write data.

10. A detection method, wherein a processor of a control device detects whether power is turned off during a process of causing a non-rewritable storage unit to store write data, Get data for writing; The write data is assigned an error detection code as first write data and stored in a first area of ​​a nonvolatile storage unit; storing the first write data as second write data in a second area of ​​the non-rewritable storage unit; storing the second write data as third write data in a third area of ​​the nonvolatile storage unit; as well as Whether or not power is turned off during writing is determined based on a comparison result of the first write data, the second write data, and the third write data.

11. A detection program for causing a processor of a control device for detecting whether power is turned off during a process of causing a non-rewritable storage unit to store write data to execute the following process: Get data for writing; The write data is assigned an error detection code as first write data and stored in a first area of ​​a nonvolatile storage unit; storing the first write data as second write data in a second area of ​​the non-rewritable storage unit; storing the second write data as third write data in a third area of ​​the nonvolatile storage unit; as well as Whether or not power is turned off during writing is determined based on a comparison result of the first write data, the second write data, and the third write data.

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