Memory monitoring method and memory

Abstract

The present disclosure relates to the field of memory, and particularly relates to a memory monitoring method and a memory. The memory monitoring method comprises: obtaining a test storage unit and a control storage unit based on an operating storage unit, the test storage unit is adjacent to the operating storage unit, the control storage unit is a first distance from the operating storage unit, the test storage unit is a second distance from the operating storage unit, and the first distance is greater than the second distance; performing a cyclic write operation on the operating storage unit, and reading first state information of the test storage unit and second state information of the control storage unit; and obtaining a monitoring result of the memory based on the first state information and the second state information. The memory monitoring method provided by the embodiment of the present disclosure is used to more accurately monitor the write operation performance of the memory.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of memory, and in particular, to a memory monitoring method and memory. BACKGROUND

[0002] Three-dimensional phase change memory technology based on phase change random access memory (PCRAM) is one of the most promising candidates in the field of non-volatile memory (NVM) due to its higher capacity than dynamic random access memory (DRAM), lower latency and byte-level addressing capability compared to Nand flash memory.

[0003] For phase change memory (PCM), "set" and "reset" represent that a memory cell stores "1" and "0", respectively, and the cell switches between "set" and "reset" by heat to realize information storage of "0" and "1".

[0004] However, the heat generated by the write operation on the target memory cell (Aggressive cell) inevitably causes thermal crosstalk to the adjacent victim memory cell, thereby reducing the threshold voltage VtR (threshold voltage VtR as the distinguishing threshold of "set" and "reset") of the victim memory cell, resulting in readout errors. SUMMARY

[0005] The purpose of the present disclosure is to provide a memory monitoring method and memory to more accurately monitor the write operation performance of the memory.

[0006] To achieve the above purpose, the present disclosure provides a memory monitoring method, comprising: obtaining a test memory cell and a control memory cell based on an operating memory cell, the test memory cell being adjacent to the operating memory cell, the control memory cell being a first distance from the operating memory cell, the test memory cell being a second distance from the operating memory cell, the first distance being greater than the second distance; performing a cyclic write operation on the operating memory cell and reading first state information of the test memory cell and second state information of the control memory cell; obtaining a monitoring result of the memory based on the first state information and the second state information.

[0007] In some embodiments, the test storage unit, the control storage unit and the operation storage unit are on the same operation line.

[0008] In some embodiments, the control storage unit is adjacent to the test storage unit, and the control storage unit is located on both sides of the test storage unit.

[0009] In some embodiments, the test storage unit is also next adjacent to the operation storage unit, and the next adjacent represents adjacent with a storage unit spacing.

[0010] In some embodiments, the operation line includes at least one of a word line or a bit line.

[0011] In some embodiments, the second state information is acquired at the same time as the first state information.

[0012] In some embodiments, the method for monitoring the memory includes acquiring an original bit error code rate based on the first state information and the second state information.

[0013] In some embodiments, the method for acquiring the original bit error code rate based on the first state information and the second state information includes: acquiring a first error code rate based on the first state information; acquiring a second error code rate based on the second state information; and acquiring the original bit error code rate based on the difference between the first error code rate and the second error code rate.

[0014] In some embodiments, before performing the cyclic write operation on the operation storage unit, the method further includes resetting the operation storage unit, the test storage unit and the control storage unit.

[0015] Accordingly, the present disclosure also provides a memory including a storage array module including a plurality of storage units, and a monitoring module connected to the storage array module and configured to monitor according to the monitoring method of the memory provided in the above embodiments.

[0016] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0017] The monitoring method of the memory provided in the embodiments of the present disclosure has an execution object including a test storage unit and a control storage unit; the test result of the test storage unit is used to represent the test result of a crosstalk storage unit, and the test result of the control storage unit is used to represent the influence degree of write-read delay; the monitoring result acquired by combining the first state information of the test storage unit and the second state information of the control storage unit excludes the monitoring influence of write-read delay on the test storage unit, so as to more accurately monitor the write operation performance of the memory.

[0018] In addition, the original bit error code rate is used as an index for measuring data transmission reliability, and is used to monitor the influence of the heat generated by operating the memory unit on the test memory unit, so that the data error rate of the test memory unit can be directly obtained.

[0019] In addition, the data consistency of the operating memory unit, the test memory unit and the reference memory unit is ensured before testing the memory by resetting the operating memory unit, the test memory unit and the reference memory unit, so that the inaccurate monitoring result caused by inconsistent initial data is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without creative labor.

[0021] Figure 1 The flowchart corresponding to each step of the memory monitoring method provided by the embodiments of the present disclosure is shown in the following description.

[0022] Figure 2 The structure diagram of the storage array corresponding to the first selection method of the test memory unit and the reference memory unit provided by the embodiments of the present disclosure is shown in the following description.

[0023] Figure 3 The structure diagram of the storage array corresponding to the second selection method of the test memory unit and the reference memory unit provided by the embodiments of the present disclosure is shown in the following description.

[0024] Figure 4 The structure diagram of the storage array corresponding to the third selection method of the test memory unit and the reference memory unit provided by the embodiments of the present disclosure is shown in the following description.

[0025] Figure 5 The structure diagram of the storage array corresponding to the fourth selection method of the test memory unit and the reference memory unit provided by the embodiments of the present disclosure is shown in the following description.

[0026] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0027] As known from the background, for a phase change memory (PCM), "set" and "reset" represent that a memory cell stores "1" and "0", respectively, and the cell switches between "set" and "reset" by means of heat, so as to realize information storage of "0" and "1".

[0028] The heat generated by the write operation on the target storage cell (Aggressive cell) inevitably causes thermal crosstalk to the adjacent victim storage cell, thereby reducing the threshold voltage VtR (threshold voltage VtR as the distinguishing threshold of "set" and "reset") of the victim storage cell, resulting in readout errors.

[0029] Since the thermal crosstalk effect of the target storage cell on the victim storage cell is inevitable, it is particularly important to monitor the write operation of the phase change memory.

[0030] In some embodiments, the write operation monitoring method of the phase change memory is as follows:

[0031] Step S1, reset the target storage cell and the victim storage cell to be in "reset".

[0032] In one example, the reset of the target storage cell and the victim storage cell is achieved by a write operation.

[0033] In one example, the write reset of the target storage cell and the victim storage cell can be performed simultaneously or in steps.

[0034] Step S2, after the reset of the target storage cell and the victim storage cell is completed, the target storage cell is subjected to a cyclic write operation.

[0035] Step S3, after the cyclic write operation of the target storage cell is completed, the state of the victim storage cell is read to determine whether it jumps, and the raw bit error rate (RBER) is calculated.

[0036] However, the above steps S1 to S3 also include a write-to-read delay (W2R delay), which causes structural relaxation and disappearance of interband defect levels in the phase change memory and the Ovonic Threshold Switch (OTS) in the victim storage cell, thereby causing the threshold voltage Vt of the victim storage cell to drift (Vtdrift) to increase, which makes it difficult to monitor the write operation of the phase change memory. For example, the write-to-read delay causes structural relaxation and disappearance of interband defect levels in the phase change memory and the Ovonic Threshold Switch in the victim storage cell, resulting in an increase in the threshold voltage Vt of the victim storage cell, so that data originally read as "1" may be read as data "0".

[0037] To solve the above problems, the present embodiment proposes a monitoring method of a memory, please refer to Figure 1 , Figure 1is a flowchart of a monitoring method of a memory of the embodiment, comprising:

[0038] In step S11, a test storage unit and a control storage unit are obtained based on an operating storage unit.

[0039] The test storage unit is adjacent to the operating storage unit, the control storage unit is a first distance from the operating storage unit, the test storage unit is a second distance from the operating storage unit, and the first distance is greater than the second distance.

[0040] In step S12, a cyclic write operation is performed on the operating storage unit, and first state information of the test storage unit and second state information of the control storage unit are read.

[0041] In step S13, a monitoring result of the memory is obtained based on the first state information and the second state information.

[0042] The monitoring method of the memory provided by the embodiment of the present disclosure has an execution object including a test storage unit and a control storage unit; the test result of the test storage unit is used to represent the test result of a crosstalk storage unit, and the test result of the control storage unit is used to represent the influence degree of write-read delay; the monitoring result obtained by combining the first state information of the test storage unit and the second state information of the control storage unit excludes the monitoring influence of the write-read delay on the test storage unit, so that the write operation performance of the memory can be more accurately monitored.

[0043] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the protection scope of the present application.

[0044] In addition, the description such as "first", "second" and the like in the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize it, and when the combination of technical solutions appears to be contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the protection scope required by the present application.

[0045] The monitoring method of the memory provided by the embodiment will be described in detail below with reference to the drawings, and specifically as shown in Figure 2 the drawings.Figure 2 is a structural schematic diagram of a memory monitoring process according to an embodiment of the present application. Please refer to Figure 2 , a memory is provided, which includes at least a memory array, the memory array includes a plurality of memory cells 100 arranged in a row-column array, memory cells 100 in the same row are connected to the same word line WL, and memory cells 100 in the same column are connected to the same bit line BL. Therefore, the memory array can be regarded as a collection of memory cells arranged along the bit line extension direction 302 and the word line extension direction 301.

[0046] It should be noted that, in the memory array shown in Figure 2 , a first insulating structure 201 is arranged around each memory cell 100, a second insulating structure 202 is arranged between memory cells 100 in the word line WL extension direction, and a third insulating structure 203 is arranged between memory cells 100 in the bit line BL extension direction. The first insulating structure 201, the second insulating structure 202, and the third insulating structure 203 are used for electrical insulation between memory cells 100 to prevent data crosstalk between memory cells 100. For read and write operations of the memory, the memory needs to select a target memory cell in the memory array based on an address signal, and then implement data writing to the target memory cell or data reading out of the target memory cell.

[0047] On this basis, the memory selects a word line WL based on a word line address, and selects a bit line BL based on a bit line address, so as to select a target memory cell in the memory array to complete the read and write operation.

[0048] Please refer to Figure 1 and Figure 2 , step S11 is executed to obtain a test memory cell 102 and a control memory cell 103 based on an operating memory cell 101.

[0049] Among them, the test memory cell 102 is adjacent to the operating memory cell 101, the control memory cell 103 is a first distance away from the operating memory cell 101, the test memory cell 102 is a second distance away from the operating memory cell 101, and the first distance is greater than the second distance.

[0050] The operating memory cell 101 (Aggressive Cell) is the target memory cell corresponding to the aforementioned read and write operation of the memory.

[0051] The test memory cell 102 (Victim Cell) is adjacent to the operating memory cell 101, that is, the heat generated by the write operation on the operating memory cell 101 will inevitably cause thermal crosstalk to the test memory cell 102, thereby reducing the threshold voltage of the test memory cell 102.

[0052] The distance between the reference storage unit 103 and the operation storage unit 101 is greater than the distance between the test storage unit 102 and the operation storage unit 101, so that the reference storage unit 103 is not affected by the heat.

[0053] In addition, other test parameters of the reference storage unit 103 and the test storage unit 102 are kept consistent to avoid the influence of other factors on the monitoring result, such as the write-read delay between the operation storage unit and the test storage unit. The monitoring result is used to characterize the influence of the heat generated by the operation storage unit 101 on the test storage unit 102.

[0054] In the present example, the selected test storage unit 102, reference storage unit 103 and operation storage unit 101 are on the same operation line. By selecting the test storage unit 102 and the reference storage unit 103 on the operation line, the read-write delay of the test storage unit 102 and the reference storage unit 103 with the operation storage unit 101 is kept consistent, so that the write operation performance of the memory can be more accurately monitored.

[0055] For the "operation line" mentioned in the present embodiment, the "operation line" includes at least one of the word line WL or the bit line BL.

[0056] In one example, the test storage unit 102 and the operation storage unit 101 are located on the same word line WL, and the reference storage unit 103 is selected as a storage unit 100 located farther away on the same word line WL. For example Figure 2 Selection of the two reference storage units 103 on the left and right.

[0057] In one example, the test storage unit 102 and the operation storage unit 101 are located on the same bit line BL, and the reference storage unit 103 is selected as a storage unit 100 located farther away on the same bit line BL. For example Figure 2 Selection of the two reference storage units 103 on the top and bottom.

[0058] Further, in some embodiments, with reference to Figure 3 , Figure 3 is a structural schematic diagram of another memory monitoring process of the present embodiment. The selected reference storage unit 103 and test storage unit 102 are adjacent, and the reference storage unit 103 and the operation storage unit 101 are located on both sides of the test storage unit 102.

[0059] By selecting the reference storage unit 103 and the test storage unit 102 adjacent to each other on the same operation line, it is further ensured that the read-write delay of the test storage unit 102 and the reference storage unit 103 with the operation storage unit 101 is consistent.

[0060] It should be noted that, Figure 2 andFigure 3 The selected test storage unit 102, the reference storage unit 103 and the operation storage unit 101 are located at the same word line WL or bit line BL. In a specific application, the test storage unit 102 and the operation storage unit 101 can be located at the same operation line, and the reference storage unit 103 and the test storage unit 102 can be located at the same operation line. For example, the test storage unit 102 and the operation storage unit 101 are located at the same word line WL, and the reference storage unit 103 and the test storage unit 102 are located at the same bit line BL; or, the test storage unit 102 and the operation storage unit 101 are located at the same bit line BL, and the reference storage unit 103 and the test storage unit 102 are located at the same word line WL.

[0061] After the operation storage unit 101, the test storage unit 102 and the reference storage unit 103 are selected, step S12 is performed.

[0062] Reference is made to Figure 1 and Figure 2 , step S12 is performed, a cyclic write operation is performed on the operation storage unit 101, and the first state information of the test storage unit 102 and the second state information of the reference storage unit 103 are read; and a monitoring result of the memory is obtained based on the first state information and the second state information.

[0063] In one example, the reading of the first state information and the second state information can be completed after each write operation, i.e., the first state information and the second state information are obtained after each write operation on the operation storage unit.

[0064] In one example, the reading of the first state information and the second state information can be completed after a preset number of write operations, i.e., the first state information and the second state information are obtained after the preset number of write operations on the operation storage unit.

[0065] In one example, the reading of the first state information and the second state information can be completed once after the cyclic write operation on the operation storage unit, i.e., the first state information and the second state information are obtained after the cyclic write operation on the operation storage unit.

[0066] In some embodiments, before the cyclic write operation on the operation storage unit is performed, the operation storage unit, the test storage unit and the reference storage unit are reset.

[0067] In one example, the operation storage unit 101, the test storage unit 102 and the reference storage unit 103 can be reset to a "reset" state, i.e., data "0" is written to the operation storage unit 101, the test storage unit 102 and the reference storage unit 103.

[0068] In one example, the operation storage unit 101, the test storage unit 102 and the control storage unit 103 can be reset to the "set" state. That is, the operation storage unit 101, the test storage unit 102 and the control storage unit 103 are written with data "1".

[0069] By resetting the operation storage unit 101, the test storage unit 102 and the control storage unit 103, the data consistency of the operation storage unit 101, the test storage unit 102 and the control storage unit 103 before testing the memory is ensured, and the inaccurate monitoring result caused by inconsistent initial data is avoided.

[0070] In some embodiments, the second state information is obtained at the same time as the first state information. By obtaining the first state information and the second state information at the same time, the timeliness of the first state information and the second state information is ensured, and the write operation performance of the memory can be more accurately monitored.

[0071] After obtaining the first state information and the second state information, step S13 is performed.

[0072] Reference Figure 1 and Figure 2 Step S13 is performed, and the monitoring result of the memory is obtained based on the first state information and the second state information.

[0073] For the monitoring method of the memory provided in the embodiment, the execution object includes the test storage unit 102 and the control storage unit 103; the monitoring result obtained in combination with the first state information of the test storage unit 102 and the second state information of the control storage unit 103 excludes the influence of other factors on the test storage unit 102, so that the write operation performance of the memory can be more accurately monitored.

[0074] In some embodiments, the method for obtaining the monitoring result of the memory includes: obtaining a raw bit error code rate based on the first state information and the second state information.

[0075] Specifically, the raw bit error code rate (RBER) refers to the ratio of the number of bits with errors to the total number of bits in data transmission before applying error correcting code (ECC). The raw bit error code rate is used as an index for measuring the reliability of data transmission, and is used in the monitoring method of the memory to monitor the influence of the heat of the operation storage unit 101 on the test storage unit 102, so that the data error rate of the test storage unit 102 can be directly obtained.

[0076] In some embodiments, the method for obtaining the original bit error code rate based on the first state information and the second state information comprises: obtaining a first error code rate based on the first state information, obtaining a second error code rate based on the second state information, and obtaining the original bit error code rate based on the difference between the first error code rate and the second error code rate.

[0077] In one example, if the first error code rate obtained based on the first state information is A1, and the second error code rate obtained based on the second state information is A2, then the original bit error code rate A = A1-A2.

[0078] Specifically, the first error code rate obtained based on the first state information contains the result of the heat influence and the result of other factors, the second error code rate obtained based on the second state information contains only the result of other factors, and the original bit error code rate obtained based on the difference between the first error code rate and the second error code rate contains only the result of the heat influence, so that the write operation performance of the memory can be more accurately monitored.

[0079] Correspondingly, the application further provides another memory monitoring method, which refers to Figure 1 and Figure 4 , Figure 4 is a structural schematic diagram of another memory monitoring process of the application. Figure 4 The embodiment shown in Figure 2 is different from the embodiment shown in

[0080] Referring to Figure 1 and Figure 4 , the step S11 is performed to obtain the test storage unit 102 and the control storage unit 103 based on the operation storage unit 101.

[0081] Among them, the test storage unit 102 is adjacent to the operation storage unit 101, the control storage unit 103 is a first distance from the operation storage unit 101, the test storage unit 102 is a second distance from the operation storage unit 101, and the first distance is greater than the second distance.

[0082] In addition, the test storage unit 102 is also diagonally adjacent to the operation storage unit 101, and diagonally adjacent means that the test storage unit 102 and the operation storage unit 101 are adjacent storage units located on different operation lines.

[0083] On this basis, the selected test storage unit 102 and the control storage unit 103 are located on the same operation line. For example, the selected test storage unit 102 and the control storage unit 103 are located on the same word line WL; or, the selected test storage unit 102 and the control storage unit 103 are located on the same bit line BL.

[0084] It should be noted that in some embodiments, the selected test storage unit 102 and the control storage unit 103 can also be in a diagonal adjacent relationship, i.e., the test storage unit 102 and the control storage unit 103 are adjacent storage units located on different operation lines.

[0085] It should be noted that the execution manner of step S12 and step S13 in this embodiment is the same as that of the above-mentioned embodiments, and the present embodiment will not be described again.

[0086] Correspondingly, the present application also provides another memory monitoring method, which refers to Figure 1 and Figure 5 , Figure 5 is a structural schematic diagram of another memory monitoring process of the present application. Figure 5 The embodiment shown in Figure 2 and Figure 4 The difference between the embodiment shown in and the embodiment shown in is that the selection manner of the test storage unit 102 and the control storage unit 103 in step S11 is different.

[0087] Referring to Figure 1 and Figure 5 , step S11 is performed to obtain the test storage unit 102 and the control storage unit 103 based on the operation storage unit 101.

[0088] Among them, the test storage unit 102 is adjacent to the operation storage unit 101, the control storage unit 103 is first distance from the operation storage unit 101, the test storage unit 102 is second distance from the operation storage unit 101, and the first distance is greater than the second distance.

[0089] In addition, referring to Figure 5 , the selected test storage unit 102 is also adjacent to the operation storage unit 101, and the adjacent represents the adjacent interval of one storage unit.

[0090] On this basis, the selected test storage unit 102 and the control storage unit 103 are located on the same operation line. For example, the selected test storage unit 102 and the control storage unit 103 are located on the same word line WL; or, the selected test storage unit 102 and the control storage unit 103 are located on the same bit line BL.

[0091] It should be noted that in Figure 4In the example, the operation storage unit 101 and the test storage unit 102 are located at the same word line WL, and at this time, the test storage unit 102 and the control storage unit 103 are located at the same bit line BL, which does not constitute a limitation on the embodiment, and in a specific application, the test storage unit 102 and the control storage unit 103 can also be arranged at the same word line WL. Correspondingly, the operation storage unit 101 and the test storage unit 102 are located at the same bit line BL, and at this time, the test storage unit 102 and the control storage unit 103 are located at the same word line WL, which does not constitute a limitation on the embodiment, and in a specific application, the test storage unit 102 and the control storage unit 103 can also be arranged at the same bit line BL.

[0092] The monitoring method of the memory provided by the embodiment of the disclosure, the execution object includes a test storage unit and a control storage unit; wherein the test result of the test storage unit is used to represent the test result of the crosstalk storage unit, and the test result of the control storage unit is used to represent the influence degree of the write-read delay; the monitoring result obtained in combination with the first state information of the test storage unit and the second state information of the control storage unit excludes the monitoring influence of the write-read delay on the test storage unit, so as to more accurately monitor the write operation performance of the memory.

[0093] It should be noted that, Figure 2 to 5 The storage array structure shown is only used to illustrate the selection manner of the operation storage unit 101, the test storage unit 102 and the control storage unit 103 in the embodiment, and does not constitute a limitation on the storage array structure.

[0094] Correspondingly, the application also provides an embodiment of a memory, referring to Figure 2 , comprising: a storage array module including a plurality of storage units; and a monitoring module 401 connected to the storage array module and configured to perform monitoring according to the monitoring method of the memory as Figure 1 shown.

[0095] For the storage array module, the storage array module includes a plurality of storage units 100, the storage units 100 are arranged in a row-column array, the storage units 100 in the same row are connected to the same word line WL, and the storage units 100 in the same column are connected to the same bit line BL. Therefore, the storage array module can be regarded as a collection of storage units arranged along the bit line extension direction 302 and the word line extension direction 301.

[0096] For the monitoring method adopted by the monitoring module 401, the monitoring object includes a test storage unit 102 and a control storage unit 103; the monitoring result obtained in combination with the first state information of the test storage unit 102 and the second state information of the control storage unit 103 excludes the monitoring influence of other factors on the test storage unit 102, so as to more accurately monitor the write operation performance of the memory.

[0097] The operation storage unit 101 (Aggressive Cell) is the target storage unit corresponding to the aforementioned memory read-write operation. The test storage unit 102 (Victim Cell) is adjacent to the operation storage unit 101. That is, the heat generated by the write operation on the operation storage unit 101 will inevitably cause thermal crosstalk to the test storage unit 102, thereby reducing the threshold voltage of the test storage unit 102. The distance between the reference storage unit 103 (Ref Cell) and the operation storage unit 101 is greater than the distance between the test storage unit 102 and the operation storage unit 101, so that the reference storage unit 103 is not affected by the heat.

[0098] For the manner in which the monitoring module 401 selects the test storage unit 102 and the reference storage unit 103 in the storage array module, refer to Figure 2 to 5 .

[0099] In some embodiments, referring to Figure 2 , the test storage unit 102, the reference storage unit 103, and the operation storage unit 101 selected by the monitoring module 401 are on the same operation line.

[0100] For the "operation line" mentioned in this embodiment, the "operation line" includes at least one of the word line WL or the bit line BL.

[0101] In one example, the test storage unit 102 and the operation storage unit 101 are located on the same word line WL, and at this time the reference storage unit 103 selects a storage unit 100 located farther away on the same word line WL.

[0102] In one example, the test storage unit 102 and the operation storage unit 101 are located on the same bit line BL, and at this time the reference storage unit 103 selects a storage unit 100 located farther away on the same bit line BL.

[0103] Further, in some embodiments, referring to Figure 3 , the reference storage unit 103 and the test storage unit 102 selected by the monitoring module are adjacent, and the reference storage unit 103 and the operation storage unit 101 are located on both sides of the test storage unit 102.

[0104] In some embodiments, referring to Figure 4 , the test storage unit 102 selected by the monitoring module 401 is also diagonally adjacent to the operation storage unit 101, and diagonally adjacent means that the test storage unit 102 and the operation storage unit 101 are adjacent storage units located on different operation lines.

[0105] On this basis, the selected test storage unit 102 and the control storage unit 103 are located on the same operation line. For example, the selected test storage unit 102 and the control storage unit 103 are located on the same word line WL; or, the selected test storage unit 102 and the control storage unit 103 are located on the same bit line BL.

[0106] It should be noted that, in some embodiments, the selected test storage unit 102 and the control storage unit 103 can also be diagonally adjacent, that is, the test storage unit 102 and the control storage unit 103 are adjacent storage units located on different operation lines.

[0107] In some embodiments, with reference to Figure 5 , the monitoring module 401 selects the test storage unit 102 which is also adjacent to the operation storage unit 101, and the adjacent means adjacent by one storage unit spacing.

[0108] On this basis, the selected test storage unit 102 and the control storage unit 103 are located on the same operation line. For example, the selected test storage unit 102 and the control storage unit 103 are located on the same word line WL; or, the selected test storage unit 102 and the control storage unit 103 are located on the same bit line BL.

[0109] It should be noted that, in the example of Figure 5 , the operation storage unit 101 and the test storage unit 102 are located on the same word line WL, at this time, the test storage unit 102 and the control storage unit 103 are located on the same bit line BL, which does not constitute a limitation on the present embodiment, and in specific applications, the test storage unit 102 and the control storage unit 103 can also be arranged on the same word line WL. Correspondingly, the operation storage unit 101 and the test storage unit 102 are located on the same bit line BL, at this time, the test storage unit 102 and the control storage unit 103 are located on the same word line WL, which does not constitute a limitation on the present embodiment, and in specific applications, the test storage unit 102 and the control storage unit 103 can also be arranged on the same bit line BL.

[0110] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the detailed description of other embodiments above, which will not be repeated here.

[0111] The above has described the basic concept, and it is obvious that the above detailed disclosure is only as an example and does not constitute a limitation on the present disclosure for those skilled in the art. Although it is not explicitly stated here, those skilled in the art can make various modifications, improvements and corrections to the present disclosure. Such modifications, improvements and corrections are suggested in the present disclosure, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present disclosure.

[0112] The above describes in detail the monitoring method of the memory and the memory provided by the embodiments of the present disclosure. The principles and implementation manners of the present disclosure are described by using specific examples. The above description of the embodiments is only used to help understand the method of the present disclosure and the core idea thereof. Meanwhile, for those skilled in the art, according to the idea of the present disclosure, the specific implementation manners and application ranges will be changed. Therefore, the content of the present description should not be understood as a limitation of the present disclosure.

Claims

1. A method of monitoring a memory, characterized by, The method comprises the following steps: acquiring a test storage unit and a control storage unit based on an operation storage unit, the test storage unit being adjacent to the operation storage unit, the control storage unit being a first distance from the operation storage unit, the test storage unit being a second distance from the operation storage unit, the first distance being greater than the second distance; performing a cyclic write operation on the operation storage unit, and reading first state information of the test storage unit and second state information of the control storage unit; acquiring a monitoring result of the memory based on the first state information and the second state information; the method of acquiring the monitoring result of the memory comprises acquiring an original bit error code rate based on the first state information and the second state information; the method of acquiring the original bit error code rate based on the first state information and the second state information comprises: acquiring a first error code rate based on the first state information; acquiring a second error code rate based on the second state information; acquiring the original bit error code rate based on a difference between the first error code rate and the second error code rate.

2. The method of claim 1, wherein, The test storage unit, the control storage unit and the operation storage unit are on the same operation line.

3. The method of claim 2, wherein, The control storage unit is adjacent to the test storage unit, and the control storage unit and the operation storage unit are located on both sides of the test storage unit.

4. The method of claim 2, wherein the memory is a dynamic random access memory (DRAM). The test storage unit is also adjacent to the operation storage unit, and the adjacent represents an interval of one storage unit.

5. The method of monitoring a memory according to any one of claims 2 to 4, wherein, The operation line comprises at least one of a word line or a bit line.

6. The method of claim 1, wherein, The second state information is acquired at the same time as the first state information.

7. The method of claim 1, wherein, Before the cyclic write operation is performed on the operation storage unit, the method further comprises resetting the operation storage unit, the test storage unit and the control storage unit.

8. A memory, comprising: The method comprises the following steps: a storage array module comprising a plurality of storage units; a monitoring module connected to the storage array module and configured to monitor according to the monitoring method of the memory according to any one of claims 1 to 7.

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