Area arc-free circuit breaker and control method

Abstract

The invention discloses a transformer area arc-free circuit breaker and a control method. The transformer area arc-free circuit breaker is connected with a voltage sensor, a current sensor, a mechanical circuit breaker, a GPS module, a wireless communication module, a thyristor driving circuit and an inverter through a microprocessor. The microprocessor receives sensing signals of the voltage sensor and the current sensor, clock signals of the GPS module and control information of the wireless communication module. According to induction signals of the voltage sensor and the current sensor, clock signals of the GPS module and control information of the wireless communication module, the operation state of the transformer area is calculated, and the mechanical circuit breaker, the thyristor driving circuit and the inverter are controlled according to calculation and analysis results. The problem that a traditional circuit breaker cannot meet the new energy requirements of more and more photovoltaic and charging piles and the like in a transformer area is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit breakers, and in particular relates to an arc-free circuit breaker in a transformer area and a control method thereof. Background Art

[0002] Previous inventions or utility models have proposed arc-free AC circuit breaker design schemes, such as an intelligent arc-free circuit breaker with patent number ZL200520096776.4, a three-phase arc-free circuit breaker with application number 201020652885.0, a high-breakage arc-free circuit breaker with application number CN201710544678.X, and an arc-extinguishing module for an arc-free miniature circuit breaker with application number 202221641724.0, but all of them have certain defects. Due to the use of new energy, there are more and more charging piles and rooftop photovoltaics in the substation area, and the power quality in the substation area is getting worse and worse. The traditional circuit breaker breaking decision can no longer meet the increasing demand for new energy in the substation area. The access to new energy has also put forward new demands for arc-free AC circuit breakers. The present invention designs an arc-free circuit breaker based on the increasing demand for new energy access in existing substations. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, the present invention provides an arc-free circuit breaker and control method for a transformer substation, which solves the problem that traditional circuit breakers can no longer meet the increasing demand for new energy sources such as photovoltaics and charging piles in transformer substations.

[0004] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention is: an arc-free circuit breaker in a transformer area, comprising a voltage sensor, a current sensor, a left-end resistor, a left-end inductor, a transformer, a mechanical circuit breaker, a right-end resistor, a right-end inductor, a thyristor, a thyristor drive circuit, a microprocessor, a wireless communication module, a GPS module and an inverter;

[0005] Wherein, the microprocessor is connected to the voltage sensor, the current sensor, the thyristor drive circuit, the wireless communication module, the GPS module and the inverter respectively; the voltage sensor is also connected to the current sensor, the left-end resistor and the left-end inductor in sequence; the left-end inductor is also connected to the No. 1 terminal of the transformer, the mechanical circuit breaker and the thyristor respectively; the inverter is connected to the No. 3 terminal and the No. 4 terminal of the transformer; the thyristor drive circuit is connected to the thyristor; the mechanical circuit breaker is also connected to the thyristor and the right-end resistor respectively; the right-end resistor is also connected to the right-end inductor;

[0006] The voltage sensor is used to collect the three-phase voltage value output by the substation transformer, the current sensor is used to collect the three-phase current value output by the substation transformer, the wireless communication module is used to receive the control information of the substation circuit breaker, the GPS module is used to provide a clock signal for the microprocessor, and the microprocessor is used to calculate the substation operation status according to the three-phase voltage and current values, clock signals and control information output by the substation transformer, and control the mechanical circuit breaker and thyristor drive circuit according to the calculation results. The thyristor is used to control the current.

[0007] Further: the inverter includes a three-phase inverter structure, and the inverter structure of each phase includes a capacitor, a connection terminal K1, a connection terminal K2, a first IGBT module, a second IGBT module, a third IGBT module, a fourth IGBT module, a first IGBT drive module, a second IGBT drive module, a third IGBT drive module, a fourth IGBT drive module, a connection port Q1, a connection port Q2, a connection port Q3 and a connection port Q4;

[0008] The connection terminal K1 is connected to the terminal No. 3 of the transformer, the connection terminal K2 is connected to the terminal No. 4 of the transformer, and the connection port Q1, the connection port Q2, the connection port Q3 and the connection port Q4 are all connected to the ports of the microprocessor;

[0009] The gate of the first IGBT module is connected to the connection port Q1 through the first IGBT driving module, the collector of the first IGBT module is connected to one end of the capacitor, the emitter of the first IGBT module is connected to the connection terminal K2 and the collector of the second IGBT module respectively, the gate of the second IGBT module is connected to the connection port Q2 through the second IGBT driving module, and the emitter of the second IGBT module is connected to the other end of the capacitor;

[0010] The gate of the fourth IGBT module is connected to the connection port Q4 through the fourth IGBT driving module, the collector of the fourth IGBT module is connected to one end of the capacitor, the emitter of the fourth IGBT module is connected to the connection terminal K1 and the collector of the third IGBT module respectively, the gate of the third IGBT module is connected to the connection port Q3 through the third IGBT driving module, and the emitter of the third IGBT module is connected to the other end of the capacitor.

[0011] The control method of the arc-free circuit breaker in the transformer area comprises the following steps:

[0012] S1, perform initialization operation through the initialization subroutine;

[0013] S2, calculating the tripping criterion through the tripping and compensation criterion calculation subroutine;

[0014] S3. In response to the tripping criterion being equal to 1, a tripping action is performed through a tripping action subroutine.

[0015] Further: In said S268, the method of calling the compensation action subroutine is specifically as follows:

[0016] S2681. Determine whether BuChangF2 is equal to 1. If so, then:

[0017] bcDataF2[2*i]=-1*BiF2*M2data[i], where i is 0 to 99;

[0018] bcDataF2[2*i+1]=(bcDataF2[2*i]+bcDataF2[2*i+2]) / 2, where i is 0 to 98;

[0019] bcDataF2

[199] =(bcDataF2[0]+bcDataF2

[198] ) / 2;

[0020] bcDataF2[i+200]=bcDataF2[i], where i is 0 to 199;

[0021] If not, bcDataF2[i]=0, where i is 0 to 399;

[0022] S2682, determine whether BuChangF3 is equal to 1. If not, bcDataF3[i]=0, where i is 0 to 399. If yes, then:

[0023] bcDataF3[2*i]=-1*BiF3*M3data[i], where i is 0 to 65;

[0024] bcDataF3[2*i+1]=(bcDataF3[2*i]+bcDataF3[2*i+2]) / 2; wherein i is 0 to 64;

[0025] bcDataF3

[131] =(bcDataF3[0]+bcDataF3

[130] ) / 2;

[0026] bcDataF3

[132] =bcDataF3

[131] ;

[0027] bcDataF3[i+133]=bcDataF3[i]; wherein i is 0 to 132;

[0028] bcDataF3

[266] =bcDataF3

[265] ;

[0029] bcDataF3[i+267]=bcDataF3[i]; wherein i is 0 to 132;

[0030] S2683, determine whether BuChangF4 is equal to 1; if not, then bcDataF4[i]=0, where i is 0-399; if yes, then:

[0031] bcDataF4[2*i]=-1*BiF4*M4data[i], i ranges from 0 to 49;

[0032] bcDataF4[2*i+1]=(bcDataF4[2*i]+bcDataF4[2*i+2]) / 2; where i ranges from 0 to 48;

[0033] bcDataF4

[99] =(bcDataF4[0]+bcDataF4

[98] ) / 2;

[0034] bcDataF4[i+100]=bcDataF4[i]; wherein i is 0 to 99;

[0035] bcDataF4[i+200]=bcDataF4[i]; wherein i is 0 to 199;

[0036] S2684: Determine whether BuChangF5 is equal to 1, if not, bcDataF5[i]=0; wherein i is 0-399;

[0037] If yes, then:

[0038] bcDataF5[2*i]=-1*BiF5*M5data[i], where i ranges from 0 to 39;

[0039] bcDataF5[2*i+1]=(bcDataF5[2*i]+bcDataF5[2*i+2]) / 2; wherein i is 0 to 38;

[0040] bcDataF5

[79] =(bcDataF5[0]+bcDataF5

[78] ) / 2;

[0041] bcDataF5[i+80]=bcDataF5[i]; wherein i is 0 to 79;

[0042] bcDataF5[i+160]=bcDataF6[i]; wherein i is 0 to 159;

[0043] bcDataF5[i+320]=bcDataF6[i]; wherein i is 0 to 79;

[0044] S2685, calculate BuChangV;

[0045] BuChangV=bcDataF2[i]+bcDataF3[i]+bcDataF4[i]+bcDataF5[i], i=0~399;

[0046] S2686, set CBuchang=0 to complete calling the compensation action subroutine.

[0047] Further: S1 comprises the following sub-steps:

[0048] S11, set the low frequency interrupt clock to 20 milliseconds, set the high frequency interrupt clock to 50 microseconds, set the wireless communication module reading interface, and set the GPS module reading interface;

[0049] S12, setting low-frequency interrupt conditions, calling low-frequency interrupt subroutine, setting high-frequency interrupt conditions, calling high-frequency interrupt subroutine;

[0050] S13. Set variables, including:

[0051] The current time in seconds is represented by MA, with a value range of 0-59. The current time in milliseconds is represented by HA, with a value range of 0-999. The current time in microseconds is represented by UA, with a value range of 0-999. The A-phase voltage phase zero millisecond moment is represented by AH0, with a unit of 50 milliseconds and a value range of 0-20. The A-phase voltage phase zero microsecond moment is represented by AU0, with a unit of microseconds and a value range of 0-20. The high-frequency interrupt counter is represented by CH, with a value range of 0-999. The trip voltage threshold is represented by VY, the trip current threshold is represented by IY, the compensation threshold is represented by BY, the trip mark is represented by TZ, the sensor reading counter is represented by CVA, with a value range of 0-999, the cycle counter is represented by CZQ, with a value range of 0-199, the voltage sum is represented by SUMV, and the current sum is represented by SUMI.

[0052] The first reading value of phase A of the voltage sensor is represented by the array AVINA

[400] , the second reading value of phase A of the voltage sensor is represented by the array AVINB

[400] , the floating point value of phase A voltage is represented by the array AFV

[400] , the first reading value of phase A of the current sensor is represented by the array AIINA

[400] , the second reading value of phase A of the current sensor is represented by the array AIINB

[400] , the floating point value of phase A current is represented by the array AFI

[400] , and the compensation of phase A is represented by the array AVBZ

[400] ;

[0053] The B-phase first reading value of the voltage sensor is represented by the array BVINA

[400] , the B-phase second reading value of the voltage sensor is represented by the array BVINB

[400] , the B-phase voltage floating point value is represented by the array BFV

[400] , the B-phase first reading value of the current sensor is represented by the array BIINA

[400] , the B-phase second reading value of the current sensor is represented by the array BIINB

[400] , the B-phase current floating point value is represented by the array BFI

[400] , and the B-phase compensation is represented by the array BVBZ

[400] ;

[0054] The first reading value of the C phase of the voltage sensor is represented by the array CVINA

[400] , the second reading value of the C phase of the voltage sensor is represented by the array CVINB

[400] , the floating point value of the C phase voltage is represented by the array CFV

[400] , the first reading value of the C phase of the current sensor is represented by the array CIINA

[400] , the second reading value of the C phase of the current sensor is represented by the array CIINB

[400] , the floating point value of the C phase current is represented by the array CFI

[400] , and the C phase compensation is represented by the array CVBZ

[400] ;

[0055] The time update data position is indicated by PT, the trip calculation variable is indicated by FTZ, the compensation calculation variable is indicated by FBZ, the low frequency interruption mark is indicated by FZD, the storage selection mark is indicated by SELF, the A phase storage position counter is indicated by ACNTVI, the B phase storage position counter is indicated by BCNTVI, and the C phase storage position counter is indicated by CCNTVI;

[0056] S14, initialize variables, the initialized variables are specifically:

[0057] MA=0, HA=0, UA=0, AH0=0, AU0=0, CH=0, PT=0, FTZ=0, FBZ=0, TZ=0, SELF=0, ACNTVI=0, BCNT VI=0, CCNTVI=0, FZD=0, FBZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0;

[0058] AVINA

[400] , AVINB

[400] , AIINA

[400] , AIINB

[400] , BVINA

[400] , BVINB

[400] , BIINA

[400] , BIINB

[400] , CVINA

[400] , CVINB

[400] , CIINA

[400] , and CIINB

[400] are initialized to all zeros;

[0059] S15. Set the first parameter M1data and comparison variables BiJiao, BiJiaoV[i].

[0060] Further: In said S12, the method of calling the low-frequency interrupt subroutine is specifically as follows:

[0061] SA1, read the data of the wireless communication module, parse the read data according to the wireless communication protocol, and update the AH0, AUO, VY, IY and BY variables;

[0062] The wireless communication protocol is arranged by bytes, in the following order: 55, AA, AH0, AU0, VY high eight bits, VY low eight bits, IY high eight bits, IY low eight bits, BY high eight bits, BY low eight bits, check bit, 33, CC;

[0063] Among them, 55, AA indicate the start of the communication packet, 33, CC indicate the end of the communication packet; the check bits are A0 high eight bits, AH0, AU0, VY low eight bits, IY high eight bits, IY low eight bits, BY high eight bits, BY low eight bits, bit by bit XOR;

[0064] SA2, read the GPS module data, parse the read data according to the GPS communication protocol, and update the MA, HA and UA variables;

[0065] The GPS communication protocol is arranged by bytes, in the following order: 55, AA, MA, AH0, AU0, check bit, 33, CC;

[0066] Among them, 55, AA indicates the beginning of the communication packet, 33, CC indicates the end of the communication packet; the check bit is MA, HA high eight bits, HA low eight bits bit by bit XOR;

[0067] SA3, assign the value of CVA to PT;

[0068] SA4, invert SELF and calculate ACNTVI, ACNTVI = AH0*20+AUO;

[0069] In response to ACNTVI being less than or equal to 133, CCNTVI=ACNTVI+133;

[0070] BCNTVI=ACNTVI+266;

[0071] In response to ACNTVI being greater than or equal to 266, CCNTVI=ACNTVI-133;

[0072] BCNTVI = ACNTVI - 266;

[0073] In response to ACNTVI being greater than 133 and less than 266, CCNTVI=ACNTVI+133, BCNTVI=ACNTVI-133;

[0074] SA5. Set FZD=1.

[0075] Further: In said S12, the method of calling the high-frequency interrupt subroutine is specifically as follows:

[0076] SB1. Set VIN[CVA] equal to the storage value of the memory corresponding to the voltage sensor, set IIN[CVA] equal to the storage value of the memory corresponding to the current sensor, and add 1 to the CVA value;

[0077] SB2, determine whether the CVA value is equal to 1000, if so, go to SB3, if not, go to SB4;

[0078] SB3, set CVA = 0, FBZ = 1;

[0079] SB4, determine whether BZ is equal to 1, if so, enter SB5, if not, complete the call of the high-frequency interrupt subroutine;

[0080] SB5. Determine whether BuChangV[CBuchang] is greater than BiJiaoV[CBuchang]. If so, control the second IGBT module to be turned on and the third IGBT module to be turned off. If not, control the second IGBT module to be turned off and the third IGBT module to be turned on.

[0081] SB6. Add 1 to the value of Cbuchang. If Cbuchang is greater than 399, set Cbuchang to 0.

[0082] SB7. Complete calling the high-frequency interrupt subroutine.

[0083] Further: S2 comprises the following sub-steps:

[0084] S21, in response to FZD being equal to 0, determining whether SELF is true, if so, proceeding to S22;

[0085] If not, for i=0-399, the value of the corresponding variable is calculated by the following formula and the process goes to S23;

[0086] AFV[i]=(AVINB[i]–32768) / 32768

[0087] AFI[i]=(AIINB[i]–32768) / 32768

[0088] BFV[i]=(BVINB[i]–32768) / 32768

[0089] BFI[i]=(BIINB[i]–32768) / 32768

[0090] CFV[i]=(CVINB[i]–32768) / 32768

[0091] CFI[i]=(CIINB[i]–32768) / 32768

[0092] S22, for i=0-399, calculate the value of the corresponding variable by the following formula, and enter S23;

[0093] AFV[i]=(AVINA[i]–32768) / 32768

[0094] AFI[i]=(AIINA[i]–32768) / 32768

[0095] BFV[i]=(BVINA[i]–32768) / 32768

[0096] BFI[i]=(BIINA[i]–32768) / 32768

[0097] CFV[i]=(CVINA[i]–32768) / 32768

[0098] CFI[i]=(CIINA[i]–32768) / 32768

[0099] S23, calculate ASUMV, BSUMV, CSUMV, ASUMI, BSUMI and CSUMI according to the calculated variables, and enter S24;

[0100]

[0101] S24, calculate the maximum value of ASUMV, BSUMV and CSUMV, expressed as MAXSUMV, calculate the maximum value of ASUMI, BSUMI and CSUMI, expressed as MAXSUMI, and enter S25;

[0102] S25, determine whether MAXSUMV is less than VY and MAXSUMI is greater than IY. If so, set the tripping criterion TZ=1 and enter S26; if not, set the tripping criterion TZ=0 and enter S26;

[0103] S26. Call the compensation judgment subroutine.

[0104] Further: S26 specifically includes:

[0105] S261. INDATA

[300] takes 300 samples before the current IIN sampling data. The sampling method is as follows: Determine whether CAV is greater than or equal to 300. If so, then INDATA

[300] = IIN[CAV - 300 ~ CAV]; if not, then the data of INDATA

[300] is the concatenation of two segments of data, IIN[1000 - CAV ~ 1000] and IIN[0 ~ CAV].

[0106] S262. Search within the range of i = 0 to 100 for the first i that simultaneously satisfies INDATA[i] * INDATA[i + 4] < 0 and INDATA[i] < INDATA[i + 4], and let j = i.

[0107] S263. Calculate SUMF1:

[0108]

[0109] S264. Take k = 1 to 25 and calculate SUMF2[k]:

[0110]

[0111] Obtain the maximum value in SUMF2[k], let the maximum value be MaxSumF2, and let MaxkF2 be the k value corresponding to the maximum value.

[0112] Calculate BiF2:

[0113] BiF2 = MaxSumF2 / SUMF1;

[0114] Determine whether BiF2 is greater than 0.03. If so, then let BuChangF2 = 1; if not, then let BuChangF2 = 0.

[0115] S265. Take k = 1 to 15 and calculate SUMF3[k]:

[0116]

[0117] In the formula, m is the remainder obtained by dividing i by 66.

[0118] Obtain the maximum value in SUMF3[k], let the maximum value be MaxSumF3, and let MaxkF3 be the k value corresponding to the maximum value.

[0119] Calculate BiF3:

[0120] BiF3 = MaxSumF3 / SUMF1

[0121] Determine whether BiF3 is greater than 0.03. If so, set BuChangF3=1; if not, set BuChangF3=0.

[0122] S266, take k=1-12, calculate SUMF4[k]:

[0123]

[0124] Where m is the remainder obtained by dividing i by 50;

[0125] Get the maximum value in SUMF4[k], let the maximum value be MaxSumF4, and let MaxkF4 be the k value that takes the maximum value;

[0126] Calculate BiF4:

[0127] BiF4=MaxSumF4 / SUMF1

[0128] Determine whether BiF4 is greater than 0.03. If so, set BuChangF4=1; if not, set BuChangF4=0.

[0129] S267, take k=1-10, calculate SUMF5[k]=:

[0130]

[0131] Where m is the remainder obtained by dividing i by 40;

[0132] Get the maximum value in SUMF5[k], let the maximum value be MaxSumF5, and let MaxkF5 be the k value that takes the maximum value;

[0133] Calculate BiF5:

[0134] BiF5=MaxSumF5 / SUMF1

[0135] Determine whether BiF5 is greater than 0.03. If so, set BuChangF5=1; if not, set BuChangF5=0.

[0136] S268, calculation is not long;

[0137] BuChang=BuChangF2+BuChangF3+BuChangF4+BuChangF5;

[0138] Determine whether BuChang is greater than or equal to 1. If so, BZ=1 and call the compensation action subroutine. If not, BZ=0.

[0139] Further: In said S3, the method of performing the tripping action through the tripping action subroutine is specifically as follows:

[0140] S31, control thyristor conduction;

[0141] S32, control the mechanical circuit breaker to disconnect;

[0142] S33, control the thyristor to disconnect.

[0143] The beneficial effects of the present invention are as follows: the present invention provides an arc-free circuit breaker and control method for a transformer substation, which is connected to a voltage sensor, a current sensor, a mechanical circuit breaker, a GPS module, a wireless communication module, a thyristor drive circuit, and an inverter through a microprocessor. The microprocessor receives the sensing signals of the voltage sensor and the current sensor, the clock signal of the GPS module, and the control information of the wireless communication module; the operating state of the transformer substation is calculated according to the sensing signals of the voltage sensor and the current sensor, the clock signal of the GPS module, and the control information of the wireless communication module, and the mechanical circuit breaker, the thyristor drive circuit, and the inverter are controlled according to the calculation and analysis results, which solves the problem that traditional circuit breakers can no longer meet the increasing demand for new energy sources such as photovoltaics and charging piles in transformer substations. BRIEF DESCRIPTION OF THE DRAWINGS

[0144] Figure 1 It is a schematic diagram of the structure of a non-arc circuit breaker in a transformer area of ​​the present invention;

[0145] Figure 2 The figure is a schematic diagram of the transformer connection method.

[0146] Figure 3 The schematic diagram of the inverter structure is shown in FIG.

[0147] Figure 4 The figure is a flow chart of the control method of the arc-free circuit breaker in the transformer area.

[0148] Wherein: 1, voltage sensor; 101, capacitor; 102-1, connection terminal K1; 102-2, connection terminal K2; 103-1, first IGBT module; 103-2, second IGBT module; 103-3, third IGBT module; 103-4, fourth IGBT module; 104-1, first IGBT driver module; 104-2, second IGBT driver module; 104-3, third IGBT driver module; 104-4, first Four IGBT drive modules; 105-1, connection port Q1; 105-2, connection port Q2; 105-3, connection port Q3; 105-4, connection port Q4; 2, current sensor; 3, left-end resistor; 4, left-end inductor; 5, transformer; 6, mechanical circuit breaker; 7, right-end resistor; 8, right-end inductor; 9, thyristor; 10, thyristor drive circuit; 11, microprocessor; 12, wireless communication module; 13, GPS module; 14, inverter. DETAILED DESCRIPTION

[0149] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0150] Embodiment 1:

[0151] like Figure 1 As shown, in one embodiment of the present invention, an arc-free circuit breaker for a transformer area includes a voltage sensor 1, a current sensor 2, a left-end resistor 3, a left-end inductor 4, a transformer 5, a mechanical circuit breaker 6, a right-end resistor 7, a right-end inductor 8, a thyristor 9, a thyristor drive circuit 10, a microprocessor 11, a wireless communication module 12, a GPS module 13 and an inverter 14;

[0152] Wherein, the microprocessor 11 is respectively connected to the voltage sensor 1, the current sensor 2, the thyristor drive circuit 10, the wireless communication module 12, the GPS module 13 and the inverter 14, the voltage sensor 1 is also connected to the current sensor 2, the left-end resistor 3 and the left-end inductor 4 in sequence, the left-end inductor 4 is also respectively connected to the No. 1 terminal of the transformer 5, the mechanical circuit breaker 6 and the thyristor 9, the inverter 14 is connected to the No. 3 terminal and the No. 4 terminal of the transformer 5, the thyristor drive circuit 10 is connected to the thyristor 9, the mechanical circuit breaker 6 is also respectively connected to the thyristor 9 and the right-end resistor 7, and the right-end resistor 7 is also connected to the right-end inductor 8;

[0153] The voltage sensor 1 is used to collect the three-phase voltage value output by the substation transformer, the current sensor 2 is used to collect the three-phase current value output by the substation transformer, the wireless communication module 12 is used to receive the control information of the substation circuit breaker, the GPS module 13 is used to provide a clock signal for the microprocessor 11, and the microprocessor 11 is used to calculate the substation operation status according to the three-phase voltage and current values, clock signals and control information output by the substation transformer, and control the mechanical circuit breaker 6 and the thyristor drive circuit 10 according to the calculation results. The thyristor 9 is used to control the current.

[0154] In this embodiment, Figure 1 Only one phase of the structure is shown. In the three-phase structure, there is only one microprocessor 11, wireless communication module 12, and GPS module 13, and the mechanical circuit breaker 6 is a three-phase circuit breaker; the other components, such as the voltage sensor 1, the current sensor 2, the left-end resistor 3, the left-end inductor 4, the right-end resistor 7, the right-end inductor 8, the thyristor 9, and the thyristor drive circuit 10, need to be used one for each phase, and three for each phase, and the connection method between each phase is the same.

[0155] The output of the substation transformer is a three-phase conductor, which passes through the voltage sensor 1 and the current sensor 2, and then is connected in series with a left-end resistor 3 and a left-end inductor 4, and then is connected to one of the phases of the mechanical circuit breaker 6 input. The connection point is connected to the No. 1 connection terminal of the transformer 5. The same phase output of the mechanical circuit breaker 6 is connected to the right-end resistor 7. A right-end inductor 8 is connected in series to the right side of the right-end resistor 7. The right-end inductor 8 is connected to the substation load to supply power to the substation load and is connected to the input end of the mechanical circuit breaker 6. The output end of the mechanical circuit breaker 6 is connected to the input end of the power quality regulation module. The voltage sensor 1 and current sensor 2 of each phase collect the voltage and current values ​​of the three phases ABC output by the substation transformer, and the sensor output is connected to the analog-to-digital conversion interface of the microprocessor 11.

[0156] The output of the thyristor driving circuit 10 is connected to the thyristor 9 to control the thyristor 9; the thyristor 9 is a bidirectional thyristor, which is composed of two thyristors connected in reverse parallel.

[0157] Transformer 5 is connected as follows Figure 2 shown.

[0158] The inverter 14 includes a three-phase inverter structure. In this embodiment, the inverter structure is as follows: Figure 3As shown, the inverter structure of each phase includes a capacitor 101, a connection terminal K1 102-1, a connection terminal K2 102-2, a first IGBT module 103-1, a second IGBT module 103-2, a third IGBT module 103-3, a fourth IGBT module 103-4, a first IGBT driver module 104-1, a second IGBT driver module 104-2, a third IGBT driver module 104-3, a fourth IGBT driver module 104-4, a connection port Q1 105-1, a connection port Q2 105-2, a connection port Q3 105-3 and a connection port Q4 105-4;

[0159] The connection terminal K1 102-1 is connected to the terminal No. 3 of the transformer 5, the connection terminal K2 102-2 is connected to the terminal No. 4 of the transformer 5, the connection port Q1 105-1, the connection port Q2 105-2, the connection port Q3 105-3 and the connection port Q4 105-4 are all connected to the ports of the microprocessor 11;

[0160] The gate of the first IGBT module 103-1 is connected to the connection port Q1 105-1 through the first IGBT driving module 104-1, the collector of the first IGBT module 103-1 is connected to one end of the capacitor 101, the emitter of the first IGBT module 103-1 is connected to the connection terminal K2 102-2 and the collector of the second IGBT module 103-2 respectively, the gate of the second IGBT module 103-2 is connected to the connection port Q2 105-1 through the second IGBT driving module 104-2, and the emitter of the second IGBT module 103-2 is connected to the other end of the capacitor 101;

[0161] The gate of the fourth IGBT module 103-4 is connected to the connection port Q4 105-4 through the fourth IGBT driving module 104-4, the collector of the fourth IGBT module 103-4 is connected to one end of the capacitor 101, the emitter of the fourth IGBT module 103-4 is connected to the connection terminal K1 102-1 and the collector of the third IGBT module 103-3 respectively, the gate of the third IGBT module 103-3 is connected to the connection port Q3 105-3 through the third IGBT driving module 104-3, and the emitter of the third IGBT module 103-3 is connected to the other end of the capacitor 101.

[0162] like Figure 4 As shown, the control method of the arc-free circuit breaker in the substation includes the following steps:

[0163] S1, perform initialization operation through the initialization subroutine;

[0164] S2, calculating the tripping criterion through the tripping and compensation criterion calculation subroutine;

[0165] S3. In response to the tripping criterion being equal to 1, a tripping action is performed through a tripping action subroutine.

[0166] The S1 comprises the following sub-steps:

[0167] S11, set the low frequency interrupt clock to 20 milliseconds, set the high frequency interrupt clock to 50 microseconds, set the wireless communication module 12 to read the interface, and set the GPS module 13 to read the interface;

[0168] S12, setting low-frequency interrupt conditions, calling low-frequency interrupt subroutine, setting high-frequency interrupt conditions, calling high-frequency interrupt subroutine;

[0169] S13. Set variables, including:

[0170] The current time in seconds is represented by MA, with a value range of 0-59. The current time in milliseconds is represented by HA, with a value range of 0-999. The current time in microseconds is represented by UA, with a value range of 0-999. The A-phase voltage phase zero millisecond moment is represented by AH0, with a unit of 50 milliseconds and a value range of 0-20. The A-phase voltage phase zero microsecond moment is represented by AU0, with a unit of microseconds and a value range of 0-20. The high-frequency interrupt counter is represented by CH, with a value range of 0-999. The trip voltage threshold is represented by VY, the trip current threshold is represented by IY, the compensation threshold is represented by BY, the trip mark is represented by TZ, the sensor reading counter is represented by CVA, with a value range of 0-999, the cycle counter is represented by CZQ, with a value range of 0-199, the voltage sum is represented by SUMV, and the current sum is represented by SUMI.

[0171] The first reading value of phase A of voltage sensor 1 is represented by array AVINA

[400] , the second reading value of phase A of voltage sensor 1 is represented by array AVINB

[400] , the floating point value of phase A voltage is represented by array AFV

[400] , the first reading value of phase A of current sensor 2 is represented by array AIINA

[400] , the second reading value of phase A of current sensor 2 is represented by array AIINB

[400] , the floating point value of phase A current is represented by array AFI

[400] , and the compensation of phase A is represented by array AVBZ

[400] ;

[0172] The first B-phase reading value of voltage sensor 1 is represented by array BVINA

[400] , the second B-phase reading value of voltage sensor 1 is represented by array BVINB

[400] , the B-phase voltage floating point value is represented by array BFV

[400] , the first B-phase reading value of current sensor 2 is represented by array BIINA

[400] , the second B-phase reading value of current sensor 2 is represented by array BIINB

[400] , the B-phase current floating point value is represented by array BFI

[400] , and the B-phase compensation is represented by array BVBZ

[400] ;

[0173] The first reading value of phase C of voltage sensor 1 is represented by array CVINA

[400] , the second reading value of phase C of voltage sensor 1 is represented by array CVINB

[400] , the floating point value of phase C voltage is represented by array CFV

[400] , the first reading value of phase C of current sensor 2 is represented by array CIINA

[400] , the second reading value of phase C of current sensor 2 is represented by array CIINB

[400] , the floating point value of phase C current is represented by array CFI

[400] , and the compensation of phase C is represented by array CVBZ

[400] ;

[0174] The time update data position is indicated by PT, the trip calculation variable is indicated by FTZ, the compensation calculation variable is indicated by FBZ, the low frequency interruption mark is indicated by FZD, the storage selection mark is indicated by SELF, the A phase storage position counter is indicated by ACNTVI, the B phase storage position counter is indicated by BCNTVI, and the C phase storage position counter is indicated by CCNTVI;

[0175] S14, initialize variables, the initialized variables are specifically:

[0176] MA=0, HA=0, UA=0, AH0=0, AU0=0, CH=0, PT=0, FTZ=0, FBZ=0, TZ=0, SELF=0, ACNTVI=0, BCNT VI=0, CCNTVI=0, FZD=0, FBZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0;

[0177] AVINA

[400] , AVINB

[400] , AIINA

[400] , AIINB

[400] , BVINA

[400] , BVINB

[400] , BIINA

[400] , BIINB

[400] , CVINA

[400] , CVINB

[400] , CIINA

[400] , and CIINB

[400] are initialized to all zeros;

[0178] S15. Set the first parameter M1data and comparison variables BiJiao and BiJiaoV[i]. The value of M1data is:

[0179] M1data

[400] ={0.015707,0.031411,0.047106,0.062791,0.078459,0.094108,0.109734,0.125333,0.140901,0.156434,0.171929,0.187381,0.2 02787,0.218143,0.233445,0.248690,0.263873,0.278991,0.294040,0.309017,0.323917,0.338738,0.353475,0.368125,0.382683,0.397148,0. 411514,0.425779,0.439939,0.453990,0.467930,0.481754,0.495459,0.509041,0.522499,0.535827,0.549023,0.562083,0.575005,0.587785, 0.600420,0.612907,0.625243,0.637424,0.649448,0.661312,0.673013,0.684547,0.695913,0.707107,0.718126,0.728969,0.739631,0.750111 ,0.760406,0.770513,0.780430,0.790155,0.799685,0.809017,0.818150,0.827081,0.835807,0.844328,0.852640,0.860742,0.868632,0.8763 07,0.883766,0.891007,0.898028,0.904827,0.911403,0.917755,0.923880,0.929776,0.935444,0.940881,0.946085,0.951057,0.955793,0.960 294,0.964557,0.968583,0.972370,0.975917,0.979223,0.982287,0.985109,0.987688,0.990024,0.992115,0.993961,0.995562,0.996917,0.9 98027,0.998890,0.999507,0.999877,1.000000,0.999877,0.999507,0.998890,0.998027,0.996917,0.995562,0.993961,0.992115,0.990024,0.987688,0.985109,0.982287,0.979223,0.975917,0.972370,0.968583,0.964557,0.960294,0.955793,0.951057,0.946085,0.940881,0.935444,0.929776,0.923880,0.917755,0.911403,0.904827,0.898028,0.891007,0.883766,0.876307,0.868632,0.860742,0.852640,0.844328,0.835807,0.827081,0.818150,0.809017,0.799685,0.790155,0.780430,0.770513,0.760406,0.750111,0.739631,0.728969,0.718126,0.707107,0.695913,0.684547,0.673013,0.661312,0.649448,0.637424,0.625243,0.612907,0.600420,0.587785,0.575005,0.562083,0.549023,0.535827,0.522499,0.509041,0.495459,0.481754,0.467930,0.453990,0.439939,0.425779,0.411514,0.397148,0.382683,0.368125,0.353475,0.338738,0.323917,0.309017,0.294040,0.278991,0.263873,0.248690,0.233445,0.218143,0.202787,0.187381,0.171929,0.156434,0.140901,0.125333,0.109734,0.094108,0.078459,0.062791,0.047106,0.031411,0.015707,0.000000,-0.015707,-0.031411,-0.047106,-0.062791,-0.078459,-0.094108,-0.109734,-0.125333,-0.140901,-0.156434,-0.171929,-0.187381,-0.202787,-0.218143,-0.233445,-0.248690,-0.263873,-0.278991,-0.294040,-0.309017,-0.323917,-0.338738,-0.353475,-0.368125,-0.382683,-0.397148,-0.411514,-0.425779,-0.439939,-0.453990,-0.467930,-0.481754,-0.495459,-0.509041,-0.522499,-0.535827,-0.549023,-0.562083,-0.575005,-0.587785,-0.600420,-0.612907,-0.625243,-0.637424,-0.649448,-0.661312,-0.673013,-0.684547,-0.695913,-0.707107,-0.718126,-0.728969,-0.739631,-0.750111,-0.760406,-0.770513,-0.780430,-0.790155,-0.799685,-0.809017,-0.818150,-0.827081,-0.835807,-0.844328,-0.852640,-0.860742,-0.868632,-0.876307,-0.883766,-0.891007,-0.898028,-0.904827,-0.911403,-0.917755,-0.923880,-0.929776,-0.935444,-0.940881,-0.946085,-0.951057,-0.955793,-0.960294,-0.964557,-0.968583,-0.972370,-0.975917,-0.979223,-0.982287,-0.985109,-0.987688,-0.990024,-0.992115,-0.993961,-0.995562,-0.996917,-0.998027,-0.998890,-0.999507,-0.999877,-1.000000,-0.999877,-0.999507,-0.998890,-0.998027,-0.996917,-0.995562,-0.993961,-0.992115,-0.990024,-0.987688,-0.985109,-0.982287,-0.979223,-0.975917,-0.972370,-0.968583,-0.964557,-0.960294,-0.955793,-0.951057,-0.946085,-0.940881,-0.935444,-0.929776,-0.923880,-0.917755,-0.911403,-0.904827,-0.898028,-0.891007,-0.883766,-0.876307,-0.868632,-0.860742,-0.852640,-0.844328,-0.835807,-0.827081,-0.8181 50,-0.809017,-0.799685,-0.790155,-0.780430,-0.770513,-0.760406,-0.750111,-0.739631,-0.728969,-0.718126,-0.707107,-0.695913,-0.684547,-0.673013,-0.661312,-0.649448,-0.637424,-0.625243,-0.612907,-0.600420,-0 .587785,-0.575005,-0.562083,-0.549023,-0.535827,-0.522499,-0.509041,-0.495459,-0.481754,-0.467930,-0.453990,-0.439939,-0.425779,-0.411514,-0.397148,-0.382683,-0.368125,-0.353475,-0.338738,-0.323917,-0. 017,-0.294040,-0.278991,-0.263873,-0.248690,-0.233445,-0.218143,-0.202787,-0.187381,-0.171929,-0.156434,-0.140901,-0.125333,-0.109734,-0.094108,-0.078459,-0.062791,-0.047106,-0.031411,-0.015707,-0.000000}. .

[0180] Setting: BiJiao

[10] = {-1,-0.6,-0.2,0.2,0.6,1,0.6,0.2,-0.2,-0.6}

[0181] i=0~399; m=i divide by 10 to get the remainder, BiJiaoV[i]=BiJiao[m].

[0182] In S12, the method of calling the low-frequency interrupt subroutine is specifically as follows:

[0183] SA1, read the data of the wireless communication module 12, parse the read data according to the wireless communication protocol, and update the AHO, AUO, VY, IY and BY variables;

[0184] The wireless communication protocol is arranged by bytes, in the following order: 55, AA, AH0, AU0, VY high eight bits, VY low eight bits, IY high eight bits, IY low eight bits, BY high eight bits, BY low eight bits, check bit, 33, CC;

[0185] Among them, 55, AA indicate the start of the communication packet, 33, CC indicate the end of the communication packet; the check bits are A0 high eight bits, AH0, AU0, VY low eight bits, IY high eight bits, IY low eight bits, BY high eight bits, BY low eight bits, bit by bit XOR;

[0186] SA2, read the data from the GPS module 13, parse the read data according to the GPS communication protocol, and update the MA, HA and UA variables;

[0187] The GPS communication protocol is arranged by bytes, in the following order: 55, AA, MA, AH0, AU0, check bit, 33, CC;

[0188] Among them, 55, AA indicates the beginning of the communication packet, 33, CC indicates the end of the communication packet; the check bit is MA, HA high eight bits, HA low eight bits bit by bit XOR;

[0189] SA3, assign the value of CVA to PT;

[0190] SA4, invert SELF and calculate ACNTVI, ACNTVI = AH0*20+AUO;

[0191] In response to ACNTVI being less than or equal to 133, CCNTVI=ACNTVI+133;

[0192] BCNTVI=ACNTVI+266;

[0193] In response to ACNTVI being greater than or equal to 266, CCNTVI=ACNTVI-133;

[0194] BCNTVI = ACNTVI - 266;

[0195] In response to ACNTVI being greater than 133 and less than 266, CCNTVI=ACNTVI+133, BCNTVI=ACNTVI-133;

[0196] SA5. Set FZD=1.

[0197] In S12, the method of calling the high-frequency interrupt subroutine is specifically as follows:

[0198] SB1. Set VIN[CVA] equal to the storage value of the memory corresponding to voltage sensor 1, set IIN[CVA] equal to the storage value of the memory corresponding to current sensor 2, and add 1 to the CVA value.

[0199] SB2, determine whether the CVA value is equal to 1000, if so, go to SB3, if not, go to SB4;

[0200] SB3, set CVA = 0, FBZ = 1;

[0201] SB4, determine whether BZ is equal to 1, if so, enter SB5, if not, complete the call of the high-frequency interrupt subroutine;

[0202] SB5. Determine whether BuChangV[CBuchang] is greater than BiJiaoV[CBuchang]. If so, control the second IGBT module 103-2 to be turned on and the third IGBT module 103-3 to be turned off. If not, control the second IGBT module 103-2 to be turned off and the third IGBT module 103-3 to be turned on.

[0203] SB6. Add 1 to the value of Cbuchang. If Cbuchang is greater than 399, set Cbuchang to 0.

[0204] SB7. Complete calling the high-frequency interrupt subroutine.

[0205] The S2 comprises the following sub-steps:

[0206] S21, in response to FZD being equal to 0, determining whether SELF is true, if so, proceeding to S22;

[0207] If not, for i=0-399, the value of the corresponding variable is calculated by the following formula and the process goes to S23;

[0208] AFV[i]=(AVINB[i]–32768) / 32768

[0209] AFI[i]=(AIINB[i]–32768) / 32768

[0210] BFV[i]=(BVINB[i]–32768) / 32768

[0211] BFI[i]=(BIINB[i]–32768) / 32768

[0212] CFV[i]=(CVINB[i]–32768) / 32768

[0213] CFI[i]=(CIINB[i]–32768) / 32768

[0214] S22, for i=0-399, calculate the value of the corresponding variable by the following formula, and enter S23;

[0215] AFV[i]=(AVINA[i]–32768) / 32768

[0216] AFI[i]=(AIINA[i]–32768) / 32768

[0217] BFV[i]=(BVINA[i]–32768) / 32768

[0218] BFI[i]=(BIINA[i]–32768) / 32768

[0219] CFV[i]=(CVINA[i]–32768) / 32768

[0220] CFI[i]=(CIINA[i]–32768) / 32768

[0221] S23, calculate ASUMV, BSUMV, CSUMV, ASUMI, BSUMI and CSUMI according to the calculated variables, and enter S24;

[0222]

[0223] S24, calculate the maximum value of ASUMV, BSUMV and CSUMV, expressed as MAXSUMV, calculate the maximum value of ASUMI, BSUMI and CSUMI, expressed as MAXSUMI, and enter S25;

[0224] S25, determine whether MAXSUMV is less than VY and MAXSUMI is greater than IY. If so, set the tripping criterion TZ=1 and enter S26; if not, set the tripping criterion TZ=0 and enter S26;

[0225] S26. Call the compensation judgment subroutine.

[0226] The S26 is specifically:

[0227] S261. Take 300 sample points before the current IIN sampling data from INDATA

[300] . The sampling method is as follows: Determine whether CAV is greater than or equal to 300. If so, then INDATA

[300] = IIN[CAV - 300 ~ CAV]; if not, then the data of INDATA

[300] is the concatenation of two segments of data, IIN[1000 - CAV ~ 1000] and IIN[0 ~ CAV].

[0228] S262. Search within the range of i = 0 to 100 for the first i that simultaneously satisfies INDATA[i] * INDATA[i + 4] < 0 and INDATA[i] < INDATA[i + 4], and let j = i;

[0229] S263. Calculate SUMF1:

[0230]

[0231] S264. Take k = 1 to 25 and calculate SUMF2[k]:

[0232]

[0233] Obtain the maximum value in SUMF2[k], let the maximum value be MaxSumF2, and let MaxkF2 be the k value corresponding to the maximum value; calculate BiF2:

[0234] BiF2 = MaxSumF2 / SUMF1;

[0235] Determine whether BiF2 is greater than 0.03. If so, then let BuChangF2 = 1; if not, then let BuChangF2 = 0;

[0236] S265. Take k = 1 to 15 and calculate SUMF3[k]:

[0237]

[0238] In the formula, m is the remainder obtained by dividing i by 66;

[0239] Obtain the maximum value in SUMF3[k], let the maximum value be MaxSumF3, and let MaxkF3 be the k value corresponding to the maximum value; calculate BiF3:

[0240] BiF3 = MaxSumF3 / SUMF1

[0241] Determine whether BiF3 is greater than 0.03. If so, then let BuChangF3 = 1; if not, then let BuChangF3 = 0;

[0242] S266. Take k = 1 to 12 and calculate SUMF4[k]:

[0243]

[0244] Where m is the remainder obtained by dividing i by 50;

[0245] Get the maximum value in SUMF4[k], let the maximum value be MaxSumF4, let MaxkF4 be the value of k that takes the maximum value; calculate BiF4:

[0246] BiF4=MaxSumF4 / SUMF1

[0247] Determine whether BiF4 is greater than 0.03. If so, set BuChangF4=1; if not, set BuChangF4=0.

[0248] S267, take k=1-10, calculate SUMF5[k]=:

[0249]

[0250] Where m is the remainder obtained by dividing i by 40;

[0251] Get the maximum value in SUMF5[k], let the maximum value be MaxSumF5, let MaxkF5 be the k value that takes the maximum value; calculate BiF5:

[0252] BiF5=MaxSumF5 / SUMF1

[0253] Determine whether BiF5 is greater than 0.03. If so, set BuChangF5=1; if not, set BuChangF5=0.

[0254] S268, calculation is not long;

[0255] BuChang=BuChangF2+BuChangF3+BuChangF4+BuChangF5;

[0256] Determine whether BuChang is greater than or equal to 1. If so, BZ=1 and call the compensation action subroutine. If not, BZ=0. In S268, the method of calling the compensation action subroutine is specifically as follows:

[0257] S2681. Determine whether BuChangF2 is equal to 1. If so, then:

[0258] bcDataF2[2*i]=-1*BiF2*M2data[i], where i is 0 to 99;

[0259] bcDataF2[2*i+1]=(bcDataF2[2*i]+bcDataF2[2*i+2]) / 2, where i is 0 to 98;

[0260] bcDataF2

[199] =(bcDataF2[0]+bcDataF2

[198] ) / 2;

[0261] bcDataF2[i+200]=bcDataF2[i], where i is 0 to 199;

[0262] If not, bcDataF2[i]=0, where i is 0 to 399;

[0263] S2682, determine whether BuChangF3 is equal to 1. If not, bcDataF3[i]=0, where i is 0 to 399. If yes, then:

[0264] bcDataF3[2*i]=-1*BiF3*M3data[i], where i is 0 to 65;

[0265] bcDataF3[2*i+1]=(bcDataF3[2*i]+bcDataF3[2*i+2]) / 2; wherein i is 0 to 64;

[0266] bcDataF3

[131] =(bcDataF3[0]+bcDataF3

[130] ) / 2;

[0267] bcDataF3

[132] =bcDataF3

[131] ;

[0268] bcDataF3[i+133]=bcDataF3[i]; wherein i is 0 to 132;

[0269] bcDataF3

[266] =bcDataF3

[265] ;

[0270] bcDataF3[i+267]=bcDataF3[i]; wherein i is 0 to 132;

[0271] S2683, determine whether BuChangF4 is equal to 1; if not, then bcDataF4[i]=0, where i is 0-399; if yes, then:

[0272] bcDataF4[2*i]=-1*BiF4*M4data[i], i ranges from 0 to 49;

[0273] bcDataF4[2*i+1]=(bcDataF4[2*i]+bcDataF4[2*i+2]) / 2; where i ranges from 0 to 48;

[0274] bcDataF4

[99] =(bcDataF4[0]+bcDataF4

[98] ) / 2;

[0275] bcDataF4[i+100]=bcDataF4[i]; wherein i is 0 to 99;

[0276] bcDataF4[i+200]=bcDataF4[i]; wherein i is 0 to 199;

[0277] S2684: Determine whether BuChangF5 is equal to 1. If not, bcDataF5[i]=0; wherein i is 0 to 399; if yes, then:

[0278] bcDataF5[2*i]=-1*BiF5*M5data[i], where i ranges from 0 to 39;

[0279] bcDataF5[2*i+1]=(bcDataF5[2*i]+bcDataF5[2*i+2]) / 2; wherein i is 0 to 38;

[0280] bcDataF5

[79] =(bcDataF5[0]+bcDataF5

[78] ) / 2;

[0281] bcDataF5[i+80]=bcDataF5[i]; wherein i is 0 to 79;

[0282] bcDataF5[i+160]=bcDataF6[i]; wherein i is 0 to 159;

[0283] bcDataF5[i+320]=bcDataF6[i]; wherein i is 0 to 79;

[0284] S2685, calculate BuChangV;

[0285] BuChangV=bcDataF2[i]+bcDataF3[i]+bcDataF4[i]+bcDataF5[i], i=0~399;

[0286] S2686, set CBuchang=0 to complete calling the compensation action subroutine.

[0287] In S3, the method of performing the tripping action through the tripping action subroutine is specifically as follows:

[0288] S31, control thyristor 9 to be turned on;

[0289] S32, control the mechanical circuit breaker 6 to disconnect;

[0290] S33, control the thyristor 9 to be turned off.

[0291] The beneficial effects of the present invention are as follows: the present invention provides an arc-free circuit breaker and control method for a transformer substation, which is connected to a voltage sensor 1, a current sensor 2, a mechanical circuit breaker 6, a GPS module 13, a wireless communication module 12, a thyristor drive circuit 10, and an inverter 14 through a microprocessor 11. The microprocessor 11 receives the sensing signals of the voltage sensor 1 and the current sensor 2, the clock signal of the GPS module 13, and the control information of the wireless communication module 12; the transformer substation operation state is calculated according to the sensing signals of the voltage sensor 1 and the current sensor 2, the clock signal of the GPS module 13, and the control information of the wireless communication module 12, and the mechanical circuit breaker 6, the thyristor drive circuit 10, and the inverter 14 are controlled according to the calculation and analysis results, which solves the problem that traditional circuit breakers can no longer meet the increasing demand for new energy sources such as photovoltaics and charging piles in transformer substations.

[0292] In the description of the present invention, it is necessary to understand that the orientation or positional relationship indicated by the terms "center", "thickness", "upper", "lower", "horizontal", "top", "bottom", "inner", "outer", "radial", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", and "third" are used only for descriptive purposes, and cannot be understood as indicating or implying the relative importance or the number of implicitly specified technical features. Therefore, the features defined by "first", "second", and "third" may explicitly or implicitly include one or more of the features.

Claims

1. A non-arc circuit breaker in a transformer area, characterized in that: It includes a voltage sensor (1), a current sensor (2), a left-end resistor (3), a left-end inductor (4), a transformer (5), a mechanical circuit breaker (6), a right-end resistor (7), a right-end inductor (8), a thyristor (9), a thyristor drive circuit (10), a microprocessor (11), a wireless communication module (12), a GPS module (13) and an inverter (14); The microprocessor (11) is respectively connected to the voltage sensor (1), the current sensor (2), the thyristor drive circuit (10), the wireless communication module (12), the GPS module (13) and the inverter (14); the voltage sensor (1) is also connected to the current sensor (2), the left-end resistor (3) and the left-end inductor (4) in sequence; the left-end inductor (4) is also respectively connected to the No. 1 terminal of the transformer (5), the mechanical circuit breaker (6) and the thyristor (9); the inverter (14) is connected to the No. 3 terminal and the No. 4 terminal of the transformer (5); the thyristor drive circuit (10) is connected to the thyristor (9); the mechanical circuit breaker (6) is also respectively connected to the thyristor (9) and the right-end resistor (7); and the right-end resistor (7) is also connected to the right-end inductor (8); The voltage sensor (1) is used to collect the three-phase voltage values ​​output by the transformer in the substation area; the current sensor (2) is used to collect the three-phase current values ​​output by the transformer in the substation area; the wireless communication module (12) is used to receive the control information of the circuit breaker in the substation area; the GPS module (13) is used to provide a clock signal for the microprocessor (11); the microprocessor (11) is used to calculate the substation area operation state according to the three-phase voltage and current values ​​output by the transformer in the substation area, the clock signal and the control information; and the mechanical circuit breaker (6) and the thyristor drive circuit (10) are controlled according to the calculation result; the thyristor (9) is used to control the current.

2. The arc-free circuit breaker in the substation according to claim 1, characterized in that: The inverter (14) comprises a three-phase inverter structure, and each phase of the inverter structure comprises a capacitor (101), a connection terminal K1 (102-1), a connection terminal K2 (102-2), a first IGBT module (103-1), a second IGBT module (103-2), a third IGBT module (103-3), a fourth IGBT module (103-4), a first IGBT drive module (104-1), a second IGBT drive module (104-2), a third IGBT drive module (104-3), a fourth IGBT drive module (104-4), a connection port Q1 (105-1), a connection port Q2 (105-2), a connection port Q3 (105-3), and a connection port Q4 (105-4); The connection terminal K1 (102-1) is connected to the terminal No. 3 of the transformer (5), the connection terminal K2 (102-2) is connected to the terminal No. 4 of the transformer (5), and the connection port Q1 (105-1), the connection port Q2 (105-2), the connection port Q3 (105-3) and the connection port Q4 (105-4) are all connected to the ports of the microprocessor (11); The gate of the first IGBT module (103-1) is connected to the connection port Q1 (105-1) through the first IGBT driving module (104-1), the collector of the first IGBT module (103-1) is connected to one end of the capacitor (101), the emitter of the first IGBT module (103-1) is connected to the connection terminal K2 (102-2) and the collector of the second IGBT module (103-2) respectively, the gate of the second IGBT module (103-2) is connected to the connection port Q2 (105-1) through the second IGBT driving module (104-2), and the emitter of the second IGBT module (103-2) is connected to the other end of the capacitor (101); The gate of the fourth IGBT module (103-4) is connected to the connection port Q4 (105-4) through the fourth IGBT driving module (104-4), the collector of the fourth IGBT module (103-4) is connected to one end of the capacitor (101), the emitter of the fourth IGBT module (103-4) is respectively connected to the connection terminal K1 (102-1) and the collector of the third IGBT module (103-3), the gate of the third IGBT module (103-3) is connected to the connection port Q3 (105-3) through the third IGBT driving module (104-3), and the emitter of the third IGBT module (103-3) is connected to the other end of the capacitor (101).

3. The control method of the non-arc circuit breaker in the substation according to any one of claims 1 to 2, characterized in that: The following steps are involved: S1, perform initialization operation through the initialization subroutine; S2, calculating the tripping criterion through the tripping and compensation criterion calculation subroutine; S3. In response to the tripping criterion being equal to 1, a tripping action is performed through a tripping action subroutine.

4. The control method according to claim 3, characterized in that: The S1 comprises the following sub-steps: S11, setting the low-frequency interrupt clock to 20 milliseconds, setting the high-frequency interrupt clock to 50 microseconds, setting the wireless communication module (12) reading interface, and setting the GPS module (13) reading interface; S12, setting low-frequency interrupt conditions, calling low-frequency interrupt subroutine, setting high-frequency interrupt conditions, calling high-frequency interrupt subroutine; S13. Set variables, including: The current time in seconds is represented by MA, with a value range of 0-59. The current time in milliseconds is represented by HA, with a value range of 0-999. The current time in microseconds is represented by UA, with a value range of 0-999. The A-phase voltage phase zero millisecond moment is represented by AH0, with a unit of 50 milliseconds and a value range of 0-20. The A-phase voltage phase zero microsecond moment is represented by AU0, with a unit of microseconds and a value range of 0-20. The high-frequency interrupt counter is represented by CH, with a value range of 0-999. The trip voltage threshold is represented by VY, the trip current threshold is represented by IY, the compensation threshold is represented by BY, the trip mark is represented by TZ, the sensor reading counter is represented by CVA, with a value range of 0-999, the cycle counter is represented by CZQ, with a value range of 0-199, the voltage sum is represented by SUMV, and the current sum is represented by SUMI. The first reading value of phase A of the voltage sensor (1) is represented by the array AVINA[400], the second reading value of phase A of the voltage sensor (1) is represented by the array AVINB[400], the floating point value of phase A voltage is represented by the array AFV[400], the first reading value of phase A of the current sensor (2) is represented by the array AIINA[400], the second reading value of phase A of the current sensor (2) is represented by the array AIINB[400], the floating point value of phase A current is represented by the array AFI[400], and the compensation of phase A is represented by the array AVBZ[400]; The first B-phase reading value of the voltage sensor (1) is represented by the array BVINA[400], the second B-phase reading value of the voltage sensor (1) is represented by the array BVINB[400], the B-phase voltage floating point value is represented by the array BFV[400], the first B-phase reading value of the current sensor (2) is represented by the array BIINA[400], the second B-phase reading value of the current sensor (2) is represented by the array BIINB[400], the B-phase current floating point value is represented by the array BFI[400], and the B-phase compensation is represented by the array BVBZ[400]; The first reading value of the C phase of the voltage sensor (1) is represented by the array CVINA[400], the second reading value of the C phase of the voltage sensor (1) is represented by the array CVINB[400], the floating point value of the C phase voltage is represented by the array CFV[400], the first reading value of the C phase of the current sensor (2) is represented by the array CIINA[400], the second reading value of the C phase of the current sensor (2) is represented by the array CIINB[400], the floating point value of the C phase current is represented by the array CFI[400], and the C phase compensation is represented by the array CVBZ[400]; The time update data position is indicated by PT, the trip calculation variable is indicated by FTZ, the compensation calculation variable is indicated by FBZ, the low frequency interruption mark is indicated by FZD, the storage selection mark is indicated by SELF, the A phase storage position counter is indicated by ACNTVI, the B phase storage position counter is indicated by BCNTVI, and the C phase storage position counter is indicated by CCNTVI; S14, initialize variables, the initialized variables are specifically: MA=0, HA=0, UA=0, AH0=0, AU0=0, CH=0, PT=0, FTZ=0, FBZ=0, TZ=0, SELF=0, ACNTVI=0, BCNT VI=0, CCNTVI=0, FZD=0, FBZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0; AVINA[400], AVINB[400], AIINA[400], AIINB[400], BVINA[400], BVINB[400], BIINA[400], BIINB[400], CVINA[400], CVINB[400], CIINA[400], and CIINB[400] are initialized to all zeros; S15. Set the first parameter M1data and comparison variables BiJiao, BiJiaoV[i].

5. The control method according to claim 4, characterized in that: In S12, the method of calling the low-frequency interrupt subroutine is specifically as follows: SA1, reading data from the wireless communication module (12), parsing the read data according to the wireless communication protocol, and updating AHO, AUO, VY, IY and BY variables; The wireless communication protocol is arranged by bytes, in the following order: 55, AA, AH0, AU0, VY high eight bits, VY low eight bits, IY high eight bits, IY low eight bits, BY high eight bits, BY low eight bits, check bit, 33, CC; Among them, 55, AA indicate the start of the communication packet, 33, CC indicate the end of the communication packet; the check bits are A0 high eight bits, AH0, AU0, VY low eight bits, IY high eight bits, IY low eight bits, BY high eight bits, BY low eight bits, bit by bit XOR; SA2, read the data from the GPS module (13), parse the read data according to the GPS communication protocol, and update the MA, HA and UA variables; The GPS communication protocol is arranged by bytes, in the following order: 55, AA, MA, AH0, AU0, check bit, 33, CC; Among them, 55, AA indicates the beginning of the communication packet, 33, CC indicates the end of the communication packet; the check bit is MA, HA high eight bits, HA low eight bits bit by bit XOR; SA3, assign the value of CVA to PT; SA4, invert SELF and calculate ACNTVI, ACNTVI = AH0*20+AUO; In response to ACNTVI being less than or equal to 133, CCNTVI=ACNTVI+133; BCNTVI=ACNTVI+266; In response to ACNTVI being greater than or equal to 266, CCNTVI=ACNTVI-133; BCNTVI = ACNTVI - 266; In response to ACNTVI being greater than 133 and less than 266, CCNTVI=ACNTVI+133, BCNTVI=ACNTVI-133; SA5. Set FZD=1.

6. The control method according to claim 4, characterized in that: In S12, the method of calling the high-frequency interrupt subroutine is specifically as follows: SB1. Set VIN[CVA] equal to the storage value of the memory corresponding to the voltage sensor (1), set IIN[CVA] equal to the storage value of the memory corresponding to the current sensor (2), and add 1 to the CVA value; SB2, determine whether the CVA value is equal to 1000, if so, go to SB3, if not, go to SB4; SB3, set CVA = 0, FBZ = 1; SB4, determine whether BZ is equal to 1, if so, enter SB5, if not, complete the call of the high-frequency interrupt subroutine; SB5. Determine whether BuChangV[CBuchang] is greater than BiJiaoV[CBuchang]. If so, control the second IGBT module (103-2) to be turned on and the third IGBT module (103-3) to be turned off. If not, control the second IGBT module (103-2) to be turned off and the third IGBT module (103-3) to be turned on. SB6. Add 1 to the value of Cbuchang. If Cbuchang is greater than 399, set Cbuchang to 0. SB7. Complete calling the high-frequency interrupt subroutine.

7. The control method according to claim 6, characterized in that: The S2 comprises the following sub-steps: S21, in response to FZD being equal to 0, determining whether SELF is true, if so, proceeding to S22; If not, for i=0-399, the value of the corresponding variable is calculated by the following formula and the process goes to S23; AFV[i]=(AVINB[i]–32768) / 32768 AFI[i]=(AIINB[i]–32768) / 32768 BFV[i]=(BVINB[i]–32768) / 32768 BFI[i]=(BIINB[i]–32768) / 32768 CFV[i]=(CVINB[i]–32768) / 32768 CFI[i]=(CIINB[i]–32768) / 32768 S22, for i=0-399, calculate the value of the corresponding variable by the following formula, and enter S23; AFV[i]=(AVINA[i]–32768) / 32768 AFI[i]=(AIINA[i]–32768) / 32768 BFV[i]=(BVINA[i]–32768) / 32768 BFI[i]=(BIINA[i]–32768) / 32768 CFV[i]=(CVINA[i]–32768) / 32768 CFI[i]=(CIINA[i]–32768) / 32768 S23, calculate ASUMV, BSUMV, CSUMV, ASUMI, BSUMI and CSUMI according to the calculated variables, and enter S24; S24, calculate the maximum value of ASUMV, BSUMV and CSUMV, expressed as MAXSUMV, calculate the maximum value of ASUMI, BSUMI and CSUMI, expressed as MAXSUMI, and enter S25; S25, determine whether MAXSUMV is less than VY and MAXSUMI is greater than IY. If so, set the tripping criterion TZ=1 and enter S26; if not, set the tripping criterion TZ=0 and enter S26; S26. Call the compensation judgment subroutine.

8. The control method according to claim 7, characterized in that: The S26 is specifically: S261. INDATA[300] takes 300 samples before the current IIN sampling data. The sampling method is as follows: Determine whether CAV is greater than or equal to 300. If so, then INDATA[300] = IIN[CAV - 300 ~ CAV]; if not, then the data of INDATA[300] is the concatenation of two segments of data, IIN[1000 - CAV ~ 1000] and IIN[0 ~ CAV]. S262. Search for the first i within the range of i = 0 to 100 that simultaneously satisfies INDATA[i] * INDATA[i + 4] < 0 and INDATA[i] < INDATA[i + 4], and let j = i. S263. Calculate SUMF1: S264. Take k = 1 to 25 and calculate SUMF2[k]: Obtain the maximum value in SUMF2[k], let the maximum value be MaxSumF2, and let MaxkF2 be the k value corresponding to the maximum value. Calculate BiF2: BiF2 = MaxSumF2 / SUMF1; Determine whether BiF2 is greater than 0.

03. If so, then let BuChangF2 = 1; if not, then let BuChangF2 = 0. S265. Take k = 1 to 15 and calculate SUMF3[k]: Where m is the remainder obtained by dividing i by 66. Obtain the maximum value in SUMF3[k], let the maximum value be MaxSumF3, and let MaxkF3 be the k value corresponding to the maximum value. Calculate BiF3: BiF3 = MaxSumF3 / SUMF1 Determine whether BiF3 is greater than 0.

03. If so, then let BuChangF3 = 1; if not, then let BuChangF3 = 0. S266. Take k = 1 to 12 and calculate SUMF4[k]: Where m is the remainder obtained by dividing i by 50. Obtain the maximum value in SUMF4[k], let the maximum value be MaxSumF4, and let MaxkF4 be the k value corresponding to the maximum value. Calculate BiF4: BiF4 = MaxSumF4 / SUMF1 Determine whether BiF4 is greater than 0.

03. If so, then let BuChangF4 = 1; if not, then let BuChangF4 = 0. S267. Take k = 1 to 10 and calculate SUMF5[k] =: Where m is the remainder obtained by dividing i by 40. Obtain the maximum value in SUMF5[k], let the maximum value be MaxSumF5, and let MaxkF5 be the k value corresponding to the maximum value. Calculate BiF5: BiF5 = MaxSumF5 / SUMF1 Determine whether BiF5 is greater than 0.

03. If so, then let BuChangF5 = 1; if not, then let BuChangF5 = 0. S268. Calculate BuChang; BuChang = BuChangF2 + BuChangF3 + BuChangF4 + BuChangF5; Determine whether BuChang is greater than or equal to 1. If so, then BZ = 1, and call the compensation action subroutine; if not, then BZ = 0.

9. The control method according to claim 8, characterized in that: In S268, the method of calling the compensation action subroutine is specifically as follows: S2681. Determine whether BuChangF2 is equal to 1. If so, then: bcDataF2[2*i]=-1*BiF2*M2data[i], where i is 0 to 99; bcDataF2[2*i+1]=(bcDataF2[2*i]+bcDataF2[2*i+2]) / 2, where i is 0 to 98; bcDataF2[199]=(bcDataF2[0]+bcDataF2[198]) / 2; bcDataF2[i+200]=bcDataF2[i], where i is 0 to 199; If not, bcDataF2[i]=0, where i is 0 to 399; S2682, determine whether BuChangF3 is equal to 1, if not, bcDataF3[i]=0, where i is 0-399; If yes, then: bcDataF3[2*i]=-1*BiF3*M3data[i], where i is 0 to 65; bcDataF3[2*i+1]=(bcDataF3[2*i]+bcDataF3[2*i+2]) / 2; wherein i is 0 to 64; bcDataF3[131]=(bcDataF3[0]+bcDataF3[130]) / 2; bcDataF3[132]=bcDataF3[131]; bcDataF3[i+133]=bcDataF3[i]; wherein i is 0 to 132; bcDataF3[266]=bcDataF3[265]; bcDataF3[i+267]=bcDataF3[i]; wherein i is 0 to 132; S2683, determine whether BuChangF4 is equal to 1; if not, bcDataF4[i]=0, where i is 0-399; If yes, then: bcDataF4[2*i]=-1*BiF4*M4data[i], i ranges from 0 to 49; bcDataF4[2*i+1]=(bcDataF4[2*i]+bcDataF4[2*i+2]) / 2; where i ranges from 0 to 48; bcDataF4[99]=(bcDataF4[0]+bcDataF4[98]) / 2; bcDataF4[i+100]=bcDataF4[i]; wherein i is 0 to 99; bcDataF4[i+200]=bcDataF4[i]; wherein i is 0 to 199; S2684: Determine whether BuChangF5 is equal to 1, if not, bcDataF5[i]=0; wherein i is 0-399; If yes, then: bcDataF5[2*i]=-1*BiF5*M5data[i], where i ranges from 0 to 39; bcDataF5[2*i+1]=(bcDataF5[2*i]+bcDataF5[2*i+2]) / 2; wherein i is 0 to 38; bcDataF5[79]=(bcDataF5[0]+bcDataF5[78]) / 2; bcDataF5[i+80]=bcDataF5[i]; wherein i is 0 to 79; bcDataF5[i+160]=bcDataF6[i]; wherein i is 0 to 159; bcDataF5[i+320]=bcDataF6[i]; wherein i is 0 to 79; S2685, calculate BuChangV; BuChangV=bcDataF2[i]+bcDataF3[i]+bcDataF4[i]+bcDataF5[i], i=0~399; S2686, set CBuchang=0 to complete calling the compensation action subroutine.

10. The control method according to claim 3, characterized in that: In S3, the method of performing the tripping action through the tripping action subroutine is specifically as follows: S31, controlling the thyristor (9) to be turned on; S32, controlling the mechanical circuit breaker (6) to disconnect; S33, control the thyristor (9) to be turned off.

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