Silicon wafer line mark processing method, silicon wafer and solar cell
Through the atomization treatment method of alkali and acid liquid, combined with alkali etching and acid polishing steps, the problem of difficult to reduce the depth of the wire mark on the surface of the silicon wafer is solved, significantly improving the smoothness and uniformity of the silicon wafer, and reducing the gate breaking of solar cells.
Patent Information
- Application Number
- CN202411929391.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-03-28
AI Technical Summary
The prior art is difficult to effectively reduce the depth of the wire mark on the surface of the silicon wafer, resulting in the intensification of the gate breakage of solar cells.
The atomization treatment method of alkali and acid liquid is adopted, and the wire mark depth on the surface of the silicon wafer is significantly reduced by two steps of alkali etching and acid polishing, making it less than 5μm.
The wire mark depth on the surface of the silicon wafer is significantly reduced, the smoothness and uniformity of the silicon wafer is improved, and the gate breakage of solar cells is reduced.
Abstract
Description
Technical Field
[0001] The invention belongs to the field of photovoltaics, and in particular relates to a silicon wafer line mark processing method, a silicon wafer and a solar cell. Background Art
[0002] In the photovoltaic industry, crystalline silicon solar cells continue to maintain their core position, and this trend has greatly promoted the vigorous development of the silicon wafer market. Among them, the rise of diamond wire cutting technology has gradually replaced the traditional mortar cutting method and become the mainstream choice in the field of monocrystalline silicon slicing. With the continuous evolution of the current large-size and thin-slicing technology of silicon wafers, more and more slicing manufacturers choose to reduce the cost of silicon wafers by refining diamond wires. This change has significantly reduced the depth of line marks on the surface of silicon wafers, which is a significant improvement compared to the mortar cutting period.
[0003] The depth of line marks on the surface of silicon wafers has an important impact on product quality. At present, the generally accepted standard in the industry is that the depth of line marks on the surface of silicon wafers should be less than or equal to 15μm. When the line mark depth of silicon wafers exceeds this threshold, the quality of the silicon wafer will be assessed as downgraded. However, with the development of technology and the need for cost control, solar cell manufacturers have begun to adopt a fine grid design with low silver paste consumption. This design makes the silver grid line thinner to reduce the amount of silver paste used, but it also leads to an increase in the broken grid of solar cells. Through in-depth research, researchers found that the broken grid problem of solar cells is closely related to the line mark depth and line mark structure of silicon wafers. Even if the line mark depth of silicon wafers is within the standard range of 15μm, it will cause the solar cell to break.
[0004] Therefore, developing a method for processing line marks on silicon wafers with smaller surface line marks has become a research direction in this field. Summary of the invention
[0005] The invention provides a method for processing line marks on a silicon wafer. The method has the characteristic of being able to produce a silicon wafer with a surface line mark depth of less than 5 μm.
[0006] The present invention also provides a silicon wafer, which has the characteristic of having a line mark depth of less than 5 μm.
[0007] The present invention also provides a solar cell, which has the characteristic of being able to produce a grid line with a relatively low width.
[0008] The present invention provides a method for processing silicon wafer line marks, which comprises the following steps:
[0009] 1) alkaline etching treatment, wherein the initial silicon wafer is contacted with alkaline mist formed by atomization of alkaline solution, and alkaline etching treatment is performed to obtain an intermediate silicon wafer;
[0010] 2) Acid polishing treatment, whereby the intermediate silicon wafer is contacted with acid mist formed by atomization of the acid solution, and acid polishing treatment is performed to obtain a product silicon wafer; the depth of the line marks on the surface of the product silicon wafer is less than 5 μm;
[0011] The alkali solution includes alkaline substances, and the acid solution includes hydrofluoric acid and an aqueous solution of an oxidant.
[0012] In the above silicon wafer line mark treatment method, the alkali solution comprises an alkaline substance and water, and the alkaline substance is selected from at least one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide;
[0013] The oxidant is selected from at least one of hydrogen peroxide, nitric acid and potassium dichromate.
[0014] In the above silicon wafer line mark treatment method, the mass fraction of alkaline substances in the alkali solution is 10-30%, and the treatment time of the alkali etching treatment is 60-300s.
[0015] In the above silicon wafer line mark treatment method, the concentration of hydrofluoric acid is 3wt%-10wt%, and the concentration of the oxidant aqueous solution is 6wt%-30wt%.
[0016] In the above silicon wafer line mark processing method, the volume ratio of hydrofluoric acid to the oxidant aqueous solution is 1:2-1:6.
[0017] In the above silicon wafer line mark processing method, the processing time of the acid polishing treatment is 180-600s.
[0018] The silicon wafer line mark processing method as above also includes a first cleaning and drying treatment of the product obtained by the alkaline etching treatment, the cleaning time is 120-200s, the temperature is 10-30°C; the drying time is 60-300s, and the temperature is 65-80°C.
[0019] The above silicon wafer line mark processing method further includes a second cleaning and drying treatment of the product obtained by the acid polishing treatment, the cleaning time is 120-200s, the temperature is room temperature; the drying time is 60-300s, the temperature is 65-80°C.
[0020] The present invention also provides a silicon wafer, which is manufactured using any of the above-mentioned silicon wafer line mark processing methods, wherein the surface line mark depth of the silicon wafer is less than 5 μm.
[0021] The present invention also provides a solar cell, which comprises a product silicon wafer prepared by using any of the above-mentioned silicon wafer line mark processing methods as a silicon wafer substrate, wherein the line mark depth on the surface of the silicon wafer substrate is less than 5 μm;
[0022] It also includes a functional layer and a gate line in contact with at least one surface of the product silicon wafer, wherein the width of the gate line is less than 30 μm.
[0023] The silicon wafer line mark processing method provided by the present invention atomizes alkali solution and acid solution and contacts them with silicon wafers to process the line marks on the surface of silicon wafers. The atomized alkali solution selectively etches the surface of silicon wafers to generate silicon compounds and hydrogen. Because the contact area between the protruding line marks on the surface of silicon wafers and the alkali solution is larger, etching starts at the line marks first, so that the line marks on the initial silicon wafer surface are etched to form a pyramid base morphology. Then, the acid solution and the oxidant aqueous solution are used to synergistically carry out oxidation and isotropic corrosion reaction. On the one hand, the pyramid base morphology formed in the alkali etching treatment can be polished and smoothed, and on the other hand, the edges and corners of the collapse pits below the surface can be polished from sharp to gentle to smooth corners. Through the coordination of alkali etching treatment and acid polishing treatment, the line marks and collapse pits on the surface of silicon wafers are solved to a certain extent, and the roughness of the surface of silicon wafers is reduced. In addition, the atomized liquid can form uniform tiny particles, covering the surface of silicon wafers, avoiding the uneven corrosion phenomenon caused by bubbles or uneven liquid concentration during immersion. The efficient contact between the atomized particles and the surface of the silicon wafer increases the uniformity and fineness of the reaction, and can gradually act on the surface with smaller doses, which facilitates the precise control of the chemical reaction rate and avoids excessive corrosion or surface damage. Finally, compared with immersion, the atomization process reduces the side effects in the chemical reaction, such as bubble interference and excessive local corrosion, and reduces physical damage through flexible processing methods, which has a significant effect on improving surface smoothness and uniformity. Therefore, the silicon wafer line mark processing method provided by the present invention can produce silicon wafers with a surface line mark depth of less than 5μm. DETAILED DESCRIPTION
[0024] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below. The specific implementation methods listed below are only for describing the principles and features of the present invention. The examples are only used to explain the present invention and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other implementation methods obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.
[0025] A first aspect of the present invention provides a method for processing silicon wafer line marks, the method comprising the following steps:
[0026] 1) alkaline etching treatment, wherein the initial silicon wafer is contacted with alkaline mist formed by atomization of alkaline solution, and alkaline etching treatment is performed to obtain an intermediate silicon wafer;
[0027] 2) Acid polishing treatment, whereby the intermediate silicon wafer is contacted with acid mist formed by atomization of the acid solution, and acid polishing treatment is performed to obtain a product silicon wafer; the depth of the line marks on the surface of the product silicon wafer is less than 5 μm;
[0028] The alkali solution includes alkaline substances, and the acid solution includes hydrofluoric acid and an aqueous solution of an oxidant.
[0029] The present invention does not limit the specific selection of the alkaline substance, and the alkaline substances commonly used in the art can be selected. For example, in one embodiment, the alkaline substance can be sodium hydroxide. It is understandable that in order to form a liquid in contact with the silicon wafer, the alkali solution also includes water. Similarly, the present invention does not limit the specific selection of the oxidant, and the oxidant commonly used in the art can be used. For example, in one embodiment, the oxidant is hydrogen peroxide. The present invention does not limit the mass fraction of each component in the alkali solution and the acid solution, and it is sufficient to meet the requirements that the alkali solution includes an alkaline substance and water, and the acid solution includes an aqueous solution of hydrogen fluoride and an aqueous solution of an oxidant. The product silicon wafer prepared using the above method has the characteristic that the surface line mark depth is less than 5μm.
[0030] The above-mentioned silicon wafer line mark processing method uses alkali solution, acid solution and initial silicon wafer as raw materials. Among them, the initial silicon wafer is the silicon wafer obtained after cutting, which has a large line mark depth and surface roughness. Generally speaking, the line mark depth is greater than 10μm and the surface roughness is greater than 2μm. Specifically, during the preparation process, an atomizing device is used to atomize the alkali solution into an alkali mist composed of fine droplets, and the alkali mist is sprayed on the surface of the initial silicon wafer. At this time, the alkali solution selectively etches the surface of the silicon wafer to generate silicon compounds and hydrogen. Because the protruding line marks on the surface of the silicon wafer have a larger contact area with the alkali solution, etching starts first at the line marks, so that the line marks on the surface of the initial silicon wafer are etched to form a pyramid base morphology. At this time, the line mark part is etched to be basically flush with the surface of the silicon wafer.
[0031] In addition, during the above-mentioned alkaline etching process, the spray formed by the alkaline solution adheres to the surface of the initial silicon wafer, forming a thin water film on the surface. The ionization and etching of the alkaline solution are both carried out in this water film, which is conducive to the desorption of hydrogen bubbles and increases the molecular exchange rate, thereby having a faster etching speed.
[0032] In step 2), an atomizing device is used to atomize the acid liquid into an acid mist composed of fine droplets, and then the acid mist is sprayed on the surface of the intermediate silicon wafer obtained by alkali etching for acid polishing. In this process, hydrofluoric acid and an aqueous oxidant solution cooperate to carry out oxidation and isotropic corrosion reactions. On the one hand, the acid polishing can polish the pyramid base morphology formed in the alkali etching treatment to be smooth, and on the other hand, the edges and corners of the collapse pits below the surface can be polished from sharp to gentle and smooth corners. As the reaction proceeds, the surface of the intermediate silicon wafer gradually becomes smooth, and finally a product silicon wafer with a line mark depth of less than 5μm is obtained. In this process, hydrofluoric acid is different from other types of common inorganic acids and can react with silicon wafers, and the oxidant contained in the aqueous oxidant solution can accelerate the process of the above-mentioned hydrofluoric acid reacting with the silicon wafer.
[0033] The present invention does not limit the specific treatment temperature and treatment time of the alkali etching treatment and the acid polishing treatment, and can be adjusted according to actual production requirements.
[0034] The inventors have found that the above-mentioned silicon wafer line mark treatment method of atomizing the alkali solution or acid solution and contacting it with the silicon wafer can significantly improve the line mark depth of the silicon wafer compared to the traditional immersion method. First, the atomized liquid can form uniform tiny particles, covering the surface of the silicon wafer, avoiding the uneven corrosion caused by bubbles or uneven liquid concentration during the immersion process. The efficient contact between the atomized particles and the surface of the silicon wafer increases the uniformity and fineness of the reaction, and can gradually act on the surface with smaller doses, which is convenient for precise control of the chemical reaction rate and avoids excessive corrosion or surface damage; finally, compared with immersion, the atomization process reduces the side effects in the chemical reaction, such as bubble interference and excessive local corrosion, and has a significant effect on improving surface smoothness and uniformity. Therefore, silicon wafers with a smaller surface line mark depth can be produced using the above method.
[0035] The line mark wet etching method for silicon wafer provided by the present invention has the following advantages:
[0036] 1) The line mark wet etching method provided by the present invention can effectively remove defects on the surface of silicon wafers and improve the overall quality of silicon wafers.
[0037] 2) Acid polishing of the intermediate silicon wafer after atomization with an acid solution including hydrofluoric acid and an oxidant aqueous solution is an isotropic reaction process, and the polishing effect is evenly distributed on the surface of the silicon wafer. In this process, hydrofluoric acid is different from other common inorganic acids and can react with the silicon wafer, while the oxidant contained in the oxidant aqueous solution can accelerate the reaction process between the hydrofluoric acid and the silicon wafer. This polishing method can significantly reduce the roughness of the silicon wafer, reduce the depth of the line marks, and improve the uniformity and smoothness of the surface.
[0038] 3) Environmental protection and energy saving: Compared with traditional wet etching and polishing processes, the vapor phase method reduces the generation of liquid waste and helps protect the environment. By optimizing the etching and polishing steps, they can be carried out at lower temperatures and pressures, reducing energy consumption.
[0039] 4) High production efficiency: Since this method combines the two steps of selective etching and polishing, it can be completed in one process, which improves production efficiency. Precisely controlling the conditions of the vapor phase reaction can achieve fast and stable etching and polishing effects, further improving production efficiency.
[0040] In one embodiment, the alkali solution includes an alkaline substance and water, the alkaline substance is selected from at least one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide; the oxidant is selected from at least one of hydrogen peroxide, nitric acid, and potassium dichromate. Specifically, the alkali solution can be selected from at least one of potassium hydroxide aqueous solution, sodium hydroxide aqueous solution, tetramethylammonium hydroxide aqueous solution, an aqueous solution including potassium hydroxide and tetramethylammonium hydroxide, an aqueous solution including sodium hydroxide and tetramethylammonium hydroxide, and an aqueous solution including potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide; the acid solution can be selected from at least one of an aqueous solution including hydrogen fluoride and hydrogen peroxide, an aqueous solution including hydrogen fluoride and nitric acid, and an aqueous solution including hydrogen fluoride, hydrogen peroxide, and nitric acid.
[0041] Further, the alkali solution concentration can be controlled to be 10%-30%, and the alkali etching treatment time is 60-300s. Among them, the alkali solution concentration is the percentage of the total mass of the alkaline compound (at least one of KOH, NaOH or tetramethylammonium hydroxide) in the alkali solution to the mass of the alkali solution. By satisfying the above ranges of the alkali solution concentration and the alkali etching treatment concentration, the rate and depth of the etching reaction can be effectively adjusted. Within this concentration range, the alkali solution can maintain sufficient etching activity to selectively etch the line marks and defects on the surface of the silicon wafer without insufficient etching due to too low a concentration or excessive etching due to too high a concentration. At the same time, the range of treatment time ensures process flexibility, which can not only meet the etching requirements of different silicon wafer surface defect characteristics, but also avoid the increase in surface roughness caused by long-term etching. Therefore, this combination of conditions can significantly reduce the line mark depth of the silicon wafer and optimize the surface uniformity, laying the foundation for the subsequent acid polishing process.
[0042] Further, in one embodiment, in the acid solution, the concentration of hydrofluoric acid is 3wt%-10wt%, and the concentration of the oxidant aqueous solution is 6wt%-30wt%. Controlling the concentration of the hydrogen fluoride aqueous solution and the concentration of the oxidant aqueous solution can achieve the best chemical reaction conditions for the acid polishing process. The concentration design of hydrofluoric acid ensures that it can react effectively with silicon, while the concentration range of the oxidant aqueous solution ensures the sufficiency of the oxidation reaction, so that the oxide layer formed on the surface of the silicon wafer is uniform and stable.
[0043] Furthermore, in the method provided by the present invention, the volume ratio of hydrofluoric acid to the aqueous oxidant solution is 1:2-1:6. By controlling the volume ratio of the two, the synergistic effect of oxidation and dissolution is further optimized, the isotropic reaction effect during the polishing process is ensured, and the line depth and roughness of the silicon wafer surface are significantly reduced. Under this condition, acid polishing not only improves the uniformity and smoothness of the silicon wafer surface, but also avoids surface damage caused by excessive reaction, thereby obtaining high-quality silicon wafers while also improving the stability and efficiency of the process.
[0044] Furthermore, controlling the acid polishing time to 180-600s can ensure sufficient reaction while avoiding surface damage caused by over-polishing. Within this time range, the synergistic effect of the oxidant and hydrogen fluoride can be fully exerted, ensuring that the depth of the line marks on the silicon wafer surface is significantly reduced, while achieving uniformity and smoothness of the surface polishing. The optimized polishing time not only improves the processing quality of the silicon wafer, but also ensures the stability and efficiency of the process.
[0045] In one embodiment, after the silicon wafer is contacted with alkaline liquid vapor and subjected to alkaline etching treatment, the product obtained by the alkaline etching treatment is subjected to a first cleaning and drying treatment, the cleaning time is 120-200s, the temperature is 10-30°C; the drying time is 60-300s, and the temperature is 65-80°C. The first cleaning and drying treatment can effectively remove the alkaline liquid and moisture remaining on the surface of the silicon wafer, avoiding interference with the subsequent acid polishing treatment. This condition ensures the thoroughness of cleaning and the uniformity of drying, while avoiding deformation or damage of the silicon wafer caused by high temperature, thereby providing a clean surface condition for subsequent processes and improving the overall quality and efficiency of silicon wafer processing. The present invention does not limit the materials used for cleaning. In one embodiment, deionized water is used to clean the product obtained by the alkaline etching treatment.
[0046] In one embodiment, the intermediate silicon wafer is contacted with the acid polishing liquid vapor, and after the acid polishing treatment, the product obtained by the acid polishing treatment is subjected to a second cleaning and drying treatment, the cleaning time is 120-200s, the temperature is room temperature; the drying time is 60-300s, and the temperature is 65-80°C. The second cleaning and drying treatment can effectively remove the acid and moisture remaining on the surface of the silicon wafer, ensure the surface cleanliness, and prevent surface damage or contamination caused by chemical residues. This treatment condition not only ensures the thoroughness of the cleaning, but also avoids the structural changes of the silicon wafer caused by excessively high temperatures through moderate drying, provides stable quality assurance for the final product, and improves the reliability and consistency of the overall process. The present invention does not limit the materials used for cleaning. In one embodiment, the product obtained by the acid polishing treatment is cleaned with deionized water.
[0047] The second aspect of the present invention provides a silicon wafer, which is made using any one of the silicon wafer line mark processing methods provided by the first aspect of the present invention. The silicon wafer has the characteristic of a small surface line mark depth. Specifically, the line mark depth on the surface of the silicon wafer is less than or equal to 5μm. The line mark depth on the silicon wafer surface has an important impact on product quality. Specifically, the line mark depth is positively correlated with the probability of the occurrence of the broken grid phenomenon when the silicon wafer is used to produce solar cells. The line mark depth on the surface of the silicon wafer provided by the present invention is less than or equal to 5μm, so when the silicon wafer provided by the present invention is used to produce solar cells, the probability of the broken grid phenomenon is low due to the small line mark depth. Furthermore, the silicon wafer provided by the present invention also has a uniformity characteristic of a surface roughness of ≤1μm, which is more conducive to the preparation of high-uniformity solar cells.
[0048] The third aspect of the present invention provides a solar cell, which uses a product silicon wafer prepared by the silicon wafer line mark processing method provided by the first aspect of the present invention as a silicon wafer substrate, and the line mark depth on the surface of the silicon wafer substrate is less than 5μm; in addition, the cell also includes a functional layer and a gate line in contact with at least one surface of the product silicon wafer, and the width of the gate line is less than 30μm.
[0049] The present invention is not limited to a specific type of solar cell, and may be a common solar cell in the art, for example, at least one of a heterojunction cell, a PERC cell, and a TOPCon cell.
[0050] The line depth of the silicon wafer surface obtained by the line mark treatment of the silicon wafer provided by the present invention is less than or equal to 5μm and the surface roughness is ≤1μm, so when the silicon wafer is used to prepare a solar cell, the grid line can be designed to be smaller in width. Generally speaking, in the prior art, the grid line width is 30μm. When the silicon wafer obtained by the line mark treatment of the silicon wafer provided by the present invention is used as a silicon wafer substrate to prepare a solar cell, the grid line width can be reduced by 10-20%, that is, the grid line width is less than 30μm, and more specifically, 24-27μm.
[0051] Further, in one embodiment, the solar cell is a heterojunction cell, and the method for preparing the functional layer includes sequentially forming a passivation layer, a doping layer, and a transparent conductive layer. Among them, the doping layer includes an n-type doping layer and a p-type doping layer. The present invention does not limit the preparation method of the passivation layer, the doping layer, and the transparent conductive layer, and common preparation methods in the art, such as PECVD process, can be used.
[0052] Hereinafter, the silicon wafer line mark wet etching method and application thereof provided by the present invention will be further described in conjunction with specific embodiments.
[0053] The initial silicon wafer used in each embodiment and comparative example was obtained by cutting. The line depth of the initial silicon wafer was measured by 3D confocal microscope to be 12.501 μm; and the surface roughness was 2.719 μm.
[0054] Example 1
[0055] 1) The initial silicon wafer is sent to the first reaction device, and the alkali solution is atomized into alkali mist, which is contacted with the single crystal silicon wafer for alkali etching. The alkali solution is a KOH aqueous solution with a concentration of 10% by mass, and the alkali etching treatment time is 300s. The product obtained by the alkali etching treatment is subjected to a first cleaning and drying treatment, the cleaning time is 120s, the temperature is room temperature; the drying time is 200s, and the temperature is 70°C, to obtain an intermediate silicon wafer.
[0056] 2) The intermediate silicon wafer is sent to the second reaction equipment, and the acid liquid is atomized into acid mist, which is contacted with the single crystal silicon wafer for acid polishing. The acid liquid is composed of a 3% HF aqueous solution and a 12% hydrogen peroxide solution, the volume ratio of the HF aqueous solution to the hydrogen peroxide solution is 1:4, and the acid polishing treatment time is 400s. The silicon wafer obtained by the acid polishing treatment is subjected to a second cleaning and drying treatment, the cleaning time is 120s, the temperature is 20°C; the drying time is 200s, and the temperature is 70°C. After the acid polishing treatment, the product silicon wafer is obtained.
[0057] Example 2
[0058] This embodiment is basically the same as Embodiment 1, except that:
[0059] In step 1), the alkali solution is a 15% NaOH aqueous solution, and the alkali etching treatment time is 200s;
[0060] The first cleaning and drying treatment has a cleaning time of 200 s and a temperature of 20°C; a drying time of 150 s and a temperature of 65°C.
[0061] In step 2), the acid solution is composed of a 4% HF aqueous solution and a 20% nitric acid solution, wherein the volume ratio of the HF aqueous solution to the nitric acid is 1:5, and the treatment time of the acid polishing treatment is 300s;
[0062] The second cleaning and drying treatment has a cleaning time of 200 s and a temperature of 20°C; a drying time of 150 s and a temperature of 65°C.
[0063] Example 3
[0064] This embodiment is basically the same as Embodiment 1, except that:
[0065] In step 1), the alkali solution is a 25% tetramethylammonium hydroxide (TMAH) aqueous solution, and the alkali etching treatment time is 250s;
[0066] The first cleaning and drying treatment has a cleaning time of 180 seconds and a temperature of 20°C; a drying time of 120 seconds and a temperature of 75°C.
[0067] In step 2), the acid solution is composed of a 10% HF aqueous solution and a 30% potassium dichromate aqueous solution, wherein the volume ratio of the HF aqueous solution to the potassium dichromate aqueous solution is 1:3, and the reaction time is 600s;
[0068] The second cleaning and drying treatment has a cleaning time of 180 seconds and a temperature of 20°C; a drying time of 120 seconds and a temperature of 75°C.
[0069] Example 4
[0070] This embodiment is basically the same as Embodiment 1, except that:
[0071] In step 1), the alkali solution is a 30% NaOH aqueous solution, and the reaction time is 100 s;
[0072] The first cleaning and drying treatment has a cleaning time of 200 s and a temperature of 20°C; a drying time of 60 s and a temperature of 80°C.
[0073] In step 2), the acid solution is composed of a 10% HF aqueous solution and a 20% nitric acid solution, wherein the volume ratio of the HF aqueous solution to the nitric acid is 1:2, and the reaction time is 600s;
[0074] The second cleaning and drying treatment has a cleaning time of 200 s and a temperature of 20°C; a drying time of 60 s and a temperature of 80°C.
[0075] Comparative Example 1
[0076] 1) The single crystal silicon wafer is sent into a reaction device, and the alkali solution is atomized into alkali mist, which is contacted with the single crystal silicon wafer for alkali etching treatment. The alkali solution is a 30% NaOH aqueous solution, and the alkali etching treatment time is 100 seconds.
[0077] 2) The etched silicon wafer is washed with deionized water to remove the residual alkali solution on the surface and then dried. The washing time is 200 seconds at a temperature of 20° C. The drying time is 60 seconds at a temperature of 80° C. After drying, the product silicon wafer is obtained.
[0078] Comparative Example 2
[0079] 1) The single crystal silicon wafer is sent into the reaction equipment, and the acid solution is atomized into acid mist, which is contacted with the single crystal silicon wafer to perform acid + oxidant polishing treatment. The acid solution is composed of a 10% HF aqueous solution and a 20% nitric acid solution, wherein the volume ratio of the HF aqueous solution to the nitric acid is 1:2, and the reaction time is 600s.
[0080] 2) The etched silicon wafer is washed with deionized water and then dried to remove the acid solution remaining on the surface. The washing time is 200 seconds at room temperature, and the drying time is 60 seconds at 80° C. After drying, the product silicon wafer is obtained.
[0081] Test example
[0082] Morphological feature test
[0083] Using a 3D confocal microscope, the line mark depth and uniformity of the silicon wafer samples prepared in each embodiment and comparative example were tested. The results are shown in Table 1.
[0084] Table 1
[0085] Line mark depth (μm) Surface roughness(μm) Example 1 3.839 0.637 Example 2 4.667 0.895 Example 3 3.354 0.529 Example 4 4.195 0.796 Comparative Example 1 11.204 2.508 Comparative Example 2 9.511 1.961
[0086] It can be seen from Table 1 that compared with the product silicon wafers prepared in Comparative Examples 1-2, the product silicon wafers prepared in Examples 1-4 have lower line mark depth and surface roughness. This shows that the silicon wafer line mark processing method provided by the present invention can produce product silicon wafers with lower line mark depth and surface roughness.
[0087] Specifically, the silicon wafer prepared in Comparative Example 1 has a higher line mark depth and surface roughness than the product silicon wafers prepared in Examples 1-4. The reason may be that Comparative Example 1 only underwent alkaline etching treatment but no acid polishing treatment, so that the surface of the silicon wafer could not be polished as a whole. Therefore, the silicon wafer prepared has a higher line mark depth and surface roughness.
[0088] In addition, the silicon wafers prepared in Comparative Example 2 have higher line mark depth and surface roughness than the product silicon wafers prepared in Examples 1-4. The reason may be that Comparative Example 2 was only subjected to acid polishing treatment but not alkaline etching treatment, and it was impossible to selectively etch the brittle pits and line mark defects on the surface of the silicon wafer. Therefore, the silicon wafers prepared have higher line mark depth and surface roughness.
[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.
Claims
1. A method for processing silicon wafer line marks, characterized in that: The steps include: 1) alkaline etching treatment, wherein the initial silicon wafer is contacted with alkaline mist formed by atomization of alkaline solution, and alkaline etching treatment is performed to obtain an intermediate silicon wafer; 2) Acid polishing treatment, wherein the intermediate silicon wafer is contacted with acid mist formed by atomization of acid liquid, and acid polishing treatment is performed to obtain a product silicon wafer; the depth of the line marks on the surface of the product silicon wafer is less than 5 μm; The alkaline solution includes an aqueous solution of an alkaline substance, and the acid solution includes an aqueous solution of hydrofluoric acid and an oxidant.
2. The silicon wafer line mark processing method according to claim 1, characterized in that: The alkaline substance is selected from at least one of potassium hydroxide, sodium hydroxide and tetramethylammonium hydroxide; The oxidant is selected from at least one of hydrogen peroxide, nitric acid and potassium dichromate.
3. The method according to claim 1 or 2, characterized in that: The mass fraction of alkaline substances in the alkaline solution is 10%-30%, and the treatment time of the alkaline etching treatment is 60-300s.
4. The method according to claim 1 or 2, characterized in that: In the acid solution, the concentration of the hydrofluoric acid is 3wt%-10wt%, and the concentration of the oxidant aqueous solution is 6wt%-30wt%.
5. The method according to claim 4, characterized in that The volume ratio of the hydrofluoric acid to the oxidant aqueous solution is 1:2-1:
6.
6. The method according to claim 4, characterized in that The acid polishing treatment takes 180-600 seconds.
7. The method according to claim 3, characterized in that The method also includes a first cleaning and drying treatment of the product obtained by the alkali etching treatment, wherein the cleaning time is 120-200 seconds and the temperature is 10-30°C; the drying time is 60-300 seconds and the temperature is 65-80°C.
8. The method according to claim 4, characterized in that The method also includes performing a second cleaning and drying treatment on the product obtained by the acid polishing treatment, wherein the cleaning time is 120-200 seconds and the temperature is room temperature; the drying time is 60-300 seconds and the temperature is 65-80°C.
9. A silicon wafer, characterized in that: The silicon wafer is prepared by the method according to any one of claims 1 to 8, wherein the surface line depth of the silicon wafer is less than 5 μm.
10. A solar cell, characterized in that: A product silicon wafer prepared by the silicon wafer line mark processing method according to any one of claims 1 to 8 is used as a silicon wafer substrate, wherein the line mark depth on the surface of the silicon wafer substrate is less than 5 μm; It also includes a functional layer and a gate line in contact with at least one surface of the product silicon wafer, wherein the width of the gate line is less than 30 μm.