IC assembly with metal passivation at bonding bound point faces

Abstract

A surface finish layer on an integrated circuit (IC) die structure or on a substrate structure to which the IC die structure is to be bonded has a chemical composition that is different from the chemical composition of the underlying metallization. The surface finish layer may include a Cu-Ni alloy. Optionally, the Cu-Ni alloy may further include Mn. Alternatively, the surface finish layer may include a noble metal, such as Pd, Pt, or Ru, or the surface finish layer may include a self-assembled monolayer (SAM) molecule including Si and C. During the bonding process, an amphiphilic surface on the IC die structure or on the substrate structure may facilitate droplet-based fine alignment of the IC die structure with the body structure. Prior to bonding, a surface finish layer may be applied on the top surface of the metallization feature and may inhibit oxidation of the top surface exposed to the droplet.

Description

Background Art

[0001] Integrated circuit (IC) dies can be assembled using solder attach techniques, in which solder features are contacted to connect the die to a body or base substrate. However, solder assembly techniques are difficult to scale below solder bond feature pitches, which are tens of microns (e.g., 10-25 μm).

[0002] The IC die can be assembled using a hybrid bonding technique instead, in which the metal bonding sites of the IC die are directly interdiffused with the corresponding metal bonding sites of the main body or base substrate. Such bonding is called "hybrid", in which a bond is also formed between the dielectric materials adjacent to the metal bonding sites. During the hybrid bonding process, components (e.g., dies) with corresponding bonding site structures are put together to dock with each other. At room temperature, the dielectric materials are fully adhered to establish an initial bond (e.g., due to van der Waals forces). Then, thermal annealing can fuse the complementary metal bonding sites and can also increase the strength of the dielectric material bonding interface. Hybrid bonding technology can be scaled to well below the bonding feature pitch, which is 1 μm. However, such nano-pitch assembly technology relies on the fine alignment of the nanoscale (e.g., <500nm) of the IC die and the base substrate, which may be time-consuming and / or expensive to implement.

[0003] Therefore, techniques and architectures for hybrid bonding at the nanoscale in high-volume manufacturing are commercially advantageous. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In the accompanying drawings, the materials described herein are illustrated by way of example and not by way of limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements. In addition, where deemed appropriate, reference numerals have been repeated among the drawings to indicate corresponding or similar elements. In the drawings:

[0005] Figure 1 is a flow chart illustrating a method for self-alignment assisted assembly (SA3) of an integrated circuit (IC) die structure according to some embodiments;

[0006] Figure 2A is a cross-sectional view of an interface layer on a main structure according to some embodiments;

[0007] Figure 2B According to some embodiments Figure 2A A plan view of the main structure shown in ;

[0008] Figure 3Ais a cross-sectional view of a body structure having a metal joint site feature including a surface finish according to some embodiments;

[0009] Figure 3B According to some embodiments Figure 3A A plan view of the main structure shown in ;

[0010] Figure 4A is a cross-sectional view of an alignment feature defined into a host structure according to some embodiments;

[0011] Figure 4B According to some embodiments Figure 4A A plan view of the main structure shown in ;

[0012] Figure 5A is a cross-sectional view of a hydrophobic feature formed on a host structure according to some embodiments;

[0013] Figure 5B According to some embodiments Figure 5A A plan view of the main structure shown in ;

[0014] Fig. 6A is a cross-sectional view of a wafer or panel including a plurality of host structures, each host structure including an amphiphilic surface structure, according to some embodiments;

[0015] Figure 6B According to some embodiments Fig. 6A A plan view of a wafer or panel as shown in ;

[0016] Fig. 7A is a cross-sectional view of an IC die structure being roughly aligned and placed on a droplet constrained in a bonding area according to some embodiments;

[0017] Figure 7B According to some embodiments, Fig. 7A A plan view of an alignment and placement IC die structure;

[0018] Figure 8 is a cross-sectional view of a composite structure including an IC die structure hybrid-bonded to a bonding region of an amphiphilic structure of a host structure according to some embodiments;

[0019] Fig. 9 is a cross-sectional view of a composite structure including an IC die structure and a dielectric material therebetween according to some embodiments;

[0020] Fig.10 is a cross-sectional view of a system including a heat sink and a body assembly assembled with a hybrid bonded composite structure that also includes an IC die structure, according to some embodiments;

[0021] Fig.11 illustrates a mobile computing platform and a data server machine using a multi-chip package according to some embodiments; and

[0022] Fig.12 is a functional block diagram of an electronic computing device according to some embodiments. DETAILED DESCRIPTION

[0023] Embodiments are described with reference to the accompanying drawings. Although specific configurations and arrangements are described and discussed in detail, this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the present specification. It will be apparent to those skilled in the relevant art that the techniques and / or arrangements described herein can be used in a variety of other systems and applications in addition to the systems and applications described in detail herein.

[0024] Reference is made to the accompanying drawings in the following detailed description, which form a part of the following detailed description and illustrate exemplary embodiments. In addition, it should be understood that other embodiments may be utilized and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references (e.g., upward, downward, top, bottom, and the like) may be used only to facilitate the description of features in the accompanying drawings. Therefore, the following detailed description should not be taken as limiting, and the scope of the claimed subject matter is limited only by the appended claims and their equivalents.

[0025] In the following description, many details are set forth. However, it will be apparent to those skilled in the art that embodiments can be implemented without these specific details. In some instances, known methods and devices are shown in block diagram form, rather than in detail, to avoid blurring the embodiments. This specification refers throughout to "embodiment" or "one embodiment" or "some embodiments" to mean that specific features, structures, functions or characteristics described in conjunction with the embodiment are included in at least one embodiment. Therefore, the phrase "in an embodiment" or "in one embodiment" or "some embodiments" throughout this specification does not necessarily refer to the same embodiment. In addition, in one or more embodiments, specific features, structures, functions or characteristics can be combined in any suitable manner. For example, the first embodiment can be combined with the second embodiment, as long as the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0026] As used in the specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0027] The terms "coupled" and "connected" and their derivatives may be used in this article to describe the functional or structural relationship between components. These terms are not intended to be synonymous with each other. On the contrary, in a particular embodiment, "connected" can be used to indicate that two or more elements are in direct physical, optical or electrical contact with each other. "Coupled" can be used to indicate that two or more elements are in direct or indirect (there are other intermediate elements between them) physical or electrical contact with each other, and / or these two or more elements cooperate or interact with each other (for example, as in a cause-and-effect relationship).

[0028] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material with respect to other components or materials where such a physical relationship is noteworthy. For example, in the context of materials, one material or layer may be in direct contact with or below another, or may have one or more intervening materials or layers. Additionally, a material between two materials or layers may be in direct contact with both materials / layers, or may have one or more intervening materials / layers. In contrast, a first material or layer "on" a second material or layer is in direct contact with the second material / layer. Similar distinctions will be made in the context of component assembly.

[0029] As used throughout this specification, and in the claims, a list of items linked by the term "at least one of" or "one or more of" may mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or, A, B, and C.

[0030] Unless otherwise indicated in the specific context of use, the term "predominantly" means more than 50%, or more than half. For example, a composition that is predominantly the first component means that more than half of the composition is the first component (e.g., >50at.%). As another example, a composition that is predominantly the first component and the second component means that more than half of the composition is the first component and the second component (e.g., >50at.%). The term "mainly" means the largest part or the largest part. For example, a composition that is predominantly the first component means that the composition has more of the first component than any other component. A composition that is predominantly the first component and the second component means that the composition has more of the first component and the second component than any other component. The term "substantially" means that there are only accidental changes. For example, a composition that is substantially the first component means that the composition may also include <1% of any other component. A composition that is substantially the first component and the second component means that the composition may also include <1% of any component that replaces the first component or the second component.

[0031] As previously described, hybrid bonding techniques provide advantages in assembling IC die structures to other IC die structures or some other main structure (e.g., a package substrate structure, an interposer structure, or the like). According to embodiments herein, the IC die structure may include any monolithic integrated circuit device that provides electrical functionality, computing functionality, memory functionality, or similar functionality. The IC die structure itself may include more than one monolithic integrated circuit device. For example, the IC die structure may include two vertically stacked IC dies or two coplanar IC dies. The IC dies within the IC die structure may be directly bonded to each other or coupled by interconnect features. For example, the IC die structure according to embodiments herein may be referred to as a "core particle," "core particle die," "dice," "tile," or "chip." Although the terms core particle and IC die or chip may be used interchangeably, a full-function ASIC is generally considered to be an IC die or chip, while a core particle or a chip may have more limited functionality, such as supplementing one or more other IC core particles that will be part of the same multi-core device. The die or chip may be, for example, a wireless radio circuit, a microprocessor core, an electronic memory circuit, a floating point gate array (FPGA), a power management and / or power supply circuit, or may include a MEMS device, for example.

[0032] In the context of hybrid bonded IC die structures, self-alignment assisted assembly (SA3) can promote greater die-to-wafer hybrid bonding (D2W HB) yields by reducing the burden of fine alignment. In some exemplary SA3 processes, the bonding area is incorporated into an "amphiphilic" or "heterogeneous" surface structure on the IC die structure or the main structure, or the bonding area is incorporated into an "amphiphilic" or "heterogeneous" surface structure on the IC die structure and the main structure. The amphiphilic / heterogeneous surface has a high wettability contrast between its different regions. As further described herein, the high wettability contrast can be achieved by physical patterning (e.g., creating grooves around the bonding area to confine liquids via the canthotaxi effect), chemical patterning (e.g., depositing a hydrophobic coating around the bonding area to reduce the surface energy), or a combination of the two (e.g., creating grooves with hydrophobically coated sidewalls around the bonding area).

[0033] In the amphiphilic surface structure, one area has high wettability relative to another area with low wettability. This wettability contrast can improve the control of droplet spreading, so that the droplet can be constrained on the bonding site of the IC tube core structure or the main structure, or so that the droplet can be constrained on the bonding site of the IC tube core structure and the main structure. When the drop evaporates, the surface tension of the drop acts to passively finely align the IC tube core structure, so that the bonding area remains in contact and is ready for hybrid bonding. At room temperature, the surface attraction between the dielectric area on the IC tube core structure and the main structure can be sufficient to temporarily stick the two. A hybrid bond can then be formed by applying pressure and / or an elevated temperature to form and / or strengthen the bond between metal features (e.g., metal pads) dispersed in the surrounding dielectric material. Once bonded, the metal features form composite metal features that electrically interconnect the IC tube core structure and the main structure. However, in some embodiments, the bond can be only dielectric-dielectric or only metal-metal (e.g., for thermal applications or some RF applications).

[0034] With SA3, a bonder can pick up an IC die structure and place it on a main structure relying solely on rough alignment (e.g., about 25-50 μm), thereby enabling rapid assembly. When a droplet is constrained to the bonding area between the IC die structure and the main structure, capillary forces and liquid surface tension induce alignment with high positional accuracy (e.g., <200 nm) due to the amphiphilic structures or transition structures on the mating surfaces of the IC die structure and / or the main structure. Therefore, such amphiphilic structures or heterostructures may be more specifically referred to as "self-aligned features" or "SA3 features."

[0035] Prior to bonding, the metallized features to be bonded may be exposed to an oxidizing atmosphere, such as air or water droplets. Such exposure may result in surface oxidation, which may result in higher contact resistance and / or yield loss. The queue time between exposure to the atmosphere and the bonding process may be controlled. However, in certain bonding processes (e.g., bonding processes utilizing SA3 technology) in which the metallized features may be exposed to water, surface oxidation reactions may still occur to form a certain thickness of metal oxide, which may reduce the electrical properties of the composite metallized features.

[0036] As described below, in order to achieve excellent performance during the hybrid bonding of the IC die structure to the main structure, a surface finish layer can be formed on the IC die structure and / or on the main structure. As further described below, the surface finish layer can have a chemical composition different from the metallization below, and thus better resist oxidation before bonding. After bonding, the surface finish layer can be retained as a bonding interface layer embedded between the metallization features of the IC die structure and the main structure. Advantageously, the composition and / or thickness of the surface finish layer ensures a sufficiently low resistance bonding interface. The resistance attributed to the bonding interface (the bonding interface includes one or more elements introduced by the surface finish layer) is advantageously significantly lower than the resistance that would otherwise be attributed to the presence of metal oxides at the bonding interface.

[0037] Figure 1 1 is a flow chart illustrating a self-alignment assisted assembly method 101 for an integrated circuit (IC) die structure according to some embodiments. According to method 101, the IC die structure is assembled to a main structure by implementing one or more SA3 techniques. Prior to assembly, the IC die structure and / or the main structure are processed to form a surface finish layer on the top surface of the metallization features to be joined during assembly. Method 101 can be implemented, for example, to form one or more of the composite assemblies described elsewhere herein. Method 101 is shown as including several discrete boxes to ensure clarity of description. However, in practice, the number of boxes and / or the order of such boxes can be modified without departing from the principles shown by method 101.

[0038] Method 101 begins with input 110, where a first structure is received. The first structure can be a portion of any wafer, panel, strip, etc., suitable for forming a bonding site structure to be directly bonded or otherwise interconnected with one or more IC die structures. The bonding site features are formed in a bonding region or bonding site of the main structure. The bonding region is advantageously integrated into one or more amphiphilic surfaces suitable for SA3 assembly.

[0039] In some embodiments, the main structure received at input 110 is a "base" substrate structure, and an IC die structure to be assembled with the main substrate structure is received at input 125. In other embodiments, the main structure received at input 110 is an IC die structure, and another IC die structure received at input 125 is assembled with the main IC die structure.

[0040] The method 101 continues at block 112 where a bonding site feature is formed on the main structure. In some exemplary embodiments where the bonding site feature includes metallization, block 112 includes a damascene metallization process that is applicable to a back-end metallization level of an IC die structure or a metallization level of a package substrate structure. The metallization process may, for example, include: forming a trench into a dielectric material; filling the trench with metallization; and planarizing the metallization, which exposes the dielectric material around the metallization trench. In some exemplary embodiments, the metallization formed at block 112 includes copper (Cu). Although Cu has excellent electrical conductivity, it is susceptible to forming oxides associated with different metal oxidation states (e.g., cuprous oxide, cupric oxide, etc.). Such oxides have significantly lower electrical conductivity and therefore may not be conducive to retention in an electrical device.

[0041] Planarization of the metallization at block 112 may result in some recessing of one of the dielectric material or the metallization relative to the other. Such "dishewing" may, for example, recess the metallization relative to the plane of the surrounding dielectric surface. Alternatively, the dielectric may be recessed relative to the plane of the metallization. Despite such recessing, the metallization feature is substantially coplanar with the surrounding dielectric.

[0042] The method 101 continues at block 114 where the metallization feature is optionally recessed relative to the surrounding dielectric material to increase the non-planarity of the metallization feature relative to the surrounding dielectric material. Block 114 is shown in dashed lines to emphasize that it is optional. For example, planarization of the metallization at block 112 may cause sufficient concavity of the metallization feature such that additional recessing at block 114 may not be necessary.

[0043] At block 115, a surface finish is formed on the surface of the metallized feature that is not protected by the surrounding dielectric material. In an exemplary embodiment, the formation of the surface finish includes the deposition of a material having a chemical composition different from the chemical composition of the metallized feature. The deposition of the finish material can be selective to the metallized feature, so that the surface finish is formed only on the metallized feature. The deposition can also be non-selective, so that the material layer is formed over the metallized feature and the surrounding dielectric material. The metallized feature can be increased by the finish material deposited at block 115 to become sufficiently coplanar with the surrounding dielectric to ensure success during the subsequent bonding process. In some embodiments, due to the non-planarity between the metallized feature and the surrounding dielectric, the finish material deposited at block 115 can be selectively removed from the dielectric material using a planarization process.

[0044] Figure 2A is a cross-sectional view illustrating deposition of a finishing layer material 231 on a body structure 200 according to some embodiments. Figure 2B is a plan view of a main structure 200 according to some further embodiments. Figure 2A The cross-sectional plane AA' shown in Figure 2B The dot-dash line A-A' is defined in FIG.

[0045] The main structure 200 includes one or more substrate materials 201. The substrate material 201 may vary depending on the implementation. In some embodiments in which the main structure 200 is a package substrate structure or a package interposer structure, the substrate material 201 may include one or more structural material layers, such as semiconductor materials (e.g., single crystals), sapphire or glass. The substrate material 201 may include any of the materials found in integrated circuit wafers, such as semiconductor materials (e.g., silicon, germanium, GaN, GaAs, InP, InGaAS, etc.), interconnect layers on the die (e.g., copper, aluminum, tantalum, other metals), and dielectrics on the die (e.g., silicon dioxide, carbon-doped silicon dioxide, silicon nitride, silicon carbide, etc.). For glass embodiments, the structural material may be predominantly silica (e.g., silicon and oxygen), and may also include one or more elements, such as hydrogen, carbon and / or metals, such as, but not limited to, copper, silver, gold, aluminum, beryllium, magnesium, calcium, strontium barium or radium. Additional dopants (eg, boron, phosphorus) may also be present in the structural material (eg, borosilicate glass, etc.).

[0046] The substrate material 201 may also include one or more levels of metallization features 230. The metallization features 230 may be embedded, for example, within a dielectric material. For example, the dielectric material may have been built on one or more sides of a structural material layer. The structural material layer may be retained or ultimately discarded so that the substrate material 201 may include only the dielectric material and the embedded wiring metallization features 230. The dielectric material may be an organic dielectric, such as an epoxy resin; phenolic glass; or a resin film, such as the GX series films available from Ajinomoto Fine Technology Co., Ltd. (ABF). The encapsulating dielectric material may include an epoxy resin (e.g., an acrylate of a resol, such as epoxyphenol resol (EPN) or epoxycresol resol (ECN)). In other examples, the encapsulating dielectric material includes an aliphatic epoxy resin, which may be monofunctional (eg, lauryl alcohol glycidyl ether), difunctional (butylene glycol diglycidyl ether), or have a higher functionality (eg, trimethylolpropane triglycidyl ether).

[0047] The main structure 200 may also include an inorganic dielectric material (e.g., including at least 20 atomic % of one or more of silicon, oxygen, or nitrogen). In some embodiments, the inorganic dielectric material is primarily silicon and oxygen (e.g., SiO 2 ), mainly silicon and nitrogen (e.g., Si 3 N 2 ), or mainly silicon, oxygen, and nitrogen (e.g., Si x O y N x ). Inorganic dielectric materials may also include one or more dopants, such as carbon. However, inorganic dielectric materials are different from organic dielectrics (e.g., epoxy resins and phenolic glasses), which have much higher carbon contents and a higher percentage of carbon-hydrogen bonds.

[0048] The substrate material 201 may also include one or more IC die structures (not depicted). In some embodiments where the main structure 200 is a package substrate or interposer, the IC die structure is embedded within the dielectric material. In other embodiments, the main structure 200 is an IC die structure. Such an IC die structure may be a fully functional ASIC, or may be a core grain or slice with more limited functionality that is used to supplement one or more other IC die structures that will become part of the same multi-chip device. For embodiments where the main structure 200 is an IC die structure, the substrate material 201 may include any of those typical materials of a monolithically manufactured IC die, such as, but not limited to, device material layers and / or silicon (e.g., single crystal) layers, inorganic dielectric materials (e.g., including at least 20 atomic % of silicon, one or more of oxygen or nitrogen), and metallization features 230.

[0049] The metallization features 230 may include one or more metals or metal alloys. In some embodiments, the metallization features 230 include a barrier material (not depicted) that may line the interface with the surrounding dielectric material. For example, the barrier material may be Ti, TiN, Ta, or TaN. In some further embodiments, the metallization features 230 include a filler metal over the barrier material. Exemplary filler metals predominantly include Cu.

[0050] like Figure 2A As shown in , the joint site structure 203 includes a plurality of metallization features 230 located within the uppermost metallization level of the main structure 200. Within the joint site structure 203, the top surface of the metallization feature 230 is recessed relative to a plane P1 corresponding to the top surface of the surrounding dielectric material. As described above, the recess of the metallization feature 230 may be attributed to the formation of a concave surface during the planarization process, or may be attributed to another selective metallization etching process. For example, in some embodiments in which the fill metal is predominantly Cu, the main structure 200 may be exposed to a wet chemical etchant capable of dissolving Cu (or its oxide). Dry etching (e.g., atomic layer etching) may also be implemented in combination with wet chemical etching, or may be implemented in place of wet chemical etching.

[0051] The thickness of the finishing layer material 231 increases the thickness of the metallization feature 230. Figure 2A and Figure 2B In the example shown in , a finishing layer material 231 has been formed over the entire body structure 200. Any deposition process suitable for the composition of the material 231 and compatible with the body structure 200 may be implemented. The surface finishing layer material 231 has a chemical composition different from the chemical composition of the metallized features 230 and will provide a surface finishing layer on the metallized features 230 that will inhibit oxidation.

[0052] In some embodiments, material 231 includes a metal that is substantially absent from metallization feature 230, such as one or more of Ni, Mn, Pd, Ti, Pt, or Ru. In some advantageous embodiments, finish layer material 231 is a Cu alloy including Ni or one or more of Mn, Pd, Ti, Pt, or Ru. For example, finish layer material 231 may be a Cu-Ni alloy, such as constantan, which typically has a Ni content of about 45 wt.%. In another example, surface finish layer material 231 is a Cu-Mn alloy, such as manganese copper, which also includes Ni (e.g., about 12 wt.% Mn and 2 wt.% Ni, the remainder being Cu). Constantan and manganese copper alloys both have a stronger resistance to oxidation than copper components lacking these minority components. It is noteworthy that, while the conductivity of these alloys is lower than that of purer Cu, the conductivity is significantly higher than that of copper oxide.

[0053] In other advantageous embodiments, the surface finishing layer material 231 is predominantly a noble metal, such as Pd, Pt or Ru. Each of these metals is more resistant to oxidation than copper and has fairly good electrical conductivity. Material 231 may also be predominantly any alternative metal, such as Ti, that provides acceptable electrical properties and improved oxidation resistance.

[0054] Depending on the metal composition of material 231, the deposition process may be non-selective to metallization features 230 (e.g. Figure 2A and Figure 2B ). For example, a substantially pure metal or metal alloy film can be sputter deposited over the entire working surface of the main structure 200. For some metals, a selective deposition process (e.g., autocatalytic deposition) can be used to selectively deposit the surface finish. Autocatalytic deposition suitable for forming Cu or Ni is commercially available, and such a process can be suitable for selectively depositing one or more of the above-mentioned Cu-Ni alloy components. For such a deposition process, the surface finish material 231 can be formed only on the metallized features 230, because the autocatalytic deposition will only deposit metal on the catalytic metal surface, and not on the non-catalytic dielectric surface.

[0055] In some other embodiments, the surface finishing layer material 231 includes a non-metal, such as an organic material, for example, including at least 10 atomic (at.)% carbon (C), and advantageously including at least 30at.% C or more. In some embodiments, the material 231 includes a self-assembled monolayer (SAM) material, such as an alkylsilane or a fluoroalkylsilane (e.g., ODS, FDTS). The SAM reaction generally forms a monolayer of molecules aligned to each other in a uniform manner. Such molecules can be introduced in the gas phase and can be "self-assembled" by forming a highly selective bond at the surface of the metallized feature 230 and orienting itself to a face perpendicular to the surface. The bond of the SAM molecule can include, for example, Si, so that the material 231 is predominantly C and also includes Si. For SAM-based materials, the material 231 can be selectively formed on the exposed surface of the metallized feature 230 without being substantially deposited on the surrounding dielectric material. Non-SAM-based materials or films are also possible. In some embodiments, material 231 is or includes a substantially amorphous polymer film, such as siloxane (e.g., PDMS and derivatives, HMDSO), silazane (HMDS) lacking the molecular ordering of SAM-based materials. Such a material can be deposited in a non-selective manner so that material 231 is formed over the metallization and dielectric of the main structure 200, substantially as shown in FIG. Figure 2A and Figure 2B as shown in .

[0056] While an organic composition may not provide high conductivity, such a composition may still be suitable for material 231 if it has a minimal as-deposited thickness T and / or material 231 is subsequently altered (e.g., partially decomposed and / or undergoes significant solid-state diffusion) after the bonding process. In general, for any interface material layer, some diffusion into metallization features 230 can be expected, so that the as-deposited thickness T can decrease with further processing of the host structure 200. The as-deposited thickness T is advantageously minimized, but sufficient to passivate the metallization features 230 by inhibiting the formation of oxygen compounds (i.e., metal oxides). In some embodiments, material 231 is deposited to a thickness T of no more than 5 nm, and advantageously less than 3 nm (e.g., 1-2 nm).

[0057] Figure 3A is a cross-sectional view further illustrating the body structure 200 including a surface finish material 231 only on the metal joint site features, according to some embodiments. Figure 3B is a plan view further illustrating the main structure 200 . Figure 3A and Figure 3B 231 (e.g., as shown in FIG. Figure 2A An embodiment in which the substrate is patterned or planarized as shown in FIG. Figure 3A and Figure 3B Also shown are embodiments in which material 231 is selectively deposited. For either embodiment, material 231 is retained only as a surface finish on metallized features 230. For embodiments in which material 231 is non-selectively deposited, a planarization process may be used to remove any material that extends above plane P1 of the surrounding dielectric material. Such a process may rely on previous recessing of metallized features 230 to retain at least a portion of material 231 as a surface finish on metallized features 230. In other embodiments, masked etching may remove surface finish material from areas outside of metallized features 230. Regardless of the technique used to pattern material 231, patterning need only prevent electrical shorts between various metallized features in metallized features 230.

[0058] Method 101( Figure 1 ) Continuing at block 116, alignment features are formed that are advantageously suitable for self-alignment assisted assembly (SA3). Such alignment features may be formed in a peripheral region adjacent to the joint site. In an exemplary embodiment, the alignment features are formed after the surface finish is applied to the joint site features. However, in other embodiments, the alignment features are formed before the surface finish is applied. Alternatively, the alignment features may be formed simultaneously with the joint site features.

[0059] In some embodiments, at least a portion of the substrate material is etched and / or recessed relative to the bonding site structure, for example to generate a topography. Depending on the material or (one or more) chemical composition of the substrate material, one or more etching processes may be employed at block 116. As described above, high wettability contrast may be achieved by physical patterning (e.g., creating grooves around the bonding area to confine liquid via the eye canthalometric effect). Thus, forming a recess or groove at block 116 may be an element of fabricating the SA3 alignment feature.

[0060] The topographic features generated at block 116 can advantageously increase the wettability contrast relative to the junction region. Such topographic features (e.g., grooves) can change the effective contact angle of the droplet to greater than 90° and thereby alter the surface energy characteristics of the droplet. In some further embodiments, block 116 causes the topographic features to have a significantly higher average surface roughness than in the junction region. Thus, block 116 can include any surface texturing technique, such as laser surface roughening.

[0061] Figure 4A is a cross-sectional view of alignment features defined into body structure 200 according to some embodiments. Figure 4B is a plan view of the main structure 200 according to some further embodiments. Figure 4A As shown in FIG. 1 , a trench 229 is etched into the substrate material 201 within the peripheral region 205 adjacent to the bonding site structure 203. During the alignment feature etching, the bonding site structure 203 can be protected by one or more mask materials 214. The trench 229 can be formed to a depth D, which can vary depending on the implementation (e.g., 10-50 nm or more). Figure 4B As shown in FIG. 2 , the groove 229 is continuous around the perimeter of the bonding site structure 203 . However, alternative embodiments may include a plurality of grooves 229 that are laterally adjacent to or define one or more edges of the bonding site structure 203 .

[0062] The surface of the groove 229 can advantageously have a roughness greater than the surface roughness of the adjacent bonding area. For example, the metallized feature 230, as passivated by the surface finishing layer material 231, can have a lower surface roughness (e.g., <15nm average roughness), while the groove 229 has a higher surface roughness (e.g., >50nm average roughness). The dielectric material within the bonding site structure 203 can also have a roughness lower than the dielectric material surface of the groove 229 (e.g., <5nm average roughness). In some embodiments, the average surface roughness of at least the bottom of the groove 229 is at least twice the average surface roughness of the surface finishing layer material 231, and can be five times, ten times, or twenty times the average surface roughness of the metallized feature 230. As used herein, the average roughness (or centerline average) is as described in ASME B46.1. The average roughness is the arithmetic average of the absolute value of the deviation of the profile height from the mean line recorded within the evaluation length. For example, the average roughness can be measured using a profilometer that includes a stylus that is moved back and forth over the surface. Figure 4B For a groove 229 having a longitudinal length in a first dimension (e.g., coinciding with the x-axis), the average roughness can be measured over a distance of approximately 60-70% of the longitudinal length while remaining near the centerline of the cross-sectional width of the groove 229, wherein the cross-sectional width is in a dimension substantially orthogonal to the first dimension (e.g., coinciding with the x-axis).

[0063] The hydrophobicity of the alignment features may be enhanced, for example, by forming a hydrophobic material in a region surrounding the bonding region. Figure 5A and Figure 5B A cross-sectional view and a plan view of a hydrophobic feature 204 formed in a peripheral region 205 according to some embodiments are shown. The hydrophobic feature 204 ensures that the main structure 200 has an amphiphilic structure or transition structure, with sufficient wettability contrast between the bonding site structure 203 (e.g., where a droplet will be formed and has high wettability) and the adjacent peripheral region 505 (e.g., where the droplet will be constrained and has low wettability). Although the liquid used for self-aligned assisted assembly can vary (polar or non-polar, etc.), in the exemplary SA3 embodiment using water, the bonding area with high wettability is hydrophilic (i.e., causing the water droplet to have a contact angle of less than 90°). Therefore, when the liquid minimizes its surface energy, the water droplet will tend to spread over the bonding area. The peripheral region 205 with low wettability is hydrophobic (i.e., causing the water droplet to have a large contact angle greater than 90°). Therefore, the water droplet on the bonding area will tend to minimize contact with the peripheral region 205.

[0064] Hydrophobic feature 204 can include any chemical coating or film material and / or topographic structure, which enhances the hydrophobic boundary of one or more edges of adjacent bonding site structure 203. In some embodiments, feature 204 includes self-assembled monolayer (SAM) material, such as alkylsilane or fluoroalkylsilane (e.g., ODS, FDTS), thiol (e.g., hexadecanethiol), phosphonic acid (e.g., octadecyl or perfluorooctanephosphonic acid) or alkanoic acid (e.g., heptadecanoic acid). Other SAM embodiments can include disulfide, amine, azole, amide, imide, pyridine derivative, cyanoacrylate derivative or other components including sulfur atoms or nitrogen atoms. SAM reaction usually forms a monolayer molecule aligned to each other in a uniform manner. Such molecules can be introduced in the gas phase and "self-assembled" by forming a highly selective bond at the surface and orienting itself to be perpendicular to the surface. However, non-SAM-based materials or films are also possible. In some embodiments, feature 204 is or includes a polymer film such as a siloxane (e.g., PDMS and derivatives, HMDSO), a silazane (HMDS), a polyolefin (e.g., PP), or a fluorinated polymer (e.g., PTFE, PFPE, PFDA, C 4 F 8 In some advantageous embodiments, feature 204 has a chemical composition with at least 10 atomic percent (at.%) carbon or at least 10 at.% fluorine.

[0065] In the example shown, the hydrophobic features 204 are in direct contact with the sidewalls of the trench 229 (or in direct contact with the barrier material lining the trench 229). However, the features 204 may be on any other surface of the trench 229. Figure 5B As shown in , feature 204 substantially surrounds the base or table of substrate material 201 as a bonding site structure 203. Feature 204 can be adjacent to multiple non-parallel edges of the bonding area and / or formed on the sidewalls of the bonding area according to any suitable (one or more) techniques. A conformal hydrophobic material layer can be formed on the exposed surface of the bonding site structure, for example, using a spin coating process or a conformal vapor deposition process. The conformal hydrophobic material layer can then be patterned with an anisotropic "spacer" etch.

[0066] The body structure 200 may be part of a wafer or panel that also includes many such body structures. Fig. 6A6 is a cross-sectional view of an exemplary wafer (or panel) 600 including a plurality of aggregated body structures 200A, 200B, 200C. In the example shown, each body structure 200A-200C includes a plurality of bond site structures 203A and 203B on a first side (e.g., top side) of one or more substrate materials 201. In some exemplary embodiments, each of the bond site structures 203A and 203B includes substantially the same passivation metallization features described above for the bond site structures 203. Figure 6B A plan view of a portion of a wafer (or panel) 600 is further shown. As shown, four bonding areas including bonding site structures 203A, 203B, 203C, and 203D are located in separate quadrants of the main structure 200A. Each of the bonding site structures is surrounded by a hydrophobic feature 204, which is within a trench (e.g., substantially as described above). In an exemplary embodiment, one IC die will be assembled on each of the bonding site structures 203A-203D. However, in other embodiments, as few as one IC die may be assembled on each of the main structures 200A-200C.

[0067] Return to Figure 1 , method 101 continues at block 120 where a droplet is formed on each of the bonded regions of the host structure. Any suitable technique for liquids, such as vapor phase condensation or direct liquid dispensing (i.e., printing), may be implemented at block 120 as the embodiments are not limited in this regard. In some exemplary embodiments, water droplets are dispensed at block 120. However, depending on the nature of the wettability contrast of the host structure, a selected polar (e.g., alcohol) or non-polar (e.g., solvent) liquid may be dispensed at block 120.

[0068] In addition to the drop formed on the bonding area at frame 120, or as an alternative to the drop formed at frame 120, the drop can be formed on the IC die structure (received at input 125). Method 101 then continues at frame 130, in which the IC die structure received at input 125 is placed on the bonding area of ​​the main structure prepared at frame 120. The die structure received at input 125 may include a single IC die, or may include any number of IC dies assembled (e.g., hybrid bonded) into a coplanar or 3D IC die structure. The IC die structure may, but need not, also include a metallization layer and / or an organic dielectric material constructed on the surface of the IC die using a suitable semi-additive process (SAP). The IC die structure may also include metallization features, the metallization features including a surface finish layer substantially the same as the surface finish layer for the main structure described above. However, in other embodiments, the metallization features of the IC die structure received at input 125 lack any surface finish layer.

[0069] Fig. 7A 2 is a cross-sectional view of IC die structures 701 and 702 undergoing initial rough alignment 250 with bonding site structures 203A and 203B. When so aligned, IC die structures 701 and 702 are placed on a droplet 705 constrained to the bonding area by the adjacent hydrophobic area. For example, the rough alignment 250 may be performed using a "pick and place" device. For example, such a device may be capable of positional accuracy within 25-50 μm in each of the x and y dimensions. Figure 7B is a plan view of a rough alignment 250 and placement of IC die structures 701 and 702 in accordance with some embodiments. Figure 7B A certain alignment error shown in will be corrected by a droplet (e.g., water droplet) 705 during a passive fine alignment (e.g., via capillary forces, etc.) phase until the drop evaporates. In an exemplary embodiment, the fine alignment is advantageously to within 200 nm in each of the x-dimension and the orthogonal y-dimension.

[0070] In the exemplary embodiment shown, the IC die structures 701, 702 each include an IC die substrate material 717, a device layer 710 in contact with the IC die substrate material 717, and an IC die metallization level 715 above the device layer 710. The IC die structure may include a through substrate via (TSV) 735 extending from the device layer 710 and extending into the IC die substrate material 717. Although the chemical composition of the IC die substrate material 717 may vary with implementation, in an exemplary embodiment, the IC die substrate material 717 is a silicon (e.g., single crystal) layer. The IC die substrate material 717 may also have alternative compositions, such as, but not limited to, germanium (Ge), silicon germanium alloy (SiGe), gallium arsenide alloy (GaAs), indium phosphide alloy (InP), gallium nitride alloy (GaN), silicon carbide alloy (SiC), etc. The device layer 710 includes active devices (not depicted). In some embodiments, the active devices within the device layer 710 are field effect transistors (FETs). The FETs can have any architecture (e.g., planar, non-planar, single-gate, multi-gate, stacked nanosheets, etc.) and can have a characteristic pitch of, for example, 10-30 nm. Additionally, or alternatively, the device layer 710 can include active devices other than FETs. For example, the device layer 710 can include electronic memory structures, spin valves, or the like.

[0071] The IC die structures 701, 702 include an IC die metallization level 715 on the front side of the device layer 710. In an exemplary embodiment, the metallization level 715 includes die metallization features embedded in a dielectric material 718. Although the IC die metallization features can have any (one or more) compositions with sufficient conductivity, in an exemplary embodiment, the IC die metallization features 730 are predominantly Cu. The IC die structure 701 shows an example in which the metallization features 730 are passivated with a surface finish material 731. The finish material 731 can have any of the compositions described elsewhere herein for the surface finish material 231. In some exemplary embodiments, the finish material 731 has substantially the same composition as the finish material 231. The IC die structure 702 shows another example in which the metallization features 730 lack any passivating surface finish material.

[0072] In some advantageous embodiments, the IC die structures 701, 702 include amphiphilic surface structures corresponding to complementary surfaces on the main structure 200A, which includes the bonding site structures 203A, 203B. The metallization features 730 can have any pitch compatible with the corresponding metallization features 230 within the bonding site structures 203A and / or 203B. In some exemplary embodiments, the individual metallization features 730 correspond to the individual metallization features 230 and have a feature pitch, for example, in the range of 100nm to 1μm. The metallization features 730 can have any suitable composition and can have substantially the same composition (e.g., the same metallization) as the metallization features 230, and can also include the same surface finish layer, or can also not include the same surface finish layer. The metallization features 730 are embedded in a dielectric material 718, which can have any inorganic composition, for example, any of the inorganic compositions described above for the main structure. For embodiments including a surface finish material 731 , the metallized features 730 may be recessed below plane P2 .

[0073] Within the periphery of the bonding site structure 703, the IC die structures 701, 702 may also include topographic alignment features, such as substantially as described above for the main structure 200 (A). As shown, the IC die structures 701, 702 may have one or more grooves at the periphery of the bonding site structure 703. The IC die structures 701, 702 also include one or more hydrophobic features 704 adjacent to the bonding site structure 703. The features 704 may have any of the properties or characteristics discussed elsewhere herein for the features 204. Thus, the amphiphilic surface of the main structure 200A and the amphiphilic surface of the IC die structure 701 may be substantially the same (as shown). The IC die structure 702 may also be substantially the same except for the lack of the surface finishing layer material 731.

[0074] If Figure 7B As shown by the dashed lines in FIG. 7 , one or more hydrophobic features 704 substantially surround the perimeter of the bonding site structure 703. The feature 704 can be a single continuous material and / or structure having a hydrophobic surface. Alternatively, the feature 704 can include multiple discontinuous segments of hydrophobic material that outline the perimeter near two or more edges of the bonding site structure 703. Although Fig. 7A and Figure 7B An example is shown where two IC die structures 701 , 702 are placed adjacent to each other on one body structure 200A, but one or more IC die structures may be placed on a single body structure.

[0075] Return to Figure 1 , method 101 continues at block 140, where the droplet between the IC die structure and the main body structure is evaporated so that the metallization features of the IC die bonding site structure are in direct contact with the metallization features of the main body structure. The IC die structure may then be bonded to the main body structure according to any suitable (one or more) bonding techniques, such as a hybrid bonding technique. Figure 8 An exemplary hybrid bonded composite structure 800 is shown, wherein the IC die structures 701, 702 are now in contact with the main structure 200A along a bonding interface 850, which is represented by a thick dashed line. The bonding interface 850 includes a surface finish layer of metallization features on the IC die structure and / or on the main structure, which has now become the interface material. The lateral offset between the metallization features 230 and 730 is shown to indicate a certain non-zero misalignment that helps define the bonding interface 850.

[0076] As shown in the enlarged view of IC die structure 701, metallization feature 230 is coupled to the overlapping portions of corresponding ones of metallization features 730 through a bonding interface 850 including surface finish materials 231 and 731. For embodiments in which materials 231 and 731 have substantially the same composition, the chemical composition of the composite metallization feature can be substantially symmetric about bonding interface 850. For example, beyond thickness T1, the concentration of metal M or carbon C can decrease monotonically with increasing distance from bonding interface 850. Beyond thickness T2, the concentration function can also decrease monotonically with increasing distance from bonding interface 850.

[0077] The sum of thicknesses T1 and T2 may be, for example, no greater than 5 nm, and components of materials 231, 731 that are not originally present in metallization features 230 and 730 may diffuse into metallization features 230 and 730 to a limited distance, depending on thermal treatment and diffusivity parameters of the mixture. In some embodiments where both surface finish materials 231 and 731 include a Cu-Ni alloy, the Ni content peaks near the bonding interface 850 (e.g., within T1 and T2). The Ni content may decrease in either z-axis direction (i.e., toward either metallization feature 230 or 730) (e.g., to less than 1 wt.% at a distance no greater than 5 nm from the bonding interface 850). In other embodiments in which materials 231 and 731 both comprise organic materials, the C content peaks near the bonding interface 850 and decreases in either z-axis direction (i.e., toward either metallization feature 230 or 730) (e.g., or to less than 1 at. % at a distance no greater than 5 nm from the bonding interface 850).

[0078] As further shown in the enlarged view of IC die structure 702, metallization features 230 are coupled to overlapping portions of corresponding ones of metallization features 730 via a bonding interface 850 including finish layer material 231. The chemical composition of the composite metallization feature may then be asymmetric about bonding interface 850, with peak concentrations of components found only within thickness T1 of material 231 on the bulk structure side of bonding interface 850. The content of metal M or carbon C may again decrease monotonically with greater distance from the peak concentration.

[0079] The dielectric material of the main structure 200A is also in direct contact with the dielectric material of the IC die structures 701, 702. Individual ones of the hydrophobic features 204 are similarly located at the same location as corresponding ones of the features 704 on the IC die structures 701, 702. The hydrophobic features 204 may also be in direct contact with the hydrophobic features 704 along the bonding interface 850, although they may not diffuse or fuse with each other to form a unified composite structure even after the thermos and / or compression bonding process. The features 204 may also be physically separated from the features 704 across the bonding interface 850. When the IC die structures 701, 702 are bonded along the substantially planar bonding interface 850, the IC die backside surfaces may not be coplanar if there is a difference between the die structure thicknesses.

[0080] Back to Figure 1, method 101 ends at output 180, in which any process can be implemented to complete the package. For example, the fill material can be deposited on the bonded IC die structure and on the portion of the main structure that is not obscured by the (one or more) IC die structures. The fill material is advantageously a dielectric material (e.g., an inorganic dielectric material or an organic dielectric material), such as any of the dielectric materials previously described. In an exemplary embodiment, the fill material is deposited to a thickness at least equal to the thickness of the IC die structure. The fill material can be deposited by any technique known to be suitable for the composition and thickness of the selected material. In some embodiments, the dielectric fill material can be applied by a spin-on process or a spray process and then cured. In other embodiments, the dielectric fill material can be deposited by a chemical vapor deposition (CVD) process. In some other embodiments, the dielectric fill material can be deposited by a molding process. Depending on the deposition process, the dielectric fill material can be flat along the length that spans the IC die structure and extends beyond the edge of the IC die structure, or it is not flat. The fill material may be planarized, for example, using a chemical mechanical planarization (CMP) system or any other suitable grinder and / or polisher.

[0081] exist Fig. 9 In the example shown in , the composite structure 900 also includes a dielectric material 905 above the IC die structures 701, 702. The dielectric material 905 also substantially backfills the gap between the adjacent edge sidewalls of the IC die structures 701, 702. In some embodiments, the dielectric material 905 is one or more of any of the inorganic dielectric compositions previously described. In some other embodiments, the dielectric material 905 is one or more of any of the organic dielectric compositions previously described. As shown, the dielectric material 905 is substantially planarized across the IC die structures 701, 702. Such planarization can be attributed to the dielectric deposition process and / or the post-deposition polishing or CMP process.

[0082] Fig.101 is a cross-sectional view of a system 1000 including a heat sink 1004 and a body assembly 1011 assembled with a hybrid bonded composite structure 900, the hybrid bonded composite structure 900 also including an IC die structure and a body structure, at least one of which has a surface finish on a metallization feature at a bonding interface, for example according to one or more embodiments described herein. The system 1000 may include any number of composite structures 900 mounted to a body 1011 via interconnects 1009, which are optionally embedded in an underfill material 1012. For example, the body 1011 may be a cored or coreless package substrate, an interposer, or a board (e.g., a motherboard).

[0083] The system 1000 also includes a power supply 1056 coupled to one or more of the body 1011 (i.e., board, package substrate, or interposer), the composite structure 900, and / or other components of the system 1000. The power supply 1056 may include a battery, a voltage converter, a power supply circuit module, or the like. The microelectronic system 1000 also includes a thermal interface material (TIM) 1001 on the composite structure 900. The TIM 1001 may include any suitable thermal interface material. The system 1000 also includes an integrated heat sink (IHS) and / or cover 1002 in contact with the TIM 1001 and extending above the composite structure 900. The system 1000 also includes another TIM 1003 in contact with the top surface of the IHS 1002. The TIM 1003 may include any suitable thermal interface material and may have the same or different composition as the TIM 1001. The system 1000 includes a heat sink 1004 (eg, an exemplary heat sink or thermal solution) in contact with the TIM 1003. For example, the system 1000 may be further integrated into a computer (eg, a mobile device or a server).

[0084] Fig.11 An exemplary computer platform 1105 including a composite structure is shown, the composite structure including a bonded IC die having an amphiphilic surface structure close to a hybrid bonding interface, the amphiphilic surface structure indicating a drop-based fine alignment technique. For example, the platform 1105 can be a mobile computing platform and / or a data server machine. The server machine can be any commercial server, for example, including any number of high-performance computing platforms placed in a rack and networked together for electronic data processing. The platform 1105 can be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. The platform 1105 may include a chip-level or package-level integrated system 1110 and a battery 1115. In some examples, the disclosed system can be implemented in a deaggregated subsystem 1160.

[0085] Subsystem 1160 may include memory circuit modules and / or processor circuit modules 1150 (e.g., RAM, microprocessor, multi-core microprocessor, graphics processor, etc.), power management integrated circuit (PMIC) 1130, and radio frequency integrated circuit (RFIC) 1125 (e.g., including a broadband RF transmitter and / or receiver (TX / RX)). As shown, one or more IC dies, (e.g., memory circuit modules and / or processor circuit modules 1150) may be co-packaged and / or co-assembled within a composite structure that includes an IC die having an amphiphilic structure near a hybrid bonding interface, such as described herein.

[0086] In some embodiments, RFIC 1125 includes a digital baseband and an analog front-end module, which also includes a power amplifier on the transmit channel and a low noise amplifier on the receive channel. Functionally, PMIC 1130 can perform battery power regulation, DC to DC conversion, etc., and thus has an input coupled to battery 1115 and an output that provides current supply to other functional modules. Fig.11 As further shown in the , in an exemplary embodiment, RFIC 1125 has an output that is coupled to an antenna (not shown) to implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. Memory circuit module and / or processor circuit module 1150 can provide memory functionality, high-level control, data processing, and the like for subsystem 1160.

[0087] Fig.12 1 is a block diagram of a cryogenically cooled computing device 1200 according to some embodiments. For example, one or more components of the computing device 1200 may include any of the devices or structures discussed elsewhere herein. Fig.121200, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some of the components included in computing device 1200 may be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various of these components may be fabricated onto a single system-on-chip (SoC) die, or may be implemented with multiple chips or slices that are broken out and packaged together. Additionally, in various embodiments, computing device 1200 may not include Fig.12 1200, but the computing device 1200 may include an interface circuit module for coupling to one or more components. For example, the computing device 1200 may not include the display device 1203, but may include a display device interface circuit module (e.g., a connector and a driver circuit module) to which the display device 1203 can be coupled.

[0088] The computing device 1200 may include a processing device 1201 (e.g., one or more processing devices). As used herein, the term processing device or processor indicates a device that processes electronic data from registers and / or memories to transform the electronic data into other electronic data that can be stored in registers and / or memories. The processing device 1201 may include a memory 1221, a communication device 1222, a refrigeration / active cooling device 1223, a battery / power regulation device 1224, a logic 1225, an interconnect 1226, a thermal regulation device 1227, and a hardware security device 1228.

[0089] The processing device 1201 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices.

[0090] The processing device 1201 may include a memory 1202, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the processing 1201 shares a package with the memory 1202. The memory may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or a spin transfer torque magnetic random access memory (STT-M RAM).

[0091] The computing device 1200 may include a thermal conditioning / refrigeration device 1223. The thermal conditioning / refrigeration device 1223 may maintain the processing device 1201 (and / or other components of the computing device 1200) at a predetermined low temperature during operation. The predetermined low temperature may be any temperature discussed elsewhere herein.

[0092] In some embodiments, computing device 1200 may include a communication chip 1207 (e.g., one or more communication chips). For example, communication chip 1207 may be configured to manage wireless communications for transmitting data to and from computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which may communicate data using modulated electromagnetic radiation through a non-solid medium.

[0093] The communication chip 1207 can implement any of a variety of wireless standards or protocols, including but not limited to the Institute of Electrical and Electronics Engineers (IEEE) standards, the Long Term Evolution (LTE) project together with any amendments, updates and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.), the IEEE standards include: Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment). Broadband wireless access (BWA) networks compatible with IEEE802.16 are generally referred to as WiMAX networks, which is an abbreviation for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass the conformance and interoperability tests of the IEEE 802.16 standard. The communication chip 1207 can operate according to the Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA) or LTE network. The communication chip 1207 may operate in accordance with GSM Enhanced Data Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1207 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and higher. In other embodiments, the communication chip 1207 may operate in accordance with other wireless protocols. The computing device 1200 may include an antenna 1213 to facilitate wireless communications and / or to receive other wireless communications (e.g., AM or FM radio transmissions).

[0094] In some embodiments, the communication chip 1207 can manage wired communications, such as electrical communication protocols, optical communication protocols, or any other suitable communication protocols (e.g., Ethernet). As described above, the communication chip 1207 may include multiple communication chips. For example, the first communication chip 1207 may be dedicated to wireless communications over shorter distances, such as Wi-Fi or Bluetooth, and the second communication chip 1207 may be dedicated to wireless communications over longer distances, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or other wireless communications over longer distances. In some embodiments, the first communication chip 1207 may be dedicated to wireless communications, and the second communication chip 1207 may be dedicated to wired communications.

[0095] Computing device 1200 may include battery / power circuit module 1208. Battery / power circuit module 1208 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit modules for coupling components of computing device 1200 to an energy source separate from computing device 1200 (e.g., an AC line power device).

[0096] Computing device 1200 may include a display device 1203 (or a corresponding interface circuit module, as discussed above). For example, display device 1203 may include any visual indicator, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0097] Computing device 1200 may include audio output device 1204 (or corresponding interface circuit modules, as discussed above). For example, audio output device 1204 may include any device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0098] The computing device 1200 may include an audio input device 1210 (or a corresponding interface circuit module, as discussed above). The audio input device 1210 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0099] The computing device 1200 may include a global positioning system (GPS) device 1209 (or a corresponding interface circuit module, as discussed above). As is known in the art, the GPS device 1209 may communicate with a satellite-based system and may receive the location of the computing device 1200.

[0100] Computing device 1200 may include another output device 1205 (or corresponding interface circuit module, as discussed above). Examples include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0101] The computing device 1200 may include another input device 1211 (or a corresponding interface circuit module, as discussed above). Examples may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (e.g., a mouse, a stylus, a touchpad), a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0102] The computing device 1200 may include a security interface device 1212. The security interface device 1212 may include any device that provides security measures for the computing device 1200, such as intrusion detection, biometric authentication, security encoding or decoding, management access lists, malware detection, or spyware detection.

[0103] Computing device 1200 or a subset of its components may have any suitable form factor, such as a handheld or mobile computing device (e.g., a cellular telephone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0104] Although certain features set forth herein have been described with reference to various implementations, this description is not intended to be understood in a limiting sense. Therefore, various modifications and other implementations of the implementations described herein are considered to be within the spirit and scope of the present disclosure, and the various modifications and other implementations are obvious to those skilled in the art to which the present disclosure belongs.

[0105] In a first example, a device includes: a body structure including a plurality of metallization levels, an uppermost metallization level of the metallization levels including one or more first metal features, the first metal features predominantly including Cu. The device includes: an integrated circuit (IC) die structure coupled to the body structure, the IC die structure including a plurality of metallization levels, an uppermost metallization level of the metallization levels including one or more second metal features, the second metal features predominantly including Cu, wherein the second metal features are in contact with corresponding first metal features of the first metal features along a bonding interface, the bonding interface including at least one of Ni, Mn, Pd, Ti, Pt, Ru, Si, or C.

[0106] In a second example, for any of the first examples, the bonding interface predominantly includes one of: Pd; Ti; Pt; Ru; predominantly Si and C; or an alloy of Ni.

[0107] In a third example, for any of the second examples, the bonding interface has a thickness no greater than 5 nm, and wherein the concentration of the Ni, Mn, Pd, Ti, Pt, Ru, Si or C within the first metal feature outside the bonding interface or within the second metal feature does not exceed 1 wt.%.

[0108] In a fourth example, for any of the third examples, the bonding interface has a thickness of no greater than 2 nm.

[0109] In a fifth example, for any of the second examples, the bonding interface includes Cu and Ni.

[0110] In a sixth example, for any of the fifth examples, the bonding interface includes at least 40 wt. % Ni.

[0111] In a seventh example, for any of the fifth examples, the bonding interface includes Cu, Ni, and Mn.

[0112] In an eighth example, for any of the seventh examples, the bonding interface includes at least 10 wt. % Mn.

[0113] In a ninth example, for any of the second examples, the bonding interface predominantly includes one of Pd, Pt, or Ru.

[0114] In a tenth example, for any of the second examples, the bonding interface predominantly includes Si and C.

[0115] In an eleventh example, a device includes: a substrate structure, the substrate structure including one or more first metal features within a first region of the substrate structure, the substrate structure also including an inorganic dielectric material, wherein the first region is adjacent to a second region of the substrate. The device includes: an integrated circuit (IC) die structure coupled to the substrate structure, wherein the IC die structure has a third region and an adjacent fourth region, the third region including an inorganic dielectric material and one or more second metal features. The second metal feature contacts at least a portion of a corresponding first metal feature of the first metal feature along a plane of a bonding interface, the bonding interface including Ni, Mn, Pd, Ti, Pt, Ru, Si, or C. At least one of the second region or the fourth region includes an organic material having a composition of at least 10 atomic percent carbon or at least 10 atomic percent fluorine.

[0116] In a twelfth example, for any of the eleventh examples, the first metal feature and the second metal feature include a fill metal comprising Cu and a barrier material between the fill metal and the inorganic dielectric material; and, within each of the first metal feature and the second metal feature, the concentration of Ni, Mn, Pd, Ti, Pt, Ru, Si or C decreases as the distance from the bonding interface increases.

[0117] In a thirteenth example, for any of the twelfth examples, the concentration of the Ni, Mn, Pd, Ti, Pt, Ru, Si or C in the first metal feature does not exceed 1 wt.% at a distance of 5 nm from the corresponding second metal feature in the second metal feature, and wherein the concentration of the Ni, Mn, Pd, Ti, Pt, Ru, Si or C in the second metal feature does not exceed 1 wt.% at a distance of 5 nm from the corresponding first metal feature in the first metal feature.

[0118] In a fourteenth example, for any of the eleventh to thirteenth examples, the inorganic dielectric material in the first region is substantially coplanar with the bonding interface, and wherein the inorganic dielectric material in the third region is substantially coplanar with the bonding interface.

[0119] In a fifteenth example, for any of the eleventh to fourteenth examples, the apparatus includes a body component interconnected to the substrate structure via solder features, the body component including a power supply path coupling the substrate structure to a power supply.

[0120] In a sixteenth example, a method includes receiving a first structure in an integrated circuit (IC) die structure or a package substrate structure, the first structure including a first region having a first metallization feature within a first trench in a dielectric material. The method includes recessing the first metallization feature below a plane of the dielectric material. The method includes forming a surface finish layer including Ni, Mn, Pd, Ti, Pt, Ru, Si, or C over the first metallization feature. The method includes bonding the first structure in the IC die structure or the package substrate structure to a second structure in the IC die structure or the package substrate structure, wherein the bonding includes coupling the first metallization feature to a corresponding second metallization feature through the surface finish layer.

[0121] In a seventeenth example, for any of the sixteenth examples, forming the surface finish layer includes: depositing the surface finish layer over the first metallization features and the dielectric material; and planarizing the surface finish layer to expose the dielectric material.

[0122] In an eighteenth example, for any of the sixteenth to seventeenth examples, the first and second metallization features predominantly include Cu, and wherein recessing the first metallization features includes atomic layer etching or wet chemical etching.

[0123] In a nineteenth example, for any of the sixteenth to eighteenth examples, forming the surface finishing layer includes: depositing a Ni—Cu alloy, or depositing at least one of Pd, Pt, or Ru.

[0124] In the twentieth example, for any of the sixteenth to nineteenth examples, the first structure in the integrated circuit (IC) die structure or the packaging substrate structure is aligned with the second structure in the integrated circuit (IC) die structure or the packaging substrate structure based on a wettability comparison between the first region and the second region.

[0125] In a twenty-first example, a device includes: a body structure including a plurality of metallization levels, a topmost metallization level in the metallization levels including one or more first metal features, the first metal features predominantly including Cu. The device includes: an integrated circuit (IC) die structure coupled to the body structure, the IC die structure including a plurality of metallization levels, a topmost metallization level in the metallization levels including one or more second metal features, the second metal features predominantly including Cu, wherein the second metal features are in direct contact with corresponding first metal features of the first metal features along a bonding interface, the bonding interface including at least one of Ni, Mn, Pd, Ti, Pt, Ru, Si, or C.

[0126] In a twenty-second example, for any of the twenty-first examples, the bonding interface predominantly includes one of: Pd; Ti; Pt; Ru; predominantly Si and C; or an alloy of Ni.

[0127] In the twenty-third example, for any of the twenty-second examples, the bonding interface has a thickness of no more than 5 nm, and wherein the concentration of the Ni, Mn, Pd, Ti, Pt, Ru, Si or C within the first metal feature outside the bonding interface or within the second metal feature does not exceed 1 wt.%.

[0128] In a twenty-fourth example, for any of the twenty-third examples, the bonding interface has a thickness of no greater than 2 nm.

[0129] In a twenty-fifth example, for any of the twenty-second examples, the bonding interface includes Cu and Ni.

[0130] In a twenty-sixth example, for any of the twenty-fifth examples, the bonding interface includes at least 40 wt. % Ni.

[0131] In a twenty-seventh example, for any of the twenty-fifth examples, the bonding interface includes Cu, Ni, and Mn.

[0132] In a twenty-eighth example, for any of the twenty-seventh examples, the bonding interface includes at least 10 wt. % Mn.

[0133] In a twenty-ninth example, for any of the twenty-second examples, the bonding interface predominantly includes one of Pd, Pt, or Ru.

[0134] In a thirtieth example, for any of the twenty-second examples, the bonding interface predominantly includes Si and C.

[0135] In a thirty-first example, a device includes: a substrate structure, the substrate structure including one or more first metal features within a first region of the substrate structure, the substrate structure also including an inorganic dielectric material, wherein the first region is adjacent to a second region of the substrate. The device includes: an integrated circuit (IC) die structure coupled to the substrate structure, wherein the IC die structure has a third region and an adjacent fourth region, the third region including an inorganic dielectric material and one or more second metal features. The second metal feature is in direct contact with at least a portion of a corresponding first metal feature in the first metal feature along a plane of a bonding interface, the bonding interface including Ni, Mn, Pd, Ti, Pt, Ru, Si, or C. At least one of the second region or the fourth region includes an organic material having a composition of at least 10 atomic percent carbon or at least 10 atomic percent fluorine.

[0136] In the thirty-second example, for any of the thirty-first examples, the first metal feature and the second metal feature include a filler metal comprising Cu and a barrier material between the filler metal and the inorganic dielectric material; and, within each of the first metal feature and the second metal feature, the concentration of Ni, Mn, Pd, Ti, Pt, Ru, Si or C decreases as the distance from the bonding interface increases.

[0137] In the thirty-third example, for any of the thirty-second examples, the concentration of the Ni, Mn, Pd, Ti, Pt, Ru, Si or C in the first metal feature does not exceed 1wt.% at a distance of 5nm from the corresponding second metal feature in the second metal feature, and wherein the concentration of the Ni, Mn, Pd, Ti, Pt, Ru, Si or C in the second metal feature does not exceed 1wt.% at a distance of 5nm from the corresponding first metal feature in the first metal feature.

[0138] In a thirty-fourth example, for any of the thirty-first to thirty-third examples, the inorganic dielectric material in the first region is substantially coplanar with the bonding interface, and wherein the inorganic dielectric material in the third region is substantially coplanar with the bonding interface.

[0139] In a thirty-fifth example, for any of the thirty-first to thirty-fourth examples, the device includes a main body component interconnected to the substrate structure via solder features, the main body component including a power supply path coupling the substrate structure to a power supply device.

[0140] It will be appreciated that the principles of the present disclosure are not limited to the embodiments described herein, but may be implemented through modification and alteration without departing from the scope of the appended claims. The above embodiments may include: employing only a subset of such features, employing a different order of such features, employing a different combination of such features, and / or employing additional features in addition to those features explicitly listed. Therefore, the scope of the embodiments should be determined by reference to the appended claims and the full scope of equivalents to which such claims are entitled.

Claims

1. A device comprising: a body structure comprising a plurality of metallization levels, an uppermost one of the metallization levels comprising one or more first metal features, the first metal features predominantly comprising Cu; An integrated circuit (IC) die structure coupled to the main structure, the IC die structure comprising a plurality of metallization levels, an uppermost one of the metallization levels comprising one or more second metal features, the second metal features predominantly comprising Cu, wherein the second metal features are in direct contact with corresponding first metal features of the first metal features along a bonding interface comprising at least one of Ni, Mn, Pd, Ti, Pt, Ru, Si or C.

2. The device according to claim 1, wherein: The bonding interface predominantly comprises one of the following: Pd; Ti; Pt; Ru; predominantly Si and C; or an alloy of Ni.

3. The device according to claim 2, wherein: The bonding interface has a thickness no greater than 5 nm, and wherein a concentration of the Ni, Mn, Pd, Ti, Pt, Ru, Si or C within the first metal feature or within the second metal feature outside the bonding interface does not exceed 1 wt.%.

4. The device according to claim 3, wherein: The bonding interface has a thickness of no greater than 2 nm.

5. The device according to any one of claims 2 to 4, wherein: The bonding interface includes Cu and Ni.

6. The device according to claim 5, wherein: The bonding interface includes at least 40 wt. % Ni.

7. The device according to claim 5, wherein: The bonding interface includes Cu, Ni and Mn.

8. The device according to claim 7, wherein: The bonding interface includes at least 10 wt. % Mn.

9. The device according to any one of claims 2 to 4, wherein: The bonding interface predominantly includes one of Pd, Pt or Ru.

10. The device according to any one of claims 2 to 4, wherein: The bonding interface predominantly includes Si and C.

11. The apparatus of claim 1, wherein: the one or more first metal features are within a first region of the body structure, the body structure further comprising an inorganic dielectric material, wherein the first region is adjacent to a second region of the body structure; The IC die structure has a third region and an adjacent fourth region, the third region comprising an inorganic dielectric material and the one or more second metal features, wherein: At least one of the second region or the fourth region includes an organic material having a composition of at least 10 atomic percent of carbon or at least 10 atomic percent of fluorine.

12. The apparatus of claim 11, wherein: The first metal feature and the second metal feature include a fill metal including Cu and a barrier material between the fill metal and the inorganic dielectric material; and In each of the first metal feature and the second metal feature, a concentration of the Ni, Mn, Pd, Ti, Pt, Ru, Si, or C decreases with increasing distance from the bonding interface.

13. The device according to claim 12, wherein: The concentration of the Ni, Mn, Pd, Ti, Pt, Ru, Si or C in the first metal feature does not exceed 1 wt.% at a distance of 5 nm from the corresponding second metal feature in the second metal feature, and wherein the concentration of the Ni, Mn, Pd, Ti, Pt, Ru, Si or C in the second metal feature does not exceed 1 wt.% at a distance of 5 nm from the corresponding first metal feature in the first metal feature.

14. The device according to any one of claims 11 to 13, wherein: The inorganic dielectric material within the first region is substantially coplanar with the bonding interface, and wherein the inorganic dielectric material within the third region is substantially coplanar with the bonding interface.

15. The apparatus of any one of claims 11-13, further comprising a power supply path coupling the body structure to a power supply.

16. A method comprising: Receiving a first structure in an integrated circuit (IC) die structure or a package substrate structure, the first structure comprising a first region having a first metallization feature within a first trench in a dielectric material; recessing the first metallization feature below the plane of the dielectric material; forming a surface finish layer comprising Ni, Mn, Pd, Ti, Pt, Ru, Si or C over the first metallization feature; as well as The first structure of the IC die structure or the package substrate structure is bonded to a second structure of the IC die structure or the package substrate structure, wherein the bonding includes coupling the first metallization feature to a corresponding second metallization feature through the surface finish layer.

17. The method according to claim 16, wherein: forming the surface finish comprises depositing the surface finish over the first metallization feature and the dielectric material; and The surface finish is planarized to expose the dielectric material.

18. The method according to claim 16, wherein: The first and second metallization features predominantly comprise Cu, and wherein recessing the first metallization features comprises atomic layer etching or wet chemical etching.

19. The method according to claim 16, wherein: Forming the surface finishing layer includes: depositing a Ni-Cu alloy, or depositing at least one of Pd, Pt or Ru.

20. The method of claim 16, further comprising: The first structure in the integrated circuit (IC) die structure or the package substrate structure is aligned with the second structure in the integrated circuit (IC) die structure or the package substrate structure based on a wettability comparison between the first region and the second region.

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