Method for detecting through hole etching defect of 3D NAND chip and 3D NAND chip

Abstract

The invention relates to a method for detecting through hole dry etching defects of a 3D NAND chip and the 3D NAND chip, the 3D NAND chip comprises a storage array area, a peripheral area located below the storage array area and a plurality of through holes subjected to etching and process treatment, the through holes penetrate through the storage array area and the peripheral area, and the through holes penetrate through the storage array area and the peripheral area. The method comprises the steps that a chessboard pattern formed by a plurality of conductive parts and a plurality of insulating parts in a periodic alternating mode is generated in a peripheral area, one part of a plurality of through holes subjected to etching and process treatment makes contact with the conductive parts of the peripheral area, and the other part of the through holes make contact with the insulating parts of the peripheral area; and determining the through hole etching defect of the 3D NAND chip by detecting the through hole etching defect on the peripheral area. According to the invention, simultaneous on-line detection of insufficient etching of the through hole on a single wafer and short circuit between floating gates can be realized, the detection time and the detection period are greatly shortened, and the consumption of a detection machine and materials can be saved.

Description

Technical Field

[0001] The present invention relates to semiconductor manufacturing technology, and in particular to a method for detecting through-hole etching defects of a 3D NAND chip, a 3D NAND chip, and a 3D NAND manufacturing system. Background Art

[0002] 3D NAND chips typically include memory cells of multiple floating gate transistors. The memory cells of current 3D NAND chips may include multiple NAND memory structures arranged in three dimensions around a central cell through hole. The floating gate is typically composed of a conductive material that acts as a charge storage element for electric charge. Generally, inline detection is performed on the wafer after the 3D NAND chip process is completed, and the inline detection data is obtained by monitoring the monitoring to achieve monitoring of the 3D NAND process.

[0003] In the manufacturing process of 3D NAND chips, a large number of cell through holes are arranged, and conductive channels are formed by etching the cell through holes and performing process treatment. Therefore, problems such as insufficient etching of the cell through holes and short circuits between adjacent floating gates usually occur, which brings great challenges to the online detection of 3D NAND chips.

[0004] Therefore, the prior art requires a solution that can simultaneously and effectively detect related defects caused by through-hole etching inside a 3D NAND chip.

[0005] The foregoing content is only intended to help understand the background of the embodiments of the present invention, and is not intended to mean that the embodiments of the present invention fall within the scope of the relevant prior art known to those skilled in the art. Summary of the invention

[0006] The present invention relates to a method for detecting through-hole etching defects of 3D NAND chips, a 3D NAND chip and a 3D NAND manufacturing system. The solution of the present invention can effectively solve the problems in the prior art that it is difficult to simultaneously detect through-hole etching defects of 3D NAND chips and the detection is time-consuming and labor-intensive.

[0007] The first aspect of the present invention provides a method for detecting through-hole etching defects of a 3D NAND chip, wherein the 3D NAND chip includes a storage array area, a peripheral area located below the storage array area, and a plurality of through-holes after etching and process treatment, wherein the plurality of through-holes pass through the storage array area and the peripheral area; the method includes: generating a checkerboard pattern formed by a plurality of conductive parts and a plurality of insulating parts periodically alternating in the peripheral area, wherein a portion of the plurality of through-holes after etching and process treatment is in contact with the conductive part of the peripheral area, and another portion is in contact with the insulating part of the peripheral area; and determining the through-hole etching defects of the 3D NAND chip by detecting through-hole etching defects on the peripheral area. The 3D NAND chip is a test chip, in which the plurality of through-holes after etching and process treatment do not form storage units in the test chip; and determining the through-hole etching defects of the 3D NAND chip by detecting through-hole etching defects of the test chip. Optionally, the plurality of through-holes after etching and process treatment form storage units in the 3D NAND chip.

[0008] The second aspect of the present invention provides a 3D NAND chip, the 3D NAND chip comprising: a storage array area, a peripheral area below the storage array area, and a plurality of through holes after etching and process treatment, the plurality of through holes passing through the storage array area and the peripheral area; wherein a checkerboard pattern formed by a plurality of conductive parts and a plurality of insulating parts periodically alternating is generated in the peripheral area, and a portion of the plurality of through holes after etching and process treatment is in contact with the conductive part of the peripheral area, and another portion is in contact with the insulating part of the peripheral area. wherein the through hole etching defect of the 3D NAND chip is determined by detecting the through hole etching defect of the peripheral area. wherein the 3D NAND chip is a test chip, in which the plurality of through holes after etching and process treatment do not form a storage unit in the test chip. wherein the through hole etching defect of the 3D NAND chip is determined by detecting the through hole etching defect of the test chip. optionally, wherein the plurality of through holes after etching and process treatment form a storage unit in the 3D NAND chip.

[0009] A third aspect of the present invention provides a 3D NAND chip manufacturing system, the 3D NAND chip manufacturing system includes the above-mentioned method for detecting through-hole etching defects of 3D NAND chips, or forms the above-mentioned 3D NAND chips.

[0010] According to the solution for detecting through-hole etching defects of 3D NAND chips of the present invention, it is possible to realize simultaneous online detection of insufficient through-hole etching and short circuits between floating gates on a single wafer, greatly shortening the detection time and detection cycle, and saving the consumption of detection equipment and materials.

[0011] The advantages of the embodiments of the present invention are not limited to the above advantages. Through the following description, those skilled in the art can clearly understand other advantages not described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of a FG-FG short circuit defect according to an embodiment of the present invention is shown.

[0013] Figure 2 A flow chart of a method for detecting via etching defects of a 3D NAND chip according to an embodiment of the present invention is shown.

[0014] Figure 3 A customized chip chessboard pattern according to an embodiment of the present invention is shown.

[0015] Figure 4 A schematic diagram of an existing 3D NAND chip manufacturing process according to an embodiment of the present invention is shown.

[0016] Figure 5 A schematic diagram of a 3D NAND test chip manufacturing process according to an embodiment of the present invention is shown.

[0017] FIG. 6( a ), FIG. 6( b ) and FIG. 6( c ) are schematic diagrams showing HEBI detection without via etching defects according to an embodiment of the present invention.

[0018] FIG. 7( a ) and FIG. 7( b ) are schematic diagrams showing a defect of insufficient through-hole etching in a HEBI test chip according to an embodiment of the present invention.

[0019] 8( a ) and 8 ( b ) are schematic diagrams showing a defect of FG-FG (between floating gates) short circuit in a HEBI test chip according to an embodiment of the present invention.

[0020] Fig. 9 A display interface diagram showing the result of HEBI detecting through-hole etching defects according to an embodiment of the present invention is shown.

[0021] The numbers are not drawn to scale. Wherever possible, the same reference numbers will be used throughout the drawings and accompanying written description to refer to the same or like parts. DETAILED DESCRIPTION

[0022] Although the following detailed description contains many specific details for the purposes of illustration, those of ordinary skill in the art will appreciate that many variations and modifications to the following details may be made and are considered to be included herein.

[0023] Therefore, the following embodiments are set forth without any loss of generality of any of the claims and without limiting any of the claims. It should also be understood that the terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. Unless otherwise defined, any technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0024] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers.

[0025] It will be understood that when a component is referred to as being "connected to" or "coupled to" another component, it can be directly connected to or coupled to the other component, or intermediate components may exist. Conversely, when a component is referred to as being "directly connected to" or "directly coupled to" another component, there are no intermediate components.

[0026] As used herein, singular forms shall include plural forms as well, unless the context clearly indicates otherwise.

[0027] It should be further understood that the terms "including" or "having", when used in this specification, specify the existence of the stated features, numbers, steps, operations, components, elements, or a combination thereof, but they do not exclude the existence or addition of one or more other features, numbers, steps, operations, components, elements, or a combination thereof.

[0028] Hereinafter, the embodiments disclosed in this specification are described with reference to the accompanying drawings, in which the same reference numerals are given to refer to the same or similar components and redundant descriptions thereof are omitted.

[0029] In the manufacturing system of 3D NAND chips, multiple through holes (pillars) are usually set on each chip (die) to form a conductive channel. The main challenge of through hole etching research and development is to improve the through holes that are under-etched (under etched), while reducing the defects of adjacent through hole-through hole short circuits (usually short circuits between floating gates (FG), or FG-FG short circuits). Such challenges lie not only in the research and development of NAND processes, but also in the development of methods for rapid defect detection. The development of defect detection methods themselves should be as important as the development of processes, because: fast online detection can increase the speed of chip development to obtain information; reliable online detection can reduce the risk of production line deviation and abnormalities. However, in the 3D NAND manufacturing system, due to the high aspect ratio of the through holes in the 3D NAND chip structure, the existing traditional online detection methods are not fast or reliable, especially in the chip development stage. This situation is more obvious. To this end, the present invention proposes a method for online detection of through-hole etching defects, which designs a source electrode with a checkerboard pattern in the peripheral area and a memory cell process flow that skips the chip, and uses the HMI electron beam inspection HEBI (Hermes Microvision Inc. E-Beam Inspection) method to quickly and reliably detect through-hole etching defects.

[0030] The existing FG-FG short circuit defects are usually detected by the morphology electron beam inspection method (GEBI, Geomorphology E-Beam Inspection), that is, a detection mode of detecting FG-FG (floating gate to floating gate) short circuit defects (FG-FG short) by comparing the morphology of different areas on the chip surface. After the through-hole etching and CGR (control gate recess) process, the EB (etch back) process flow is carried out, that is, the oxide-polysilicon layer stack structure is periodically etched to stop at certain "weak" WL layers (weak wordline, word line) (usually less than 10 WL measurements), and then GEBI is used to detect FG-FG short circuit defects on each "weak" WL layer. However, in the research and development of the through-hole etching process, it is a challenge to first determine the "weak" WL list, because each through-hole etching process recipe (wherein the process recipe refers to the process recipe generated according to the product, equipment and process steps in the process) has different "weak" WLs. Weak WL refers to WL that will have FG-FG short circuit defects. Therefore, for new process recipes, the above method will fail to measure because it is impossible to accurately locate the number of truly "weak" WL layers, and the NAND performance reflected by the detected defects will be greatly underestimated.

[0031] In the 3D NAND manufacturing process, after the through hole (pillar) is formed, the chemical solvent in the wet etching will etch the polysilicon layer laterally along the through hole (pillar), and the remaining polysilicon will be the control gate (CG). The ring etched out will form the floating gate (FG) later. If the FGs of two adjacent through holes (pillars) are connected together (that is, there is no remaining polysilicon as CG), it will cause a short circuit (FG-FG short) defect between the floating gate and the floating gate.

[0032] Figure 1 A schematic diagram of a FG-FG (between adjacent floating gates) short circuit defect according to an embodiment of the present invention is shown.

[0033] exist Figure 1 In the figure, the left box indicates two through holes (pillars) are etched by dry etching, and the right box indicates CG (i.e., CGR) is etched laterally by wet etching on the basis of the original through hole. The ring position indicates FG. If two adjacent FGs touch each other and a short circuit occurs, an FG-FG short circuit is generated.

[0034] In the 3D NAND manufacturing process, insufficient through-hole etching (Pillar UE) is another typical failure mode in 3D NAND storage arrays, which can be detected by HEBI (HMI E-Beam Inspection). The HEBI detection method is to compare the relative voltage intensity (VC) of different areas on the chip surface, and then use it to detect whether the through-hole / channel (pillar / channel) is connected to the source, so as to detect the open circuit defect mode caused by insufficient etching (ie: Under etch). However, in the existing HEBI detection of 3D NAND, it is necessary to go through the process of forming a complete storage unit (cell) and a through-hole conductive channel in the chip (die), which usually takes several weeks to detect. In the HEBI online detection, such a long detection cycle time greatly delays the R&D cycle of through-hole etching.

[0035] According to one or more embodiments of the present invention, the present invention adopts the HMI (Hermes Microvision Inc.) EBI (HEBI) detection method. Other EBI detection methods can also be used in the process of realizing through-hole etching defects. The image of the chip surface is displayed by testing the contrast of the voltage intensity on the chip surface, so as to judge the location and defect rate of the defect according to the brightness or darkness of the image.

[0036] When a through-hole under-etching defect occurs, that is, the through-hole is not etched to the bottom source, but to the middle oxide layer, the HEBI detector pulls out / pushes electrons (conductive / insulating) through the contact area, thereby testing the voltage intensity comparison on the chip surface. Through the display interface of the HEBI detector, it can be observed that the through-hole should be displayed as bright (bright color), but it is displayed as dark (dark color).

[0037] In the HEBI detection method, the voltage contrast (VC) mode can detect the electrical connection status of the contacts, which is good at finding open contacts. HEBI pulls out / pushes electrons (conductive / insulating) in the contact area, accumulates voltage during charging, and the voltage change further produces a contrast in voltage intensity. In the GEBI detection method, the difference in electronic detection depends on the morphology of the chip surface.

[0038] The current problems with GEBI detection include: (1) GEBI can only detect a limited number of "weak" WLs by etching the WL layer, and because the WL caused by the FG-FG short defect will vary with different through-hole etching process recipes, there is no good way to identify the "weak" WL layer in advance in the early stage of developing new through-hole etching process recipes; (2) GEBI needs to stop at certain specific WLs by performing EB on the wafer, and then scan each layer of WL one by one. Because the EB process is destructive, it requires expensive wafer processing and consumption costs, and also brings heavy GEBI working time and a long detection cycle; (3) The EB process itself requires a lot of research and development before it can start working.

[0039] The existing problems of HEBI detection include: (1) the detection cycle is long (usually more than 3 weeks); (2) the complex process of forming the memory cell will lead to deviations in the detection results.

[0040] In view of the two existing detection methods of FG-FG short circuit and pillar UE, the existing technology usually requires these two detection modes to evaluate the process recipe performance of the same through-hole etching on two separate wafers, and the two detection results are completed 2-3 weeks apart, which is not ideal in terms of actual application wafer cost and detection cycle.

[0041] Therefore, the present invention provides a method for online detection of through-hole UE and FG-FG short circuit on a single wafer simultaneously using a customized source patterning and a process flow for skipping memory cell formation. The customized source pattern (or source patterning) is designed in the peripheral area of ​​the chip to ensure sufficient sample volume of through-holes and flexibility of production line sampling.

[0042] Figure 2 A flow chart of a method for detecting through-hole etching defects of a 3D NAND chip (die) according to an embodiment of the present invention is shown.

[0043] like Figure 2 As shown, first at S201, a 3D NAND chip is customized. The 3D NAND chip includes a storage array area, a peripheral area below the storage array, and a plurality of through holes after etching and process treatment, and the plurality of through holes pass through the storage array area and the peripheral area. At S202, the peripheral area for the 3D NAND chip is subjected to a graphical process, that is, a checkerboard pattern formed by periodically alternating multiple conductive parts and multiple insulating parts is generated in the peripheral area, and a portion of the multiple through holes after etching and process treatment is in contact with the conductive part of the peripheral area, and another portion is in contact with the insulating part of the peripheral area. At S203, the through-hole etching defects of the 3D NAND are detected by the HEBI detection method. After the through-hole is etched and processed to form a conductive channel, it is detected by the HEBI detector. That is, multiple through holes after etching and process treatment form multiple conductive channels in the test chip. If the through holes are in contact with the conductive part at the bottom of the peripheral area, the conductive channels are detected as conductive (displayed as bright colors) in the HEBI detector. If the through holes are in contact with the insulating part at the bottom of the peripheral area, the conductive channels are detected as non-conductive (displayed as dark colors) in the HEBI detector. The HEBI detector detects the through hole etching defects of the test chip by detecting the changes in the relative voltage intensity of multiple through holes on the surface of the test chip.

[0044] According to one or more embodiments of the present invention, the 3D NAND chip is a test chip, in which a plurality of through holes after etching and process treatment do not form storage units in the test chip. The through hole etching defects of the 3D NAND chip are determined by detecting the through hole etching defects of the test chip. By obtaining the through hole etching defects in the test chip, the through hole etching defects in the 3D NAND chip can be determined, because in the mass production of 3D NAND, the etching defects formed by the same through hole etching process recipe and the through hole etching defects of the test chip are the same, except that in the test chip, no storage units are formed. Optionally, a plurality of through holes after etching and process treatment form storage units in the 3D NAND chip. The detection method of the present invention can directly detect the through hole etching defects of the 3D NAND including the above-mentioned customized checkerboard pattern.

[0045] According to one or more embodiments of the present invention, the customized source patterning is formed in the peripheral area of ​​the chip, which is easily observed by XSEM / planar FIB (focused ion beam). In addition, during the detection process, this customized source checkerboard pattern in the peripheral area of ​​the test chip can be easily detected by reverse engineering technology FIB / XSEM / TEM (transmission electron microscope). In addition, since the storage cell formation process is skipped when customizing the 3D NAND chip, FIB / XSEM / TEM can easily identify the unique customized structure formed by skipping the cell manufacturing process.

[0046] Figure 3 A customized chip chessboard pattern according to an embodiment of the present invention is shown.

[0047] like Figure 3 As shown, the chip (die) on the left includes patterns of the storage array area and the peripheral area. In the storage array area of ​​a normal chip, the pattern including the through hole and the source electrode is enlarged as shown in the upper right figure. According to an embodiment of the present invention, a customized chessboard pattern is used in the peripheral area of ​​the chip, and the chessboard pattern includes Figure 3 The oxide insulating portion is shown as a circle in the figure. The customized checkerboard pattern in the peripheral area creates a periodic alternation of conductive-insulating portions for the vias to connect downward (contact each other), where the vias are spaced equally from each other. After the vias are etched, some of the vias fall on the normal conductive source (i.e., polysilicon poly and metal), and others are designed to fall on the insulator (i.e., Figure 3 After the through-hole patterning, the through-holes in the wafer are processed by a conductive channel process, and then the test chip is sent to the HEBI detector, and the HEBI detection method is used to test the FG-FG short circuit defects and insufficient through-hole etching defects in the chip.

[0048] Figure 4 A schematic diagram of an existing 3D NAND chip manufacturing process according to an embodiment of the present invention is shown.

[0049] Depend on Figure 4 As shown, in Figure 4 In (a), the through hole is etched downward and vertically passes through the multi-layer thin film stack structure, wherein the multi-layer thin film stack structure includes, from top to bottom, a silicon nitride layer, a selective gate-drain layer, a multi-layer polysilicon layer / oxide layer, a selective gate-source layer, an oxide layer, a source polysilicon / tungsten silicide layer and an oxide layer, wherein the polysilicon layer and the tungsten silicide layer constitute the source in the chip. Figure 3 The image on the upper right shows a via that lands on the source level. Figure 4In (b), the multi-layer polysilicon / oxide layer of the chip is subjected to CGR, that is, the polysilicon layer is eaten laterally by wet etching to form reserved positions for CG (control gate) and FG (floating gate), and then an insulating layer is deposited on the side wall. Figure 4 In (c), a storage cell is formed or generated in the 3D NAND chip. The process of forming the storage cell mainly involves making the storage cell, including making a complete floating gate FG. Figure 4 In (d), the through hole is processed to form a complete conductive channel. Then the chip is sent to the HEBI detector for testing to test the through hole etching defects of the 3D NAND chip. Figure 4 As can be seen from (d), the chip sent to HEBI for testing includes a complex conductive channel process for forming through-holes: a layer of oxide is formed on the sidewall of the through-hole by chemical vapor deposition (CVD) as a tunneling layer (tunneling oxide layer), and then a layer of polysilicon conductive layer is formed by diffusion as a conductive channel. After that, the inside of the through-hole is filled with insulating oxide by chemical vapor deposition, and finally a conductive plug is formed on the top for subsequent connection to the bit line to form a conductive loop. Figure 4 As can be seen from (d), it is very time-consuming and labor-intensive to perform through-hole etching defect detection on conductive channels.

[0050] Figure 5 A schematic diagram of a 3D NAND test chip manufacturing process according to an embodiment of the present invention is shown.

[0051] like Figure 5 As stated in Figure 5 In (e), two adjacent vias fall on the source and oxide at the bottom of the peripheral region, respectively. Figure 3 In the pattern of the peripheral area shown in the lower right figure, part of the through holes fall on the polysilicon layer of the source (conductive area), while the other part of the through holes fall on the oxide layer (insulating area). Figure 5 (f) and Figure 4 The same process as (b) is to perform CGR on the multi-layer polysilicon / oxide layer of the chip, that is, to eat the polysilicon layer laterally by wet etching to form the reserved positions of CG (control gate) and FG (floating gate), and then deposit an insulating layer on the side wall. Figure 5In the process, since the process is a test chip (die), the process of skipping the formation of the storage cell (cell) and simplifying the subsequent process of forming the conductive channel is chosen, which includes: 1) skipping the process of forming the storage cell (cell), that is, omitting the complete production process of FG in both the storage array area and the peripheral area; 2) simplifying the subsequent process, that is, directly depositing polysilicon to form a conductive layer in the through hole. Therefore, part of the polysilicon in the conductive channel in the peripheral area falls on the source, and the other part falls on the oxide. This simple checkerboard pattern and the special structure of skipping cell formation and subsequent simplified process flow make it easier to realize the rapid online detection of UE and FG-FG short circuit defects by the HEBI detector, thereby saving a lot of detection cycles and detection resources. The above-mentioned checkerboard pattern in the peripheral area is included in the 3D NAND test chip of the present invention, but no storage cell is formed in the test chip.

[0052] 6( a ), FIG. 6( b ) and FIG. 6( c ) are schematic diagrams showing HEBI detection of a short circuit defect between a UE and a floating gate (FG) caused by non-through hole etching according to an embodiment of the present invention.

[0053] As shown in FIG6 , FIG6 (a) shows the result of using the HEBI detection method to detect a chip without the above two through-hole etching defects. On the HEBI display interface, when the through-hole falls on the conductive part of the peripheral area, a bright color is displayed on the HEBI display interface; when the through-hole falls on the insulating part of the peripheral area, the through-hole on the insulating part is displayed as a dark color on the HEBI display interface; by comparing the bright and dark patterns of the chip surface displayed on the HEBI display interface with the original design pattern, the through-hole etching defects of the chip are detected. Specifically, in FIG6 (a), the through-hole (or conductive channel) marked as ① falls on the source, that is, on the source polysilicon layer and the source metal as shown in FIG6 (b), and is displayed as a bright color on the HEBI display interface; the through-hole (or conductive channel) marked as ② falls on the oxide, that is, on the oxide layer as shown in FIG6 (b), and is displayed as a dark color on the HEBI display interface. FIG6(c) shows a side view of the underlying structure in the peripheral area observed by FIB (focused ion beam). It can be seen from the figure that a normal chip has no through-hole etching defects.

[0054] FIG. 7( a ) and FIG. 7( b ) are schematic diagrams showing a defect of insufficient through-hole etching in a HEBI test chip according to an embodiment of the present invention.

[0055] As shown in FIG7(a), when the defect of insufficient through-hole etching occurs, the through-hole ① originally appears as a bright through-hole on the HEBI interface (that is, if the defect of insufficient through-hole etching does not occur, the conductive channel formed by etching and processing the through-hole falls on the source polysilicon layer and metal). If the defect of insufficient through-hole etching occurs, the conductive channel does not fall on the source polysilicon layer and metal at the bottom of the peripheral area, but falls on the oxide layer (insulating part) in the middle, so the through-hole ① appears as a dark color on the HEBI interface. As shown in FIG7(b), when the conductive channel formed by the through-hole does not fall on the source polysilicon layer and source metal in the peripheral area, but falls on the oxide insulating layer, the HEBI interface will not detect the conductive part of the conductive channel, so the through-hole ② appears as a dark color on the HEBI interface.

[0056] FIG. 8( a ) and FIG. 8( b ) are schematic diagrams showing a defect of FG-FG short circuit in a HEBI test chip according to an embodiment of the present invention.

[0057] As shown in FIG8(a), when a FG-FG short circuit defect occurs, via ② is originally displayed as a dark through hole on the HEBI interface (i.e., if there is no FG-FG short circuit defect, the conductive channel formed by etching and processing the through hole falls on the oxide). If a FG-FG short circuit defect occurs, the conductive channel of via ② is connected to via ① due to the short circuit between FG and FG. Therefore, in the pattern of the peripheral area, both via ① and via ② can be connected to the conductive part (source polysilicon layer and source metal) at the bottom, so both via ① and via ② appear as bright colors on the HEBI interface. As shown in FIG8(b), FIG8(b) is a side view of FIG8(a) (top view). When a short circuit occurs between the conductive channels formed by through hole ① and through hole ② (FG-FG short circuit), both can be connected to the conductive part (source polysilicon layer and source metal) at the bottom of through hole ①, so through hole ① and through hole ② are both displayed as bright colors on the HEBI interface.

[0058] Fig. 9 A display interface diagram showing the result of HEBI detecting through-hole etching defects according to an embodiment of the present invention is shown.

[0059] like Fig. 9 As shown in the figure, when multiple continuous bright patterns appear in the black box on the right, it means that the FG-FG short circuit defect occurs in the chip. When multiple continuous dark patterns appear in the black box on the left, it means that the through hole etching is insufficient in the chip.

[0060] Therefore, according to one or more embodiments of the present invention, if all via patterns are correct without any under-etching and FG-FG short circuit defects, the vias on the bottom oxide in the peripheral area will appear dark (or dark), while other vias on the bottom source in the normal peripheral area will appear light (or bright). If an FG-FG short circuit (short circuit between floating gates) occurs, the vias that should be open (the bottom contact platform is an insulating oxide) will appear conductive and connectable, and if under-etched vias occur, the vias on the conductive part (the bottom contact platform in the peripheral area of ​​the chip is the source conductive polysilicon / metal) will be cut off as open circuits. By analyzing the HEBI light and dark patterns and comparing them with the original design patterns, the FG-FG short circuit defect rate and the under-etching defect rate of the via corresponding to a given via etching process recipe can be obtained.

[0061] According to one or more embodiments of the present invention, a 3D NAND chip is provided, the 3D NAND chip comprising: a storage array area, a peripheral area below the storage array area, and a plurality of through holes after etching and process treatment, the plurality of through holes passing through the storage array area and the peripheral area; wherein a checkerboard pattern formed by a plurality of conductive parts and a plurality of insulating parts periodically alternating is generated in the peripheral area, and a portion of the plurality of through holes after etching and process treatment is in contact with the conductive part of the peripheral area, and another portion is in contact with the insulating part of the peripheral area. wherein the through hole etching defects of the 3D NAND chip are determined by detecting the through hole etching defects of the peripheral area. wherein the 3D NAND chip may be a test chip, in which the plurality of through holes after etching and process treatment do not form a storage unit in the test chip. wherein the through hole etching defects of the 3D NAND chip are determined by detecting the through hole etching defects of the test chip. Optionally, a plurality of through holes after etching and process treatment form storage cells in the 3D NAND chip, and the HEBI detector determines the through hole etching defects of the 3D NAND chip by detecting a checkerboard pattern in a peripheral area of ​​the 3D NAND containing the storage cells and by detecting through hole etching defects on the peripheral area.

[0062] In the test chip, the plurality of through holes after etching and process processing do not form a storage unit (cell) in the test chip. The plurality of through holes after etching and process processing form a conductive channel with a high aspect ratio in the test chip.

[0063] According to one or more embodiments of the present invention, when the present invention uses a customized test chip to detect via etching defects, a single wafer is used to simultaneously detect via etching deficiencies and FG-FG short defects, compared to two separate wafers in a traditional process.

[0064] According to one or more embodiments of the present invention, when the present invention adopts a customized test chip to detect through-hole etching defects, it can achieve a short detection cycle and a simple process flow, avoiding the complex storage unit (cell) formation in the online HEBI detection in the prior art and the GEBI that needs to go through a long EB (Etch Back) process flow to detect. Compared with the traditional solution that takes 3-4 weeks to detect through-hole etching defects, the solution of the present invention can reduce the detection cycle by 2 weeks.

[0065] According to one or more embodiments of the present invention, the use of a customized test chip in the present invention skips the process of forming a storage unit, and can save equipment and consumables resources by eliminating multiple process steps.

[0066] The following are further examples of the present invention:

[0067] Example 1. A method for detecting through-hole etching defects in a 3D NAND chip, the 3D NAND chip comprising a storage array area, a peripheral area located below the storage array area, and a plurality of through-holes after etching and process treatment, the plurality of through-holes passing through the storage array area and the peripheral area; the method comprising: generating a checkerboard pattern formed by periodically alternating multiple conductive parts and multiple insulating parts in the peripheral area, a portion of the multiple through-holes after etching and process treatment are in contact with the conductive parts of the peripheral area, and another portion are in contact with the insulating parts of the peripheral area; determining the through-hole etching defects of the 3D NAND chip by detecting through-hole etching defects on the peripheral area.

[0068] Example 2. The method of Example 1, wherein the spacing between the plurality of through holes in the checkerboard pattern is the same.

[0069] Example 3. The method according to the example, wherein the conductive portion of the peripheral region is a conductive electrode and the insulating portion is an oxide.

[0070] Example 4. A method according to Example 1, wherein the relative intensity change of voltage of multiple through holes in the surface of the test chip is detected by an electron beam detection method EBI to determine the through hole etching defects of the test chip, and the through holes on the conductive part are displayed as bright colors on the display interface of the EBI; the through holes on the insulating part are displayed as dark colors on the display interface of the EBI; and the through hole etching defects of the 3D NAND chip are detected by comparing the bright and dark patterns of the multiple through holes on the display interface with the original design pattern.

[0071] Example 5. The method according to Example 4, wherein the through-hole etching defects include insufficient through-hole etching defects and short circuit defects between floating gates.

[0072] Example 6. According to the method described in Example 5, when there is no defect of insufficient via etching, the via on the conductive part appears as a light color, and when there is a defect of insufficient via etching, the via on the conductive part appears as a dark color; and when there is no defect of short circuit between floating gates, the via on the insulating part appears as a dark color, and when there is a defect of short circuit between floating gates, the via on the insulating part appears as a light color.

[0073] Example 7. The method according to Example 1, wherein the 3D NAND chip is a test chip, in which a plurality of through holes after etching and process treatment do not form storage units in the test chip.

[0074] Example 8. The method according to Example 7, wherein the 3D NAND chip through-hole etching defects are determined by detecting through-hole etching defects of the test chip.

[0075] Example 9. The method according to Example 1, wherein a plurality of through holes after etching and process treatment form a storage unit in the 3D NAND chip.

[0076] Example 10. The method of example 1, wherein the plurality of vias form a conductive channel having a high aspect ratio.

[0077] Example 11. A 3D NAND chip, comprising: a storage array area, a peripheral area located below the storage array area, and a plurality of through holes after etching and process treatment, wherein the plurality of through holes pass through the storage array area and the peripheral area; wherein a checkerboard pattern formed by periodically alternating multiple conductive parts and multiple insulating parts is generated in the peripheral area, and a portion of the plurality of through holes after etching and process treatment is in contact with the conductive part of the peripheral area, and another portion is in contact with the insulating part of the peripheral area.

[0078] Example 12. The 3D NAND chip according to Example 11, wherein via etch defects of the 3D NAND chip are determined by detecting via etch defects of the peripheral region.

[0079] Example 13. The 3D NAND chip of Example 11, wherein the spacing between the plurality of vias in the checkerboard pattern is the same.

[0080] Example 14. The 3D NAND chip of Example 11, wherein the conductive portion of the peripheral region is a conductive electrode and the insulating portion is an oxide.

[0081] Example 15. The 3D NAND chip according to Example 11, wherein the 3D NAND chip is a test chip, in which a plurality of through holes after etching and process treatment do not form storage cells in the test chip.

[0082] Example 16. The 3D NAND chip according to Example 15, wherein the through-hole etching defects of the 3D NAND chip are determined by detecting through-hole etching defects of the test chip.

[0083] Example 17. The 3D NAND chip of Example 11, wherein a plurality of through holes after etching and processing form memory cells in the 3D NAND chip.

[0084] Example 18. The 3D NAND chip according to Example 11, wherein the plurality of through holes after etching and processing form a conductive channel with a high aspect ratio in the 3D NAND chip.

[0085] Example 19. A 3D NAND chip manufacturing system, the 3D NAND chip manufacturing system comprising the method for detecting 3D NAND chip through-hole etching defects according to any one of Examples 1-10, or forming the 3D NAND chip according to any one of Examples 11-18.

[0086] Example 20. A method for detecting through-hole etching defects in a 3D NAND chip, the method comprising: customizing a test chip for detecting the through-hole etching defects, the test chip comprising a storage array area, a peripheral area located below the storage array area, and a plurality of through-holes after etching and process treatment, the plurality of through-holes passing through the storage array area and the peripheral area; generating a checkerboard pattern formed by periodically alternating multiple conductive parts and multiple insulating parts in the peripheral area, a portion of the multiple through-holes after etching and process treatment are in contact with the conductive parts of the peripheral area, and another portion are in contact with the insulating parts of the peripheral area; determining the through-hole etching defects of the 3D NAND chip by detecting the through-hole etching defects of the test chip.

[0087] Example 21. A test chip for detecting through-hole etching defects of a 3D NAND chip, wherein the test chip includes a storage array area, a peripheral area located below the storage array area, and a plurality of through-holes after etching and process treatment, wherein the plurality of through-holes pass through the storage array area and the peripheral area; a checkerboard pattern formed by a plurality of conductive parts and a plurality of insulating parts periodically alternating is generated in the peripheral area, and a portion of the plurality of through-holes after etching and process treatment is in contact with the conductive part of the peripheral area, and another portion is in contact with the insulating part of the peripheral area; wherein the through-hole etching defects of the 3D NAND chip are determined by detecting the through-hole etching defects of the test chip. wherein, in the test chip, the plurality of through-holes after etching and process treatment do not form storage units in the test chip.

[0088] While specific embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that various modifications and variations may be made thereto without departing from the technical spirit of the present invention as provided by the claims hereinafter appended.

Claims

1. A method for detecting through-hole etching defects in a 3D NAND chip, wherein the 3D NAND chip comprises a storage array area, a peripheral area below the storage array area, and a plurality of through-holes after etching and process treatment, wherein the plurality of through-holes pass through the storage array area and the peripheral area; The method comprises: A checkerboard pattern formed by periodically alternating a plurality of conductive portions and a plurality of insulating portions is generated in the peripheral region, and a portion of the plurality of through holes after etching and process treatment is in contact with the conductive portions of the peripheral region, and another portion is in contact with the insulating portions of the peripheral region; The 3D NAND chip through-hole etching defects are determined by detecting the through-hole etching defects on the peripheral area.

2. The method according to claim 1, wherein: The spacings between the plurality of through holes in the checkerboard pattern are the same. 3 . The method according to claim 1 , wherein the conductive portion of the peripheral region is a conductive electrode and the insulating portion is an oxide.

4. The method according to claim 1, wherein: Detecting the relative intensity changes of voltages of multiple through holes on the surface of the test chip by an electron beam inspection method EBI to determine through hole etching defects of the test chip, wherein through holes on the conductive part are displayed as bright colors on the display interface of the EBI; through holes on the insulating part are displayed as dark colors on the display interface of the EBI; and The through-hole etching defects of the 3D NAND chip are detected by comparing the light and dark patterns of the plurality of through-holes on the display interface with the original design patterns.

5. The method according to claim 4, wherein: The through hole etching defects include insufficient through hole etching defects and short circuit defects between floating gates.

6. The method according to claim 5, wherein When a through-hole under-etching defect does not occur, the through-hole on the conductive portion appears as a light color, and when a through-hole under-etching defect occurs, the through-hole on the conductive portion appears as a dark color; and When a defect of a short circuit between floating gates does not occur, the via hole on the insulating portion appears dark, and when a defect of a short circuit between floating gates occurs, the via hole on the insulating portion appears light.

7. The method according to claim 1, wherein: The 3D NAND chip is a test chip, in which a plurality of through holes after etching and process treatment do not form storage units in the test chip. 8 . The method according to claim 7 , wherein the through-hole etching defects of the 3D NAND chip are determined by detecting the through-hole etching defects of the test chip.

9. The method according to claim 1, wherein: After etching and process treatment, a plurality of through holes form storage units in the 3D NAND chip.

10. The method of claim 1, wherein the plurality of vias form a conductive channel having a high aspect ratio.

11. A 3D NAND chip, comprising: A storage array area, a peripheral area below the storage array area, and a plurality of through holes after etching and process treatment, wherein the plurality of through holes pass through the storage array area and the peripheral area; wherein, A checkerboard pattern formed by periodically alternating multiple conductive parts and multiple insulating parts is generated in the peripheral area, and a part of the multiple through holes after etching and process treatment are in contact with the conductive parts of the peripheral area, and another part is in contact with the insulating parts of the peripheral area.

12. The 3D NAND chip according to claim 11, wherein: The through-hole etching defects of the 3D NAND chip are determined by detecting the through-hole etching defects in the peripheral area.

13. The 3D NAND chip according to claim 11, wherein: The spacings between the plurality of through holes in the checkerboard pattern are the same. 14 . The 3D NAND chip according to claim 11 , wherein the conductive portion of the peripheral region is a conductive electrode, and the insulating portion is an oxide. 15 . The 3D NAND chip according to claim 11 , wherein the 3D NAND chip is a test chip, in which a plurality of through holes after etching and process treatment do not form storage units in the test chip.

16. The 3D NAND chip according to claim 15, wherein: The through-hole etching defects of the 3D NAND chip are determined by detecting the through-hole etching defects of the test chip.

17. The 3D NAND chip according to claim 11, wherein: After etching and process treatment, a plurality of through holes form storage units in the 3D NAND chip.

18. The 3D NAND chip according to claim 11, wherein: The plurality of through holes after etching and process treatment form a conductive channel with a high aspect ratio in the 3D NAND chip.

19. A 3D NAND chip manufacturing system, comprising the method for detecting 3D NAND chip through-hole etching defects according to any one of claims 1 to 10, or forming the 3D NAND chip according to any one of claims 11 to 18.

Images