A trimming circuit built into a chip, a chip having the trimming circuit, and a trimming method

Abstract

The present invention provides a chip-based trimming circuit, a chip having the trimming circuit, and a trimming method. The chip includes pins Vinn and Vinp. The chip trimming circuit includes: a converter; a first pin din and a first pin clk, respectively connected to the two output ends of the converter; a decoder, which receives digital signal data and clock signal data, processes them, and outputs them via a second pin din, a second pin clk, and a pin blown; a register group, including n registers, which receive and store digital signal data; and a fuse group, including n fuses. When pin blown sends a blow signal to a fuse connected to the register via the register, causing any fuse to be blown, the digital signal data in the register connected to the blown fuse will be burned into the blown fuse, thereby completing the chip trimming. After adopting the above technical solution, the chip interior can be trimmed through existing pins without changing the existing package.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics, and in particular to a trimming circuit built into a chip, a chip having the trimming circuit, and a trimming method. Background Art

[0002] Many high-performance, high-precision chips require extremely precise voltage outputs and very small offset voltages. For example, high-precision operational amplifiers require extremely accurate offset voltages (typically in the microvolt range). Due to process variations, technicians can typically only achieve a minimum offset of a few millivolts. This is typically reduced to tens of microvolts through trimming during the wafer processing process. However, after the wafer is packaged, the offset voltage can vary significantly due to packaging stress, potentially destroying the voltage value that was trimmed to perfection during wafer production.

[0003] However, packaged chips have a limited number of pins. There are no additional pins for post-package adjustments. For example, an op amp typically has five package pins, corresponding to VDD, GND, VINp, VINn, and VOUT. These pins all have their own functional uses, leaving no additional pins for adjustment. Furthermore, due to high performance requirements, it's difficult to simply add to the existing pins without compromising performance. Therefore, adjustment can only be performed during the CP (wafer) process using additional pins. Direct access to the corresponding adjustment pins is impossible after packaging, making it impossible to achieve optimal offset voltage and other performance parameters.

[0004] Therefore, a trimming circuit and a trimming method are needed to perform trimming after packaging to achieve the optimal performance of the packaged chip. Summary of the Invention

[0005] In order to overcome the above technical defects, the purpose of the present invention is to provide a trimming circuit built into a chip, a chip having the trimming circuit and a trimming method, which can trim the inside of the chip through existing pins without changing the existing package.

[0006] The present invention discloses a trimming circuit built into a chip, wherein the chip includes a protruding pin Vinn and a protruding pin Vinp, and is characterized in that the chip trimming circuit includes:

[0007] A converter connected to pin Vinn and pin Vinp;

[0008] A first pin din and a first pin clk are connected to two output terminals of the converter respectively, wherein the first pin din outputs digital signal data, and the first pin clk outputs clock signal data;

[0009] The decoder includes two input terminals and three output terminals. The three output terminals include a second pin din, a second pin clk, and a pin blowen. The two input terminals are connected to the first pin din and the first pin clk, respectively. The decoder receives digital signal data and clock signal data for post-processing and outputs the data through the second pin din, the second pin clk, and the pin blowen. The output of the second pin clk and the pin blowen can be selectively enabled.

[0010] The register group is powered by a voltage source VDD and includes n registers, wherein adjacent registers are connected end to end, and the first register is connected to the second pin din and the second pin clk to receive and store digital signal data;

[0011] The fuse group includes n fuses, each of which is connected to a register. The blown pin is connected to the register group. When the blown pin sends a blow signal to the fuse connected to the register through the register, causing any fuse to be blown, the digital signal data in the register connected to the blown fuse will be burned into the blown fuse to complete the chip adjustment.

[0012] Preferably, the converter comprises:

[0013] A first AND gate has one input connected to the pin Vinn, another input connected to the last register of the register group and then inverted, and an output connected to the first pin clk;

[0014] A second AND gate has one input connected to the pin Vinp, the other input connected to the last register of the register group and then inverted, and an output connected to the first pin din;

[0015] When the last register is not blown and the pin Vinn sends a positive voltage input, the first AND gate outputs clock signal data via the first pin clk;

[0016] When the last register is blown and the pin Vinn sends a positive voltage input, the first AND gate outputs a low level through the first pin clk;

[0017] When the last register is not blown and the pin Vinp sends a negative voltage input, the second AND gate outputs digital signal data through the first pin din;

[0018] When the last register is blown and the pin Vinp sends a negative voltage input, the second AND gate outputs a low level through the first pin din.

[0019] Preferably, the converter comprises:

[0020] A first CMOS transmission gate, the first CMOS transmission gate comprising a first NMOS transistor and a first PMOS transistor, the drain of the first NMOS transistor being connected to the pin Vinn, the gate being connected to the last register of the register group and then inverted, the source being connected to the first pin din, the source of the first PMOS transistor being connected to the pin Vinn, and the drain being connected to the first pin din;

[0021] A second CMOS transmission gate, comprising a second NMOS transistor and a second PMOS transistor, wherein the drain of the second NMOS transistor is connected to the pin Vinp, the gate is connected to the last register of the register group and then inverted, and the source is connected to the first pin clk; the source of the second PMOS transistor is connected to the pin Vinp, and the drain is connected to the first pin clk;

[0022] A diode, wherein the anode of the diode is connected to the inverting phase of the last register of the register group, and the cathode of the diode is respectively connected to the gate of the first PMOS tube and the gate of the second PMOS tube and then inverted.

[0023] Preferably, the register group further includes m password registers; each adjacent password register is connected end to end, the input end of the first password register is connected to the last register of the register group, the output end of the last password register is connected to a third AND gate, and the output end of the third AND gate is connected to the blowen pin; when the digital signal received by each password register is 1, the third AND gate outputs a high-level signal to the blowen pin to enable the blowen pin.

[0024] Preferably, the password register group is connected to an input terminal of the third AND gate;

[0025] Another input terminal of the third AND gate is connected to the first pin clk, and another input terminal of the third AND gate is connected to the trimming data pin;

[0026] One output end of the third AND gate is connected to the decoder, and the other output end is connected to the Blowen signal chip. The Blowen signal chip outputs the Blowen signal only when and only when it receives the high level signal sent by the third AND gate.

[0027] Preferably, it also includes:

[0028] The delay module is connected to the blowen pin and the register group. Based on the high and low level changes of the Blowen signal of the blowen pin, the delay module generates a reset signal to the reset interface of the register group, thereby resetting the password register and disabling the blowen pin.

[0029] Preferably, the delay module includes:

[0030] Voltage source Vdd, supplies power to the delay module;

[0031] The square wave signal generation module generates a square wave signal por after power-on;

[0032] Pin por is connected to the reset interface of the register group to reset the register group.

[0033] The present invention also discloses a chip, comprising the above-mentioned trimming circuit.

[0034] The present invention further discloses a chip adjustment method, comprising the following steps:

[0035] The chip trimming circuit is configured as follows: the chip includes extended pins Vinn and Vinp, and the chip trimming circuit includes: a converter connected to pins Vinn and Vinp; a first pin din and a first pin clk, respectively connected to two output terminals of the converter, wherein the first pin din outputs digital signal data and the first pin clk outputs clock signal data; a decoder including two input terminals and three output terminals, wherein the three output terminals include a second pin din, a second pin clk, and a pin blown, and the two input terminals are respectively connected to the first pin din and the first pin clk is connected to receive digital signal data and clock signal data for post-processing, and outputs the data through the second pin din, the second pin clk, and the pin blowen, wherein either the second pin clk or the pin blowen is selectively enabled; a register group is powered by a voltage source VDD and includes n registers, wherein adjacent registers are connected end to end, and the first register is connected to the second pin din and the second pin clk to receive and store digital signal data; a fuse group includes n fuses, each fuse is connected to a register, and the pin blowen is connected to the register group;

[0036] When the pin blown sends a blow signal to the fuse connected to the register through the register, causing any fuse to be blown, the digital signal data in the register connected to the blown fuse will be burned into the blown fuse to complete the chip trimming.

[0037] Preferably, the method further comprises the following steps:

[0038] The register group is further configured as follows: m password registers are included; the input end of each password register is connected to the last register in the register group, the output end is connected to a third AND gate, and the output end of the third AND gate is connected to the blowen pin; when the digital signal received by each password register is 1, the third AND gate outputs a high-level signal to the blowen pin to enable the blowen pin;

[0039] The chip trimming circuit is configured as follows: it also includes a delay module, which is connected to the blowen pin and the register group. The delay module generates a reset signal to the reset interface of the register group based on the high and low level changes of the blowen signal of the blowen pin, thereby resetting the password register and disabling the blowen pin.

[0040] Compared with the existing technology, the above technical solution has the following beneficial effects:

[0041] 1. Even after the chip is wafered, the internal structure of the chip can be adjusted through the existing pins;

[0042] 2. The trimming information can be temporarily programmed and stored in registers. The corresponding changes in chip performance can be measured in real time, and the trimming data can be adjusted at any time. The data can also be permanently burned into fuses.

[0043] 3. Performance is not affected by potentially redundant pins, and ATE FT testing time is not significantly increased. No special ATE (Automatic Test Equipment, in the semiconductor industry, refers to integrated circuit (IC) automatic testers used to test the integrity of integrated circuit functions) is required, thus achieving optimal chip performance after packaging.

[0044] 4. It saves the time of the entire CP (wafer) step and the corresponding R&D management costs (including the R&D and production of needle cards, CP (wafer) program R&D and the rental time of CP (wafer) machines for mass production), greatly increases the yield of products, and also greatly improves the performance parameters and consistency of mass-produced products. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A topological diagram of a trimming circuit in accordance with a preferred embodiment of the present invention;

[0046] Figure 2 A topological diagram for isolating the trimming circuit and the normal use circuit of the chip in accordance with a preferred embodiment of the present invention;

[0047] Figure 3 To comply with another preferred embodiment of the present invention, a topology diagram for isolating the trimming circuit and the normal chip use circuit;

[0048] Figure 4 A digital circuit diagram for switching between a fusing mode and a trimming mode in accordance with a preferred embodiment of the present invention;

[0049] Figure 5 A schematic diagram of the connection between the register group and the fuse group in accordance with a preferred embodiment of the present invention;

[0050] Figure 6 1 is a circuit diagram of a delay module according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0051] The advantages of the present invention are further described below with reference to the accompanying drawings and specific embodiments.

[0052] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0053] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0054] It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining."

[0055] In the description of the present invention, it should be understood that the terms "longitudinal", "transverse", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0056] In the description of the present invention, unless otherwise specified and limited, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or it can be the internal communication between two components. It can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to the specific circumstances.

[0057] In the following description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention and have no specific meaning. Therefore, "module" and "component" can be used interchangeably.

[0058] In order to utilize existing pins, the same pin can be used for both chip operation and post-packaging adjustments. The present invention utilizes the Vinp and Vinn pins extending from the chip. The use of these two pins is mainly due to the fact that in chips such as operational amplifiers, all the clk, din, and blown pins are unusable. Therefore, it is necessary to design a circuit to use the existing pins so that these pins can be used for normal applications and also for adjustments. The operational amplifier has five pins: Vdda, Vssa, Vout, Vinp, and Vinn. Vdda and vssa are corresponding power sources and cannot be used for digital signals. Vout generally has a strong internal current driving capability, making it difficult to effectively control it with fast digital signals from the outside. Therefore, we selected the Vinp and Vinn pins for modification. Because for operational amplifiers, they are usually the gates of MOS transistors or the bases of BJTs, which can be controlled by fast digital signals. The mode can be switched. When adjusting the chip parameters, since the overall adjustment circuit will have a first pin din, a first pin clk and a pin blown, which are used to input adjustment data, control the adjustment clock and the control signal of the fuse respectively, it is necessary to first convert the output of pin Vinp and pin Vinn into the input of three pins.

[0059] For this, see Figure 1The chip trimming circuit includes a converter and a decoder. The converter is connected to pins Vinn and Vinp, and first receives inputs from these pins. The first pin din and the first pin clk, used for trimming, are respectively connected to the converter's two output terminals. The first pin din outputs digital signal data, and the first pin clk outputs clock signal data. Therefore, the converter can be a variety of circuit designs capable of outputting high and low levels. The decoder includes two input terminals and three output terminals. The three output terminals include a second pin din, a second pin clk, and a blown pin (fuse enable). The two input terminals are respectively connected to the first pin din and the first pin clk, receiving digital signal data and clock signal data, respectively, for post-processing, and outputting them through the second pin din, the second pin clk, and the blown pin. Either the second pin clk or the blown pin can be enabled. In other words, when the second pin clk is enabled, the trimming circuit can be used to trim chip parameters. When the blown pin is enabled, the input digital signal data containing the trimming data is burned into the fuse. Once the fuse blows, the trimming data is permanently retained. A register bank, powered by a voltage source VDD, includes n registers, where adjacent registers are connected end-to-end. The first register is connected to the second pin din and the second pin clk to receive and store digital signal data. During reception, the digital signal data is continuously recorded and transmitted to the next register based on the toggle of the clock signal data. The fuse bank includes n fuses, each connected to a register. The blown pin is connected to the register bank. When the blown pin generates a blow signal, the register sends a blow signal to the fuse connected to the register. When the fuse blows, the digital signal data in the register connected to the blown fuse is burned into the blown fuse, completing the chip trimming.

[0060] More specifically, a column of registers (for example, 48) is used. Each register is connected end to end. The first pin, clk, controls the clock for all registers. The first pin, din, transmits digital data from the first register's input. Then, as the clock signal on the first pin, clk, toggles, the digital data from the first register flows into the second register. And so on. In this way, data is input into all 48 registers. Each register stores the data to be adjusted (0 or 1). Each register also controls its own corresponding fuse. To burn data into a fuse, the data is first transmitted to the corresponding register via the first pin, clk, and the first pin, din. Then, a blown signal is sent via the blown pin to open the buffer that controls the blown fuse, allowing a large current to flow through the fuse, effectively blowing the corresponding fuse in a very short time, permanently preserving the fuse.

[0061] Furthermore, due to the specific nature of fuses and current limitations, a single blown operation can only blow one fuse at a time. This also limits the feasibility of fuse blown operations. Furthermore, the connection between multiple fuses and pin blowns primarily relies on the following technologies: Wire bonding: This is a traditional packaging method. After dicing a wafer into dies, the dies are bonded to corresponding islands on a substrate frame (leadframe pad). Wires are then used to connect the die's bond pads to the substrate's pins (wire bonding) to achieve an electrical connection. Flip chip bonding: Flip chip bonding combines die bonding with wire bonding, connecting the die to the substrate by forming bumps on the die's pads. This technology eliminates interconnect wires, significantly shortening the interconnect length, reducing RC (resistance-capacitance) delay, and effectively improving electrical performance. Tape Automated Bonding (TAB): Tape bonding is commonly used for soldering large components such as chips, resistors, and capacitors. During the bonding process, the component pins are soldered to solder points on the circuit board (by converting gold wire into copper foil, which is then bonded to the bumps on the chip pins). Copper Clip Bonding: This packaging process uses a solid copper bridge bonded to the solder to connect the chip and pins. Compared to traditional bonded packaging methods, Cu Clip technology can achieve unique package resistance values, higher current capacity, and better thermal conductivity. Chip-on-Board (COB) technology: COB technology coats the silicon die mounting points on the substrate surface with a thermally conductive, silver-doped epoxy resin. The chip is then directly placed on the substrate surface and heat-treated until it is firmly fixed to the substrate. Wire bonding is then used to establish electrical connections between the chip and substrate. These technologies ensure that multiple fuses and blown pins on the chip can effectively connect to external circuits or other chips, providing both electrical and physical connection paths. Each technology has its own specific application scenarios and advantages. During design, it is necessary to select the appropriate connection method based on actual needs.

[0062] With the above configuration, when the chip wafer is completed, for the user of the chip, all the circuits of the trimming part will not be accessible to the user. The user inputs any voltage to Vinp and Vinn, which will not change any working performance of the chip, so the user cannot perceive the existence of the trimming circuit. In other words, in order to isolate the trimming circuit from the normal use circuit, a switch is used for control. The control source of the switch should be a fuse, such as the last fuse (i.e. the 48th fuse in the above embodiment). <48> ) is specifically used to control the switch for isolation adjustment and normal circuit use. That is, when all tests are completed, we will blow this fuse. After all ATE tests are completed, users can use the chip normally.

[0063] See Figure 2In a preferred embodiment, the digital circuit within the converter that converts pins Vinn and Vinp into a fuse signal capable of controlling a fuse blow includes: a first AND gate having one input connected to pin Vinn and another input connected to the last register in the register group, then inverted (i.e., inverting the output signal received from the last register), with its output connected to the first pin clk; and a second AND gate having one input connected to pin Vinp and another input connected to the last register in the register group, then inverted, with its output connected to the first pin din. With this connection configuration, when the last register is not blown, its output is low (signal 0). After inversion, the input to the first AND gate is a high signal. Furthermore, when pin Vinn receives a positive voltage input, the input to the first AND gate is also a high signal. Consequently, both inputs of the first AND gate, after logical determination, output a high signal, causing the first pin clk (also referred to as inclk) to output clock signal data. When the last register is blown, its output is a high level (signal is 1). After inversion, the input to the first AND gate is a low level signal. When the pin Vinn sends a positive voltage input, the two input ends of the first AND gate output a low level after logic judgment, and the first pin clk outputs a low level, that is, the first pin clk does not output a signal; when the last register is not blown, its output is a low level (signal is 0). After inversion, the input to the second AND gate is a high level signal. When the pin Vinp sends a negative voltage input, the two input ends of the second AND gate output a high level after logic judgment, so that the first pin din (also called indata) outputs digital signal data; when the last register is blown, its output is a high level (signal is 1). After inversion, the input to the second AND gate is a low level signal. When the pin Vinp sends a negative voltage input, the two input ends of the second AND gate output a low level after logic judgment, and the first pin din outputs a low level. When the pin Vinn does not send a positive voltage input, or the pin Vinp does not send a negative voltage input, naturally, no adjustment instruction is input, the first pin clk outputs a low level, the first pin din outputs a low level, and does not accept any adjustment data.

[0064] Thus, through the above configuration, the trimming circuit can be permanently isolated from normal use.

[0065] In the above embodiment, considering that the first pin clk outputs a low level and the first pin din outputs a low level, thus shutting down the digital circuit, the presence of the AND gate still affects the normal operation of the operational amplifier. This is because operational amplifiers typically have very low input bias current and input offset current, even as low as 1pA. However, the addition of this digital circuit AND gate still draws a current of nearly 1nA even after shutdown, and this current increases exponentially with increasing temperature (this is because this leakage current flows from the drain terminal and is theoretically much greater than the gate oxide leakage current). Therefore, under certain conditions, users can still detect the trimming circuit through certain means, affecting the normal operation of the chip circuit.

[0066] Therefore, see Figure 3 In another embodiment, a converter circuit of another topology is adopted. In this embodiment, the converter includes: a first CMOS transmission gate, the first CMOS transmission gate includes a first NMOS transistor and a first PMOS transistor, the drain of the first NMOS transistor is connected to the pin Vinn, the gate is connected to the last register of the register group and then inverted (or it can be understood that the inverted signal of the signal of the last register is input to the gate of the first NMOS transistor), the source is connected to the first pin din, the source of the first PMOS transistor is connected to the pin Vinn, and the drain is connected to the first pin din; a second CMOS transmission gate, the second CMOS transmission gate includes a second NMOS transistor and a second PMOS transistor, the drain of the second NMOS transistor is connected to the pin Vinp, and the gate is connected to The last register in the register group is connected and then inverted (or, it can be understood that the inverted signal of the last register's signal is input to the gate of the second NMOS transistor), with its source connected to the first pin clk. The source of the second PMOS transistor is connected to pin Vinp, and its drain is connected to the first pin clk. A diode has its anode connected to the inverted phase of the last register in the register group (or, it can be understood that the inverted signal of the last register's signal is input to the anode of the diode), and its cathode connected to the gates of the first and second PMOS transistors, respectively, and then inverted (or, it can be understood that the inverted signal of the cathode of the diode is input to the gates of the first and second PMOS transistors). With these connections, the first and second CMOS transmission gates function as AND gates.

[0067] With the above configuration, when the last fuse is unblown and outputs a low-level signal, it is first inverted to a high level. The signal input to the gate of the first NMOS transistor is 1, turning on the first NMOS transistor. Simultaneously, the inverted high-level signal is transmitted via a diode to the gate of the first PMOS transistor. Before transmission, it is inverted again to a low level. The signal input to the gate of the first PMOS transistor is 0, turning on the first PMOS transistor. Simultaneously, the inverted high-level signal input to the gate of the second NMOS transistor is 1, turning on the second NMOS transistor. The inverted high-level signal is transmitted via a diode to the gate of the second PMOS transistor. Before transmission, it is inverted again to a low level. The signal input to the gate of the second PMOS transistor is 0, turning on the second PMOS transistor. Thus, when the last fuse is unblown, the first and second CMOS transmission gates are fully conductive. Conversely, when the last fuse blows, outputting a high-level signal, it is first inverted to a low level. The signal input to the gate of the first NMOS transistor is 0, turning off the first NMOS transistor. Simultaneously, the inverted low-level signal is transmitted via the diode to the gate of the first PMOS transistor. Before transmission, it is inverted again to a high level, turning off the first PMOS transistor. Simultaneously, the inverted low-level signal input to the gate of the second NMOS transistor is 0, turning off the second NMOS transistor. The inverted low-level signal is transmitted via the diode to the gate of the second PMOS transistor. Before transmission, it is inverted again to a high level, turning off the second PMOS transistor. Therefore, the signal input to the gate of the second PMOS transistor is 1, turning off the second PMOS transistor. Therefore, when the last fuse blows, the first and second CMOS transmission gates are completely disconnected, cutting off the signal to the trimming circuit while also negligibly reducing the overall chip power consumption.

[0068] See Figure 5 To completely separate the register's normal programming mode and fuse mode and prevent them from interfering with each other, an additional digital circuit is added as a cipher. The fuse mode is triggered only when a specific password sequence is input. Specifically, the register group includes m password registers; each adjacent password register is connected end to end, with the input of the first password register connected to the last register in the register group to receive digital signal data sent from the last register (via the din pin). The output of each password register is connected to a third AND gate, and the output of the third AND gate is connected to the blown pin. When the digital signal received by each password register is 1, the third AND gate outputs a high-level signal to the blown pin, enabling the blown pin.

[0069] In this embodiment, the number of password registers can be five. The password sequence for enabling the blown pin is set to 11111. This is enabled by setting the digital signal to 1 because, when nothing is done, the outputs of these registers default to 00000. To minimize false triggering, a mode where all five passwords are 1 is used. To further increase the complexity of the password, more password registers can be added. Furthermore, the automatic reset count of the counter (the adaptability of the clk pin, i.e., the second clk pin connected to all registers and the password register) has been increased from 48 to 53 to accommodate the new number of registers.

[0070] When entering the fuse mode, you need to enter the corresponding data to be burned into the fuse, and enter the password into all registers and password registers. This disconnects the pin Vinp from the first pin clk. Any subsequent operation on the pin Vinp will no longer change the first pin clk, but will directly control the signal of the pin blown. In other words, in this mode, the pin Vinp controls the pin blown, and the pin Vinn controls the first pin din. The first pin clk is temporarily inaccessible. When in this mode, the fuse can be blown using the original method. For this, see Figure 4 , the password register group is connected to one input end of the third AND gate; the other input end of the third AND gate is connected to the first pin clk, and another input end of the third AND gate is connected to the adjustment data pin; one output end of the third AND gate is connected to the decoder, and the other output end is connected to the Blowen signal chip. The Blowen signal chip outputs the Blowen signal only when and only when it receives a high-level signal sent by the third AND gate.

[0071] In order to continue to input new data and restore the participation of the clk signal, it is preferably necessary to set a configuration for exiting the fuse mode. To this end, the following configuration is proposed: each time a fuse is blown, new data must be written, that is, when the blown signal is pulled high and then pulled low, a delay module is added to the trimming circuit. Figure 6The delay module is connected to the blown pin and the register bank. Based on the high-low level transitions of the blown signal on the blown pin, the delay module generates a reset signal to the register bank's reset interface, resetting the cipher registers and disabling the blown pin. In other words, the delay module senses the falling edge of the blown signal and self-generates a square pulse (delay). It then controls a reset_all signal to reset all registers to zero. This resets the "1" data stored in the cipher registers, thereby exiting the blown mode. This allows for repeated switching between blown mode and input mode. More specifically, the delay module includes a voltage source (Vdd) that supplies power to the delay module; a square wave signal generation module that generates a square wave signal (por) upon power-up; and pin (por), which is connected to the register bank's reset interface to reset the register bank. As each fuse is gradually blown according to this operation, the final fuse blows, completely disconnecting the trimming circuit from the normal operating circuit, allowing users to use the chip normally.

[0072] The present invention also discloses a chip, comprising the above-mentioned trimming circuit.

[0073] The present invention further discloses a chip trimming method, comprising the following steps: configuring a chip trimming circuit as follows: the chip includes a protruding pin Vinn and a pin Vinp, and the chip trimming circuit includes: a converter connected to the pin Vinn and the pin Vinp; a first pin din and a first pin clk connected to two output ends of the converter, wherein the first pin din outputs digital signal data and the first pin clk outputs clock signal data; a decoder including two input ends and three output ends, wherein the three output ends include a second pin din, a second pin clk and a pin blown, wherein the two input ends are connected to the first pin din and the first pin clk respectively, receive the digital signal data and the clock signal data for post-processing, and output the digital signal data and the clock signal data through the second pin din , the second pin clk and the pin blowen output, wherein the second pin clk and the pin blowen output can be selectively enabled; the register group is powered by a voltage source VDD, including n registers, wherein adjacent registers are connected end to end, and the first register is connected to the second pin din and the second pin clk to receive and store digital signal data; the fuse group includes n fuses, each fuse is connected to a register, and the pin blowen is connected to the register group; when the pin blowen sends a fuse signal to the fuse connected to the register through the register, so that any fuse is blown, the digital signal data in the register connected to the blown fuse will be burned into the blown fuse to complete the chip trimming.

[0074] Preferably, the following steps are also included: the register group is further configured as follows: it also includes m password registers; the input end of each password register is connected to the last register of the register group, the output end is connected to a third AND gate, and the output end of the third AND gate is connected to the blowen pin; when the digital signals received by each password register are all 1, the third AND gate outputs a high-level signal to the blowen pin to enable the blowen pin; the chip trimming circuit is configured as follows: it also includes a delay module, the delay module is connected to the blowen pin and the register group, and the delay module generates a reset signal to the reset interface of the register group based on the high and low level changes of the Blowen signal of the blowen pin, so that the password register is reset and the blowen pin is disabled.

[0075] It should be noted that the embodiments of the present invention have better practicability and do not impose any form of limitation on the present invention. Any technician familiar with the field may use the technical content disclosed above to change or modify it into an equivalent effective embodiment. However, any modification or equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A trimming circuit built into a chip, the chip comprising a protruding pin Vinn and a protruding pin Vinp, characterized in that: The chip trimming circuit includes: A converter connected to the pin Vinn and the pin Vinp; A first pin din and a first pin clk are connected to two output terminals of the converter respectively, wherein the first pin din outputs digital signal data, and the first pin clk outputs clock signal data; A decoder comprising two input terminals and three output terminals, wherein the three output terminals include a second pin din, a second pin clk, and a pin blowen. The two input terminals are connected to the first pin din and the first pin clk, respectively, receive the digital signal data and clock signal data for post-processing, and output them via the second pin din, the second pin clk, and the pin blowen. The output of the second pin clk and the pin blowen can be selectively enabled. A register group, powered by a voltage source VDD, includes n registers, wherein adjacent registers are connected end to end, and a first register is connected to the second pin din and the second pin clk to receive and store the digital signal data; A fuse group includes n fuses, each of which is connected to a register. The blown pin is connected to the register group. When the blown pin sends a blow signal to the fuse connected to the register via the register, causing any fuse to be blown, the digital signal data in the register connected to the blown fuse will be burned into the blown fuse to complete the chip adjustment.

2. The trimming circuit according to claim 1, wherein: The converter comprises: A first AND gate, having one input terminal connected to the pin Vinn, another input terminal connected to the last register of the register group and then inverted, and an output terminal connected to the first pin clk; A second AND gate, having one input terminal connected to the pin Vinp, another input terminal connected to the last register of the register group and then inverted, and an output terminal connected to the first pin din; When the last register is not blown and the pin Vinn sends a positive voltage input, the first AND gate outputs clock signal data via the first pin clk; When the last register is blown and the pin Vinn sends a positive voltage input, the first AND gate outputs a low level through the first pin clk; When the last register is not blown and the pin Vinp sends a negative voltage input, the second AND gate outputs digital signal data via the first pin din; When the last register is blown and the pin Vinp sends a negative voltage input, the second AND gate outputs a low level through the first pin din.

3. The trimming circuit according to claim 1, wherein: The converter comprises: a first CMOS transmission gate, the first CMOS transmission gate comprising a first NMOS transistor and a first PMOS transistor, the drain of the first NMOS transistor being connected to the pin Vinn, the gate being connected to the last register of the register group and then inverted, the source being connected to the first pin din, the source of the first PMOS transistor being connected to the pin Vinn, and the drain being connected to the first pin din; a second CMOS transmission gate, the second CMOS transmission gate comprising a second NMOS transistor and a second PMOS transistor, the drain of the second NMOS transistor being connected to the pin Vinp, the gate being connected to the last register of the register group and then inverted, the source being connected to the first pin clk, the source of the second PMOS transistor being connected to the pin Vinp, and the drain being connected to the first pin clk; A diode, wherein the anode of the diode is connected to the inverting phase of the last register of the register group, and the cathode of the diode is respectively connected to the gate of the first PMOS tube and the gate of the second PMOS tube and then inverted.

4. The trimming circuit according to claim 1, wherein: The register group also includes m password registers; Each adjacent password register is connected end to end, the input end of the first password register is connected to the last register of the register group, the output end of each password register is connected to a third AND gate, and the output end of the third AND gate is connected to the blown pin; When the digital signals received by each password register are all 1, the third AND gate outputs a high level signal to the pin blowen to enable the pin blowen.

5. The trimming circuit according to claim 4, wherein: The password register group is connected to an input terminal of a third AND gate; Another input terminal of the third AND gate is connected to the first pin clk, and another input terminal of the third AND gate is connected to the trimming data pin; One output end of the third AND gate is connected to the decoder, and the other output end is connected to the Blowen signal chip. The Blowen signal chip outputs the Blowen signal only when and only when receiving the high level signal sent by the third AND gate.

6. The trimming circuit according to claim 4, wherein: Also includes: A delay module is connected to the blowen pin and the register group. The delay module generates a reset signal to the reset interface of the register group based on the high and low level changes of the Blowen signal of the blowen pin, so that the password register is reset and the blowen pin is disabled.

7. The trimming circuit according to claim 6, wherein: The delay module includes: A voltage source Vdd, for supplying power to the delay module; The square wave signal generation module generates a square wave signal por after power-on; The pin por is connected to the reset interface of the register group to reset the register group.

8. A chip, characterized in that: The method comprises the trimming circuit according to any one of claims 1 to 6.

9. A chip adjustment method, characterized in that: The following steps are involved: The chip trimming circuit is configured as follows: the chip includes a protruding pin Vinn and a pin Vinp, and the chip trimming circuit includes: a converter connected to the pin Vinn and the pin Vinp; a first pin din and a first pin clk, respectively connected to two output terminals of the converter, wherein the first pin din outputs digital signal data and the first pin clk outputs clock signal data; a decoder including two input terminals and three output terminals, wherein the three output terminals include a second pin din, a second pin clk, and a pin blown, wherein the two input terminals are respectively connected to the first pin din and the first pin clk. The first register is connected to the second pin din and the second pin clk, receives the digital signal data and the clock signal data, processes them, and outputs them through the second pin din, the second pin clk, and the blowen pin, wherein either the second pin clk or the blowen pin is selectively enabled; a register group is powered by a voltage source VDD and includes n registers, wherein adjacent registers are connected end to end, and the first register is connected to the second pin din and the second pin clk to receive and store the digital signal data; a fuse group includes n fuses, each of the fuses is connected to a register, and the blowen pin is connected to the register group; When the pin blown sends a blown signal to the fuse connected to the register through the register, so that any fuse is blown, the digital signal data in the register connected to the blown fuse will be burned into the blown fuse to complete the trimming of the chip.

10. The adjustment method according to claim 9, wherein: The following steps are also included: The register group is further configured as follows: it includes m password registers; an input end of each password register is connected to the last register in the register group, and an output end is connected to a third AND gate, and an output end of the third AND gate is connected to a blown pin; when the digital signals received by each password register are all 1, the third AND gate outputs a high-level signal to the blown pin to enable the blown pin; The chip trimming circuit is configured as follows: it also includes a delay module, which is connected to the blowen pin and the register group. The delay module generates a reset signal to the reset interface of the register group based on the high and low level changes of the Blowen signal of the blowen pin, so that the password register is reset and the blowen pin is disabled.

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