Device cutting method, packaging method and application thereof

Abstract

The invention relates to the technical field of chips, in particular to a device cutting method, a packaging method and application thereof. The cutting method comprises the following steps: providing a wafer to be cut, arranging a wave-shaped cutting channel in a cutting area, and arranging a plurality of through holes in the cutting area according to the wave-shaped cutting channel; the line shape of the wave-shaped cutting channel is an arc line and / or a broken line; and cutting the wafer to be cut along the wave-shaped cutting channel, and cutting at least two adjacent chip areas into independent chip units. After the chip is cut by the cutting method, the cutting residual area at the edge of the chip is of a concave-convex structure, the convex part of the cutting residual area has a relatively large size, a plurality of through holes can be reasonably arranged, the cutting residual area at the edge of the chip is fully utilized, the utilization rate of the chip is improved, the integration density of the through holes of the chip is improved, and the chip yield is improved. The size of a subsequent packaging body is reduced, the packaging integration level is improved, and subsequent stacking, packaging and other operations are facilitated.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular relates to a device cutting method, a packaging method and applications thereof. Background Art

[0002] With the miniaturization and multifunctionalization of devices and terminal products, chip functions are becoming more and more complex and chip sizes are continuously shrinking. At present, the mode of driving technological progress by reducing the size of transistors is becoming more and more difficult. Advanced packaging technology is considered to be the most critical way to promote the continuous improvement of integrated circuit chip performance. Among them, high-density through-holes are the most important means to improve the interconnection density, such as through-silicon vias (TSV) or through-glass vias (TGV). Through-holes are usually arranged in the cutting residual area at the edge of the chip in the integration method. Compared with nano-level transistors, through-holes of several microns or even tens of microns are like "monsters", which greatly occupy the position of the chip and cause area waste. In addition, the filling metal of TSV is usually Cu, and the thermal expansion coefficient CTE matching effect of Cu and Si substrate is not good. It is usually necessary to design a KOZ area (Keep Out Zone, isolation area) to avoid potential reliability risks. The existence of the KOZ area further reduces the area utilization of the chip. In addition, the width of the chip cutting road is usually at the level of tens of microns. This area is an invalid use area of ​​the chip, which also causes a waste of chip area. Moreover, currently, chip cutting is mainly carried out by mechanical and laser cutting, and the shape of the cutting path is usually straight or rectangular. If large-sized TSV or TGV vias are arranged in the cutting path, due to the via size and the existence of the isolation area, the overall size of the straight cutting path is required to be larger, which cannot increase the utilization rate of the chip.

[0003] Therefore, how to increase the through-hole integration density within the effective chip area and improve the chip utilization is an urgent problem that needs to be solved. Summary of the invention

[0004] The purpose of the present application is to provide a device cutting method, a packaging method and their applications, aiming to solve the technical problems of low chip utilization and low chip through-hole integration density in existing cutting methods.

[0005] In order to achieve the above application purpose, the technical solution adopted in this application is as follows:

[0006] The first aspect of the present application provides a cutting method, comprising the following steps:

[0007] Providing a wafer to be cut, wherein the wafer to be cut comprises a plurality of chip regions and a cutting region, and two adjacent chip regions are separated by the cutting region;

[0008] A wavy cutting path is provided in the cutting area, and a plurality of through holes are arranged in the cutting area according to the wavy cutting path; the line shape of the wavy cutting path is an arc line and / or a broken line;

[0009] The wafer to be cut is cut along the wavy cutting road to cut at least two adjacent chip areas into independent chip units.

[0010] In such a cutting method, a wavy cutting path with an arc and / or a broken line is set in the cutting area between two adjacent chip areas, and after a plurality of through holes are arranged in the cutting area according to the wavy cutting path, the wafer to be cut is cut along the wavy cutting path. After cutting by this cutting method, the cutting residual area at the edge of the chip has a concave-convex structure, and the convex part of the cutting residual area has a relatively large size so that several through holes can be reasonably arranged, thereby improving the integration density of the chip through holes and facilitating the subsequent stacking, packaging and other operations of the chip unit. In this way, the cutting residual area at the edge of the chip is fully utilized, the utilization rate of the chip is improved, the waste of chip area is avoided, the size of the subsequent package body is reduced, and the packaging integration is improved. Furthermore, the wavy cutting path cutting method can be applied to chips with smaller cutting area sizes. Specifically, even if a small-sized cutting area is cut by the wavy cutting method, the wavy cutting path divides the small-sized cutting area into a concave-convex structure along the cutting path, so that the cutting residual area formed at the edge of two adjacent chips is a convex one by one. The convex cutting residual area still has a larger size, which can meet the space required for the layout of the through hole and the surrounding safety area. Moreover, large-sized through holes can also be laid out in the convex cutting residual area.

[0011] As some possible implementations of the cutting method of the present application, in the wavy cutting path, the center angle θ1 of the arc is 0°<θ1<180°. In this case, the center angle of the arc makes the cutting path extend in a wavy shape in the cutting area. At this time, the cutting residual area formed on the edge of the adjacent chip after cutting is correspondingly an alternating concave-convex structure, and the cutting residual area with the concave-convex structure is more conducive to the layout of the through hole. Thereby improving the utilization rate of the chip and the integration density of the through hole.

[0012] As some possible implementations of the cutting method of the present application, in the wavy cutting path, the fold angle θ2 of the fold line is 0°<θ2<180°. In this case, the fold angle of the fold line makes the cutting path extend in a wavy shape in the cutting area. At this time, the cutting residual area formed on the edge of the adjacent chip after cutting is correspondingly an alternating concave-convex structure, and the cutting residual area with the concave-convex structure is more conducive to the layout of the through hole. Thereby improving the utilization rate of the chip and the integration density of the through hole.

[0013] As some possible implementations of the cutting method of the present application, in the wavy cutting path, the radius r of the arc is 0<r<50μm. In this case, when the central angle of the arc in the wavy cutting path is constant, the larger the radius of the arc, the larger the area of ​​the cutting residual area of ​​the concave-convex structure formed on the edge of the chip after cutting according to the wavy cutting path with the arc shape, and the more through-hole arrays that can be accommodated. At this time, more through-holes can be arranged in the convex cutting residual area, which is conducive to improving the integration density of the through-holes.

[0014] As some possible implementations of the cutting method of the present application, along the wave propagation direction perpendicular to the wavy cutting road, the cutting area includes a first safety zone, a cutting road path zone, and a second safety zone arranged in sequence, the wavy cutting road is arranged in the cutting road path zone, and cutting is performed along the wavy cutting road in the cutting road path zone. Among them, the first safety zone and the second safety zone are directly connected to adjacent chips respectively, and are used to protect the chips and prevent the chips from being damaged during cutting. The cutting road path zone is the area specifically involved in the cutting of the wavy cutting road, and cutting is performed along the wavy cutting road in the cutting road path zone, and the cutting road path zone is cut into alternating concave and convex structures.

[0015] As some possible implementations of the cutting method of the present application, the width d of the cutting area = the width d0 of the cutting path area + the width d2 of the first safety area + the width d3 of the second safety area.

[0016] As some possible implementations of the cutting method of the present application, the linear shape of the wavy cutting path is an arc, and the relationship between the width d0 of the cutting path area and the center angle θ1 of the arc and the radius r of the arc satisfies: d0=2r(1-cosθ1). In this case, when the linear shape of the wavy cutting path is an arc, the width d0 of the cutting path area can be calculated according to the center angle θ1 of the arc and the radius r of the arc, and the center angle and radius of the arc of the wavy cutting path can also be reasonably set based on the relationship between the three.

[0017] As some possible implementations of the cutting method of the present application, the width d of the cutting area is 12μm to 70μm. In this case, due to the use of a wavy cutting path cutting method for cutting, the small-sized cutting area is divided into alternating concave-convex structures along the cutting path, so that the cutting residual area formed at the edges of two adjacent chips is a convexity, and the convex cutting residual area is still relatively large, which can meet the space required to be reserved for the layout of the through hole and its surrounding safety area.

[0018] As some possible implementations of the cutting method of the present application, the ratio d1 / d of the width d1 of the wavy cutting road to the width d of the cutting area is (0.02857-0.5): 1. In this case, the width of the wavy cutting road occupies a smaller space in the cutting area, and more space is reserved for the cutting residual area, which is beneficial to the subsequent layout of the through holes.

[0019] As some possible implementations of the cutting method of the present application, the width d1 of the wavy cutting road is 2 μm to 20 μm. The width of the wavy cutting road is related to the cutting method, and the width refers to the width of the cutting road formed by different cutting methods.

[0020] As some possible implementations of the cutting method of the present application, the ratio d2 / d of the width d2 of the first safety zone to the width d of the cutting area is 1: (5-10). In this case, the safety zone is reserved in the area at the edge of the chip to protect the chip from being damaged during cutting. The ratio of the width of the safety zone to the width of the cutting area can effectively protect the chip from being damaged during cutting, and the safety zone occupies a smaller space in the cutting area.

[0021] As some possible implementations of the cutting method of the present application, the ratio d3 / d of the width d3 of the second safety zone to the width d of the cutting area is 1: (5-10). In this case, the safety zone is reserved in the area at the edge of the chip to protect the chip from being damaged during cutting. The ratio of the width of the safety zone to the width of the cutting area can effectively protect the chip from being damaged during cutting, and the safety zone occupies a smaller space in the cutting area.

[0022] As some possible implementations of the cutting method of the present application, the width d2 of the first safety zone is 2 μm to 15 μm. In this case, the width of the safety zone fully ensures the safety of the chip during cutting and is conducive to cutting along the wavy cutting path.

[0023] As some possible implementations of the cutting method of the present application, the width d3 of the second safety zone is 2 μm to 15 μm. In this case, the width of the safety zone fully ensures the safety of the chip during cutting and is conducive to cutting along the wavy cutting path.

[0024] As some possible implementations of the cutting method of the present application, the ratio d1 / D of the width d1 of the wavy cutting road to the diameter D of the through hole is (0.1-5): 1. In this case, when the width of the cutting area is fixed, the smaller the width of the wavy cutting road, the more through holes can be arranged in the cutting area, and the larger the size of the through holes that can be arranged.

[0025] As some possible implementations of the cutting method of the present application, the diameter of the through hole is 1 μm to 10 μm. In this case, it can be a large-sized through hole with a large diameter to solve the problem of large-sized through hole layout, or it can be a small-sized through hole to improve the integration density of the through holes on the chip.

[0026] As some possible implementations of the cutting method of the present application, the depth of the through hole is 10 μm to 50 μm. In this case, the depth of the through hole can be selected to a suitable size according to the actual application.

[0027] As some possible implementations of the cutting method of the present application, an isolation region is provided around the through hole, and the width d5 ​​of the isolation region is 2 μm to 10 μm. In this case, the width of the isolation region is sufficient to protect the through hole, so as to prevent the through hole from causing stress to the active silicon region near the opening of the through hole and interfering with the operation of the circuit.

[0028] As some possible implementations of the cutting method of the present application, the ratio d4 / d5 of the spacing d4 between two adjacent through holes to the width d5 ​​of the isolation region is (1-4): 1. In this case, it is fully ensured that the spacing between two adjacent through holes at least meets the size of an isolation region, and d4 / d5 is (1-4): 1, which not only ensures the safety of the through holes and does not interfere with the circuit, but also helps to avoid excessive spacing between through holes and improve the layout density of through holes in the cutting area.

[0029] As some possible implementations of the cutting method of the present application, the ratio d4 / D of the spacing d4 between two adjacent through holes to the diameter D of the through hole is (1-2): 1. In this case, the ratio relationship between the spacing d4 between two adjacent through holes and the diameter D of the through hole is beneficial to both protecting the safety of the through hole and manufacturing the through hole.

[0030] As some possible implementations of the cutting method of the present application, the spacing d4 between two adjacent through holes is 2 μm to 20 μm. In this case, the spacing d4 between the two adjacent through holes ensures both the safety of the through holes and the integration density of the through holes in the cutting area.

[0031] As some possible implementations of the cutting method of the present application, the cutting process adopts at least one of dry etching, laser cutting, plasma cutting, and deep silicon etching. These cutting methods all have good cutting efficiency.

[0032] As some possible implementations of the cutting method of the present application, the through hole includes a through silicon via or a through glass via.

[0033] In a second aspect, the present application provides a packaging method, comprising the following steps:

[0034] Obtaining a clean base layer, and sequentially preparing a first insulating layer and a first redistribution layer on a surface of one side of the base layer;

[0035] Performing temporary bonding on a surface of the first redistribution layer away from the first insulating layer;

[0036] After thinning the surface of the base layer away from the first insulating layer, a wavy cutting path is provided in the cutting area of ​​the thinned surface of the base layer, and a plurality of through holes are prepared on the thinned surface according to the wavy cutting path; the line shape of the wavy cutting path is an arc line and / or a broken line;

[0037] Sequentially preparing a second insulating layer and a second rewiring layer on the surface of the base layer where the through hole is formed, to obtain a chip to be cut;

[0038] Cutting the chip to be cut along the wavy cutting path, and after debonding, obtaining a chip unit;

[0039] The chip units are stacked to obtain a chip package structure.

[0040] In the packaging method of the present application, after the first insulating layer and the first rewiring layer are prepared in sequence on the surface of the clean base layer, temporary bonding is performed, and then the base layer is thinned, and a wavy cutting path with arc and / or fold line is set in the cutting area of ​​the thinned surface, and a plurality of through holes are prepared on the thinned surface according to the wavy cutting path; then the second insulating layer and the second rewiring layer are prepared in sequence on the surface formed with the through holes to obtain the chip to be cut. The chip to be cut is cut along the wavy cutting path, and the bonding is debonded to obtain a chip unit, and the cutting residual area of ​​the concave-convex structure at the edge of the chip unit is arranged with through holes, and the layout of the through holes can improve the integration of the chip in the three-dimensional direction, that is, improve the packaging integration, which is conducive to the stacking of chip units to obtain a chip package structure.

[0041] As some possible implementations of the packaging method of the present application, the cutting process adopts the above-mentioned cutting method.

[0042] In a third aspect, the present application provides a chip unit, which is manufactured by cutting using the above-mentioned cutting method, or is packaged using the above-mentioned packaging method.

[0043] The chip unit of the present application is obtained by cutting using the above-mentioned cutting method, which makes full use of the cutting residual area at the edge of the chip, improves the integration density of the chip through-holes, improves the utilization rate of the chip, avoids the waste of chip area, reduces the size of the subsequent package body, is beneficial to the subsequent stacking, packaging and other operations of the chip unit, and improves the packaging integration. The cutting residual area at the edge of the chip unit is a concave-convex structure with through-holes, which is particularly suitable for packaging using the above-mentioned packaging method, improves the packaging integration, simplifies the operation process, reduces the packaging materials, and thus can also reduce costs, while also reducing the parasitics caused by the packaging, thereby improving the chip performance.

[0044] As some possible implementations of the chip unit of the present application, the chip unit includes external connection terminals, and the external connection terminals are used for interconnecting chips within the chip unit and / or for connecting external electronic devices.

[0045] As some possible implementations of the chip unit of the present application, the chip unit is a power semiconductor device chip, a power management chip or a battery management chip.

[0046] In a fourth aspect, the present application provides an electronic device, comprising the above-mentioned chip unit.

[0047] The electronic device of the present application includes the above-mentioned chip unit with high packaging integration, which is conducive to reducing the size of transistors and meeting the application requirements of miniaturized and multifunctional electronic devices.

[0048] As some possible implementations of the electronic device of the present application, the electronic device further includes a circuit board, and wiring in the circuit board interconnects the chips in the chip unit.

[0049] As some possible implementations of the electronic device of the present application, the electronic device also includes a circuit board, on which the chip unit and at least one electronic device are arranged, and the external connection terminals of the chip unit are electrically connected to the electronic device through wiring in the circuit board.

[0050] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a schematic diagram of the process of the cutting method provided in the embodiment of the present application;

[0052] Figure 2 is a schematic diagram of a wafer to be cut after cutting provided by an embodiment of the present application;

[0053] Figure 3 The embodiment of the present application provides a schematic diagram of a wavy cutting path with an arc shape. Figure 1 ;

[0054] Figure 4 This is a schematic diagram of the embodiment of the present application providing a wavy cutting path with a broken line. Figure 1 ;

[0055] Figure 5 The embodiment of the present application provides a schematic diagram of a wavy cutting path with an arc shape. Figure 2 ;

[0056] Figure 6 This is a schematic diagram of the embodiment of the present application providing a wavy cutting path with a broken line. Figure 2 ;

[0057] Figure 7 is a schematic diagram of an embodiment of the present application providing a wavy cutting path with a line shape including both an arc line and a broken line;

[0058] Figure 8 It is a schematic diagram of the influence of the radius of the arc on the layout of the through holes when the line shape of the wavy cutting road provided by the embodiment of the present application is an arc;

[0059] Fig. 9 The embodiment of the present application provides a schematic diagram of dividing the cutting area along the wave propagation direction perpendicular to the wavy cutting path;

[0060] Fig.10 Schematic diagram of the influence of the width of the wavy cutting lanes and the through-hole layout provided by the embodiment of the present application;

[0061] Fig.11 It is a schematic diagram of the influence of the diameter size of the through hole and the through hole layout provided in the embodiment of the present application;

[0062] Fig.12 is a schematic diagram of an isolation region of a through hole provided in an embodiment of the present application;

[0063] Fig.13 This is a schematic diagram of the packaging method provided in the embodiment of the present application. Figure 1 ;

[0064] Fig.14 This is a schematic diagram of the packaging method provided in the embodiment of the present application. Figure 2 .

[0065] Among them, the reference numerals in the figure are:

[0066] 110—chip area; 111—cutting residual area at the edge of the chip;

[0067] 120—cutting area; 121—first safety zone; 122—cutting path zone; 123—second safety zone;

[0068] 130—through hole; 131—isolation area. DETAILED DESCRIPTION

[0069] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0070] In this application, the term "and / or" describes the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0071] In this application, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, "at least one of a, b, or c", or "at least one of a, b, and c" can all mean: a, b, c, ab (i.e., a and b), ac, bc, or abc, where a, b, c can be single or multiple, respectively.

[0072] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution, some or all of the steps can be executed in parallel or sequentially, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0073] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0074] The term "scribe line" is called "scribe line" in English. Chip cutting refers to separating multiple chips on the wafer to be cut so that a single chip can be pasted, bonded, and other operations can be performed in subsequent packaging. The cut part is the scribe line.

[0075] The term "TSV" is an abbreviation for "Through-Silicon Via", which means through-silicon via, which is the latest technology to interconnect chips by making vertical conductions between chips and wafers. TSV technology achieves vertical electrical interconnection of through-silicon vias by filling conductive materials such as copper, tungsten, and polysilicon. It can maximize the density of chip stacking in the three-dimensional direction, minimize the interconnection lines between chips, and minimize the external dimensions, significantly improve chip speed, and reduce chip power consumption. Therefore, it has become one of the most eye-catching technologies in current electronic packaging technology. This technology is currently the main vertical electrical interconnection technology and one of the key technologies to achieve 3D advanced packaging.

[0076] The term "KOZ" is an abbreviation for "keep out zone", which means an isolation zone. TSV will bring stress to the active silicon area near the via opening, which may interfere with the operation of the circuit. This requires setting an isolation zone in the TSV hole, that is, an area surrounding a TSV where no active circuit can be inserted.

[0077] The term "TGV" is an abbreviation for "Through-Glass Via", which means through-glass via, which is a vertical electrical interconnection that passes through a glass substrate. Corresponding to TSV, it is a material that may replace silicon substrates. Through-glass via TGV technology is considered to be a key technology for the next generation of three-dimensional integration, and the core of this technology is the deep hole formation method.

[0078] The term "packaging technology" refers to a technology that packages integrated circuits with insulating plastic or ceramic materials.

[0079] At present, the stages of chip manufacturing process mainly include: manufacturing crystal rods → producing wafers → wafer coating → wafer development and etching → doping → wafer needle testing → cutting, packaging → testing → completion. Among them, in the cutting stage, it is necessary to separate multiple chips along the cutting road between two adjacent chips, so as to paste and bond the single chip in the subsequent packaging. When the wafer is cut, the width of the chip remaining at the edge of the chip after cutting along the cutting road is usually at the level of tens of microns. This area is the cutting residual area at the edge of the chip, resulting in a waste of chip area. In addition, the current processing methods for chip cutting roads are mainly through mechanical blade cutting, laser cutting, plasma cutting and deep silicon etching, and these cutting methods will form a wider cutting road, and can only be cut into a rectangular or straight line, resulting in a narrow cutting residual area at the edge of the chip, which is difficult to further use in the future, forming an invalid use area.

[0080] From the perspective of the development of the market situation, with the miniaturization and multifunctionalization of devices and terminal products, chip functions are becoming more and more complex and chip sizes are also shrinking. At present, the mode of driving technological progress by reducing the size of transistors is becoming more and more difficult. Advanced packaging technology is considered to be the most critical way to promote the continuous improvement of integrated circuit chip performance. Among them, high-density through-holes are the most important means to improve the interconnection density. Currently, through-holes include through-silicon vias (TSV) or through-glass vias (TGV). Through advanced packaging, the integration of electronic components can be greatly improved, and the geometric size and weight of the package can be reduced. Overcome the shortcomings of the existing 2D-SIP (System Ina Package, two-dimensional system-level packaging) and PoP (Package on Package, three-dimensional packaging stacking) systems to meet the requirements of microelectronic products for multifunctionality and miniaturization. In addition, since through-hole technologies such as TSV or TGV can greatly shorten the length of electrical interconnections, it can well solve problems such as signal delay in SOC (two-dimensional system-on-chip) technology and improve electrical performance. In addition, through TSV interconnection, different functional chips (such as RF, memory, logic, digital and MEMS, etc.) can be integrated together to realize the multi-function of electronic components.

[0081] In the integration method, TSV or TGV is usually arranged in the cutting residual area at the edge of the chip. After arranging TSV or TGV in the cutting residual area at the edge of the chip, the cutting residual area is converted into an effective area. Compared with nano-level transistors, TSV or TGV of several microns or even tens of microns is like a "giant", which greatly occupies the position of the chip and causes a waste of area. In addition, the filling metal of TSV is usually Cu, and the thermal expansion coefficient CTE matching effect of Cu and Si substrate is not good. It is usually necessary to design a KOZ isolation area to avoid potential reliability risks. The existence of the KOZ area further reduces the area utilization of the chip. Therefore, due to the size of through holes such as TSV or TGV and the need to design the KOZ area of ​​TSV in order to avoid reliability risks, the utilization rate of the chip is greatly reduced. In addition, the current chip cutting road width is usually at the level of tens of microns. This area is an invalid use area of ​​the chip, which also causes a waste of chip area. Moreover, chip cutting is currently mainly carried out by mechanical and laser cutting, and the shape of the cutting road is usually straight or rectangular. For the currently common straight cutting paths, within the small-sized cutting area (12 to 70 μm), the cutting residue area at the edge of the chip after cutting along the straight cutting path is narrow, and TSV cannot be laid out. If through holes such as SV or TGV are to be laid out in the straight cutting path, especially if large-sized through holes are to be laid out in the cutting path, due to the size of the through hole itself and the existence of the isolation area, this requires the overall size of the straight cutting path to be larger. This also cannot increase the utilization rate of the chip. Without occupying the effective area of ​​the chip, how to improve the utilization rate of the cutting residue area at the edge of the chip within the effective chip area and increase the integration density of through holes such as TSV or TGV on the chip is a problem that needs to be solved urgently. In particular, it is necessary to realize the layout of large-sized through holes such as TSV or TGV by utilizing the invalid area of ​​the chip (such as the cutting residue area at the edge).

[0082] In some known technologies, the connection terminals are connected through TSV in the cutting line, and conductive materials such as solder balls are filled in the TSV, and finally the connection terminals and TSV holes are cut into two parts, and the cutting line is straight. The connection terminals are laid out through TSV in the cutting line, mainly for solder conductive filling. However, this solution will destroy the TSV holes when the chip is cut; since the filling is mainly solder, the size of the TSV hole is relatively large (millimeter level), and the number of connection terminals that can be laid out in the cutting line is small. In addition, for straight cutting lines, if TSV is laid out in the cutting path, since the chip edge safety zone and KOZ zone required for the layout of TSV are relatively large, this requires a larger size of the cutting line, which will cause a waste of chip area; it is impossible to improve the utilization rate of the invalid use area of ​​the chip in this way, nor can it improve the chip TSV integration density.

[0083] Based on the above considerations, in order to improve the utilization of chips, increase the density of chip through-hole integration, and especially realize the layout of through-holes such as large-size TSV or TGV in chips, etc. After in-depth research, a cutting method is proposed, in which a wavy cutting path with a line shape of an arc and / or a fold line is set in the cutting area between two adjacent chip areas of the wafer to be cut, and then a plurality of through-holes are arranged in the cutting area according to the wavy cutting path; and then the wafer to be cut is cut along the wavy cutting path, and at least two adjacent chip areas are cut into independent chip units.

[0084] In such a cutting method, a wavy cutting path with an arc and / or a broken line is set in the cutting area between two adjacent chip areas, and after a plurality of through holes are arranged in the cutting area according to the wavy cutting path, the wafer to be cut is cut along the wavy cutting path. After cutting by this cutting method, the cutting residual area at the edge of the chip has a concave-convex structure, and the convex part of the cutting residual area has a relatively large size, which can reasonably arrange several through holes, thereby improving the integration density of the chip through holes and facilitating the subsequent stacking, packaging and other operations of the chip unit. In this way, the cutting residual area at the edge of the chip is fully utilized, the utilization rate of the chip is improved, the waste of chip area is avoided, the size of the subsequent package body is reduced, and the packaging integration is improved. Moreover, the cutting method of the wavy cutting road can be applied to chips with smaller cutting area sizes. Specifically, even if a small-sized cutting area is cut by the wavy cutting method, the wavy cutting road divides the small-sized cutting area into a concave-convex structure along the cutting road, so that the cutting residual area formed at the edge of two adjacent chips is a convexity. The convex cutting residual area still has a large size, which can meet the space required to reserve for the layout of through holes and the safety area around them. Moreover, large-sized through holes can also be arranged in the convex cutting residual area. However, if a straight-line cutting method is adopted, the space occupied by the width of the cutting road itself causes the cutting residual area at the edges of the two adjacent chips to be very narrow after the small-sized cutting area is cut by the straight-line cutting method, which cannot meet the safety space required to reserve for the layout of through holes and their surroundings. Therefore, it is difficult to arrange through holes in the cutting residual area at the edge of the chip using the straight-line cutting method in the small-sized cutting area.

[0085] For ease of understanding, the present application is specifically described by the following examples. It should be understood that the following examples are only used to further illustrate the present application scheme and are not used to limit the scope of the present application.

[0086] First, as Figure 1 As shown, the embodiment of the present application provides a cutting method, comprising the following steps:

[0087] S10. Providing a wafer to be cut, the wafer to be cut includes a plurality of chip regions 110 and a cutting region 120, and two adjacent chip regions 110 are separated by the cutting region 120;

[0088] S20. A wavy cutting path is provided in the cutting area 120, and a plurality of through holes 130 are arranged in the cutting area 120 according to the wavy cutting path; the line shape of the wavy cutting path is an arc and / or a fold line;

[0089] S30 . Cut the wafer to be cut along the wavy cutting road, and cut at least two adjacent chip areas 110 into independent chip units.

[0090] Thus, the cutting method provided in the embodiment of the present application, the wafer to be cut, as shown in the attached Figure 2 As shown, it includes multiple chip areas 110, and a cutting area 120 is between two adjacent chip areas 110, and the two adjacent chip areas 110 are separated by the cutting area 120; after a wavy cutting path with an arc and / or a fold line is set in the cutting area 120 between the two adjacent chip areas 110, a plurality of through holes 130 are arranged in the cutting area 120 according to the wavy cutting path, and then the wafer to be cut is cut along the wavy cutting path, and at least two adjacent chip areas 110 are cut into independent chip units. On the one hand, after cutting by this cutting method, the cutting residual area 111 at the edge of two adjacent chips presents an alternating concave-convex structure, and the convex part of the cutting residual area 111 has a relatively large size, so that several through holes 130 can be reasonably arranged, as shown in the attached Figure 2 As shown, the integration density of the chip through hole 130 is improved, which is beneficial to the subsequent stacking, packaging and other operations of the chip unit. Therefore, the cutting residual area 111 at the edge of the chip is fully utilized, the utilization rate of the chip is improved, the waste of chip area is avoided, the size of the subsequent package body is reduced, and the package integration is improved. On the other hand, the cutting method of the wavy cutting road can be applied to chips with a smaller cutting area 120. Specifically: even if the small-sized cutting area 120 is cut by the wavy cutting method, the small-sized cutting area 120 is divided into alternating concave-convex structures along the cutting road due to the setting of the wavy cutting road, so that the cutting residual area 111 formed at the edge of two adjacent chips is a convex one by one, and the convex cutting residual area 111 still has a large size, which can meet the space required to be reserved for the layout of the through hole 130 and its surrounding safety area. In addition, a larger-sized through hole 130 can also be arranged in the convex cutting residual area 111 to realize the layout of the large-sized through hole 130 in the chip, solving the problem of the layout of the large-sized through hole 130. The cutting residual area 111 of the chip unit is fully utilized to improve the utilization rate of the chip, so as to meet the application scenario requirements of large-size through-hole 130 packaging, make the chip packaging structure more compact, improve the packaging density, and reduce the size and cost of the package body.

[0091] In contrast, if a linear cutting method is used to cut the small-size cutting area 120, due to the small size of the cutting area 120 and the width of the cutting path itself will occupy a certain space in the cutting area 120, after the small-size cutting area 120 is cut in a linear cutting method, the cutting residual area 111 at the edges of two adjacent chips is very narrow and cannot meet the space required for the layout of the through hole 130 and its surrounding safety area. Therefore, if a linear cutting method is used for the small-size cutting area 120, it is difficult to layout the through hole 130 in the cutting residual area 111 at the edge of the chip.

[0092] In the above step S10, the wafer to be cut is provided, as shown in the attached Figure 2 As shown, the wafer to be cut includes a plurality of chip regions 110 and cutting regions 120 , and two adjacent chip regions 110 are separated by the cutting region 120 .

[0093] In some possible implementations, the substrate of the wafer to be cut may be a silicon substrate or a glass substrate.

[0094] In some possible implementations, the plurality of chip regions 110 on the wafer to be cut may be arranged in a regular array, in which case the width of the cutting region 120 between two adjacent chip regions 110 is the same. In addition, the plurality of chip regions 110 on the wafer to be cut may also be arranged irregularly, in which case the width of the cutting region 120 between two adjacent chip regions 110 is the same or different.

[0095] In the above step S20, a wavy cutting path is set in the cutting area 120, and the line shape of the wavy cutting path is an arc and / or a broken line. The arc refers to a plane curve, which is a section between two points on a circle and includes two end points. Figure 3 A polyline is a geometric figure, which is composed of several line segments that are not all on the same straight line. Each line segment is called an edge or node of the polyline, and the endpoints of each line segment are called vertices of the polyline. Two adjacent vertices are called adjacent vertices. Figure 4 shown.

[0096] In some possible implementations, in the wavy cutting path, the center angle θ1 of the arc is 0°<θ1<180°. Figure 3As shown. Exemplarily, in the wavy cutting path, the central angle θ1 of the arc can be 1° to 179°, 10° to 170°, 20° to 160°, 30° to 150°, 40° to 140°, 50° to 130°, 60° to 120°, 70° to 110°, 80° to 100°, 90° to 100°, 30° to 150°, 30° to 60°, 40° to 70°, 50° to 100°, 60° to 120°, 70° to 160°, 80° to 175°, 30° to 90°, 60° to 150°, etc.

[0097] In some possible implementations, in the wavy cutting path, the folding angle θ2 of the folding line is 0°<θ2<180°, as shown in the attached Figure 4 As shown. Exemplarily, in the wavy cutting path, the fold angle θ2 of the fold line can be 1° to 179°, 10° to 170°, 20° to 160°, 30° to 150°, 40° to 140°, 50° to 130°, 60° to 120°, 70° to 110°, 80° to 100°, 90° to 100°, 30° to 150°, 30° to 60°, 40° to 70°, 50° to 100°, 60° to 120°, 70° to 160°, 80° to 175°, 30° to 90°, 60° to 150°, etc.

[0098] In the above embodiment, the cutting path extends in a wave shape in the cutting area 120 through the central angle of the arc or the folding angle of the folding line. At this time, the cutting residual area 111 formed at the edge of the adjacent chips after cutting is correspondingly an alternating concave-convex structure, and the cutting residual area 111 with the concave-convex structure is more conducive to the layout of the through hole 130. Thereby, the utilization rate of the chip is improved, and the integration density of the through hole 130 is improved.

[0099] In some possible implementations, in the wavy cutting path, as shown in the attached Figure 3 As shown in FIG. 1 , the radius r of the arc is 0<r<50μm. In this case, as shown in FIG. Figure 8As shown, when the parameters such as the width of the cutting area 120, the width of the first safety zone 121, the width of the second safety zone 123, the width of the cutting path, and the center angle of the arc in the wavy cutting path are the same, the larger the radius of the arc, the larger the area of ​​the cutting residual area 111 with a concave-convex structure formed at the edge of the chip after cutting according to the wavy cutting path with an arc shape, and the more arrays of through holes 130 that can be accommodated. At this time, more through holes 130 can be arranged in the raised cutting residual area 111, which is conducive to improving the integration density of the through holes 130. When the radius of the arc is constant, the larger the center angle of the arc, the greater the fluctuation of the concave-convex structure of the cutting residual area 111 formed at the edge of the chip after cutting, which is also conducive to arranging more through holes 130 in the raised cutting residual area 111, and improving the integration density of the through holes 130. Exemplarily, the radius r of the arc can be 1μm to 50μm, 5μm to 45μm, 10μm to 40μm, 15μm to 35μm, 20μm to 30μm, 5μm to 10μm, 10μm to 20μm, 30μm to 40μm, 40μm to 50μm, 25μm to 35μm, 35μm to 45μm, etc.

[0100] In some possible implementations, in the wavy cutting path, the central angle θ1 of the arc is 30°<θ1<150°, and the radius r of the arc is 0<r<50μm. In this case, after cutting along the wavy cutting path of the arc, the cutting residual area 111 of the raised structure formed at the edge of the chip is conducive to the layout of the through hole 130 and improves the integration density of the through hole 130.

[0101] In some possible embodiments, when the line shape of the wavy cutting path is a broken line, when the length of the line segment in the broken line is constant, the bending angle θ2 is within a certain range, and the larger the bending angle of the broken line is, the smaller and smoother the fluctuation of the concave-convex structure of the cutting residual area 111 formed at the edge of the chip after cutting according to the wavy cutting path with a broken line shape; the larger the bending angle of the broken line is, the larger the fluctuation of the concave-convex structure of the cutting residual area 111 formed at the edge of the chip after cutting according to the wavy cutting path with a broken line shape, and at this time, more through holes 130 can be arranged in the raised cutting residual area 111, which is more conducive to improving the integration density of the through holes 130.

[0102] In some possible implementations, the fold angle θ2 of the fold line in the wavy cutting path is 30°<θ2<150°. In this case, after cutting along the wavy cutting path in the fold line shape, the cutting residual area 111 of the raised structure formed at the edge of the chip is conducive to the layout of the through hole 130 and improves the integration density of the through hole 130.

[0103] The embodiment of the present application does not specifically limit the specific shape and size of the wavy cutting road. In actual application, any wavy cutting road that meets the application requirements can be set in the cutting area 120.

[0104] In some possible implementations, the wavy cutting paths provided in the cutting area 120 divide the entire cutting area 120 into cutting residual areas 111 with a concave-convex structure of appropriate size as much as possible.

[0105] In some possible implementations, when the line shape of the wavy cutting road is a broken line, the shape of the cutting residual area 111 of the protruding structure formed on the edge of the chip after cutting can be an irregular shape such as a triangle, a quadrilateral, or a polygon.

[0106] In some possible implementations, the wavy cutting path only includes arc-shaped propagation bands, and the center angle and radius of the arc-shaped bands at each stage may be the same, as shown in the attached Figure 3 As shown; the central angle and radius of the arc-shaped bands in each stage can also be different, as shown in the attached Figure 5 When the center angle and radius of the arc-shaped wave bands at each stage are the same, the wavy cutting path is a regular shape; when the center angle and radius of the arc-shaped wave bands at each stage are different, the wavy cutting path is an irregular shape.

[0107] In some possible implementations, the wavy cutting path only includes a zigzag propagation waveband, and the fold angle and line segment length of the zigzag waveband at each stage may be the same, as shown in the attached Figure 4 As shown in the figure; the folding angle and line length of the broken line bands in each stage can also be different, as shown in the figure Figure 6 When the fold angles and line segments of the zigzag wave segments at each stage are the same, the zigzag cutting path is a regular shape; when the fold angles and line segments of the zigzag wave segments at each stage are different, the zigzag cutting path is an irregular shape.

[0108] In some possible implementations, the wavy cutting path may include propagation bands that are both arcs and folds, as shown in the attached figure. Figure 7 As shown, the central angle and radius of the arc-shaped wave bands in each stage can be the same or different, and the fold angle and line segment length of the fold line wave bands in each stage can be the same or different.

[0109] In some possible implementations, multiple through holes 130 are arranged in the cutting area 120 according to the wavy cutting road, that is, the through holes 130 are arranged in the cutting residual area 111 according to the shape and size of the cutting residual area 111 formed at the edge of the chip after the wavy cutting road is cut in the cutting area 120. The cutting residual area 111 formed at the edge of the chip after the wavy cutting road is cut is a concave-convex structure, and the convex part has a relatively large size, so that several through holes 130 can be reasonably arranged, which improves the integration density of the chip through holes 130, and is beneficial to the subsequent stacking, packaging and other operations of the chip unit.

[0110] In some possible implementations, when the substrate of the wafer to be cut is a silicon substrate, the layout of the through hole 130 is a TSV silicon through hole 130; when the substrate of the wafer to be cut is a glass substrate, the layout of the through hole 130 is a TGV glass through hole 130. Among them, TSV realizes direct interconnection between chips by making vertical through holes 130 between chips and chips, and between wafers. It can maximize the density of chip stacking in the three-dimensional direction, minimize the interconnection lines between chips, and minimize the external dimensions, significantly improve chip speed, and reduce chip power consumption, so it has become one of the most eye-catching technologies in current electronic packaging technology. However, silicon is a semiconductor material with poor electrical properties. The carriers around TSV can move freely under the action of electric or magnetic fields. When transmitting signals, the signal has a strong electromagnetic coupling effect with the substrate material, and eddy currents are generated in the substrate, resulting in poor signal integrity (insertion loss, crosstalk, etc.), affecting chip performance. Glass materials do not have freely moving charges, have excellent dielectric properties, and have a coefficient of thermal expansion (CTE) close to that of silicon. The Through Glass Via (TGV) technology, which uses glass to replace silicon materials, can avoid the problem of TSV and is an ideal three-dimensional integration solution. In addition, TGV technology does not require the production of an insulating layer, reducing operational complexity and processing costs. TGV and related technologies have broad application prospects in the fields of optical communications, radio frequency, microwaves, micro-electromechanical systems, microfluidic devices, and three-dimensional integration.

[0111] In some possible implementations, as shown in the attached Fig. 9 As shown, along the wave propagation direction perpendicular to the wavy cutting path, the cutting area 120 includes a first safety zone 121, a cutting path zone 122, and a second safety zone 123 arranged in sequence, and the wavy cutting path is set in the cutting path zone 122, and cutting is performed along the wavy cutting path in the cutting path zone 122. Among them, the first safety zone 121 and the second safety zone 123 are directly connected to the adjacent chips respectively, and are used to protect the chips and prevent the chips from being damaged during cutting. Among them, the cutting path zone 122 is the area specifically involved in the wavy cutting path during cutting, and cutting is performed along the wavy cutting path in the cutting path zone 122, and the cutting path zone 122 is cut into an alternating concave and convex structure.

[0112] In some possible implementations, along the wave propagation direction perpendicular to the wavy cutting road, the width d of the cutting area 120 = the width d0 of the cutting road path area 122 + the width d2 of the first safety area 121 + the width d3 of the second safety area 123, that is, d = d0 + d2 + d3. The width of the cutting road path area 122 is the height difference between the wave crest and the wave trough in the wavy cutting road.

[0113] In some possible implementations, the linear shape of the wavy cutting road is an arc, and the relationship between the width d0 of the cutting road path area 122 and the central angle θ1 of the arc and the radius r of the arc satisfies: d0=2r(1-cosθ1). In this case, when the linear shape of the wavy cutting road is an arc, the width d0 of the cutting road path area 122 can be calculated according to the central angle θ1 of the arc and the radius r of the arc, and the central angle and radius of the arc of the wavy cutting road can also be reasonably set based on the relationship between the three.

[0114] In some possible implementations, the width d of the cutting area 120 is 12 μm to 70 μm. That is, the cutting area 120 between two adjacent chips is not higher than 70 μm, which belongs to a small-sized cutting area 120. In this case, due to the use of a wavy cutting road cutting method for cutting, the small-sized cutting area 120 is divided into alternating concave-convex structures along the cutting road, so that the cutting residual area 111 formed at the edge of two adjacent chips is a convexity. The convex cutting residual area 111 still has a large size, which can meet the space required to reserve for the layout of the through hole 130 and its surrounding safety area. In addition, since the cutting residual area 111 of the convex structure has a relatively large size, a larger-sized through hole 130 can also be arranged in the convex cutting residual area 111, so as to realize the layout of the large-sized through hole 130 in the chip and solve the problem of the layout of the large-sized through hole 130. However, if a straight cutting path is used, the through hole 130 can only be arranged on both sides of the straight cutting path, and the width of the cutting path itself will occupy a certain space in the cutting area 120, resulting in that after the small-sized cutting area 120 is cut in a straight-line cutting manner, the cutting residual area 111 at the edges of two adjacent chips is very narrow, and cannot meet the space required for the layout of the through hole 130 and its surrounding safety area. Therefore, if a straight-line cutting method is used in the small-sized cutting area 120, it is difficult to layout the through hole 130 in the cutting residual area 111 at the edge of the chip.

[0115] In some possible implementations, the ratio d1 / d of the width d1 of the wavy cutting road to the width d of the cutting area 120 is (0.02857-0.5): 1. The width of the wavy cutting road refers to the width that the cutting method needs to occupy / use when cutting along the wavy cutting road. Therefore, the width of the wavy cutting road is related to the cutting method, and the width belongs to a fixed loss space in the cutting area 120. Therefore, the narrower the width of the wavy cutting road, the smaller the loss space in the cutting area 120, and the larger the cutting residual area 111 formed at the edge of the chip, which is more conducive to the layout of the through hole 130 in the cutting residual area 111. As shown in the attached figure Fig.10As shown, when the parameters such as the width of the cutting area 120, the width of the first safety zone 121, the width of the second safety zone 123, the diameter of the through hole 130, and the linear shape of the wavy cutting road are the same, the narrower the road width of the wavy cutting road, the more through holes 130 can be arranged in the cutting residual area 111. The ratio d1 / d of the road width d1 of the wavy cutting road to the width d of the cutting area 120 in the embodiment of the present application makes the road width of the wavy cutting road occupy a smaller space in the cutting area 120, and reserves more space for the cutting residual area 111, which is conducive to the subsequent arrangement of the through holes 130. Exemplarily, the ratio d1 / d of the width d1 of the wavy cutting road to the width d of the cutting area 120 can be (0.02857~0.03): 1, (0.03~0.04): 1, (0.04~0.05): 1, (0.05~0.06): 1, (0.06~0.07): 1, (0.07~0.08): 1, (0.08~0.09): 1, (0.1~0.15): 1, (0.15~0.2): 1, (0.2~0.25): 1, (0.25~0.3): 1, (0.3~0.35): 1, (0.35~0.4): 1, (0.4~0.45): 1, (0.45~0.5): 1, etc.

[0116] In some possible implementations, the width d1 of the wavy cutting path is 2 μm to 20 μm. The width of the wavy cutting path in the embodiment of the present application is related to the cutting method, and the width refers to the width of the cutting path formed by different cutting methods. In practical applications, the width of the cutting path adapted to the cutting area 120 is determined according to the width of the cutting area 120, and then the corresponding cutting method is selected to cut along the wavy cutting path. Exemplarily, the width d1 of the wavy cutting road can typically but not limitatively be 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, etc., or the width d1 of the wavy cutting road can be any value or interval value between 2μm and 20μm, such as 2μm to 5μm, 5μm to 10μm, 10μm to 15μm, 15μm to 20μm, etc.

[0117] In some possible implementations, when the width d of the cutting area 120 is 12 μm to 70 μm and the ratio d1 / d of the width d1 of the wavy cutting road to the width d of the cutting area 120 is (0.02857 to 0.5): 1, the width d1 of the wavy cutting road is 2 μm to 20 μm. In this case, ensure that the width of the cutting road path area 122 is adapted to the width of the cutting road.

[0118] In some possible implementations, the ratio d2 / d of the width d2 of the first safety zone 121 to the width d of the cutting area 120 is 1:(5-10). In this case, the safety zone is reserved in the area at the edge of the chip to protect the chip from being damaged during cutting. The ratio of the width of the safety zone to the width of the cutting area 120 can effectively protect the chip from being damaged during cutting, and the safety zone occupies a smaller space in the cutting area 120, thereby reserving more cutting space for the wavy cutting road, which is more conducive to the setting and cutting of the wavy cutting road. After cutting, a larger raised cutting residual area 111 is formed at the edge of the chip, which is more conducive to the layout of the through hole 130. Exemplarily, the ratio d2 / d of the width d2 of the first safety zone 121 to the width d of the cutting area 120 can typically but not limitatively be 1:5, 1:6, 1:7, 1:8, 1:9, 1:10, etc.; or it can be any interval value between 1:(5~10), such as 1:(5~6), 1:(6~7), 1:(7~8), 1:(8~9), 1:(9~10), etc.

[0119] In some possible implementations, the width d2 of the first safety zone 121 is 2μm to 15μm. In this case, the width of the safety zone fully ensures the safety of the chip during cutting, and is conducive to cutting along the wavy cutting path. Exemplarily, the width d2 of the first safety zone 121 can be typically but not limited to 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, etc., or the width d2 of the first safety zone 121 can be any value or interval between 2μm and 15μm, such as 2μm to 3μm, 3μm to 5μm, 5μm to 7μm, 7μm to 10μm, 10μm to 12μm, 12μm to 13μm, 13μm to 15μm, etc.

[0120] In some possible implementations, the ratio d3 / d of the width d3 of the second safety zone 123 to the width d of the cutting area 120 is 1:(5-10). In this case, the safety zone is reserved in the area at the edge of the chip to protect the chip from being damaged during cutting. The ratio of the width of the safety zone to the width of the cutting area 120 can effectively protect the chip from being damaged during cutting, and the safety zone occupies a smaller space in the cutting area 120, thereby reserving more cutting space for the wavy cutting road, which is more conducive to the setting and cutting of the wavy cutting road. After cutting, a larger raised cutting residual area 111 is formed at the edge of the chip, which is more conducive to the layout of the through hole 130. Exemplarily, the ratio d3 / d of the width d2 of the second safety zone 123 to the width d of the cutting area 120 can typically but not limitatively be 1:5, 1:6, 1:7, 1:8, 1:9, 1:10, etc.; or it can be any interval value between 1:(5~10), such as 1:(5~6), 1:(6~7), 1:(7~8), 1:(8~9), 1:(9~10), etc.

[0121] In some possible implementations, the width d3 of the second safety zone 123 is 2μm to 15μm. In this case, the width of the safety zone fully ensures the safety of the chip during cutting, and is conducive to cutting along the wavy cutting path. Exemplarily, the width d3 of the second safety zone 123 can be typically but not limited to 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, etc., or the width d3 of the second safety zone 123 can be any value or interval between 2μm and 15μm, such as 2μm to 3μm, 3μm to 5μm, 5μm to 7μm, 7μm to 10μm, 10μm to 12μm, 12μm to 13μm, 13μm to 15μm, etc.

[0122] In some possible implementations, the ratio d1 / D of the width d1 of the wavy cutting road to the diameter D of the through hole 130 is (0.1-5):1. In this case, when the width of the cutting area 120 is fixed, the smaller the width of the wavy cutting road, the more through holes 130 can be arranged in the cutting area 120, and the larger the size of the through holes 130 that can be arranged. In addition, the smaller the diameter of the through hole 130, the more through holes 130 can be arranged in the cutting area 120, and the larger the diameter of the through hole 130, the fewer the through holes 130 that can be arranged in the cutting area 120. In the case of this ratio of the width d1 of the wavy cutting road to the diameter D of the through hole 130, it is beneficial to arrange large or small sized through holes 130 in the cutting area 120. Exemplarily, the ratio d1 / D of the width d1 of the wavy cutting road to the diameter D of the through hole 130 can be typically but not limitatively (0.1~0.5):1, (0.5~1.0):1, (1.0~1.5):1, (1.5~2):1, (2~2.5):1, (2.5~3):1, (3~3.5):1, (3.5~4):1, (4~4.5):1, (4.5~5):1, etc.

[0123] In some possible implementations, the diameter of the through hole 130 is 1 μm to 10 μm; in this case, it can be a large-sized through hole 130 with a large diameter to solve the layout problem of the large-sized through hole 130, or it can be a small-sized through hole 130 to improve the integration density of the through holes 130 on the chip. Fig.11 As shown, when the parameters such as the width of the cutting area 120, the width of the cutting road, the width of the first safety zone 121, the width of the second safety zone 123, and the linear shape of the wavy cutting road are the same, the smaller the diameter of the through hole 130, the more through holes 130 can be arranged. Exemplarily, the diameter of the through hole 130 can be typically but not limited to 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc., or the diameter of the through hole 130 can be any value or interval value between 1μm and 10μm, such as 1μm to 2μm, 2μm to 3μm, 3μm to 5μm, 5μm to 7μm, 7μm to 10μm, etc.

[0124] In some possible implementations, the depth of the through hole 130 is 10 μm to 50 μm. In this case, the depth of the through hole 130 can be selected according to the actual application. When the thickness of the wafer to be cut is high, the depth of the prepared through hole 130 is deep, and when the thickness of the wafer to be cut is low, the depth of the prepared through hole 130 is low. Exemplarily, the depth of the through hole 130 can be typically but not limited to 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc.; or the depth of the through hole 130 can be any value or interval value between 10 μm and 50 μm, such as 10 μm to 20 μm, 20 μm to 30 μm, 30 μm to 40 μm, 40 μm to 50 μm, etc.

[0125] In some possible implementations, an isolation region 131 is disposed around the through hole 130, and the width d5 ​​of the isolation region 131 is 2 μm to 10 μm. Fig.12 As shown, D is the diameter of the through hole 130, and d5 is the width of the isolation region 131. In this case, the width of the isolation region 131 is sufficient to protect the through hole 130, so as to prevent the through hole 130 from causing stress to the active silicon region near the opening of the through hole and interfering with the operation of the circuit. Exemplarily, the width d5 ​​of the isolation region 131 can be typically but not limited to 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc., or any value or interval between 2μm and 10μm, such as 2μm to 3μm, 3μm to 5μm, 5μm to 7μm, 7μm to 10μm, etc.

[0126] In some possible implementations, the ratio d4 / d5 of the spacing d4 between two adjacent through holes 130 to the width d5 ​​of the isolation region 131 is (1-4):1. In this case, it is fully ensured that the spacing between two adjacent through holes 130 at least meets the size of one isolation region 131, thereby ensuring that there is no interference with the circuit and ensuring the safety of the through holes 130. d4 / d5 being (1-4):1 not only ensures the safety of the through holes 130 and does not interfere with the circuit, but also helps to avoid excessive spacing between the through holes 130 and improve the layout density of the through holes 130 in the cutting area 120. Exemplarily, the ratio d4 / d5 of the spacing d4 between two adjacent through holes 130 to the width d5 ​​of the isolation region 131 can be (1-2):1, (2-3):1, (3-4):1, (2-4):1, (1-3):1, etc.

[0127] In some possible implementations, the ratio d4 / D of the spacing d4 between two adjacent through holes 130 to the diameter D of the through hole 130 is (1-2):1, specifically (1-1.5):1, (1.5-2):1, etc. In this case, the ratio relationship between the spacing d4 between two adjacent through holes 130 and the diameter D of the through hole 130 is beneficial to both protecting the safety of the through hole 130 and facilitating the manufacturing of the through hole 130.

[0128] In some possible implementations, the distance d4 between two adjacent through holes 130 is 2 μm to 20 μm. In this case, the distance d4 between two adjacent through holes 130 ensures both the safety of the through holes 130 and the integration density of the through holes 130 in the cutting area 120 . Exemplarily, the spacing d4 between two adjacent through holes 130 can be typically but not limitatively 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, etc., or any value or interval between 2μm and 20μm, such as 2μm to 3μm, 3μm to 4μm, 4μm to 5μm, 5μm to 7μm, 7μm to 10μm, 10μm to 13μm, 13μm to 15μm, 15μm to 18μm, 18μm to 20μm, etc.

[0129] In some possible implementations, the through hole 130 includes a TSV silicon through hole 130 or a TGV glass through hole 130. In some embodiments, the method of preparing the TSV through hole 130 in the cutting area 120 includes, but is not limited to, deep reactive ion etching (DRIE) to make TSV holes, plasma enhanced chemical vapor deposition (PECVD) to make dielectric layers, physical vapor deposition (PVD) to make barrier layers and seed layers, electroplating copper (Cu) to fill holes, and chemical mechanical polishing (CMP) to remove excess metal. In addition, due to the need for chip stacking integration, for 3D IC / Si integration, there are also key steps such as wafer thinning and thin crystal bonding. In other embodiments, the method of preparing the TGV through hole 130 in the cutting area 120 includes, but is not limited to, sandblasting, photosensitive glass method, focused power generation method, plasma etching method, laser ablation method, electrochemical discharge machining method, laser induced etching method, etc.

[0130] In the above step S30 , the wafer to be cut is cut along the wavy cutting road to cut at least two adjacent chip areas 110 into independent chip units. The cutting residual area 111 at the edge of the chip unit is a concave-convex structure with through holes 130 arranged therein.

[0131] In some possible implementations, the cutting process adopts at least one of dry etching, laser cutting, plasma cutting, and deep silicon etching. Among them, dry etching refers to an etching technology that uses glow discharge to generate plasma containing charged particles such as ions and electrons and highly chemically active neutral atoms, molecules and free radicals to perform pattern transfer. It is the main method for etching devices at submicron size. According to the material, it can be divided into: metal etching, dielectric etching, silicon etching, and according to the etching mechanism, it can be divided into chemical corrosion and physical corrosion. Laser cutting is a horizontal laser beam emitted by a laser that is converted into a vertical downward laser beam through a 45° total reflection mirror, and then focused by a lens to form a very small light spot at the focus. When the light spot is irradiated on the material, the material is quickly heated to the vaporization temperature, evaporated to form a hole, and as the light beam moves to the material, and the auxiliary gas (carbon dioxide gas, oxygen, nitrogen, etc.) blows away the molten waste, so that the hole continuously forms a very narrow width (such as about 0.1mm) slit to complete the cutting of the material. Plasma cutting is a method of cutting using the heat of a plasma arc. During cutting, the plasma arc melts the workpiece and removes the molten metal by the force of the plasma flow, thereby forming a slit. Deep silicon etching, also known as deep etching method or deep etching technology, is a process technology for etching silicon materials. It is mainly used in the fields of integrated circuits and microfluidics to make tiny structures with a high depth-to-width ratio. Among the cutting methods, the deep silicon etching method can achieve a very high aspect ratio, that is, the ratio of etching depth to structure size, which makes this method very suitable for making tiny structures and nanoscale devices. The etching solution used in the deep silicon etching method can selectively etch silicon materials while having little effect on other materials, which means that the integrity of other parts on the chip can be effectively protected during the etching process. The deep silicon etching method can achieve precise control of the etching process by adjusting etching parameters (such as time, voltage, temperature, etc.), which can ensure the consistency and accuracy of the etching depth. The deep silicon etching method has an efficient etching rate and can achieve the required depth in a relatively short time, which greatly improves the efficiency of chip manufacturing.

[0132] Second, as attached Fig.13 and attached Fig.14 As shown, the embodiment of the present application provides a packaging method, comprising the following steps:

[0133] S01. Obtaining a clean base layer, and sequentially preparing a first insulating layer and a first rewiring layer on one surface of the base layer;

[0134] S02. Temporary bonding is performed on the surface of the first rewiring layer away from the first insulating layer;

[0135] S03. After thinning the surface of the base layer away from the first insulating layer, a wavy cutting path is provided in the cutting area 120 of the thinned surface of the base layer, and a plurality of through holes 130 are prepared on the thinned surface according to the wavy cutting path; the line shape of the wavy cutting path is an arc and / or a broken line;

[0136] S04. A second insulating layer and a second rewiring layer are sequentially prepared on the surface of the base layer having a through hole 130 to obtain a chip to be cut;

[0137] S05. Cutting the chip to be cut along the wavy cutting path, and after debonding, obtaining a chip unit;

[0138] S06. Stacking the chip units to obtain a chip package structure.

[0139] In the packaging method of the embodiment of the present application, after the first insulating layer and the first rewiring layer are sequentially prepared on the surface of the clean base layer, temporary bonding is performed, and then the base layer is thinned, and a wavy cutting path with arc and / or fold line is set in the cutting area of ​​the thinned surface, and a plurality of through holes 130 are prepared on the thinned surface according to the wavy cutting path; then the second insulating layer and the second rewiring layer are sequentially prepared on the surface formed with the through holes 130 to obtain the chip to be cut. The chip to be cut is cut along the wavy cutting path, and the chip unit is debonded to obtain the chip unit, and the cutting residual area 111 of the concave-convex structure at the edge of the chip unit is arranged with the through hole 130, and the layout of the through hole 130 can improve the integration of the chip in the three-dimensional direction, that is, improve the packaging integration, which is conducive to the stacking of the chip units to obtain the chip package structure.

[0140] In the above step S01, the base layer is cleaned to obtain a clean base layer. In some embodiments, the base layer can be a silicon wafer carrier or a glass wafer carrier.

[0141] In some embodiments, as shown in the attached Fig.14 In (1), the method for preparing the first insulating layer includes but is not limited to, using plasma enhanced chemical vapor deposition (PECVD) to deposit SiO2 to prepare the first insulating layer.

[0142] In some embodiments, as shown in the attached Fig.14 In (2), the method for preparing the first redistribution layer includes, but is not limited to, using physical vapor deposition (PVD) + electroplating to prepare the first redistribution layer (RDL).

[0143] In the above step S02, as shown in the attached Fig.14In (3), temporary bonding is a technology used to temporarily connect electronic devices or chips. Through temporary bonding, the connection between each other can be completed during testing, packaging or other steps that require temporary connection. Temporary bonding methods include but are not limited to: wire bonding, using gold wire to connect the pins of the chip to the substrate or package contact pads. Solder bonding, using solder material to connect the pins of the chip to the substrate or package contact pads. Piezoelectric bonding (Thermosonic bonding), using ultrasound and heat to connect the pins of the chip to the substrate or package contact pads.

[0144] In the above step S03, as shown in the attached Fig.14 In (4), a wavy cutting path is provided in the cutting area 120 of the thinned surface of the base layer, and a plurality of through holes 130 are prepared on the thinned surface according to the wavy cutting path; the line shape of the wavy cutting path is an arc line and / or a broken line.

[0145] In some possible implementations, in the wavy cutting path, the center angle θ1 of the arc is 0°<θ1<180°.

[0146] In some possible implementations, in the wavy cutting path, the fold angle θ2 of the fold line is 0°<θ2<180°.

[0147] In some possible implementations, in the wavy cutting road, the radius r of the arc is 0<r<50 μm.

[0148] In some possible embodiments, along a wave propagation direction perpendicular to the wavy cutting road, the cutting area 120 includes a first safety zone 121, a cutting road path zone 122, and a second safety zone 123 arranged in sequence, the wavy cutting road is set in the cutting road path zone 122, and cutting is performed along the wavy cutting road in the cutting road path zone 122.

[0149] In some possible implementations, along a wave propagation direction perpendicular to the wavy cutting road, the width d of the cutting area 120 = the width d0 of the cutting road path area 122 + the width d2 of the first safety area 121 + the width d3 of the second safety area 123 .

[0150] In some possible implementations, the line shape of the wavy cutting road is an arc, and the relationship between the width d0 of the cutting road path area 122 and the central angle θ1 of the arc and the radius r of the arc satisfies: d0=2r(1-cosθ1).

[0151] In some possible implementations, the width d of the cutting region 120 is 12 μm to 70 μm.

[0152] In some possible implementations, the ratio d1 / d of the width d1 of the wavy cutting street to the width d of the cutting area 120 is (0.02857-0.5):1.

[0153] In some possible implementations, the width d1 of the wavy cutting street is 2 μm to 20 μm.

[0154] In some possible implementations, a ratio d2 / d of a width d2 of the first safety zone 121 to a width d of the cutting area 120 is 1:(5-10).

[0155] In some possible implementations, a ratio d3 / d of the width d3 of the second safety zone 123 to the width d of the cutting area 120 is 1:(5-10).

[0156] In some possible implementations, the width d2 of the second safety area 123 is 2 μm to 15 μm.

[0157] In some possible implementations, the width d3 of the second safety area 123 is 2 μm to 15 μm.

[0158] In some possible implementations, the ratio d1 / D of the width d1 of the wavy cutting street to the diameter D of the through hole 130 is (0.1-5):1.

[0159] In some possible implementations, the diameter of the through hole 130 is 1 μm to 10 μm.

[0160] In some possible implementations, the depth of the through hole 130 is 10 μm to 50 μm.

[0161] In some possible implementations, an isolation region 131 is disposed around the through hole 130 , and a width d5 ​​of the isolation region 131 is 2 μm to 10 μm.

[0162] In some possible implementations, a ratio d4 / d5 of a distance d4 between two adjacent through holes 130 and a width d5 ​​of the isolation region 131 is (1-4):1.

[0163] In some possible implementations, a ratio d4 / D of a distance d4 between two adjacent through holes 130 to a diameter D of the through hole 130 is (1-2):1.

[0164] In some possible implementations, the interval d4 between two adjacent through holes 130 is 2 μm to 20 μm.

[0165] The beneficial effects of the above embodiments of the present application have been discussed in detail in the previous text and will not be repeated here.

[0166] In the above step S04, as shown in the attached Fig.14In (5), the method for preparing the second insulating layer includes but is not limited to, using plasma enhanced chemical vapor deposition (PECVD) to deposit SiO2 to prepare the second insulating layer.

[0167] In some embodiments, as shown in the attached Fig.14 In (5), the method of preparing the second redistribution layer includes, but is not limited to, preparing the second redistribution layer (RDL) by physical vapor deposition (PVD) or electroplating.

[0168] In the above step S05, as shown in the attached Fig.14 In (6), the chip to be cut is cut along the wavy cutting path. In some possible implementations, the cutting process adopts the above-mentioned cutting method, including but not limited to at least one of dry etching, laser cutting, plasma cutting, and deep silicon etching.

[0169] In some possible implementations, as shown in the attached Fig.14 In (7), debonding refers to the process of breaking a temporarily connected bond. Debonding is usually performed after chip testing is completed, or before chip packaging or other subsequent steps are required. Debonding methods include, but are not limited to, thermal release bonding: by heating the bonding area, the temporary bonded material is decomposed or invalidated to disconnect the connection. RF release bonding: using high-frequency current or energy to break the bond. Laser release bonding: using a laser beam to process the bonding area to invalidate the bond.

[0170] In the above step S06, as shown in the attached Fig.14 In (7), the chip units are stacked, including bump stacking or bonding stacking, wherein bump stacking refers to the technology of stacking the solder balls (bumps) of multiple electronic devices together in a vertical direction, so as to achieve high-density, low-power and small-size electronic device assembly. Bonding stacking refers to the method of connecting multiple electronic devices together through bonding technology. Among them, the bump stacking method includes but is not limited to: ball bonding: using solder balls to stack multiple electronic devices together and connect them through a bonding method; induction bonding: using adhesives to stack multiple electronic devices in a vertical direction and fix them together. Bonding stacking methods include but are not limited to: wire bonding: bonding multiple electronic devices together through gold wires; solder bonding: bonding multiple electronic devices together through solder materials.

[0171] In a third aspect, an embodiment of the present application provides a chip unit, which is manufactured by cutting using the above-mentioned cutting method, or is packaged using the above-mentioned packaging method.

[0172] The chip unit of the embodiment of the present application is obtained by cutting using the above-mentioned cutting method, and the cutting residual area 111 at the edge of the chip is fully utilized, thereby increasing the integration density of the chip through-hole 130, increasing the utilization rate of the chip, avoiding the waste of chip area, reducing the size of the subsequent package body, facilitating the subsequent stacking, packaging and other operations of the chip unit, and improving the packaging integration. The cutting residual area 111 at the edge of the chip unit is a concave-convex structure with through-holes 130, which is particularly suitable for packaging using the above-mentioned packaging method, improving the packaging integration, saving operations, reducing packaging materials, and thus reducing costs, and at the same time reducing parasitics caused by packaging, thereby improving chip performance.

[0173] In some possible implementations, the chip unit includes external connection terminals, which are used to interconnect chips within the chip unit and / or to connect external electronic devices. The present application embodiment does not specifically limit the preparation operation of the external connection terminals in the chip unit, and the method of connecting the external connection terminals to the chip and the external electronic devices, as long as the pads on the chip can be brought out and the chip unit is convenient for electrical connection with other electronic devices.

[0174] In some possible implementations, the chip unit is a power semiconductor device chip, a power management chip or a battery management chip. However, the embodiment of the present application does not limit the type of chip unit. As long as there is a need for parallel, series or series-parallel connection, the chip unit of the embodiment of the present application can be used. Among them, the power semiconductor device chip refers to an electronic device used to control and manage high-power current and high voltage, which are usually used in applications such as power supply, drive, conversion and control. Some common power semiconductor device chips include power MOSFET (metal oxide semiconductor field effect transistor), IGBT (insulated gate bipolar transistor), power diode, power integrated circuit, etc. The application scenarios of power semiconductor device chips include but are not limited to: automotive electronics such as engine control, electric vehicles, hybrid vehicles; industrial automation such as industrial motor drive, industrial control system, robot; communication and network equipment such as power amplifier, optical communication, wireless communication base station; consumer electronics such as television, audio, home appliances. Among them, the power management chip (Power Management Integrated Circuit, PMIC) is a chip that integrates multiple functional modules and is used to manage and control various functions of the power system, including power conversion, battery charge and discharge management, power management, etc. The application scenarios of power management chips include but are not limited to: mobile devices such as smartphones, tablets, and laptops; wearable devices such as smart watches and smart glasses; and household appliances such as televisions, set-top boxes, and audio equipment. Among them, battery management chips are chips specifically used for battery management, which are mainly used to monitor, control, and protect batteries, including battery charging and discharging control, battery status monitoring, and temperature protection. The application scenarios of battery management chips include but are not limited to: battery management and protection of mobile devices such as smartphones and tablets; battery management in battery-powered power tools and equipment; and battery management and protection of electric vehicles such as electric vehicles and electric bicycles. The advantages of these chips include: High efficiency: Power semiconductor device chips have high power conversion efficiency and can effectively reduce power consumption. High reliability: Power management chips and battery management chips can provide functions such as current stabilization, temperature protection, and overvoltage protection, enhancing the reliability and safety of the system. High integration: These chips often integrate multiple functional modules, which can reduce the number of components in the system, save space, and simplify system design and assembly. Precise control: These chips provide precise control and monitoring functions, which can achieve high-precision control and management of parameters such as power, voltage, and current.

[0175] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes the above-mentioned chip unit.

[0176] The electronic device of the embodiment of the present application includes the above-mentioned chip unit with high packaging integration, which is conducive to reducing the size of transistors and meeting the application requirements of miniaturized and multifunctional electronic devices.

[0177] In some possible implementations, the electronic device further includes a circuit board, and wiring in the circuit board interconnects the chips in the chip unit.

[0178] In some possible implementations, the electronic device further includes a circuit board, on which a chip unit and at least one electronic device are disposed, and external connection terminals of the chip unit are electrically connected to the electronic device via wiring in the circuit board.

[0179] Example

[0180] The following is explained in conjunction with specific embodiments. The embodiments described below are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. If no specific techniques or conditions are indicated in the embodiments, the techniques or conditions described in the literature in this area or the product specifications are used. If the manufacturer of the reagents or instruments is not indicated, they are all conventional products that can be obtained commercially.

[0181] Example 1

[0182] The embodiment of the present application provides a cutting method, and the set cutting parameters are: the width of the cutting area 120 between two adjacent chip areas 110 is 60um, wherein the widths of the first safety zone 121 and the second safety zone 123 at the edge of the chip are 10um respectively; the unilateral offset of the graphic production equipment during operation is 2um; the width of the KOZ area is 10um; the spacing between adjacent TSVs is 2 times the TSV diameter; the width of the cutting road is 4μm, and the line shape of the wavy cutting road is an arc. In addition, the chip size is 15*15mm, that is, the length of the cutting area 120 is 15mm.

[0183] Based on the above cutting line parameters, under different TSV diameter conditions, the number of TSVs that can be arranged in the cutting area 120 is calculated according to the wavy cutting line and the straight cutting line (Comparative Example 1):

[0184] According to the width d of the cutting area 120 of 60um, the width d2 of the first safety zone 121 of 10μm, the width d3 of the second safety zone 123 of 10μm, and the single-side offset during operation of 2um, the width of the cutting path area 122 can be calculated to be d0=60-10*2-2*2=36μm; in addition, the width of the cutting path d1 is 4μm, therefore, the actually available width in the cutting area 120 is 36-4=32μm.

[0185] If a straight cutting path is used for cutting, the chip must be symmetrical on one side, that is, the straight cutting path is arranged in the middle of the cutting area 120. At this time, the width of the cutting residual area 111 at the edge of the chip after cutting that can be used to arrange TSV is 32 / 2=16μm. When the diameter of the laid TSV is 4μm, plus the width of the KOZ area around the TSV is 10um, the space required to lay out a TSV is at least 10*2+4=24μm, which is obviously larger than the width of the cutting residual area 111 at the edge of the chip after cutting that can be used to lay out TSV, which is 16μm. Therefore, if a straight cutting path is used, TSV cannot be laid out in the cutting area 120.

[0186] When the diameter of TSV is 6 μm, referring to the above calculation, the space required to lay out a TSV is at least 10*2+6=26 μm, which is obviously larger than the width of the dicing residual area 111 at the edge of the chip after dicing, which can be used to lay out TSV. Therefore, TSV cannot be laid out in the dicing area 120 either.

[0187] When the diameter of TSV is 8 μm, referring to the above calculation, the space required to lay out a TSV is at least 10*2+8=28 μm, which is obviously larger than the width of the dicing residual area 111 at the edge of the chip after dicing, which can be used to lay out TSV. Therefore, TSV cannot be laid out in the dicing area 120 either.

[0188] If a wavy cutting path is used for cutting, the number of TSVs with different diameters that can be laid out varies according to the changes in the center angle and radius of the arc of the wavy cutting path. The calculation results are shown in Table 1 below:

[0189] Table 1

[0190]

[0191] Example 2

[0192] The embodiment of the present application provides a cutting method, and the cutting parameters set in the method are different from those in Embodiment 1 in that the width of the cutting path is 6 μm.

[0193] Based on the above cutting line parameters, under different TSV diameter conditions, the number of TSVs that can be arranged in the cutting area 120 is calculated according to the wavy cutting line and the straight cutting line (Comparative Example 2):

[0194] According to the width d of the cutting area 120 being 60um, the width d2 of the first safety zone 121 being 10μm, the width d3 of the second safety zone 123 being 10μm, and the single-side offset during operation being 2um, it can be calculated that the width of the cutting path area 122 is d0=60-10*2-2*2=36μm; in addition, the width of the cutting path d1 is 6μm, and therefore, the actually available width in the cutting area 120 is 36-6=30μm.

[0195] If a straight cutting path is used for cutting, the chip must be symmetrical on one side, that is, the straight cutting path is arranged in the middle of the cutting area 120. At this time, the width of the cutting residual area 111 at the edge of the chip after cutting that can be used to arrange TSV is 30 / 2=15μm. When the diameter of the laid TSV is 4μm, plus the width of the KOZ area around the TSV is 10um, the space required to lay out a TSV is at least 10*2+4=24μm, which is obviously larger than the width of the cutting residual area 111 at the edge of the chip after cutting that can be used to lay out TSV, which is 15μm. Therefore, if a straight cutting path is used, TSV cannot be laid out in the cutting area 120.

[0196] When the diameter of TSV is 6 μm, referring to the above calculation, the space required for laying out one TSV is at least 10*2+6=26 μm, which is obviously larger than the width of the dicing residual area 111 of the chip edge after dicing, which can be used to lay out TSV, 15 μm. Therefore, TSV cannot be laid out in the dicing area 120 either.

[0197] When the diameter of TSV is 8 μm, referring to the above calculation, the space required for laying out one TSV is at least 10*2+8=28 μm, which is obviously larger than the width of the dicing residual area 111 of the chip edge after dicing, which can be used to lay out TSV, 15 μm. Therefore, TSV cannot be laid out in the dicing area 120 either.

[0198] If a wavy cutting path is used for cutting, the number of TSVs with different diameters that can be laid out varies according to the changes in the center angle and radius of the arc of the wavy cutting path. The calculation results are shown in Table 2 below:

[0199] Table 2

[0200]

[0201] Example 3

[0202] The embodiment of the present application provides a cutting method, and the cutting parameters set in the method are different from those in Embodiment 1 in that the width of the cutting path is 2 μm.

[0203] Based on the above cutting line parameters, under different TSV diameter conditions, the number of TSVs that can be arranged in the cutting area 120 is calculated according to the wavy cutting line and the straight cutting line (Comparative Example 3):

[0204] According to the width d of the cutting area 120 of 60um, the width d2 of the first safety zone 121 of 10μm, the width d3 of the second safety zone 123 of 10μm, and the single-side offset during operation of 2um, the width of the cutting path area 122 can be calculated to be d0=60-10*2-2*2=36μm; in addition, the width of the cutting path d1 is 2μm, therefore, the actually available width in the cutting area 120 is 36-2=34μm.

[0205] If a straight cutting path is used for cutting, the chip must be symmetrical on one side, that is, the straight cutting path is arranged in the middle of the cutting area 120. At this time, the width of the cutting residual area 111 at the edge of the chip after cutting that can be used to arrange TSV is 34 / 2=17μm. When the diameter of the laid TSV is 4μm, plus the width of the KOZ area around the TSV is 10um, the space required to lay out a TSV is at least 10*2+4=24μm, which is obviously larger than the width of the cutting residual area 111 at the edge of the chip after cutting that can be used to lay out TSV 17μm. Therefore, if a straight cutting path is used, TSV cannot be laid out in the cutting area 120.

[0206] When the diameter of TSV is 6 μm, referring to the above calculation, the space required to lay out a TSV is at least 10*2+6=26 μm, which is obviously larger than the width of the dicing residual area 111 at the edge of the chip after dicing, which can be used to lay out TSV. Therefore, TSV cannot be laid out in the dicing area 120 either.

[0207] When the diameter of TSV is 8 μm, referring to the above calculation, the space required to lay out a TSV is at least 10*2+8=28 μm, which is obviously larger than the width of the dicing residual area 111 at the edge of the chip after dicing, which can be used to lay out TSV. Therefore, TSV cannot be laid out in the dicing area 120 either.

[0208] If a wavy cutting path is used for cutting, the number of TSVs with different diameters that can be laid out varies according to the changes in the center angle and radius of the arc of the wavy cutting path. The calculation results are shown in Table 3 below:

[0209] Table 3

[0210]

[0211] It can be seen from the test data in Tables 1 to 3 that in the cutting methods of Examples 1 to 3 of the present application, a wavy cutting path is set in the cutting area 120, and the wafer to be cut is cut along the wavy cutting path. After cutting, the cutting residual area 111 at the edges of two adjacent chips presents an alternating concave and convex structure, and the convex parts of the cutting residual area 111 have a relatively large size, so that several through holes 130 can be reasonably arranged, thereby improving the integration density of the chip through holes 130, which is beneficial to the subsequent stacking, packaging and other operations of the chip units. However, when comparative examples 1 to 3 use a straight cutting path for cutting, when the cutting area 120 is small, due to the small size of the cutting area 120, the width of the cutting path itself, and the cutting offset, a certain space will be occupied in the cutting area 120. As a result, after the small-sized cutting area 120 is cut in a straight-line cutting manner, the cutting residual area 111 at the edge of the chip is very narrow and cannot meet the space required for the layout of the through hole 130 and its surrounding safety area. Therefore, if a straight-line cutting method is used for the small-sized cutting area 120, it is difficult to layout the through hole 130 in the cutting area 120 between two adjacent chips.

[0212] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the aforementioned embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in each embodiment can be combined in any way. The scope of protection of the present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims. Therefore, the scope of protection of the present application shall be based on the scope of protection of the claims.

Claims

1. A cutting method, characterized in that: The following steps are involved: Providing a wafer to be cut, wherein the wafer to be cut comprises a plurality of chip regions and a cutting region, and two adjacent chip regions are separated by the cutting region; A wavy cutting path is provided in the cutting area, and a plurality of through holes are arranged in the cutting area according to the wavy cutting path; the line shape of the wavy cutting path is an arc line and / or a broken line; The wafer to be cut is cut along the wavy cutting path to cut at least two adjacent chip regions into independent chip units.

2. The cutting method according to claim 1, characterized in that: In the wavy cutting path, the center angle θ1 of the arc is 0°<θ1<180°; And / or, in the wavy cutting path, the fold angle θ2 of the fold line is 0°<θ2<180°.

3. The cutting method according to claim 2, characterized in that: In the wavy cutting path, the radius r of the arc is 0<r≤50 μm.

4. The cutting method according to any one of claims 1 to 3, characterized in that: Along a wave propagation direction perpendicular to the wavy cutting road, the cutting area includes a first safety zone, a cutting road path zone and a second safety zone arranged in sequence, the wavy cutting road is set in the cutting road path zone, and cutting is performed along the wavy cutting road in the cutting road path zone.

5. The cutting method according to claim 4, characterized in that: The width d of the cutting area=the width d0 of the cutting path area+the width d2 of the first safety area+the width d3 of the second safety area.

6. The cutting method according to claim 5, characterized in that: The linear shape of the wavy cutting path is an arc, and the relationship between the width d0 of the cutting path area, the central angle θ1 of the arc, and the radius r of the arc satisfies: d0=2r(1-cosθ1).

7. The cutting method according to any one of claims 5 to 6, characterized in that: The width d of the cutting area is 12 μm to 70 μm.

8. The cutting method according to claim 7, characterized in that: The ratio d1 / d of the width d1 of the wavy cutting road to the width d of the cutting area is (0.02857-0.5):

1.

9. The cutting method according to claim 8, characterized in that: The width d1 of the wavy cutting road is 2 μm to 20 μm.

10. The cutting method according to claim 7, characterized in that: The ratio d2 / d of the width d2 of the first safety zone to the width d of the cutting zone is 1:(5-10); And / or, the ratio d3 / d of the width d3 of the second safety zone to the width d of the cutting area is 1:(5-10).

11. The cutting method according to claim 10, characterized in that: The width d2 of the first safety zone is 2 μm to 15 μm; And / or, the width d3 of the second safety zone is 2 μm to 15 μm.

12. The cutting method according to any one of claims 1 to 3, 5 to 6, and 8 to 11, characterized in that: The ratio d1 / D of the width d1 of the wavy cutting road to the diameter D of the through hole is (0.1-5):

1.

13. The cutting method according to claim 12, characterized in that: The diameter of the through hole is 1 μm to 10 μm; And / or, the through hole has a depth of 10 μm to 50 μm.

14. The cutting method according to any one of claims 1 to 3, 5 to 6, 8 to 11 or 13, characterized in that: An isolation region is arranged around the through hole, and a width d5 ​​of the isolation region is 2 μm to 10 μm.

15. The cutting method according to claim 14, characterized in that: The ratio d4 / d5 of the distance d4 between two adjacent through holes to the width d5 ​​of the isolation region is (1-4):

1.

16. The cutting method according to claim 14, characterized in that: The ratio d4 / D of the distance d4 between two adjacent through holes to the diameter D of the through holes is (1-2):

1.

17. The cutting method according to claim 15 or 16, characterized in that: The distance d4 between two adjacent through holes is 2 μm to 20 μm.

18. The cutting method according to any one of claims 1 to 3, 5 to 6, 8 to 11, 13, 15 to 16, characterized in that: The cutting process adopts at least one of dry etching, laser cutting, plasma cutting and deep silicon etching.

19. The cutting method according to any one of claims 1 to 3, 5 to 6, 8 to 11, 13, 15 to 16, characterized in that: The through-hole comprises a through-silicon via or a through-glass via.

20. A packaging method, characterized in that: The following steps are involved: Obtaining a clean base layer, and sequentially preparing a first insulating layer and a first redistribution layer on a surface of one side of the base layer; Performing temporary bonding on a surface of the first redistribution layer away from the first insulating layer; After thinning the surface of the base layer away from the first insulating layer, a wavy cutting path is provided in the cutting area of ​​the thinned surface of the base layer, and a plurality of through holes are prepared on the thinned surface according to the wavy cutting path; the line shape of the wavy cutting path is an arc line and / or a broken line; Sequentially preparing a second insulating layer and a second rewiring layer on the surface of the base layer where the through hole is formed, to obtain a chip to be cut; Cutting the chip to be cut along the wavy cutting path, and after debonding, obtaining a chip unit; The chip units are stacked to obtain a chip package structure.

21. The packaging method according to claim 20, characterized in that: The cutting process adopts the cutting method according to any one of claims 1 to 19.

22. A chip unit, characterized in that: The chip unit is cut by the cutting method described in any one of claims 1 to 19, or is packaged by the packaging method described in any one of claims 20 to 21.

23. The chip unit according to claim 22, characterized in that: The chip unit comprises external connection terminals, and the external connection terminals are used for interconnecting chips within the chip unit and / or for connecting external electronic devices.

24. The chip unit according to claim 22 or 23, characterized in that: The chip unit is a power semiconductor device chip, a power management chip or a battery management chip.

25. An electronic device, characterized in that: The electronic device comprises the chip unit according to any one of claims 22 to 24.

26. The electronic device as claimed in claim 25, characterized in that The electronic device further comprises a circuit board, wherein wiring in the circuit board interconnects the chips in the chip unit; Alternatively, the electronic device further comprises a circuit board, on which the chip unit and at least one electronic device are arranged, and the external connection terminals of the chip unit are electrically connected to the electronic device via wiring in the circuit board.

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