High-density fan-out packaging method and product

Abstract

The invention discloses a high-density fan-out type packaging method and a product. The method comprises the following steps: preparing a dielectric substance layer on the surface of a silicon slide; preparing a first organic passivation layer on the surface of the dielectric substance layer and forming an opening; preparing a first metal circuit layer on the first organic passivation layer; preparing a rewiring layer on the surfaces of the first organic passivation layer and the first metal circuit layer; connecting a chip on the surface of the rewiring layer; filling a gap between the chip and the rewiring layer; performing plastic packaging; grinding and thinning the silicon slide; removing the residual silicon slide residues, and exposing the dielectric substance layer; removing the dielectric substance layer to expose the first organic passivation layer and the metal interconnection structure; grinding and thinning the plastic sealing surface to expose the back surface of the chip; and cutting the packaging body into single particles, mounting the single particles on the surface of the substrate, and carrying out ball mounting. According to the invention, temporary bonding and debonding processes are cancelled, and related equipment and materials are not used any more, so that the packaging cost is remarkably reduced, and the process flow is simplified.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a high-density fan-out packaging method and product. Background Art

[0002] Since it can realize the integrated packaging of high I / O density chips such as SoC and HBM, high-density fan-out packaging has been widely used in high-performance computing, artificial intelligence and other fields. In traditional high-density fan-out packaging, temporary bonding and laser debonding processes based on glass carriers are generally used. In this process, there are some unavoidable problems that need to be solved:

[0003] 1) The equipment and materials used in temporary bonding and debonding processes are monopolized by foreign suppliers, and the cost is quite high;

[0004] 2) The temporary bonding and debonding process is complicated. During the production and processing, various abnormalities are prone to occur, such as temporary bonding glue delamination, temporary bonding glue bulging, incomplete cleaning of residual glue, and laser damage to the redistribution layer. These abnormalities may cause serious yield loss. Summary of the invention

[0005] In order to solve the technical problems existing in the prior art, the object of the present invention is to provide a high-density fan-out packaging method and product.

[0006] In order to achieve the above purpose and the above technical effect, the technical solution adopted by the present invention is:

[0007] A high-density fan-out packaging method comprises the following steps:

[0008] Step 1: preparing a dielectric layer on the surface of a silicon carrier;

[0009] Step 2: preparing a first organic passivation layer on the surface of the dielectric layer and forming an opening at a specific position;

[0010] Step 3: preparing a first metal circuit layer on the first organic passivation layer, wherein the first metal circuit layer comprises a metal interconnect structure filling the opening and a metal routing on the surface of the first organic passivation layer;

[0011] Step 4: preparing a redistribution layer on the surface of the first organic passivation layer and the first metal circuit layer, and then forming metal bumps on the surface of the redistribution layer;

[0012] Step 5: Connect several chips on the surface of the redistribution layer;

[0013] Step 6: Use underfill glue to fill the gap between the chip and the redistribution layer;

[0014] Step 7, performing plastic encapsulation processing on the whole reconstructed wafer obtained in step 6;

[0015] Step 8, grinding and thinning the silicon carrier, and retaining a portion of the silicon carrier;

[0016] Step 9: removing the remaining silicon carrier residue and exposing the dielectric layer;

[0017] Step 10: removing the dielectric layer to expose the first organic passivation layer and the metal interconnect structure;

[0018] Step 11: forming a C4 metal bump at the metal interconnection structure position;

[0019] Step 12: Grind and thin the plastic cover of the reconstructed wafer to expose the back side of the chip;

[0020] Step 13: Cut the package obtained in step 12 into individual pieces, mount them on the surface of the substrate, and perform ball planting on the side of the substrate away from the package.

[0021] Furthermore, in step one, the dielectric layer is made of silicon oxide or silicon nitride.

[0022] Furthermore, in step 2, a first organic passivation layer is formed on the surface of the dielectric layer by using a photolithography process, and an opening is formed at a specific position.

[0023] Furthermore, the first organic passivation layer is made of photosensitive polyimide or epoxy resin material.

[0024] Furthermore, the shape of the opening is circular, and the opening size is 10-60 microns.

[0025] Furthermore, in step 4, the redistribution layer includes an organic passivation layer and a metal circuit layer that are alternately distributed.

[0026] Furthermore, in step five, a metal bump structure is prepared on the surface of the chip, and several chips are welded to the surface of the redistribution layer through a flip chip welding process. The metal bump structure and the metal bumps are welded to form a physical connection and realize signal connection.

[0027] Furthermore, in step thirteen, the package body and the substrate are connected via C4 metal bumps, and glue is filled between the package body and the substrate.

[0028] The invention also discloses a high-density fan-out packaging structure prepared by a high-density fan-out packaging method.

[0029] Furthermore, the high-density fan-out packaging structure includes a substrate, a plurality of packaging bodies are connected to the substrate, the packaging body includes a redistribution layer, a plastic package, and a plurality of chips encapsulated therein and connected to the redistribution layer, a C4 metal bump is provided on the side of the redistribution layer away from the chip, a connection is formed between the packaging body and the substrate through the C4 metal bump, glue is filled between the packaging body and the substrate, and a ball planting process is performed on the side of the substrate away from the packaging body to form a solder joint.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1) The present invention eliminates the temporary bonding and debonding processes, and no longer uses related equipment and materials, which significantly reduces packaging costs;

[0032] 2) The present invention eliminates the temporary bonding and debonding processes, simplifies the process flow, and avoids various abnormal problems existing in the existing packaging technology, such as temporary bonding glue delamination, temporary bonding glue bulging, incomplete cleaning of residual glue, and laser damage to the redistribution layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a structural schematic diagram of step 1 of the present invention;

[0034] Figure 2 It is a structural schematic diagram of step 2 of the present invention;

[0035] Figure 3 It is a structural schematic diagram of step three of the present invention;

[0036] Figure 4 It is a structural schematic diagram of step 4 of the present invention;

[0037] Figure 5 It is a structural schematic diagram of step five of the present invention;

[0038] Figure 6 It is a structural schematic diagram of step six of the present invention;

[0039] Figure 7 It is a structural schematic diagram of step seven of the present invention;

[0040] Figure 8 It is a structural schematic diagram of step eight of the present invention;

[0041] Fig. 9 It is a structural schematic diagram of step nine of the present invention;

[0042] Fig.10 It is a structural schematic diagram of step ten of the present invention;

[0043] Fig.11 It is a structural schematic diagram of step eleven of the present invention;

[0044] Fig.12 It is a structural schematic diagram of step twelve of the present invention;

[0045] Fig.13 It is a structural schematic diagram of step thirteen of the present invention. DETAILED DESCRIPTION

[0046] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0047] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or critical elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0048] like Figure 1-13 As shown, a high-density fan-out packaging method includes the following steps:

[0049] Step 1: Figure 1 As shown, a dielectric layer 2 with a thickness of 0.1-2 microns is deposited on the surface of the silicon carrier 1. The silicon carrier 1 is usually a circular carrier. The dielectric layer 2 can be made of materials such as silicon oxide or silicon nitride. The role of the dielectric layer 2 is, on the one hand, to enhance the bonding force between the silicon carrier 1 and the subsequent redistribution layer, and on the other hand, to serve as a stop layer for the subsequent removal process of the silicon carrier 1;

[0050] Step 2: Figure 2 As shown, a first organic passivation layer 3 is formed on the surface of the dielectric layer 2 by photolithography, with a thickness of 3-10 microns, and an opening 301 is formed at a specific position. The shape of the opening 301 is preferably circular, and the opening size is preferably 10-60 microns. The first organic passivation layer 3 is usually a photosensitive polyimide or epoxy resin material, and its original form can be a liquid material or a solid dry film material. The function of the opening 301 is to form a metal interconnection structure between the redistribution layer and the C4 metal bump;

[0051] Step 3: Figure 3 As shown, the first metal circuit layer 4 is then prepared by metal sputtering, photolithography and electroplating, which is usually a copper circuit. The first metal circuit layer 4 includes a metal interconnect structure filling the opening 301 and a metal trace on the surface of the first organic passivation layer 3;

[0052] Step 4: Figure 4As shown, multiple layers of organic passivation layers and metal circuit layers are then sequentially prepared on the surface of the first organic passivation layer 3 and the first metal circuit layer 4 to form a redistribution layer 5. The organic passivation layers and metal circuit layers in the redistribution layer 5 are alternately distributed. The number of metal circuit layers can be 1 layer or multiple layers, and there is no specific limitation. The line width and line spacing of the metal circuit layer can usually be very small, such as 1μm / 1μm, 1.5μm / 1.5μm, 2μm / 2μm, 4μm / 4μm, 5μm / 5μm, 10μm / 10μm, etc. Fine metal circuits are conducive to realizing signal interconnection between high I / O density chips, such as SoC, HBM, etc. Then, metal bumps 6 are formed on the surface of the redistribution layer 5, and their structure is usually copper-nickel-tin-silver or copper-nickel-gold or copper-nickel-copper-tin-silver, etc.;

[0053] Step 5: Figure 5 As shown, a plurality of chips 7 that need to be integrated and packaged are welded to the surface of the redistribution layer 5 by a flip chip welding process, and a metal bump structure 8 is prepared on the surface of the chip 7. The metal bump structure 8 can be copper-nickel-tin-silver or copper-nickel-gold or copper-nickel-copper-tin-silver, etc. The metal bump structure 8 is welded with the metal bump 6 to form a physical connection and realize signal connection;

[0054] Step 6: Figure 6 As shown, the gap between the chip 7 and the redistribution layer 5 is filled with underfill glue 9 by using the underfill process. The underfill glue 9 can buffer stress and block water and oxygen.

[0055] Step 7: Figure 7 As shown, the whole reconstructed wafer obtained in step six is ​​encapsulated with a plastic encapsulation material 10 using a wafer-level encapsulation process. The plastic encapsulation material 10 can protect the chip 7 and can also be used as a carrier for subsequent processing of the reconstructed wafer. The key to the encapsulation process is to control the warpage value of the entire wafer encapsulation body after encapsulation. If the warpage value is large, the uniformity of the remaining silicon thickness will be poor after grinding. When removing the remaining silicon, it may further cause the dielectric layer 2 to be removed prematurely, and ultimately damage the first organic passivation layer 3. There are three ways to control the warpage: first, increase the silicon ratio of the entire wafer in design, such as attaching a small silicon wafer to the edge of the wafer to make a fake chip; second, select a suitable plastic encapsulation material, focusing on the thermal expansion coefficient and Young's modulus of the plastic encapsulation material. The above method can effectively control the plastic encapsulation warpage value and ensure that the remaining silicon thickness after grinding has good uniformity;

[0056] Step 8: Figure 8 As shown, the silicon carrier 1 is ground and thinned to a thickness of 5-30 microns;

[0057] Step 9: Fig. 9As shown, the remaining silicon carrier residue is removed by dry etching or wet etching, and the dielectric layer 2 is exposed. When dry etching is used to remove the remaining silicon, the difficulty is that it is difficult for the silicon etcher to absorb the warped plastic packaging material. Before the operation, it is necessary to stick an electrostatic film on the surface of the plastic packaging body to enhance the electrostatic adsorption capacity of the silicon etcher stage. The difficulty of wet etching to remove the remaining silicon is that the solution that corrodes silicon may also corrode the plastic packaging material. Therefore, a single-chip spray device should be selected for the operation, and a tank immersion device cannot be selected for the operation. The above method can effectively remove the remaining silicon carrier residue;

[0058] Step 10: Fig.10 As shown, the dielectric layer 2 is removed by chemical mechanical polishing or dry etching or wet etching process to expose the first organic passivation layer 3 and the metal interconnect structure. The difficulty of using dry etching to remove the dielectric layer 2 is that it is difficult for the dry etcher to absorb the warped plastic package sheet. Before the operation, it is necessary to stick an electrostatic film on the surface of the plastic package to enhance the electrostatic adsorption capacity of the silicon etcher stage. The difficulty of using wet etching to remove the dielectric layer 2 is that the solution that corrodes the dielectric layer 2 may also corrode the plastic package material. Therefore, a single-chip spray device should be selected for the operation, and a tank immersion device cannot be selected for the operation. The above method can effectively remove the dielectric layer 2;

[0059] Step 11: Fig.11 As shown, a C4 metal bump 11 is formed at the metal interconnect structure position by electroplating or printing solder paste or ball planting process, and the C4 metal bump 11 can be copper-nickel-tin-silver or copper-tin-silver;

[0060] Step 12: Fig.12 As shown, the plastic cover of the reconstructed wafer is ground and thinned to expose the back side 701 of the chip 7, in order to enhance the heat dissipation of the chip 7;

[0061] Step 13: Fig.13 As shown, the package obtained in step twelve is then cut into individual pieces and mounted on the surface of the substrate 12, and the package and the substrate 12 are connected via the C4 metal bumps 11; glue 13 is filled between the individual package and the substrate 12, and a ball planting process is performed on the side of the substrate 12 away from the package to form solder joints 14, which are usually solder balls composed of copper, tin and silver.

[0062] The present invention also discloses a high-density fan-out packaging structure, which is prepared by the high-density fan-out packaging method as described above. The high-density fan-out packaging structure includes a substrate 12, and a plurality of packaging bodies are connected to the substrate 12. The packaging body includes a redistribution layer 5, a plastic package, and a plurality of chips 7 encapsulated therein and connected to the redistribution layer 5. A C4 metal bump 11 is provided on the side of the redistribution layer 5 away from the chip 7. The packaging body and the substrate 12 are connected via the C4 metal bump 11. Glue 13 is filled between the packaging body and the substrate 12. A ball planting process is performed on the side of the substrate 12 away from the packaging body to form a solder joint 14.

[0063] Example 1

[0064] like Figure 1-13 As shown, a high-density fan-out packaging method includes the following steps:

[0065] Step 1: Figure 1 As shown, a dielectric layer 2 with a thickness of 1 micron is deposited on the surface of the silicon carrier 1. The silicon carrier 1 is usually a circular carrier. The dielectric layer 2 can be made of silicon oxide material. The role of the dielectric layer 2 is, on the one hand, to enhance the bonding force between the silicon carrier 1 and the subsequent redistribution layer, and on the other hand, to serve as a cutoff layer for the subsequent removal process of the silicon carrier 1;

[0066] Step 2: Figure 2 As shown, a first organic passivation layer 3 is formed on the surface of the dielectric layer 2 by photolithography, with a thickness of 5 microns, and an opening 301 is formed at a specific position. The shape of the opening 301 is circular, and the opening size is 10 microns. The first organic passivation layer 3 is made of photosensitive polyimide material. The function of the opening 301 is to form a metal interconnection structure between the redistribution layer and the C4 metal bump;

[0067] Step 3: Figure 3 As shown, the first metal circuit layer 4 is then prepared by metal sputtering, photolithography and electroplating, which is usually a copper circuit. The first metal circuit layer 4 includes a metal interconnect structure filling the opening 301 and a metal trace on the surface of the first organic passivation layer 3;

[0068] Step 4: Figure 4 As shown, four layers of organic passivation layer and metal circuit layer are sequentially prepared on the surface of the first organic passivation layer 3 and the first metal circuit layer 4 to form a redistribution layer 5. The organic passivation layer and the metal circuit layer in the redistribution layer 5 are alternately distributed. The line width and line spacing of the metal circuit layer can usually be made very small, 1μm / 1μm. Fine metal circuits are conducive to realizing signal interconnection between high I / O density chips, such chips are SoCs. Then, metal bumps 6 are formed on the surface of the redistribution layer 5, and their structure is copper-nickel-tin-silver;

[0069] Step 5: Figure 5As shown, a plurality of chips 7 that need to be integrated and packaged are welded to the surface of the redistribution layer 5 by a flip chip welding process, and a metal bump structure 8 is prepared on the surface of the chip 7. The metal bump structure 8 is copper-nickel-tin-silver. The metal bump structure 8 is welded with the metal bump 6 to form a physical connection and realize signal connection;

[0070] Step 6: Figure 6 As shown, the gap between the chip 7 and the redistribution layer 5 is filled with underfill glue 9 by using the underfill process. The underfill glue 9 can buffer stress and block water and oxygen.

[0071] Step 7: Figure 7 As shown, the whole reconstructed wafer obtained in step six is ​​encapsulated with a plastic encapsulation material 10 using a wafer-level encapsulation process. The plastic encapsulation material 10 can protect the chip 7 and can also be used as a carrier for subsequent processing of the reconstructed wafer. The key to the encapsulation process is to control the warpage value of the entire wafer encapsulation body after encapsulation. If the warpage value is large, the uniformity of the remaining silicon thickness will be poor after grinding. When removing the remaining silicon, it may further cause the dielectric layer 2 to be removed prematurely, and ultimately damage the first organic passivation layer 3. There are three ways to control the warpage: first, increase the silicon ratio of the entire wafer in design, such as attaching a small silicon wafer to the edge of the wafer to make a fake chip; second, select a suitable plastic encapsulation material, focusing on the thermal expansion coefficient and Young's modulus of the plastic encapsulation material. The above method can effectively control the plastic encapsulation warpage value and ensure that the remaining silicon thickness after grinding has good uniformity;

[0072] Step 8: Figure 8 As shown, the silicon carrier 1 is ground and thinned to a thickness of 10 microns;

[0073] Step 9: Fig. 9 As shown, the remaining silicon carrier residue is removed by dry etching, and the dielectric layer 2 is exposed. When the remaining silicon is removed by dry etching, the difficulty is that it is difficult for the silicon etcher to absorb the warped plastic packaging material. Before the operation, an electrostatic film needs to be attached to the surface of the plastic packaging body to enhance the electrostatic adsorption ability of the silicon etcher stage;

[0074] Step 10: Fig.10 As shown, the dielectric layer 2 is removed by chemical mechanical polishing to expose the first organic passivation layer 3 and the metal interconnect structure;

[0075] Step 11: Fig.11 As shown, a C4 metal bump 11 is formed at the metal interconnect structure position by an electroplating process, and the C4 metal bump 11 is copper-nickel-tin-silver;

[0076] Step 12: Fig.12 As shown, the plastic cover of the reconstructed wafer is ground and thinned to expose the back side 701 of the chip 7, in order to enhance the heat dissipation of the chip 7;

[0077] Step 13: Fig.13 As shown, the package obtained in step twelve is then cut into individual pieces and mounted on the surface of the substrate 12, and the package and the substrate 12 are connected via the C4 metal bumps 11; glue 13 is filled between the individual package and the substrate 12, and a ball planting process is performed on the side of the substrate 12 away from the package to form solder joints 14, which are usually solder balls composed of copper, tin and silver.

[0078] A high-density fan-out packaging structure is prepared by the high-density fan-out packaging method as described above, the high-density fan-out packaging structure includes a substrate 12, a plurality of packaging bodies are connected to the substrate 12, the packaging body includes a redistribution layer 5, a plastic package, and a plurality of chips 7 encapsulated therein and connected to the redistribution layer 5, a C4 metal bump 11 is provided on the side of the redistribution layer 5 away from the chip 7, a connection is formed between the packaging body and the substrate 12 through the C4 metal bump 11, glue 13 is filled between the packaging body and the substrate 12, and a ball planting process is performed on the side of the substrate 12 away from the packaging body to form a solder joint 14.

[0079] Parts or structures not specifically described in the present invention may adopt existing technologies or existing products and will not be described in detail here.

[0080] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A high-density fan-out packaging method, characterized in that: The following steps are involved: Step 1: preparing a dielectric layer on the surface of a silicon carrier; Step 2: preparing a first organic passivation layer on the surface of the dielectric layer and forming an opening at a specific position; Step 3: preparing a first metal circuit layer on the first organic passivation layer, wherein the first metal circuit layer comprises a metal interconnect structure filling the opening and a metal routing on the surface of the first organic passivation layer; Step 4: preparing a redistribution layer on the surface of the first organic passivation layer and the first metal circuit layer, and then forming metal bumps on the surface of the redistribution layer; Step 5: Connect several chips on the surface of the redistribution layer; Step 6: Use underfill glue to fill the gap between the chip and the redistribution layer; Step 7, performing plastic encapsulation processing on the whole reconstructed wafer obtained in step 6; Step 8, grinding and thinning the silicon carrier, and retaining a portion of the silicon carrier; Step 9: removing the remaining silicon carrier residue and exposing the dielectric layer; Step 10: removing the dielectric layer to expose the first organic passivation layer and the metal interconnect structure; Step 11: forming a C4 metal bump at the metal interconnection structure position; Step 12: Grind and thin the plastic cover of the reconstructed wafer to expose the back side of the chip; Step 13: Cut the package obtained in step 12 into individual pieces, mount them on the surface of the substrate, and perform ball planting on the side of the substrate away from the package.

2. A high-density fan-out packaging method according to claim 1, characterized in that: In step 1, the dielectric layer is made of silicon oxide or silicon nitride.

3. A high-density fan-out packaging method according to claim 1, characterized in that: In step 2, a first organic passivation layer is formed on the surface of the dielectric layer by using a photolithography process, and an opening is formed at a specific position.

4. A high-density fan-out packaging method according to claim 3, characterized in that: The first organic passivation layer is made of photosensitive polyimide or epoxy resin material.

5. A high-density fan-out packaging method according to claim 3, characterized in that: The opening is circular in shape and has a size of 10-60 microns.

6. A high-density fan-out packaging method according to claim 1, characterized in that: In step 4, the redistribution layer includes an organic passivation layer and a metal circuit layer that are alternately distributed.

7. A high-density fan-out packaging method according to claim 1, characterized in that: In step five, a metal bump structure is prepared on the surface of the chip, and several chips are welded to the surface of the redistribution layer through a flip chip welding process. The metal bump structure and the metal bumps are welded to form a physical connection and realize signal connection.

8. A high-density fan-out packaging method according to claim 1, characterized in that: In step thirteen, the package body and the substrate are connected via C4 metal bumps, and glue is filled between the package body and the substrate.

9. A high-density fan-out packaging structure prepared by the high-density fan-out packaging method described in any one of claims 1-8.

10. A high-density fan-out packaging structure, characterized in that: It includes a substrate, on which a plurality of packages are connected, the packages include a redistribution layer, a plastic package, and a plurality of chips encapsulated therein and connected to the redistribution layer, a C4 metal bump is provided on the side of the redistribution layer away from the chip, the package and the substrate are connected via the C4 metal bump, glue is filled between the package and the substrate, and a ball planting process is performed on the side of the substrate away from the package to form a solder joint.

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